!28 升级到3.8.0版本
From: @liusirui91 Reviewed-by: @liuzhiqiang26 Signed-off-by: @liuzhiqiang26
This commit is contained in:
openeuler-ci-bot
Gitee
commit
614c9131f0
@ -2,7 +2,7 @@ diff -up pciutils-3.0.0/Makefile.idpath pciutils-3.0.0/Makefile
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--- pciutils-3.0.0/Makefile.idpath 2008-04-10 21:19:43.000000000 +0200
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+++ pciutils-3.0.0/Makefile 2008-09-01 15:16:19.000000000 +0200
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@@ -27,7 +27,7 @@ ABI_VERSION=.3
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PREFIX=/usr/local
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BINDIR=$(PREFIX)/bin
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SBINDIR=$(PREFIX)/sbin
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SHAREDIR=$(PREFIX)/share
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-IDSDIR=$(SHAREDIR)
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@ -1,121 +0,0 @@
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From e79a42076aebbbe1fbd2d68bd9bc53f22066ab56 Mon Sep 17 00:00:00 2001
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From: Dongdong Liu <liudongdong3@huawei.com>
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Date: Sat, 29 Aug 2020 18:58:41 +0800
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Subject: [PATCH openEuler-22.03-LTS 5/5] lspci: Adjust PCI_EXP_DEV2_* to
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PCI_EXP_DEVCTL2_* macro definition
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Adjust PCI_EXP_DEV2_* to PCI_EXP_DEVCTL2_* macro definition to keep the
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same style between the Linux kernel source [1] and lspci.
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h#n651
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Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
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Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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Signed-off-by: Wangming Shao <shaowangming@h-partners.com>
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---
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lib/header.h | 26 ++++++++++++++------------
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ls-caps.c | 20 ++++++++++----------
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2 files changed, 24 insertions(+), 22 deletions(-)
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diff --git a/lib/header.h b/lib/header.h
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index 57a9343..5fdea88 100644
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--- a/lib/header.h
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+++ b/lib/header.h
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@@ -873,6 +873,13 @@
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#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
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#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
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#define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */
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+#define PCI_EXP_DEVCAP2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
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+#define PCI_EXP_DEVCAP2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */
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+#define PCI_EXP_DEVCAP2_ARI 0x0020 /* ARI Forwarding Supported */
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+#define PCI_EXP_DEVCAP2_ATOMICOP_ROUTING 0x0040 /* AtomicOp Routing Supported */
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+#define PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP 0x0080 /* 32bit AtomicOp Completer Supported */
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+#define PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP 0x0100 /* 64bit AtomicOp Completer Supported */
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+#define PCI_EXP_DEVCAP2_128BIT_CAS_COMP 0x0200 /* 128bit CAS Completer Supported */
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#define PCI_EXP_DEVCAP2_NROPRPRP 0x0400 /* No RO-enabled PR-PR Passing */
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#define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */
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#define PCI_EXP_DEVCAP2_TPH_COMP(x) (((x) >> 12) & 3) /* TPH Completer Supported */
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@@ -887,18 +894,13 @@
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#define PCI_EXP_DEVCAP2_EPR_INIT 0x04000000 /* Emergency Power Reduction Initialization Required */
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#define PCI_EXP_DEVCAP2_FRS 0x80000000 /* FRS supported */
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#define PCI_EXP_DEVCTL2 0x28 /* Device Control */
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-#define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
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-#define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
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-#define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */
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-#define PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */
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-#define PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */
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-#define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */
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-#define PCI_EXP_DEVCAP2_ATOMICOP_ROUTING 0x0040 /* AtomicOp Routing Supported */
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-#define PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP 0x0080 /* 32bit AtomicOp Completer Supported */
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-#define PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP 0x0100 /* 64bit AtomicOp Completer Supported */
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-#define PCI_EXP_DEVCAP2_128BIT_CAS_COMP 0x0200 /* 128bit CAS Completer Supported */
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-#define PCI_EXP_DEV2_LTR 0x0400 /* LTR enabled */
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-#define PCI_EXP_DEV2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */
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+#define PCI_EXP_DEVCTL2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
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+#define PCI_EXP_DEVCTL2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable */
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+#define PCI_EXP_DEVCTL2_ARI 0x0020 /* ARI Forwarding */
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+#define PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */
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+#define PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */
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+#define PCI_EXP_DEVCTL2_LTR 0x0400 /* LTR enabled */
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+#define PCI_EXP_DEVCTL2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */
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#define PCI_EXP_DEVSTA2 0x2a /* Device Status */
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#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */
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#define PCI_EXP_LNKCAP2_SPEED(x) (((x) >> 1) & 0x7f)
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diff --git a/ls-caps.c b/ls-caps.c
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index a09b0cf..a068fd3 100644
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--- a/ls-caps.c
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+++ b/ls-caps.c
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@@ -1085,8 +1085,8 @@ static void cap_express_dev2(struct device *d, int where, int type)
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l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
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printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c",
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- cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
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- FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS),
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+ cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)),
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+ FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS),
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FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP),
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FLAG(l, PCI_EXP_DEVCAP2_LTR));
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printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c",
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@@ -1115,7 +1115,7 @@ static void cap_express_dev2(struct device *d, int where, int type)
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printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l)));
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if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
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- printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
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+ printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI));
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else
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printf("\n");
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if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
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@@ -1135,12 +1135,12 @@ static void cap_express_dev2(struct device *d, int where, int type)
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w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
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printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c OBFF %s,",
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- cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
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- FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS),
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- FLAG(w, PCI_EXP_DEV2_LTR),
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- cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w)));
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+ cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
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+ FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS),
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+ FLAG(w, PCI_EXP_DEVCTL2_LTR),
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+ cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)));
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if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
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- printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
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+ printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
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else
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printf("\n");
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if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
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@@ -1150,10 +1150,10 @@ static void cap_express_dev2(struct device *d, int where, int type)
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printf("\t\t\t AtomicOpsCtl:");
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if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
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type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
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- printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
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+ printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN));
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if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
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type == PCI_EXP_TYPE_DOWNSTREAM)
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- printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK));
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+ printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
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printf("\n");
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}
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}
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--
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2.33.0
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@ -1,52 +0,0 @@
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From 3afdb452bc82421a18e57913f57d8d4caf50dbcc Mon Sep 17 00:00:00 2001
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From: Dongdong Liu <liudongdong3@huawei.com>
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Date: Sat, 29 Aug 2020 18:58:42 +0800
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Subject: [PATCH openEuler-22.03-LTS 4/4] lspci: Decode 10-Bit Tag Requester
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Enable
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Decode 10-Bit Tag Requester Enable bit in Device Control 2 Register.
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Sample output changes:
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- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- OBFF Disabled, ARIFwd-
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+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- 10BitTagReq- OBFF Disabled, ARIFwd-
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Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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Signed-off-by: Wangming Shao <shaowangming@h-partners.com>
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---
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lib/header.h | 1 +
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ls-caps.c | 3 ++-
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/lib/header.h b/lib/header.h
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index 5fdea88..f53ab43 100644
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--- a/lib/header.h
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+++ b/lib/header.h
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@@ -900,6 +900,7 @@
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#define PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */
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#define PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */
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#define PCI_EXP_DEVCTL2_LTR 0x0400 /* LTR enabled */
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+#define PCI_EXP_DEVCTL2_10BIT_TAG_REQ 0x1000 /* 10 Bit Tag Requester enabled */
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#define PCI_EXP_DEVCTL2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */
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#define PCI_EXP_DEVSTA2 0x2a /* Device Status */
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#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */
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diff --git a/ls-caps.c b/ls-caps.c
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index a068fd3..b616a4b 100644
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--- a/ls-caps.c
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+++ b/ls-caps.c
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@@ -1134,10 +1134,11 @@ static void cap_express_dev2(struct device *d, int where, int type)
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}
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w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
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- printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c OBFF %s,",
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+ printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c 10BitTagReq%c OBFF %s,",
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cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
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FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS),
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FLAG(w, PCI_EXP_DEVCTL2_LTR),
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+ FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
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cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)));
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if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
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printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
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--
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2.33.0
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@ -1,64 +0,0 @@
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From 053d08d21d869a95d3f869316ce2d8ddab9104d0 Mon Sep 17 00:00:00 2001
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From: Dongdong Liu <liudongdong3@huawei.com>
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Date: Tue, 9 Mar 2021 21:35:18 +0800
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Subject: [PATCH openEuler-22.03-LTS 3/3] lspci: Decode VF 10-Bit Tag Requester
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Decode VF 10-Bit Tag Requester Supported and Enable bit
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in SR-IOV Capabilities Register.
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Sample output:
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IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
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IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy- 10BitTagReq-
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Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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Signed-off-by: Wangming Shao <shaowangming@h-partners.com>
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---
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lib/header.h | 2 ++
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ls-ecaps.c | 8 ++++----
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2 files changed, 6 insertions(+), 4 deletions(-)
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diff --git a/lib/header.h b/lib/header.h
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index d4b40aa..ec1bb63 100644
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--- a/lib/header.h
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+++ b/lib/header.h
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@@ -1126,6 +1126,7 @@
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/* Single Root I/O Virtualization */
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#define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */
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#define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */
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+#define PCI_IOV_CAP_VF_10BIT_TAG_REQ 0x00000004 /* VF 10-Bit Tag Requester Supported */
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#define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */
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#define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */
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#define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */
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@@ -1133,6 +1134,7 @@
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#define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */
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#define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */
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#define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
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+#define PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN 0x0020 /* VF 10-Bit Tag Requester Enable */
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#define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */
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#define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */
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#define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially associated */
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diff --git a/ls-ecaps.c b/ls-ecaps.c
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index 99c55ff..1cea315 100644
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--- a/ls-ecaps.c
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+++ b/ls-ecaps.c
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@@ -369,13 +369,13 @@ cap_sriov(struct device *d, int where)
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return;
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l = get_conf_long(d, where + PCI_IOV_CAP);
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- printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
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- FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
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+ printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c Interrupt Message Number: %03x\n",
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+ FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
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w = get_conf_word(d, where + PCI_IOV_CTRL);
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- printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
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+ printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
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FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
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FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
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- FLAG(w, PCI_IOV_CTRL_ARI));
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+ FLAG(w, PCI_IOV_CTRL_ARI), FLAG(w, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN));
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w = get_conf_word(d, where + PCI_IOV_STATUS);
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printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
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w = get_conf_word(d, where + PCI_IOV_INITIALVF);
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--
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2.33.0
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@ -1,65 +0,0 @@
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From c5db7af4dee09016489185e26af66cf2f4725a21 Mon Sep 17 00:00:00 2001
|
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From: Dongdong Liu <liudongdong3@huawei.com>
|
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Date: Tue, 9 Mar 2021 21:35:19 +0800
|
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Subject: [PATCH openEuler-22.03-LTS 2/3] lspci: Update tests files with VF
|
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10-Bit Tag Requester
|
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|
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Update the tests files with the new field 10BitTagReq
|
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in SR-IOV Capabilities Register.
|
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|
||||
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
|
||||
Signed-off-by: Wangming Shao <shaowangming@h-partners.com>
|
||||
---
|
||||
tests/cap-dvsec-cxl | 4 ++--
|
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tests/cap-ea-1 | 4 ++--
|
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tests/cap-pcie-2 | 4 ++--
|
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3 files changed, 6 insertions(+), 6 deletions(-)
|
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|
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diff --git a/tests/cap-dvsec-cxl b/tests/cap-dvsec-cxl
|
||||
index c499d0e..a24e3fb 100644
|
||||
--- a/tests/cap-dvsec-cxl
|
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+++ b/tests/cap-dvsec-cxl
|
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@@ -79,8 +79,8 @@
|
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PTMControl: Enabled:- RootSelected:-
|
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PTMEffectiveGranularity: Unknown
|
||||
Capabilities: [b80 v1] Single Root I/O Virtualization (SR-IOV)
|
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- IOVCap: Migration-, Interrupt Message Number: 000
|
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- IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy-
|
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+ IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
|
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+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy- 10BitTagReq-
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IOVSta: Migration-
|
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Initial VFs: 6, Total VFs: 6, Number of VFs: 0, Function Dependency Link: 00
|
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VF offset: 16, stride: 2, Device ID: 0d52
|
||||
diff --git a/tests/cap-ea-1 b/tests/cap-ea-1
|
||||
index df88ba9..776839d 100644
|
||||
--- a/tests/cap-ea-1
|
||||
+++ b/tests/cap-ea-1
|
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@@ -57,8 +57,8 @@
|
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ARICtl: MFVC- ACS-, Function Group: 0
|
||||
Capabilities: [108 v1] Vendor Specific Information: ID=00a0 Rev=1 Len=040 <?>
|
||||
Capabilities: [180 v1] Single Root I/O Virtualization (SR-IOV)
|
||||
- IOVCap: Migration-, Interrupt Message Number: 000
|
||||
- IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy+
|
||||
+ IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
|
||||
+ IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy+ 10BitTagReq-
|
||||
IOVSta: Migration-
|
||||
Initial VFs: 128, Total VFs: 128, Number of VFs: 128, Function Dependency Link: 00
|
||||
VF offset: 1, stride: 1, Device ID: a034
|
||||
diff --git a/tests/cap-pcie-2 b/tests/cap-pcie-2
|
||||
index 47c8953..9bde139 100644
|
||||
--- a/tests/cap-pcie-2
|
||||
+++ b/tests/cap-pcie-2
|
||||
@@ -48,8 +48,8 @@
|
||||
ARICap: MFVC- ACS-, Next Function: 1
|
||||
ARICtl: MFVC- ACS-, Function Group: 0
|
||||
Capabilities: [160] Single Root I/O Virtualization (SR-IOV)
|
||||
- IOVCap: Migration-, Interrupt Message Number: 000
|
||||
- IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy-
|
||||
+ IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
|
||||
+ IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy- 10BitTagReq-
|
||||
IOVSta: Migration-
|
||||
Initial VFs: 8, Total VFs: 8, Number of VFs: 1, Function Dependency Link: 00
|
||||
VF offset: 384, stride: 2, Device ID: 10ca
|
||||
--
|
||||
2.33.0
|
||||
|
||||
Binary file not shown.
BIN
pciutils-3.8.0.tar.gz
Normal file
BIN
pciutils-3.8.0.tar.gz
Normal file
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
Name: pciutils
|
||||
Version: 3.7.0
|
||||
Release: 3
|
||||
Version: 3.8.0
|
||||
Release: 1
|
||||
Summary: PCI bus related utilities
|
||||
License: GPLv2+
|
||||
URL: http://atrey.karlin.mff.cuni.cz/~mj/pciutils.shtml
|
||||
@ -10,10 +10,6 @@ Source0: https://mirrors.edge.kernel.org/pub/software/utils/pciutils/%{na
|
||||
Patch0: 0000-pciutils-2.2.1-idpath.patch
|
||||
# patch1 is from fedora, rhbz#195327
|
||||
Patch1: 0001-pciutils-dir-d.patch
|
||||
Patch2: 0002-lspci-Adjust-PCI_EXP_DEV2_-to-PCI_EXP_DEVCTL2_-macro.patch
|
||||
Patch3: 0003-lspci-Decode-10-Bit-Tag-Requester-Enable.patch
|
||||
Patch4: 0004-lspci-Decode-VF-10-Bit-Tag-Requester.patch
|
||||
Patch5: 0005-lspci-Update-tests-files-with-VF-10-Bit-Tag-Requeste.patch
|
||||
|
||||
ExclusiveOS: Linux
|
||||
BuildRequires: gcc sed kmod-devel pkgconfig zlib-devel
|
||||
@ -88,7 +84,7 @@ rm -rf $RPM_BUILD_ROOT/usr/share/hwdata/pci.ids*
|
||||
%files
|
||||
%defattr(-,root,root,-)
|
||||
%doc README ChangeLog pciutils.lsm COPYING
|
||||
/sbin/lspci
|
||||
/usr/bin/lspci
|
||||
/sbin/setpci
|
||||
/sbin/update-pciids
|
||||
/%{_lib}/libpci.so.*
|
||||
@ -109,6 +105,9 @@ rm -rf $RPM_BUILD_ROOT/usr/share/hwdata/pci.ids*
|
||||
rm -rf $RPM_BUILD_ROOT
|
||||
|
||||
%changelog
|
||||
* Fri Oct 28 2022 liusirui <liusirui@huawei.com> - 3.8.0-1
|
||||
- update to v3.8.0
|
||||
|
||||
* Tue Sep 6 2022 Wangming Shao <shaowangming@h-partners.com> - 3.7.0-3
|
||||
- DESC:add support lspci querying 10-bit tag information
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user