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update to v3.8.0

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liusirui 2022-10-28 16:10:24 +08:00
parent 29403584ba
commit 3b6fd68c99
8 changed files with 7 additions and 310 deletions
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2
0000-pciutils-2.2.1-idpath.patch
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@ -2,7 +2,7 @@ diff -up pciutils-3.0.0/Makefile.idpath pciutils-3.0.0/Makefile
--- pciutils-3.0.0/Makefile.idpath 2008-04-10 21:19:43.000000000 +0200
+++ pciutils-3.0.0/Makefile 2008-09-01 15:16:19.000000000 +0200
@@ -27,7 +27,7 @@ ABI_VERSION=.3
PREFIX=/usr/local
BINDIR=$(PREFIX)/bin
SBINDIR=$(PREFIX)/sbin
SHAREDIR=$(PREFIX)/share
-IDSDIR=$(SHAREDIR)

121
0002-lspci-Adjust-PCI_EXP_DEV2_-to-PCI_EXP_DEVCTL2_-macro.patch
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@ -1,121 +0,0 @@
From e79a42076aebbbe1fbd2d68bd9bc53f22066ab56 Mon Sep 17 00:00:00 2001
From: Dongdong Liu <liudongdong3@huawei.com>
Date: Sat, 29 Aug 2020 18:58:41 +0800
Subject: [PATCH openEuler-22.03-LTS 5/5] lspci: Adjust PCI_EXP_DEV2_* to
PCI_EXP_DEVCTL2_* macro definition
Adjust PCI_EXP_DEV2_* to PCI_EXP_DEVCTL2_* macro definition to keep the
same style between the Linux kernel source [1] and lspci.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h#n651
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Wangming Shao <shaowangming@h-partners.com>
---
lib/header.h | 26 ++++++++++++++------------
ls-caps.c | 20 ++++++++++----------
2 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/lib/header.h b/lib/header.h
index 57a9343..5fdea88 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -873,6 +873,13 @@
#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
#define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */
+#define PCI_EXP_DEVCAP2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
+#define PCI_EXP_DEVCAP2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */
+#define PCI_EXP_DEVCAP2_ARI 0x0020 /* ARI Forwarding Supported */
+#define PCI_EXP_DEVCAP2_ATOMICOP_ROUTING 0x0040 /* AtomicOp Routing Supported */
+#define PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP 0x0080 /* 32bit AtomicOp Completer Supported */
+#define PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP 0x0100 /* 64bit AtomicOp Completer Supported */
+#define PCI_EXP_DEVCAP2_128BIT_CAS_COMP 0x0200 /* 128bit CAS Completer Supported */
#define PCI_EXP_DEVCAP2_NROPRPRP 0x0400 /* No RO-enabled PR-PR Passing */
#define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */
#define PCI_EXP_DEVCAP2_TPH_COMP(x) (((x) >> 12) & 3) /* TPH Completer Supported */
@@ -887,18 +894,13 @@
#define PCI_EXP_DEVCAP2_EPR_INIT 0x04000000 /* Emergency Power Reduction Initialization Required */
#define PCI_EXP_DEVCAP2_FRS 0x80000000 /* FRS supported */
#define PCI_EXP_DEVCTL2 0x28 /* Device Control */
-#define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
-#define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
-#define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */
-#define PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */
-#define PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */
-#define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */
-#define PCI_EXP_DEVCAP2_ATOMICOP_ROUTING 0x0040 /* AtomicOp Routing Supported */
-#define PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP 0x0080 /* 32bit AtomicOp Completer Supported */
-#define PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP 0x0100 /* 64bit AtomicOp Completer Supported */
-#define PCI_EXP_DEVCAP2_128BIT_CAS_COMP 0x0200 /* 128bit CAS Completer Supported */
-#define PCI_EXP_DEV2_LTR 0x0400 /* LTR enabled */
-#define PCI_EXP_DEV2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */
+#define PCI_EXP_DEVCTL2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
+#define PCI_EXP_DEVCTL2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable */
+#define PCI_EXP_DEVCTL2_ARI 0x0020 /* ARI Forwarding */
+#define PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */
+#define PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */
+#define PCI_EXP_DEVCTL2_LTR 0x0400 /* LTR enabled */
+#define PCI_EXP_DEVCTL2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */
#define PCI_EXP_DEVSTA2 0x2a /* Device Status */
#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */
#define PCI_EXP_LNKCAP2_SPEED(x) (((x) >> 1) & 0x7f)
diff --git a/ls-caps.c b/ls-caps.c
index a09b0cf..a068fd3 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -1085,8 +1085,8 @@ static void cap_express_dev2(struct device *d, int where, int type)
l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c",
- cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
- FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS),
+ cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)),
+ FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS),
FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP),
FLAG(l, PCI_EXP_DEVCAP2_LTR));
printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c",
@@ -1115,7 +1115,7 @@ static void cap_express_dev2(struct device *d, int where, int type)
printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l)));
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
- printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
+ printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI));
else
printf("\n");
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
@@ -1135,12 +1135,12 @@ static void cap_express_dev2(struct device *d, int where, int type)
w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c OBFF %s,",
- cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
- FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS),
- FLAG(w, PCI_EXP_DEV2_LTR),
- cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w)));
+ cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
+ FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS),
+ FLAG(w, PCI_EXP_DEVCTL2_LTR),
+ cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)));
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
- printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
+ printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
else
printf("\n");
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
@@ -1150,10 +1150,10 @@ static void cap_express_dev2(struct device *d, int where, int type)
printf("\t\t\t AtomicOpsCtl:");
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
- printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
+ printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN));
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
type == PCI_EXP_TYPE_DOWNSTREAM)
- printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK));
+ printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
printf("\n");
}
}
--
2.33.0

52
0003-lspci-Decode-10-Bit-Tag-Requester-Enable.patch
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@ -1,52 +0,0 @@
From 3afdb452bc82421a18e57913f57d8d4caf50dbcc Mon Sep 17 00:00:00 2001
From: Dongdong Liu <liudongdong3@huawei.com>
Date: Sat, 29 Aug 2020 18:58:42 +0800
Subject: [PATCH openEuler-22.03-LTS 4/4] lspci: Decode 10-Bit Tag Requester
Enable
Decode 10-Bit Tag Requester Enable bit in Device Control 2 Register.
Sample output changes:
- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- OBFF Disabled, ARIFwd-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- 10BitTagReq- OBFF Disabled, ARIFwd-
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Wangming Shao <shaowangming@h-partners.com>
---
lib/header.h | 1 +
ls-caps.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/lib/header.h b/lib/header.h
index 5fdea88..f53ab43 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -900,6 +900,7 @@
#define PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */
#define PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */
#define PCI_EXP_DEVCTL2_LTR 0x0400 /* LTR enabled */
+#define PCI_EXP_DEVCTL2_10BIT_TAG_REQ 0x1000 /* 10 Bit Tag Requester enabled */
#define PCI_EXP_DEVCTL2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */
#define PCI_EXP_DEVSTA2 0x2a /* Device Status */
#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */
diff --git a/ls-caps.c b/ls-caps.c
index a068fd3..b616a4b 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -1134,10 +1134,11 @@ static void cap_express_dev2(struct device *d, int where, int type)
}
w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
- printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c OBFF %s,",
+ printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c 10BitTagReq%c OBFF %s,",
cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS),
FLAG(w, PCI_EXP_DEVCTL2_LTR),
+ FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)));
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
--
2.33.0

64
0004-lspci-Decode-VF-10-Bit-Tag-Requester.patch
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@ -1,64 +0,0 @@
From 053d08d21d869a95d3f869316ce2d8ddab9104d0 Mon Sep 17 00:00:00 2001
From: Dongdong Liu <liudongdong3@huawei.com>
Date: Tue, 9 Mar 2021 21:35:18 +0800
Subject: [PATCH openEuler-22.03-LTS 3/3] lspci: Decode VF 10-Bit Tag Requester
Decode VF 10-Bit Tag Requester Supported and Enable bit
in SR-IOV Capabilities Register.
Sample output:
IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy- 10BitTagReq-
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Wangming Shao <shaowangming@h-partners.com>
---
lib/header.h | 2 ++
ls-ecaps.c | 8 ++++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/lib/header.h b/lib/header.h
index d4b40aa..ec1bb63 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1126,6 +1126,7 @@
/* Single Root I/O Virtualization */
#define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */
#define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */
+#define PCI_IOV_CAP_VF_10BIT_TAG_REQ 0x00000004 /* VF 10-Bit Tag Requester Supported */
#define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */
#define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */
#define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */
@@ -1133,6 +1134,7 @@
#define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */
#define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */
#define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
+#define PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN 0x0020 /* VF 10-Bit Tag Requester Enable */
#define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */
#define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */
#define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially associated */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index 99c55ff..1cea315 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -369,13 +369,13 @@ cap_sriov(struct device *d, int where)
return;
l = get_conf_long(d, where + PCI_IOV_CAP);
- printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
- FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
+ printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c Interrupt Message Number: %03x\n",
+ FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
w = get_conf_word(d, where + PCI_IOV_CTRL);
- printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
+ printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
- FLAG(w, PCI_IOV_CTRL_ARI));
+ FLAG(w, PCI_IOV_CTRL_ARI), FLAG(w, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN));
w = get_conf_word(d, where + PCI_IOV_STATUS);
printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
w = get_conf_word(d, where + PCI_IOV_INITIALVF);
--
2.33.0

65
0005-lspci-Update-tests-files-with-VF-10-Bit-Tag-Requeste.patch
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@ -1,65 +0,0 @@
From c5db7af4dee09016489185e26af66cf2f4725a21 Mon Sep 17 00:00:00 2001
From: Dongdong Liu <liudongdong3@huawei.com>
Date: Tue, 9 Mar 2021 21:35:19 +0800
Subject: [PATCH openEuler-22.03-LTS 2/3] lspci: Update tests files with VF
10-Bit Tag Requester
Update the tests files with the new field 10BitTagReq
in SR-IOV Capabilities Register.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Wangming Shao <shaowangming@h-partners.com>
---
tests/cap-dvsec-cxl | 4 ++--
tests/cap-ea-1 | 4 ++--
tests/cap-pcie-2 | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/cap-dvsec-cxl b/tests/cap-dvsec-cxl
index c499d0e..a24e3fb 100644
--- a/tests/cap-dvsec-cxl
+++ b/tests/cap-dvsec-cxl
@@ -79,8 +79,8 @@
PTMControl: Enabled:- RootSelected:-
PTMEffectiveGranularity: Unknown
Capabilities: [b80 v1] Single Root I/O Virtualization (SR-IOV)
- IOVCap: Migration-, Interrupt Message Number: 000
- IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy-
+ IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
+ IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy- 10BitTagReq-
IOVSta: Migration-
Initial VFs: 6, Total VFs: 6, Number of VFs: 0, Function Dependency Link: 00
VF offset: 16, stride: 2, Device ID: 0d52
diff --git a/tests/cap-ea-1 b/tests/cap-ea-1
index df88ba9..776839d 100644
--- a/tests/cap-ea-1
+++ b/tests/cap-ea-1
@@ -57,8 +57,8 @@
ARICtl: MFVC- ACS-, Function Group: 0
Capabilities: [108 v1] Vendor Specific Information: ID=00a0 Rev=1 Len=040 <?>
Capabilities: [180 v1] Single Root I/O Virtualization (SR-IOV)
- IOVCap: Migration-, Interrupt Message Number: 000
- IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy+
+ IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
+ IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy+ 10BitTagReq-
IOVSta: Migration-
Initial VFs: 128, Total VFs: 128, Number of VFs: 128, Function Dependency Link: 00
VF offset: 1, stride: 1, Device ID: a034
diff --git a/tests/cap-pcie-2 b/tests/cap-pcie-2
index 47c8953..9bde139 100644
--- a/tests/cap-pcie-2
+++ b/tests/cap-pcie-2
@@ -48,8 +48,8 @@
ARICap: MFVC- ACS-, Next Function: 1
ARICtl: MFVC- ACS-, Function Group: 0
Capabilities: [160] Single Root I/O Virtualization (SR-IOV)
- IOVCap: Migration-, Interrupt Message Number: 000
- IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy-
+ IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
+ IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy- 10BitTagReq-
IOVSta: Migration-
Initial VFs: 8, Total VFs: 8, Number of VFs: 1, Function Dependency Link: 00
VF offset: 384, stride: 2, Device ID: 10ca
--
2.33.0

BIN
pciutils-3.7.0.tar.gz
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pciutils-3.8.0.tar.gz Normal file
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13
pciutils.spec
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@ -1,6 +1,6 @@
Name: pciutils
Version: 3.7.0
Release: 3
Version: 3.8.0
Release: 1
Summary: PCI bus related utilities
License: GPLv2+
URL: http://atrey.karlin.mff.cuni.cz/~mj/pciutils.shtml
@ -10,10 +10,6 @@ Source0: https://mirrors.edge.kernel.org/pub/software/utils/pciutils/%{na
Patch0: 0000-pciutils-2.2.1-idpath.patch
# patch1 is from fedora, rhbz#195327
Patch1: 0001-pciutils-dir-d.patch
Patch2: 0002-lspci-Adjust-PCI_EXP_DEV2_-to-PCI_EXP_DEVCTL2_-macro.patch
Patch3: 0003-lspci-Decode-10-Bit-Tag-Requester-Enable.patch
Patch4: 0004-lspci-Decode-VF-10-Bit-Tag-Requester.patch
Patch5: 0005-lspci-Update-tests-files-with-VF-10-Bit-Tag-Requeste.patch
ExclusiveOS: Linux
BuildRequires: gcc sed kmod-devel pkgconfig zlib-devel
@ -88,7 +84,7 @@ rm -rf $RPM_BUILD_ROOT/usr/share/hwdata/pci.ids*
%files
%defattr(-,root,root,-)
%doc README ChangeLog pciutils.lsm COPYING
/sbin/lspci
/usr/bin/lspci
/sbin/setpci
/sbin/update-pciids
/%{_lib}/libpci.so.*
@ -109,6 +105,9 @@ rm -rf $RPM_BUILD_ROOT/usr/share/hwdata/pci.ids*
rm -rf $RPM_BUILD_ROOT
%changelog
* Fri Oct 28 2022 liusirui <liusirui@huawei.com> - 3.8.0-1
- update to v3.8.0
* Tue Sep 6 2022 Wangming Shao <shaowangming@h-partners.com> - 3.7.0-3
- DESC:add support lspci querying 10-bit tag information