upgrade to mesa-23.3.1
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zppzhangpan
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@ -1,26 +0,0 @@
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From 0ec3bdb2264b491fd3f5dc4e638b4c12611ef219 Mon Sep 17 00:00:00 2001
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From: Igor Gnatenko <i.gnatenko.brain@gmail.com>
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Date: Sun, 20 Mar 2016 13:27:45 +0100
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Subject: [PATCH 3/4] evergreen big endian
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Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
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---
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src/gallium/drivers/r600/r600_state_common.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
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index cac240e..4b620a1 100644
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--- a/src/gallium/drivers/r600/r600_state_common.c
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+++ b/src/gallium/drivers/r600/r600_state_common.c
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@@ -2716,7 +2716,7 @@ uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format forma
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uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
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{
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- if (R600_BIG_ENDIAN) {
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+ if (0 && R600_BIG_ENDIAN) {
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switch(colorformat) {
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/* 8-bit buffers. */
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case V_0280A0_COLOR_4_4:
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--
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2.7.4
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File diff suppressed because it is too large
Load Diff
@ -1,116 +0,0 @@
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From b4cc97ac05b70fa328ad57cf6defee8113666cac Mon Sep 17 00:00:00 2001
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From: Alex Fan <alex.fan.q@gmail.com>
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Date: Fri, 29 Jul 2022 12:44:14 +1000
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Subject: [PATCH] llvmpipe: add riscv support in orcjit
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assume cpu supports extension +i,+m,+a,+f,+d,+c
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---
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diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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index 8ea4df7..91dde78 100644
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--- a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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+++ b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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@@ -44,7 +44,7 @@
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/* conflict with ObjectLinkingLayer.h */
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#include "util/u_memory.h"
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-#if (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
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+#if defined(PIPE_ARCH_RISCV64) || defined(PIPE_ARCH_RISCV32) || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
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/* use ObjectLinkingLayer (JITLINK backend) */
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#define USE_JITLINK
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#endif
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@@ -551,6 +551,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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options.StackAlignmentOverride = 4;
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#endif
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+#if defined(PIPE_ARCH_RISCV64)
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+#if defined(__riscv_float_abi_soft)
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+ options.MCOptions.ABIName = "lp64";
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+#elif defined(__riscv_float_abi_single)
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+ options.MCOptions.ABIName = "lp64f";
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+#elif defined(__riscv_float_abi_double)
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+ options.MCOptions.ABIName = "lp64d";
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+#else
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+#error "GALLIVM: unknown target riscv float abi"
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+#endif
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+#endif
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+
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+#if defined(PIPE_ARCH_RISCV32)
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+#if defined(__riscv_float_abi_soft)
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+ options.MCOptions.ABIName = "ilp32";
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+#elif defined(__riscv_float_abi_single)
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+ options.MCOptions.ABIName = "ilp32f";
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+#elif defined(__riscv_float_abi_double)
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+ options.MCOptions.ABIName = "ilp32d";
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+#else
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+#error "GALLIVM: unknown target riscv float abi"
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+#endif
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+#endif
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+
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JTMB.setOptions(options);
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std::vector<std::string> MAttrs;
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@@ -649,6 +673,14 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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MAttrs.push_back("+fp64");
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#endif
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+#if defined(PIPE_ARCH_RISCV64)
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+ /* Before riscv is more matured and util_get_cpu_caps() is implemented,
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+ * assume this for now since most of linux capable riscv machine are
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+ * riscv64gc
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+ */
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+ MAttrs = {"+m","+c","+a","+d","+f"};
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+#endif
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+
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JTMB.addFeatures(MAttrs);
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if (::gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
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@@ -716,6 +748,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
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#endif
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+#if defined(PIPE_ARCH_RISCV64)
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+ /**
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+ * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
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+ * set it anyway for llvm 14
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+ */
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+ if (MCPU == "generic")
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+ MCPU = "generic-rv64";
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+
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+ JTMB.setCodeModel(CodeModel::Medium);
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+ JTMB.setRelocationModel(Reloc::PIC_);
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+#endif
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+
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+#if defined(PIPE_ARCH_RISCV32)
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+ /**
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+ * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
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+ * set it anyway for llvm 14
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+ */
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+ if (MCPU == "generic")
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+ MCPU = "generic-rv32";
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+
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+ JTMB.setCodeModel(CodeModel::Medium);
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+ JTMB.setRelocationModel(Reloc::PIC_);
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+#endif
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+
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JTMB.setCPU(MCPU);
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if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
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debug_printf("llc -mcpu option: %s\n", MCPU.c_str());
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diff --git a/src/util/detect_arch.h b/src/util/detect_arch.h
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index 334358f..8c7bd15 100644
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--- a/src/util/detect_arch.h
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+++ b/src/util/detect_arch.h
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@@ -137,4 +137,14 @@
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#define DETECT_ARCH_MIPS 0
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#endif
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+#if defined(__riscv)
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+#if __riscv_xlen == 64
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+#define PIPE_ARCH_RISCV64
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+#elif __riscv_xlen == 32
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+#define PIPE_ARCH_RISCV32
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+#else
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+#error "pipe: unknown target riscv xlen"
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+#endif
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+#endif
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+
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#endif /* UTIL_DETECT_ARCH_H_ */
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@ -1,23 +0,0 @@
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From 3148f08bd0207a8bd50ff5c8b82d7a5b0871c3d1 Mon Sep 17 00:00:00 2001
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From: Alex Fan <alex.fan.q@gmail.com>
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Date: Mon, 28 Nov 2022 22:29:44 +1100
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Subject: [PATCH] llvmpipe: make unnamed global have internal linkage
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work around bug https://github.com/llvm/llvm-project/issues/54813
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Being unnamed makes it not useable from other module, therefore
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changing to internal linkage is safe
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Signed-off-by: Alex Fan <alex.fan.q@gmail.com>
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---
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diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c b/src/gallium/drivers/llvmpipe/lp_state_fs.c
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index 4e0b693..5b29610 100644
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--- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
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+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
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@@ -3320,6 +3320,7 @@ generate_fragment(struct llvmpipe_context *lp,
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LLVMValueRef glob_sample_pos =
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LLVMAddGlobal(gallivm->module,
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LLVMArrayType(flt_type, key->coverage_samples * 2), "");
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+ LLVMSetLinkage(glob_sample_pos, LLVMInternalLinkage);
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LLVMValueRef sample_pos_array;
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if (key->multisample && key->coverage_samples == 4) {
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Binary file not shown.
10
mesa.spec
10
mesa.spec
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Name: mesa
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Summary: Mesa graphics libraries
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Version: 23.2.1
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Version: 23.3.1
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Release: 1
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License: MIT
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@ -59,10 +59,6 @@ URL: http://www.mesa3d.org
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Source0: https://mesa.freedesktop.org/archive/%{name}-%{version}.tar.xz
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Patch1: backport-fix-build-err-on-arm.patch
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Patch2: 0001-evergreen-big-endian.patch
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Patch3: llvmpipe-add-an-implementation-with-llvm-orcjit.patch
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Patch4: llvmpipe-add-riscv-support-in-orcjit.patch
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Patch5: llvmpipe-make-unnamed-global-have-internal-linkage.patch
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BuildRequires: gcc
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BuildRequires: gcc-c++
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@ -494,6 +490,7 @@ done
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%if 0%{?with_kmsro}
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%{_libdir}/dri/armada-drm_dri.so
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%{_libdir}/dri/exynos_dri.so
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%{_libdir}/dri/hdlcd_dri.so
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%{_libdir}/dri/hx8357d_dri.so
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%{_libdir}/dri/ili9225_dri.so
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%{_libdir}/dri/ili9341_dri.so
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@ -571,6 +568,9 @@ done
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%endif
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%changelog
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* Tue Dec 19 2023 zhangpan <zhangpan103@h-partners.com> - 23.3.1-1
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- upgrade to mesa-23.3.1
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* Thu Nov 02 2023 Jingwiw <wangjingwei@iscas.ac.cn> - 23.2.1-1
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- upgrade to version 23.2.1
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- fix llvmpipe interface support for the new version
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