117 lines
3.5 KiB
Diff
117 lines
3.5 KiB
Diff
From b4cc97ac05b70fa328ad57cf6defee8113666cac Mon Sep 17 00:00:00 2001
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From: Alex Fan <alex.fan.q@gmail.com>
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Date: Fri, 29 Jul 2022 12:44:14 +1000
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Subject: [PATCH] llvmpipe: add riscv support in orcjit
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assume cpu supports extension +i,+m,+a,+f,+d,+c
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---
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diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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index 8ea4df7..91dde78 100644
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--- a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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+++ b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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@@ -44,7 +44,7 @@
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/* conflict with ObjectLinkingLayer.h */
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#include "util/u_memory.h"
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-#if (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
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+#if defined(PIPE_ARCH_RISCV64) || defined(PIPE_ARCH_RISCV32) || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
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/* use ObjectLinkingLayer (JITLINK backend) */
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#define USE_JITLINK
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#endif
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@@ -551,6 +551,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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options.StackAlignmentOverride = 4;
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#endif
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+#if defined(PIPE_ARCH_RISCV64)
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+#if defined(__riscv_float_abi_soft)
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+ options.MCOptions.ABIName = "lp64";
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+#elif defined(__riscv_float_abi_single)
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+ options.MCOptions.ABIName = "lp64f";
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+#elif defined(__riscv_float_abi_double)
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+ options.MCOptions.ABIName = "lp64d";
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+#else
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+#error "GALLIVM: unknown target riscv float abi"
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+#endif
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+#endif
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+
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+#if defined(PIPE_ARCH_RISCV32)
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+#if defined(__riscv_float_abi_soft)
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+ options.MCOptions.ABIName = "ilp32";
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+#elif defined(__riscv_float_abi_single)
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+ options.MCOptions.ABIName = "ilp32f";
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+#elif defined(__riscv_float_abi_double)
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+ options.MCOptions.ABIName = "ilp32d";
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+#else
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+#error "GALLIVM: unknown target riscv float abi"
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+#endif
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+#endif
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+
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JTMB.setOptions(options);
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std::vector<std::string> MAttrs;
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@@ -649,6 +673,14 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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MAttrs.push_back("+fp64");
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#endif
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+#if defined(PIPE_ARCH_RISCV64)
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+ /* Before riscv is more matured and util_get_cpu_caps() is implemented,
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+ * assume this for now since most of linux capable riscv machine are
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+ * riscv64gc
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+ */
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+ MAttrs = {"+m","+c","+a","+d","+f"};
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+#endif
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+
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JTMB.addFeatures(MAttrs);
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if (::gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
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@@ -716,6 +748,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
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#endif
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+#if defined(PIPE_ARCH_RISCV64)
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+ /**
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+ * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
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+ * set it anyway for llvm 14
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+ */
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+ if (MCPU == "generic")
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+ MCPU = "generic-rv64";
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+
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+ JTMB.setCodeModel(CodeModel::Medium);
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+ JTMB.setRelocationModel(Reloc::PIC_);
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+#endif
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+
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+#if defined(PIPE_ARCH_RISCV32)
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+ /**
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+ * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
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+ * set it anyway for llvm 14
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+ */
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+ if (MCPU == "generic")
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+ MCPU = "generic-rv32";
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+
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+ JTMB.setCodeModel(CodeModel::Medium);
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+ JTMB.setRelocationModel(Reloc::PIC_);
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+#endif
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+
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JTMB.setCPU(MCPU);
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if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
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debug_printf("llc -mcpu option: %s\n", MCPU.c_str());
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diff --git a/src/util/detect_arch.h b/src/util/detect_arch.h
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index 334358f..8c7bd15 100644
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--- a/src/util/detect_arch.h
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+++ b/src/util/detect_arch.h
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@@ -137,4 +137,14 @@
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#define DETECT_ARCH_MIPS 0
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#endif
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+#if defined(__riscv)
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+#if __riscv_xlen == 64
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+#define PIPE_ARCH_RISCV64
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+#elif __riscv_xlen == 32
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+#define PIPE_ARCH_RISCV32
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+#else
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+#error "pipe: unknown target riscv xlen"
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+#endif
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+#endif
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+
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#endif /* UTIL_DETECT_ARCH_H_ */
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