veega2022
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1295d6c317
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add hikptool sas/sata features source code
add support hikptool sas/sata dfx cmd
Signed-off-by: nifujia <nifujia1@hisilicon.com>
Signed-off-by: veega2022 <zhuweijia@huawei.com>
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2022-10-28 16:19:00 +08:00 |
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openeuler-ci-bot
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5d554c72ca
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!4 上传pcie、roce、roh、cxl、serdes、socip特性源码
From: @veega2022
Reviewed-by: @chenjunxin1992
Signed-off-by: @kongzizaixian
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2022-10-28 07:17:12 +00:00 |
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veega2022
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46da047b4f
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add hikptool roce/roh/cxl/serdes/socip/pcie features source code
add support hikptool roce/roh/cxl/serdes/socip/pcie dfx cmd
Signed-off-by: veega2022 <zhuweijia@huawei.com>
Signed-off-by: shushengming <shushengming1@huawei.com>
Signed-off-by: wangkang <wangkang124@hisilicon.com>
Signed-off-by: fangjian <f.fangjian@huawei.com>
Signed-off-by: hesiyuan <hesiyuan4@huawei.com>
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2022-10-28 10:52:32 +08:00 |
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openeuler-ci-bot
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73468dcfe1
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!1 初始hikptool仓库，新增spec文件和第一版源码
From: @veega2022
Reviewed-by: @kongzizaixian
Signed-off-by: @kongzizaixian
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2022-10-14 06:03:44 +00:00 |
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veega2022
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4d5465ee95
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init repo with spec and source code
first add hikptool spec and source code, first version is 1.0.0
Signed-off-by: veega2022 <zhuweijia@huawei.com>
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2022-10-13 19:18:48 +08:00 |
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openeuler-ci-bot
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ef391f2c26
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Initial commit
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2022-10-12 02:05:10 +00:00 |
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