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!143 [sync] PR-136: Enable Intel AVX512_FP16 instructions

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From: @openeuler-sync-bot 
Reviewed-by: @eastb233 
Signed-off-by: @eastb233
This commit is contained in:
openeuler-ci-bot 2022-09-07 01:25:27 +00:00 committed by Gitee
commit e1fb11784d
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GPG Key ID: 173E9B9CA92EEF8F
30 changed files with 130189 additions and 1 deletions
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155
0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch Normal file
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@ -0,0 +1,155 @@
From 154b353f689cad41ed9455088b3dede30d9f2e00 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Wed, 14 Jul 2021 14:17:48 -0700
Subject: [PATCH] x86: Add int1 as one byte opcode 0xf1
Also change the x86 disassembler to disassemble 0xf1 as int1, instead of
icebp.
gas/
PR gas/28088
* testsuite/gas/i386/opcode.s: Add int1.
* testsuite/gas/i386/x86-64-opcode.s: Add int1, int3 and int.
* testsuite/gas/i386/opcode-intel.d: Updated.
* testsuite/gas/i386/opcode-suffix.d: Likewise.
* testsuite/gas/i386/opcode.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
opcodes/
PR gas/28088
* i386-dis.c (dis386): Replace icebp with int1.
* i386-opc.tbl: Add int1.
* i386-tbl.h: Regenerate.
diff --git a/gas/testsuite/gas/i386/opcode-intel.d b/gas/testsuite/gas/i386/opcode-intel.d
index 68e1e8810e6..732b033c916 100644
--- a/gas/testsuite/gas/i386/opcode-intel.d
+++ b/gas/testsuite/gas/i386/opcode-intel.d
@@ -588,6 +588,7 @@ Disassembly of section .text:
*[0-9a-f]+: 85 c3 [ ]*test[ ]+ebx,eax
*[0-9a-f]+: 85 d8 [ ]*test[ ]+eax,ebx
*[0-9a-f]+: 85 18 [ ]*test[ ]+(DWORD PTR )?\[eax\],ebx
+ *[0-9a-f]+: f1[ ]+int1[ ]+
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp edx,DWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp edx,DWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp dx,WORD PTR \[eax-0x6f6f6f70\]
diff --git a/gas/testsuite/gas/i386/opcode-suffix.d b/gas/testsuite/gas/i386/opcode-suffix.d
index 8d7716b6fa8..6a9c4cd8717 100644
--- a/gas/testsuite/gas/i386/opcode-suffix.d
+++ b/gas/testsuite/gas/i386/opcode-suffix.d
@@ -588,6 +588,7 @@ Disassembly of section .text:
*[0-9a-f]+: 85 c3 [ ]*testl[ ]+%eax,%ebx
*[0-9a-f]+: 85 d8 [ ]*testl[ ]+%ebx,%eax
*[0-9a-f]+: 85 18 [ ]*testl[ ]+%ebx,\(%eax\)
+ *[0-9a-f]+: f1[ ]+int1[ ]+
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovpl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnpl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovpw -0x6f6f6f70\(%eax\),%dx
diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d
index cc57b9edb80..9c1f67f5fd1 100644
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -587,6 +587,7 @@ Disassembly of section .text:
9f5: 85 c3 [ ]*test %eax,%ebx
9f7: 85 d8 [ ]*test %ebx,%eax
9f9: 85 18 [ ]*test %ebx,\(%eax\)
+ 9fb: f1 [ ]*int1
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%dx
diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s
index 1f803c38e5d..d3255f2b80c 100644
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -585,6 +585,8 @@ foo:
test %ebx,%eax
test (%eax),%ebx
+ int1
+
cmovpe 0x90909090(%eax),%edx
cmovpo 0x90909090(%eax),%edx
cmovpe 0x90909090(%eax),%dx
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
index ab55d2ca350..c925938fdc4 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -325,6 +325,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f 07 sysretq *
[ ]*[a-f0-9]+: 0f 01 f8 swapgs
[ ]*[a-f0-9]+: 66 68 22 22 pushw \$0x2222
+[ ]*[a-f0-9]+: f1 int1 +
+[ ]*[a-f0-9]+: cc int3 +
+[ ]*[a-f0-9]+: cd 90 int \$0x90
[ ]*[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl
[ ]*[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx
[ ]*[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s
index 28c100f812e..6575cc33438 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -454,6 +454,10 @@
pushw $0x2222
+ int1
+ int3
+ int $0x90
+
.byte 0xf6, 0xc9, 0x01
.byte 0x66, 0xf7, 0xc9, 0x02, 0x00
.byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 21e40850544..122f4af0b46 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1965,7 +1965,7 @@ static const struct dis386 dis386[] = {
{ "outG", { indirDX, zAX }, 0 },
/* f0 */
{ Bad_Opcode }, /* lock prefix */
- { "icebp", { XX }, 0 },
+ { "int1", { XX }, 0 },
{ Bad_Opcode }, /* repne */
{ Bad_Opcode }, /* repz */
{ "hlt", { XX }, 0 },
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index b0530e5fb82..49e72d28b56 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -537,6 +537,7 @@ bts, 0xfba, 5, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8, Reg
// See gas/config/tc-i386.c for conversion of 'int $3' into the special
// int 3 insn.
int, 0xcd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
+int1, 0xf1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
int3, 0xcc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
into, 0xce, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
iret, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, {}
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index df139ba6121..15c0b47a915 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -5229,6 +5229,19 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0 } } } },
+ { "int1", 0xf1, None, 0,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0 } },
+ { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0 } } } },
{ "int3", 0xcc, None, 0,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
--
2.33.0

255
0002-x86-drop-OP_Mask.patch Normal file
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@ -0,0 +1,255 @@
From d0579d4d1c724b524da43ad164ce140218497ead Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:01:09 +0200
Subject: [PATCH] x86: drop OP_Mask()
By moving its vex.r check there it becomes fully redundant with OP_G().
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 50a11f417ad..2ed8f6730c5 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -151,9 +151,9 @@
},
/* PREFIX_EVEX_0FC2 */
{
- { "vcmppX", { XMask, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
+ { "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
{ VEX_W_TABLE (EVEX_W_0FC2_P_1) },
- { "vcmppX", { XMask, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
+ { "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
{ VEX_W_TABLE (EVEX_W_0FC2_P_3) },
},
/* PREFIX_EVEX_0FE6 */
@@ -238,14 +238,14 @@
/* PREFIX_EVEX_0F3826 */
{
{ Bad_Opcode },
- { "vptestnm%BW", { XMask, Vex, EXx }, 0 },
- { "vptestm%BW", { XMask, Vex, EXx }, 0 },
+ { "vptestnm%BW", { MaskG, Vex, EXx }, 0 },
+ { "vptestm%BW", { MaskG, Vex, EXx }, 0 },
},
/* PREFIX_EVEX_0F3827 */
{
{ Bad_Opcode },
- { "vptestnm%DQ", { XMask, Vex, EXx }, 0 },
- { "vptestm%DQ", { XMask, Vex, EXx }, 0 },
+ { "vptestnm%DQ", { MaskG, Vex, EXx }, 0 },
+ { "vptestm%DQ", { MaskG, Vex, EXx }, 0 },
},
/* PREFIX_EVEX_0F3828 */
{
@@ -256,7 +256,7 @@
/* PREFIX_EVEX_0F3829 */
{
{ Bad_Opcode },
- { "vpmov%BW2m", { XMask, EXx }, 0 },
+ { "vpmov%BW2m", { MaskG, EXx }, 0 },
{ VEX_W_TABLE (EVEX_W_0F3829_P_2) },
},
/* PREFIX_EVEX_0F382A */
@@ -310,7 +310,7 @@
/* PREFIX_EVEX_0F3839 */
{
{ Bad_Opcode },
- { "vpmov%DQ2m", { XMask, EXx }, 0 },
+ { "vpmov%DQ2m", { MaskG, EXx }, 0 },
{ "vpmins%DQ", { XM, Vex, EXx }, 0 },
},
/* PREFIX_EVEX_0F383A */
@@ -338,7 +338,7 @@
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vp2intersect%DQ", { XMask, Vex, EXx, EXxEVexS }, 0 },
+ { "vp2intersect%DQ", { MaskG, Vex, EXx, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F3872 */
{
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index 637ab846562..2c7d9bc2e34 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -142,7 +142,7 @@
},
/* EVEX_W_0F66 */
{
- { "vpcmpgtd", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtd", { MaskG, Vex, EXx }, PREFIX_DATA },
},
/* EVEX_W_0F6A */
{
@@ -201,7 +201,7 @@
},
/* EVEX_W_0F76 */
{
- { "vpcmpeqd", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpeqd", { MaskG, Vex, EXx }, PREFIX_DATA },
},
/* EVEX_W_0F78_P_0 */
{
@@ -270,12 +270,12 @@
},
/* EVEX_W_0FC2_P_1 */
{
- { "vcmpss", { XMask, VexScalar, EXxmm_md, EXxEVexS, CMP }, 0 },
+ { "vcmpss", { MaskG, VexScalar, EXxmm_md, EXxEVexS, CMP }, 0 },
},
/* EVEX_W_0FC2_P_3 */
{
{ Bad_Opcode },
- { "vcmpsd", { XMask, VexScalar, EXxmm_mq, EXxEVexS, CMP }, 0 },
+ { "vcmpsd", { MaskG, VexScalar, EXxmm_mq, EXxEVexS, CMP }, 0 },
},
/* EVEX_W_0FD2 */
{
@@ -450,7 +450,7 @@
/* EVEX_W_0F3829_P_2 */
{
{ Bad_Opcode },
- { "vpcmpeqq", { XMask, Vex, EXx }, 0 },
+ { "vpcmpeqq", { MaskG, Vex, EXx }, 0 },
},
/* EVEX_W_0F382A_P_1 */
{
@@ -496,7 +496,7 @@
/* EVEX_W_0F3837 */
{
{ Bad_Opcode },
- { "vpcmpgtq", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtq", { MaskG, Vex, EXx }, PREFIX_DATA },
},
/* EVEX_W_0F383A_P_1 */
{
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 151f61d95a4..5f1ebaded85 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -114,8 +114,8 @@ static const struct dis386 evex_table[][256] = {
{ "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
{ VEX_W_TABLE (EVEX_W_0F62) },
{ "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
- { "vpcmpgtb", { XMask, Vex, EXx }, PREFIX_DATA },
- { "vpcmpgtw", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtb", { MaskG, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtw", { MaskG, Vex, EXx }, PREFIX_DATA },
{ VEX_W_TABLE (EVEX_W_0F66) },
{ "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
/* 68 */
@@ -132,8 +132,8 @@ static const struct dis386 evex_table[][256] = {
{ REG_TABLE (REG_EVEX_0F71) },
{ REG_TABLE (REG_EVEX_0F72) },
{ REG_TABLE (REG_EVEX_0F73) },
- { "vpcmpeqb", { XMask, Vex, EXx }, PREFIX_DATA },
- { "vpcmpeqw", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpeqb", { MaskG, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpeqw", { MaskG, Vex, EXx }, PREFIX_DATA },
{ VEX_W_TABLE (EVEX_W_0F76) },
{ Bad_Opcode },
/* 78 */
@@ -453,7 +453,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ "vperm%BW", { XM, Vex, EXx }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpshufbitqmb", { XMask, Vex, EXx }, PREFIX_DATA },
+ { "vpshufbitqmb", { MaskG, Vex, EXx }, PREFIX_DATA },
/* 90 */
{ "vpgatherd%DQ", { XMGatherD, MVexVSIBDWpX }, PREFIX_DATA },
{ "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
@@ -617,8 +617,8 @@ static const struct dis386 evex_table[][256] = {
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A1B) },
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F3A1D) },
- { "vpcmpu%DQ", { XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
- { "vpcmp%DQ", { XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
+ { "vpcmpu%DQ", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
+ { "vpcmp%DQ", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
/* 20 */
{ VEX_LEN_TABLE (VEX_LEN_0F3A20) },
{ VEX_W_TABLE (EVEX_W_0F3A21) },
@@ -653,8 +653,8 @@ static const struct dis386 evex_table[][256] = {
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A3B) },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmpu%BW", { XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
- { "vpcmp%BW", { XMask, Vex, EXx, VPCMP }, PREFIX_DATA },
+ { "vpcmpu%BW", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
+ { "vpcmp%BW", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
/* 40 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -698,8 +698,8 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfpclassp%XW%XZ", { XMask, EXx, Ib }, PREFIX_DATA },
- { "vfpclasss%XW", { XMask, EXVexWdqScalar, Ib }, PREFIX_DATA },
+ { "vfpclassp%XW%XZ", { MaskG, EXx, Ib }, PREFIX_DATA },
+ { "vfpclasss%XW", { MaskG, EXVexWdqScalar, Ib }, PREFIX_DATA },
/* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 122f4af0b46..f88276ced6b 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -116,8 +116,6 @@ static void FXSAVE_Fixup (int, int);
static void MOVSXD_Fixup (int, int);
-static void OP_Mask (int, int);
-
struct dis_private {
/* Points to first byte not fetched. */
bfd_byte *max_fetched;
@@ -406,7 +404,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
#define EXxEVexS { OP_Rounding, evex_sae_mode }
-#define XMask { OP_Mask, mask_mode }
#define MaskG { OP_G, mask_mode }
#define MaskE { OP_E, mask_mode }
#define MaskBDE { OP_E, mask_bd_mode }
@@ -12017,12 +12014,12 @@ OP_G (int bytemode, int sizeflag)
break;
case mask_bd_mode:
case mask_mode:
- if ((modrm.reg + add) > 0x7)
+ if (add || (vex.evex && !vex.r))
{
oappend ("(bad)");
return;
}
- oappend (names_mask[modrm.reg + add]);
+ oappend (names_mask[modrm.reg]);
break;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
@@ -13720,23 +13717,6 @@ MOVSXD_Fixup (int bytemode, int sizeflag)
OP_E (bytemode, sizeflag);
}
-static void
-OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
-{
- if (!vex.evex
- || (bytemode != mask_mode && bytemode != mask_bd_mode))
- abort ();
-
- USED_REX (REX_R);
- if ((rex & REX_R) != 0 || !vex.r)
- {
- BadOp ();
- return;
- }
-
- oappend (names_mask [modrm.reg]);
-}
-
static void
OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
--
2.33.0

173
0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch Normal file
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@ -0,0 +1,173 @@
From be2f8fcd9df7d50fd17125eccecf7fc0bad6b2c8 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:02:08 +0200
Subject: [PATCH] x86: correct VCVT{,U}SI2SD rounding mode handling
With EVEX.W clear the instruction doesn't ignore the rounding mode, but
(like for other insns without rounding semantics) EVEX.b set causes #UD.
Hence the handling of EVEX.W needs to be done when processing
evex_rounding_64_mode, not at the decode stages.
Derive a new 64-bit testcase from the 32-bit one to cover the different
EVEX.W treatment in both cases.
diff --git a/gas/testsuite/gas/i386/evex.d b/gas/testsuite/gas/i386/evex.d
index 2fbe295b86b..b02bca39098 100644
--- a/gas/testsuite/gas/i386/evex.d
+++ b/gas/testsuite/gas/i386/evex.d
@@ -1,5 +1,5 @@
#objdump: -dw -Msuffix
-#name: i386 EVX insns
+#name: i386 EVEX insns
.*: +file format .*
@@ -8,9 +8,12 @@ Disassembly of section .text:
0+ <_start>:
+[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sdl %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sdl %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ssl %eax,%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
#pass
diff --git a/gas/testsuite/gas/i386/evex.s b/gas/testsuite/gas/i386/evex.s
index a64cc573dcd..90c635a27b6 100644
--- a/gas/testsuite/gas/i386/evex.s
+++ b/gas/testsuite/gas/i386/evex.s
@@ -4,8 +4,11 @@
.text
_start:
.byte 0x62, 0xf1, 0xd6, 0x38, 0x2a, 0xf0
+ .byte 0x62, 0xf1, 0x57, 0x38, 0x2a, 0xf0
.byte 0x62, 0xf1, 0xd7, 0x38, 0x2a, 0xf0
.byte 0x62, 0xf1, 0xd6, 0x08, 0x7b, 0xf0
+ .byte 0x62, 0xf1, 0x57, 0x08, 0x7b, 0xf0
.byte 0x62, 0xf1, 0xd7, 0x08, 0x7b, 0xf0
.byte 0x62, 0xf1, 0xd6, 0x38, 0x7b, 0xf0
+ .byte 0x62, 0xf1, 0x57, 0x38, 0x7b, 0xf0
.byte 0x62, 0xf1, 0xd7, 0x38, 0x7b, 0xf0
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 1e0a363a803..6f9543eec3a 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -929,6 +929,7 @@ if [gas_64_check] then {
run_dump_test "x86-64-avx512er-intel"
run_dump_test "x86-64-avx512pf"
run_dump_test "x86-64-avx512pf-intel"
+ run_dump_test "x86-64-evex"
run_dump_test "x86-64-evex-lig256"
run_dump_test "x86-64-evex-lig512"
run_dump_test "x86-64-evex-lig256-intel"
diff --git a/gas/testsuite/gas/i386/x86-64-evex.d b/gas/testsuite/gas/i386/x86-64-evex.d
new file mode 100644
index 00000000000..b360aa74a17
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-evex.d
@@ -0,0 +1,20 @@
+#objdump: -dw
+#name: x86-64 EVEX insns
+#source: evex.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ss %rax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sd %eax,\(bad\),%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sd %rax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ss %rax,%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sd %rax,%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ss %rax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd %eax,\(bad\),%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sd %rax,\{rd-sae\},%xmm5,%xmm6
+#pass
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 2ed8f6730c5..9ad9372a221 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -30,7 +30,7 @@
{ Bad_Opcode },
{ "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_0F2A_P_3) },
+ { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
},
/* PREFIX_EVEX_0F51 */
{
@@ -134,7 +134,7 @@
{ Bad_Opcode },
{ "vcvtusi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ VEX_W_TABLE (EVEX_W_0F7B_P_2) },
- { VEX_W_TABLE (EVEX_W_0F7B_P_3) },
+ { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
},
/* PREFIX_EVEX_0F7E */
{
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index 2c7d9bc2e34..8af4695a004 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -37,11 +37,6 @@
{
{ "vmovshdup", { XM, EXx }, 0 },
},
- /* EVEX_W_0F2A_P_3 */
- {
- { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Ed }, 0 },
- { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
- },
/* EVEX_W_0F51_P_1 */
{
{ "vsqrtss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
@@ -243,11 +238,6 @@
{ "vcvtps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 },
{ "vcvtpd2qq", { XM, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_0F7B_P_3 */
- {
- { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, Ed }, 0 },
- { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
- },
/* EVEX_W_0F7E_P_1 */
{
{ Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f88276ced6b..ccc49ff023f 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1476,7 +1476,6 @@ enum
EVEX_W_0F12_P_3,
EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1,
- EVEX_W_0F2A_P_3,
EVEX_W_0F51_P_1,
EVEX_W_0F51_P_3,
EVEX_W_0F58_P_1,
@@ -1521,7 +1520,6 @@ enum
EVEX_W_0F7A_P_2,
EVEX_W_0F7A_P_3,
EVEX_W_0F7B_P_2,
- EVEX_W_0F7B_P_3,
EVEX_W_0F7E_P_1,
EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2,
@@ -13724,7 +13722,7 @@ OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
switch (bytemode)
{
case evex_rounding_64_mode:
- if (address_mode != mode_64bit)
+ if (address_mode != mode_64bit || !vex.w)
{
oappend ("(bad)");
break;
--
2.33.0

70
0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch Normal file
View File

@ -0,0 +1,70 @@
From 3fa77affb00ef5d9bcb7f080750625749cdfa611 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:02:54 +0200
Subject: [PATCH] x86-64: generalize OP_G()'s EVEX.R' handling
EVEX.R' is invalid to be clear not only for mask registers, but also for
GPRs - IOW everything handled in this function.
diff --git a/gas/testsuite/gas/i386/evex.d b/gas/testsuite/gas/i386/evex.d
index b02bca39098..367b2eb1321 100644
--- a/gas/testsuite/gas/i386/evex.d
+++ b/gas/testsuite/gas/i386/evex.d
@@ -16,4 +16,6 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
+[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
+ +[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,%eax
+ +[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,%k0
#pass
diff --git a/gas/testsuite/gas/i386/evex.s b/gas/testsuite/gas/i386/evex.s
index 90c635a27b6..ff6cb43499b 100644
--- a/gas/testsuite/gas/i386/evex.s
+++ b/gas/testsuite/gas/i386/evex.s
@@ -12,3 +12,5 @@ _start:
.byte 0x62, 0xf1, 0xd6, 0x38, 0x7b, 0xf0
.byte 0x62, 0xf1, 0x57, 0x38, 0x7b, 0xf0
.byte 0x62, 0xf1, 0xd7, 0x38, 0x7b, 0xf0
+ .byte 0x62, 0xe1, 0x7e, 0x08, 0x2d, 0xc0
+ .byte 0x62, 0xe1, 0x7c, 0x08, 0xc2, 0xc0, 0x00
diff --git a/gas/testsuite/gas/i386/x86-64-evex.d b/gas/testsuite/gas/i386/x86-64-evex.d
index b360aa74a17..3a7b48e0bf9 100644
--- a/gas/testsuite/gas/i386/x86-64-evex.d
+++ b/gas/testsuite/gas/i386/x86-64-evex.d
@@ -17,4 +17,6 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ss %rax,\{rd-sae\},%xmm5,%xmm6
+[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd %eax,\(bad\),%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sd %rax,\{rd-sae\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,\(bad\)
+ +[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,\(bad\)
#pass
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index ccc49ff023f..e95d2ef9d64 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11934,6 +11934,13 @@ OP_G (int bytemode, int sizeflag)
{
int add = 0;
const char **names;
+
+ if (vex.evex && !vex.r && address_mode == mode_64bit)
+ {
+ oappend ("(bad)");
+ return;
+ }
+
USED_REX (REX_R);
if (rex & REX_R)
add += 8;
@@ -12012,7 +12019,7 @@ OP_G (int bytemode, int sizeflag)
break;
case mask_bd_mode:
case mask_mode:
- if (add || (vex.evex && !vex.r))
+ if (add)
{
oappend ("(bad)");
return;
--
2.33.0

61
0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch Normal file
View File

@ -0,0 +1,61 @@
From bac11f2cfe7913ef4c37af608454451e27f78eff Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:03:16 +0200
Subject: [PATCH] x86-64: properly bounds-check %bnd<N> in OP_G()
The restriction to %bnd0-%bnd3 requires to also check REX.R is clear,
just like OP_E_Register() also includes REX.B in its check.
diff --git a/gas/testsuite/gas/i386/x86-64-mpx.d b/gas/testsuite/gas/i386/x86-64-mpx.d
index f3217e07016..2f45af0d6e4 100644
--- a/gas/testsuite/gas/i386/x86-64-mpx.d
+++ b/gas/testsuite/gas/i386/x86-64-mpx.d
@@ -191,5 +191,7 @@ Disassembly of section .text:
[a-f0-9]+ <bad>:
[ ]*[a-f0-9]+: 0f 1a 30 bndldx \(%rax\),\(bad\)
[ ]*[a-f0-9]+: 66 0f 1a c4 bndmov \(bad\),%bnd0
+[ ]*[a-f0-9]+: 66 41 0f 1a c0 bndmov \(bad\),%bnd0
+[ ]*[a-f0-9]+: 66 44 0f 1a c0 bndmov %bnd0,\(bad\)
[ ]*[a-f0-9]+: f3 0f 1b 05 90 90 90 90 bndmk \(bad\),%bnd0
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-mpx.s b/gas/testsuite/gas/i386/x86-64-mpx.s
index b113590cf76..3594d8e9c88 100644
--- a/gas/testsuite/gas/i386/x86-64-mpx.s
+++ b/gas/testsuite/gas/i386/x86-64-mpx.s
@@ -227,6 +227,20 @@ bad:
.byte 0x1a
.byte 0xc4
+ # bndmov with REX.B set
+ .byte 0x66
+ .byte 0x41
+ .byte 0x0f
+ .byte 0x1a
+ .byte 0xc0
+
+ # bndmov with REX.R set
+ .byte 0x66
+ .byte 0x44
+ .byte 0x0f
+ .byte 0x1a
+ .byte 0xc0
+
# bndmk (bad),%bnd0
.byte 0xf3
.byte 0x0f
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index e95d2ef9d64..203dcefa360 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11966,7 +11966,7 @@ OP_G (int bytemode, int sizeflag)
oappend (names64[modrm.reg + add]);
break;
case bnd_mode:
- if (modrm.reg > 0x3)
+ if (modrm.reg + add > 0x3)
{
oappend ("(bad)");
return;
--
2.33.0

183
0006-x86-fold-duplicate-register-printing-code.patch Normal file
View File

@ -0,0 +1,183 @@
From 5f6b8397a40ca30460464e115c6aed8b7b6679f8 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:03:37 +0200
Subject: [PATCH] x86: fold duplicate register printing code
What so far was OP_E_register() can be easily reused also for OP_G().
Add suitable parameters to the function and move the invocation of
swap_operand() to OP_E(). Adjust MOVSXD's first operand: There never was
a need to use movsxd_mode there, and its use gets in the way of the code
folding.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 203dcefa360..725b38b1dda 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -50,7 +50,6 @@ static void oappend (const char *);
static void append_seg (void);
static void OP_indirE (int, int);
static void print_operand_value (char *, int, bfd_vma);
-static void OP_E_register (int, int);
static void OP_E_memory (int, int);
static void print_displacement (char *, bfd_vma);
static void OP_E (int, int);
@@ -4180,7 +4179,7 @@ static const struct dis386 x86_64_table[][2] = {
/* X86_64_63 */
{
{ "arpl", { Ew, Gw }, 0 },
- { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
+ { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
},
/* X86_64_6D */
@@ -11290,21 +11289,14 @@ intel_operand_size (int bytemode, int sizeflag)
}
static void
-OP_E_register (int bytemode, int sizeflag)
+print_register (unsigned int reg, unsigned int rexmask, int bytemode, int sizeflag)
{
- int reg = modrm.rm;
const char **names;
- USED_REX (REX_B);
- if ((rex & REX_B))
+ USED_REX (rexmask);
+ if (rex & rexmask)
reg += 8;
- if ((sizeflag & SUFFIX_ALWAYS)
- && (bytemode == b_swap_mode
- || bytemode == bnd_swap_mode
- || bytemode == v_swap_mode))
- swap_operand ();
-
switch (bytemode)
{
case b_mode:
@@ -11924,7 +11916,15 @@ OP_E (int bytemode, int sizeflag)
codep++;
if (modrm.mod == 3)
- OP_E_register (bytemode, sizeflag);
+ {
+ if ((sizeflag & SUFFIX_ALWAYS)
+ && (bytemode == b_swap_mode
+ || bytemode == bnd_swap_mode
+ || bytemode == v_swap_mode))
+ swap_operand ();
+
+ print_register (modrm.rm, REX_B, bytemode, sizeflag);
+ }
else
OP_E_memory (bytemode, sizeflag);
}
@@ -11932,104 +11932,13 @@ OP_E (int bytemode, int sizeflag)
static void
OP_G (int bytemode, int sizeflag)
{
- int add = 0;
- const char **names;
-
if (vex.evex && !vex.r && address_mode == mode_64bit)
{
oappend ("(bad)");
return;
}
- USED_REX (REX_R);
- if (rex & REX_R)
- add += 8;
- switch (bytemode)
- {
- case b_mode:
- if (modrm.reg & 4)
- USED_REX (0);
- if (rex)
- oappend (names8rex[modrm.reg + add]);
- else
- oappend (names8[modrm.reg + add]);
- break;
- case w_mode:
- oappend (names16[modrm.reg + add]);
- break;
- case d_mode:
- case db_mode:
- case dw_mode:
- oappend (names32[modrm.reg + add]);
- break;
- case q_mode:
- oappend (names64[modrm.reg + add]);
- break;
- case bnd_mode:
- if (modrm.reg + add > 0x3)
- {
- oappend ("(bad)");
- return;
- }
- oappend (names_bnd[modrm.reg]);
- break;
- case v_mode:
- case dq_mode:
- case dqb_mode:
- case dqd_mode:
- case dqw_mode:
- case movsxd_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- oappend (names64[modrm.reg + add]);
- else if (bytemode != v_mode && bytemode != movsxd_mode)
- oappend (names32[modrm.reg + add]);
- else
- {
- if (sizeflag & DFLAG)
- oappend (names32[modrm.reg + add]);
- else
- oappend (names16[modrm.reg + add]);
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case va_mode:
- names = (address_mode == mode_64bit
- ? names64 : names32);
- if (!(prefixes & PREFIX_ADDR))
- {
- if (address_mode == mode_16bit)
- names = names16;
- }
- else
- {
- /* Remove "addr16/addr32". */
- all_prefixes[last_addr_prefix] = 0;
- names = (address_mode != mode_32bit
- ? names32 : names16);
- used_prefixes |= PREFIX_ADDR;
- }
- oappend (names[modrm.reg + add]);
- break;
- case m_mode:
- if (address_mode == mode_64bit)
- oappend (names64[modrm.reg + add]);
- else
- oappend (names32[modrm.reg + add]);
- break;
- case mask_bd_mode:
- case mask_mode:
- if (add)
- {
- oappend ("(bad)");
- return;
- }
- oappend (names_mask[modrm.reg]);
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- break;
- }
+ print_register (modrm.reg, REX_R, bytemode, sizeflag);
}
static bfd_vma
--
2.33.0

56
0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch Normal file
View File

@ -0,0 +1,56 @@
From 4454883ff0ee338b1f6aab7f65ab1081af307e7c Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:03:53 +0200
Subject: [PATCH] x86: fold duplicate code in MOVSXD_Fixup()
There's no need to have two paths printing the "xd" mnemonic suffix.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 725b38b1dda..ddb659fb041 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -13601,31 +13601,25 @@ MOVSXD_Fixup (int bytemode, int sizeflag)
switch (bytemode)
{
case movsxd_mode:
- if (intel_syntax)
+ if (!intel_syntax)
{
- *p++ = 'x';
- *p++ = 'd';
- goto skip;
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ {
+ *p++ = 'l';
+ *p++ = 'q';
+ break;
+ }
}
- USED_REX (REX_W);
- if (rex & REX_W)
- {
- *p++ = 'l';
- *p++ = 'q';
- }
- else
- {
- *p++ = 'x';
- *p++ = 'd';
- }
+ *p++ = 'x';
+ *p++ = 'd';
break;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
break;
}
- skip:
mnemonicendp = p;
*p = '\0';
OP_E (bytemode, sizeflag);
--
2.33.0

79
0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch Normal file
View File

@ -0,0 +1,79 @@
From 54ca11a48eba11788445247b16bc77637e3aa84a Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:07:27 +0200
Subject: [PATCH] x86: correct EVEX.V' handling outside of 64-bit mode
Unlike the high bit of VEX.vvvv / EVEX.vvvv, EVEX.V' is not ignored
outside of 64-bit mode. Oddly enough there already are tests for these
cases, but their expectations were wrong. (This may have been based on
an old SDM version, where the restriction wasn't properly spelled out.)
diff --git a/gas/testsuite/gas/i386/noextreg.d b/gas/testsuite/gas/i386/noextreg.d
index 08bad494a80..ba175fc001e 100644
--- a/gas/testsuite/gas/i386/noextreg.d
+++ b/gas/testsuite/gas/i386/noextreg.d
@@ -13,14 +13,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f1 7d 08 db c0 vpandd %xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 d1 7d 08 db c0 vpandd %xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 f1 3d 08 db c0 vpandd %xmm0,%xmm0,%xmm0
-[ ]*[a-f0-9]+: 62 f1 7d 00 db c0 vpandd %xmm0,%xmm0,%xmm0
+[ ]*[a-f0-9]+: 62 f1 7d 00 db c0 vpandd %xmm0,\(bad\),%xmm0
[ ]*[a-f0-9]+: c4 e3 79 4c c0 00 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: c4 c3 79 4c c0 00 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: c4 e3 39 4c c0 00 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: c4 e3 79 4c c0 80 vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 f2 7d 0f 90 0c 00 vpgatherdd \(%eax,%xmm0,1\),%xmm1\{%k7\}
[ ]*[a-f0-9]+: 62 d2 7d 0f 90 0c 00 vpgatherdd \(%eax,%xmm0,1\),%xmm1\{%k7\}
-[ ]*[a-f0-9]+: 62 f2 7d 07 90 0c 00 vpgatherdd \(%eax,%xmm0,1\),%xmm1\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 7d 07 90 0c 00 vpgatherdd \(%eax,\(bad\),1\),%xmm1\{%k7\}
[ ]*[a-f0-9]+: c4 e2 78 f2 00 andn \(%eax\),%eax,%eax
[ ]*[a-f0-9]+: c4 e2 38 f2 00 andn \(%eax\),%eax,%eax
[ ]*[a-f0-9]+: c4 c2 78 f2 00 andn \(%eax\),%eax,%eax
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index ddb659fb041..267d58d535e 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -9316,7 +9316,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
/* In 16/32-bit mode silently ignore following bits. */
rex &= ~REX_B;
vex.r = 1;
- vex.v = 1;
}
need_vex = 1;
@@ -11718,8 +11717,13 @@ OP_E_memory (int bytemode, int sizeflag)
*obufp = '\0';
}
if (haveindex)
- oappend (address_mode == mode_64bit && !addr32flag
- ? indexes64[vindex] : indexes32[vindex]);
+ {
+ if (address_mode == mode_64bit || vindex < 16)
+ oappend (address_mode == mode_64bit && !addr32flag
+ ? indexes64[vindex] : indexes32[vindex]);
+ else
+ oappend ("(bad)");
+ }
else
oappend (address_mode == mode_64bit && !addr32flag
? index64 : index32);
@@ -13256,7 +13260,15 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
reg = vex.register_specifier;
vex.register_specifier = 0;
if (address_mode != mode_64bit)
- reg &= 7;
+ {
+ if (vex.evex && !vex.v)
+ {
+ oappend ("(bad)");
+ return;
+ }
+
+ reg &= 7;
+ }
else if (vex.evex && !vex.v)
reg += 16;
--
2.33.0

74
0009-x86-drop-vex_mode-and-vex_scalar_mode.patch Normal file
View File

@ -0,0 +1,74 @@
From 605228fcaf91a86b5ae898415374a9382c85f76f Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:07:42 +0200
Subject: [PATCH] x86: drop vex_mode and vex_scalar_mode
These are fully redundant with, respectively, x_mode and scalar_mode.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 267d58d535e..20bf9b282c9 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -384,10 +384,10 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define XMM0 { XMM_Fixup, 0 }
#define FXSAVE { FXSAVE_Fixup, 0 }
-#define Vex { OP_VEX, vex_mode }
-#define VexW { OP_VexW, vex_mode }
-#define VexScalar { OP_VEX, vex_scalar_mode }
-#define VexScalarR { OP_VexR, vex_scalar_mode }
+#define Vex { OP_VEX, x_mode }
+#define VexW { OP_VexW, x_mode }
+#define VexScalar { OP_VEX, scalar_mode }
+#define VexScalarR { OP_VexR, scalar_mode }
#define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
#define VexGdq { OP_VEX, dq_mode }
@@ -546,8 +546,6 @@ enum
dw_mode,
/* registers like dq_mode, memory like d_mode. */
dqd_mode,
- /* normal vex mode */
- vex_mode,
/* Operand size depends on the VEX.W bit, with VSIB dword indices. */
vex_vsib_d_w_dq_mode,
@@ -558,8 +556,6 @@ enum
/* scalar, ignore vector length. */
scalar_mode,
- /* like vex_mode, ignore vector length. */
- vex_scalar_mode,
/* Operand size depends on the VEX.W bit, ignore vector length. */
vex_scalar_w_dq_mode,
@@ -13274,7 +13270,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
switch (bytemode)
{
- case vex_scalar_mode:
+ case scalar_mode:
oappend (names_xmm[reg]);
return;
@@ -13343,7 +13339,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
case 128:
switch (bytemode)
{
- case vex_mode:
+ case x_mode:
names = names_xmm;
break;
case dq_mode:
@@ -13369,7 +13365,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
case 256:
switch (bytemode)
{
- case vex_mode:
+ case x_mode:
names = names_ymm;
break;
case mask_bd_mode:
--
2.33.0

168
0010-x86-fold-duplicate-vector-register-printing-code.patch Normal file
View File

@ -0,0 +1,168 @@
From b0556968af05310748d7a1286b8d7639de67831e Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:08:05 +0200
Subject: [PATCH] x86: fold duplicate vector register printing code
The bulk of OP_XMM() can be easily reused also for OP_EX(). Break the
shared logic out of the function, and invoke the new helper from both
places.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 20bf9b282c9..e750c94704a 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -12530,20 +12530,10 @@ OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
}
static void
-OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+print_vector_reg (unsigned int reg, int bytemode)
{
- int reg = modrm.reg;
const char **names;
- USED_REX (REX_R);
- if (rex & REX_R)
- reg += 8;
- if (vex.evex)
- {
- if (!vex.r)
- reg += 16;
- }
-
if (bytemode == xmmq_mode
|| bytemode == evex_half_bcst_xmmq_mode)
{
@@ -12564,7 +12554,6 @@ OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
names = names_ymm;
else if (bytemode == tmm_mode)
{
- modrm.reg = reg;
if (reg >= 8)
{
oappend ("(bad)");
@@ -12574,7 +12563,14 @@ OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
}
else if (need_vex
&& bytemode != xmm_mode
- && bytemode != scalar_mode)
+ && bytemode != scalar_mode
+ && bytemode != xmmdw_mode
+ && bytemode != xmmqd_mode
+ && bytemode != xmm_mb_mode
+ && bytemode != xmm_mw_mode
+ && bytemode != xmm_md_mode
+ && bytemode != xmm_mq_mode
+ && bytemode != vex_scalar_w_dq_mode)
{
switch (vex.length)
{
@@ -12604,6 +12600,26 @@ OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
oappend (names[reg]);
}
+static void
+OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+{
+ unsigned int reg = modrm.reg;
+
+ USED_REX (REX_R);
+ if (rex & REX_R)
+ reg += 8;
+ if (vex.evex)
+ {
+ if (!vex.r)
+ reg += 16;
+ }
+
+ if (bytemode == tmm_mode)
+ modrm.reg = reg;
+
+ print_vector_reg (reg, bytemode);
+}
+
static void
OP_EM (int bytemode, int sizeflag)
{
@@ -12679,7 +12695,6 @@ static void
OP_EX (int bytemode, int sizeflag)
{
int reg;
- const char **names;
/* Skip mod/rm byte. */
MODRM_CHECK;
@@ -12708,66 +12723,10 @@ OP_EX (int bytemode, int sizeflag)
|| bytemode == q_swap_mode))
swap_operand ();
- if (need_vex
- && bytemode != xmm_mode
- && bytemode != xmmdw_mode
- && bytemode != xmmqd_mode
- && bytemode != xmm_mb_mode
- && bytemode != xmm_mw_mode
- && bytemode != xmm_md_mode
- && bytemode != xmm_mq_mode
- && bytemode != xmmq_mode
- && bytemode != evex_half_bcst_xmmq_mode
- && bytemode != ymm_mode
- && bytemode != tmm_mode
- && bytemode != vex_scalar_w_dq_mode)
- {
- switch (vex.length)
- {
- case 128:
- names = names_xmm;
- break;
- case 256:
- names = names_ymm;
- break;
- case 512:
- names = names_zmm;
- break;
- default:
- abort ();
- }
- }
- else if (bytemode == xmmq_mode
- || bytemode == evex_half_bcst_xmmq_mode)
- {
- switch (vex.length)
- {
- case 128:
- case 256:
- names = names_xmm;
- break;
- case 512:
- names = names_ymm;
- break;
- default:
- abort ();
- }
- }
- else if (bytemode == tmm_mode)
- {
- modrm.rm = reg;
- if (reg >= 8)
- {
- oappend ("(bad)");
- return;
- }
- names = names_tmm;
- }
- else if (bytemode == ymm_mode)
- names = names_ymm;
- else
- names = names_xmm;
- oappend (names[reg]);
+ if (bytemode == tmm_mode)
+ modrm.rm = reg;
+
+ print_vector_reg (reg, bytemode);
}
static void
--
2.33.0

664
0011-x86-drop-xmm_m-b-w-d-q-_mode.patch Normal file
View File

@ -0,0 +1,664 @@
From c1d66d5f24eb54a6453b3a813cbc7a7e0b5d15fe Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:08:39 +0200
Subject: [PATCH] x86: drop xmm_m{b,w,d,q}_mode
They're effectively redundant with {b,w,d,q}_mode.
diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h
index a1cd69a1c9e..7a372ce8c0b 100644
--- a/opcodes/i386-dis-evex-mod.h
+++ b/opcodes/i386-dis-evex-mod.h
@@ -1,28 +1,28 @@
{
/* MOD_EVEX_0F12_PREFIX_0 */
- { "vmovlpX", { XMM, Vex, EXxmm_mq }, PREFIX_OPCODE },
+ { "vmovlpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
{ VEX_W_TABLE (EVEX_W_0F12_P_0_M_1) },
},
{
/* MOD_EVEX_0F12_PREFIX_2 */
- { "vmovlpX", { XMM, Vex, EXxmm_mq }, PREFIX_OPCODE },
+ { "vmovlpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
},
{
/* MOD_EVEX_0F13 */
- { "vmovlpX", { EXxmm_mq, XMM }, PREFIX_OPCODE },
+ { "vmovlpX", { EXq, XMM }, PREFIX_OPCODE },
},
{
/* MOD_EVEX_0F16_PREFIX_0 */
- { "vmovhpX", { XMM, Vex, EXxmm_mq }, PREFIX_OPCODE },
+ { "vmovhpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
{ VEX_W_TABLE (EVEX_W_0F16_P_0_M_1) },
},
{
/* MOD_EVEX_0F16_PREFIX_2 */
- { "vmovhpX", { XMM, Vex, EXxmm_mq }, PREFIX_OPCODE },
+ { "vmovhpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
},
{
/* MOD_EVEX_0F17 */
- { "vmovhpX", { EXxmm_mq, XMM }, PREFIX_OPCODE },
+ { "vmovhpX", { EXq, XMM }, PREFIX_OPCODE },
},
{
/* MOD_EVEX_0F2B */
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 9ad9372a221..417eb1bfbff 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -111,16 +111,16 @@
/* PREFIX_EVEX_0F78 */
{
{ VEX_W_TABLE (EVEX_W_0F78_P_0) },
- { "vcvttss2usi", { Gdq, EXxmm_md, EXxEVexS }, 0 },
+ { "vcvttss2usi", { Gdq, EXd, EXxEVexS }, 0 },
{ VEX_W_TABLE (EVEX_W_0F78_P_2) },
- { "vcvttsd2usi", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
+ { "vcvttsd2usi", { Gdq, EXq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F79 */
{
{ VEX_W_TABLE (EVEX_W_0F79_P_0) },
- { "vcvtss2usi", { Gdq, EXxmm_md, EXxEVexR }, 0 },
+ { "vcvtss2usi", { Gdq, EXd, EXxEVexR }, 0 },
{ VEX_W_TABLE (EVEX_W_0F79_P_2) },
- { "vcvtsd2usi", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
+ { "vcvtsd2usi", { Gdq, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F7A */
{
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index 8af4695a004..cb27d96d30d 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -1,11 +1,11 @@
/* EVEX_W_0F10_P_1 */
{
- { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
+ { "vmovss", { XMScalar, VexScalarR, EXd }, 0 },
},
/* EVEX_W_0F10_P_3 */
{
{ Bad_Opcode },
- { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
+ { "vmovsd", { XMScalar, VexScalarR, EXq }, 0 },
},
/* EVEX_W_0F11_P_1 */
{
@@ -18,7 +18,7 @@
},
/* EVEX_W_0F12_P_0_M_1 */
{
- { "vmovhlps", { XMM, Vex, EXxmm_mq }, 0 },
+ { "vmovhlps", { XMM, Vex, EXq }, 0 },
},
/* EVEX_W_0F12_P_1 */
{
@@ -39,30 +39,30 @@
},
/* EVEX_W_0F51_P_1 */
{
- { "vsqrtss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
+ { "vsqrtss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
},
/* EVEX_W_0F51_P_3 */
{
{ Bad_Opcode },
- { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vsqrtsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F58_P_1 */
{
- { "vaddss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
+ { "vaddss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
},
/* EVEX_W_0F58_P_3 */
{
{ Bad_Opcode },
- { "vaddsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vaddsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F59_P_1 */
{
- { "vmulss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
+ { "vmulss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
},
/* EVEX_W_0F59_P_3 */
{
{ Bad_Opcode },
- { "vmulsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vmulsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F5A_P_0 */
{
@@ -70,7 +70,7 @@
},
/* EVEX_W_0F5A_P_1 */
{
- { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md, EXxEVexS }, 0 },
+ { "vcvtss2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
},
/* EVEX_W_0F5A_P_2 */
{
@@ -80,7 +80,7 @@
/* EVEX_W_0F5A_P_3 */
{
{ Bad_Opcode },
- { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F5B_P_0 */
{
@@ -97,39 +97,39 @@
},
/* EVEX_W_0F5C_P_1 */
{
- { "vsubss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
+ { "vsubss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
},
/* EVEX_W_0F5C_P_3 */
{
{ Bad_Opcode },
- { "vsubsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vsubsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F5D_P_1 */
{
- { "vminss", { XMScalar, VexScalar, EXxmm_md, EXxEVexS }, 0 },
+ { "vminss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
},
/* EVEX_W_0F5D_P_3 */
{
{ Bad_Opcode },
- { "vminsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS }, 0 },
+ { "vminsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* EVEX_W_0F5E_P_1 */
{
- { "vdivss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
+ { "vdivss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
},
/* EVEX_W_0F5E_P_3 */
{
{ Bad_Opcode },
- { "vdivsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexR }, 0 },
+ { "vdivsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* EVEX_W_0F5F_P_1 */
{
- { "vmaxss", { XMScalar, VexScalar, EXxmm_md, EXxEVexS }, 0 },
+ { "vmaxss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
},
/* EVEX_W_0F5F_P_3 */
{
{ Bad_Opcode },
- { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS }, 0 },
+ { "vmaxsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* EVEX_W_0F62 */
{
@@ -260,12 +260,12 @@
},
/* EVEX_W_0FC2_P_1 */
{
- { "vcmpss", { MaskG, VexScalar, EXxmm_md, EXxEVexS, CMP }, 0 },
+ { "vcmpss", { MaskG, VexScalar, EXd, EXxEVexS, CMP }, 0 },
},
/* EVEX_W_0FC2_P_3 */
{
{ Bad_Opcode },
- { "vcmpsd", { MaskG, VexScalar, EXxmm_mq, EXxEVexS, CMP }, 0 },
+ { "vcmpsd", { MaskG, VexScalar, EXq, EXxEVexS, CMP }, 0 },
},
/* EVEX_W_0FD2 */
{
@@ -382,8 +382,8 @@
},
/* EVEX_W_0F3819_L_n */
{
- { "vbroadcastf32x2", { XM, EXxmm_mq }, PREFIX_DATA },
- { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
+ { "vbroadcastf32x2", { XM, EXq }, PREFIX_DATA },
+ { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
},
/* EVEX_W_0F381A_M_0_L_n */
{
@@ -499,8 +499,8 @@
},
/* EVEX_W_0F3859 */
{
- { "vbroadcasti32x2", { XM, EXxmm_mq }, PREFIX_DATA },
- { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
+ { "vbroadcasti32x2", { XM, EXq }, PREFIX_DATA },
+ { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
},
/* EVEX_W_0F385A_M_0_L_n */
{
@@ -561,12 +561,12 @@
},
/* EVEX_W_0F3A0A */
{
- { "vrndscaless", { XMScalar, VexScalar, EXxmm_md, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vrndscaless", { XMScalar, VexScalar, EXd, EXxEVexS, Ib }, PREFIX_DATA },
},
/* EVEX_W_0F3A0B */
{
{ Bad_Opcode },
- { "vrndscalesd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vrndscalesd", { XMScalar, VexScalar, EXq, EXxEVexS, Ib }, PREFIX_DATA },
},
/* EVEX_W_0F3A18_L_n */
{
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index e750c94704a..27b6b8e8f44 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -352,6 +352,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define EMd { OP_EM, d_mode }
#define EMx { OP_EM, x_mode }
#define EXbwUnit { OP_EX, bw_unit_mode }
+#define EXb { OP_EX, b_mode }
#define EXw { OP_EX, w_mode }
#define EXd { OP_EX, d_mode }
#define EXdS { OP_EX, d_swap_mode }
@@ -364,10 +365,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define EXtmm { OP_EX, tmm_mode }
#define EXxmmq { OP_EX, xmmq_mode }
#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
-#define EXxmm_mb { OP_EX, xmm_mb_mode }
-#define EXxmm_mw { OP_EX, xmm_mw_mode }
-#define EXxmm_md { OP_EX, xmm_md_mode }
-#define EXxmm_mq { OP_EX, xmm_mq_mode }
#define EXxmmdw { OP_EX, xmmdw_mode }
#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
@@ -488,14 +485,6 @@ enum
xmmq_mode,
/* Same as xmmq_mode, but broadcast is allowed. */
evex_half_bcst_xmmq_mode,
- /* XMM register or byte memory operand */
- xmm_mb_mode,
- /* XMM register or word memory operand */
- xmm_mw_mode,
- /* XMM register or double word memory operand */
- xmm_md_mode,
- /* XMM register or quad word memory operand */
- xmm_mq_mode,
/* 16-byte XMM, word, double word or quad word operand. */
xmmdw_mode,
/* 16-byte XMM, double word, quad word operand or xmm word operand. */
@@ -3610,9 +3599,9 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_VEX_0F10 */
{
{ "vmovups", { XM, EXx }, 0 },
- { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
+ { "vmovss", { XMScalar, VexScalarR, EXd }, 0 },
{ "vmovupd", { XM, EXx }, 0 },
- { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
+ { "vmovsd", { XMScalar, VexScalarR, EXq }, 0 },
},
/* PREFIX_VEX_0F11 */
@@ -3649,31 +3638,31 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_VEX_0F2C */
{
{ Bad_Opcode },
- { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
+ { "vcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
{ Bad_Opcode },
- { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
+ { "vcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
},
/* PREFIX_VEX_0F2D */
{
{ Bad_Opcode },
- { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
+ { "vcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
{ Bad_Opcode },
- { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
+ { "vcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F2E */
{
- { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
+ { "vucomisX", { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
+ { "vucomisX", { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
},
/* PREFIX_VEX_0F2F */
{
- { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
+ { "vcomisX", { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
+ { "vcomisX", { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
},
/* PREFIX_VEX_0F41_L_1_M_1_W_0 */
@@ -3789,45 +3778,45 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_VEX_0F51 */
{
{ "vsqrtps", { XM, EXx }, 0 },
- { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vsqrtss", { XMScalar, VexScalar, EXd }, 0 },
{ "vsqrtpd", { XM, EXx }, 0 },
- { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vsqrtsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F52 */
{
{ "vrsqrtps", { XM, EXx }, 0 },
- { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
},
/* PREFIX_VEX_0F53 */
{
{ "vrcpps", { XM, EXx }, 0 },
- { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vrcpss", { XMScalar, VexScalar, EXd }, 0 },
},
/* PREFIX_VEX_0F58 */
{
{ "vaddps", { XM, Vex, EXx }, 0 },
- { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vaddss", { XMScalar, VexScalar, EXd }, 0 },
{ "vaddpd", { XM, Vex, EXx }, 0 },
- { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vaddsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F59 */
{
{ "vmulps", { XM, Vex, EXx }, 0 },
- { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vmulss", { XMScalar, VexScalar, EXd }, 0 },
{ "vmulpd", { XM, Vex, EXx }, 0 },
- { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vmulsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F5A */
{
{ "vcvtps2pd", { XM, EXxmmq }, 0 },
- { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vcvtss2sd", { XMScalar, VexScalar, EXd }, 0 },
{ "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
- { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F5B */
@@ -3840,33 +3829,33 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_VEX_0F5C */
{
{ "vsubps", { XM, Vex, EXx }, 0 },
- { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vsubss", { XMScalar, VexScalar, EXd }, 0 },
{ "vsubpd", { XM, Vex, EXx }, 0 },
- { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vsubsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F5D */
{
{ "vminps", { XM, Vex, EXx }, 0 },
- { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vminss", { XMScalar, VexScalar, EXd }, 0 },
{ "vminpd", { XM, Vex, EXx }, 0 },
- { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vminsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F5E */
{
{ "vdivps", { XM, Vex, EXx }, 0 },
- { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vdivss", { XMScalar, VexScalar, EXd }, 0 },
{ "vdivpd", { XM, Vex, EXx }, 0 },
- { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vdivsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F5F */
{
{ "vmaxps", { XM, Vex, EXx }, 0 },
- { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vmaxss", { XMScalar, VexScalar, EXd }, 0 },
{ "vmaxpd", { XM, Vex, EXx }, 0 },
- { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
+ { "vmaxsd", { XMScalar, VexScalar, EXq }, 0 },
},
/* PREFIX_VEX_0F6F */
@@ -4005,9 +3994,9 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_VEX_0FC2 */
{
{ "vcmpps", { XM, Vex, EXx, CMP }, 0 },
- { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
+ { "vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
{ "vcmppd", { XM, Vex, EXx, CMP }, 0 },
- { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
+ { "vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
},
/* PREFIX_VEX_0FD0 */
@@ -6441,8 +6430,8 @@ static const struct dis386 vex_table[][256] = {
/* 08 */
{ "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
{ "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
- { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
- { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
+ { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
+ { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
{ "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
@@ -6549,12 +6538,12 @@ static const struct dis386 vex_table[][256] = {
/* 68 */
{ "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
{ "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
- { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
- { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
{ "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
{ "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
- { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
- { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
/* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -6567,12 +6556,12 @@ static const struct dis386 vex_table[][256] = {
/* 78 */
{ "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
{ "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
- { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
- { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
{ "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
{ "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
- { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
- { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
/* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -6813,7 +6802,7 @@ static const struct dis386 vex_len_table[][2] = {
/* VEX_LEN_0F7E_P_1 */
{
- { "vmovq", { XMScalar, EXxmm_mq }, 0 },
+ { "vmovq", { XMScalar, EXq }, 0 },
},
/* VEX_LEN_0F7E_P_2 */
@@ -7533,11 +7522,11 @@ static const struct dis386 vex_w_table[][2] = {
},
{
/* VEX_W_0F3818 */
- { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
+ { "vbroadcastss", { XM, EXd }, PREFIX_DATA },
},
{
/* VEX_W_0F3819_L_1 */
- { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
+ { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
},
{
/* VEX_W_0F381A_M_0_L_1 */
@@ -7609,11 +7598,11 @@ static const struct dis386 vex_w_table[][2] = {
},
{
/* VEX_W_0F3858 */
- { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
+ { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
},
{
/* VEX_W_0F3859 */
- { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
+ { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
},
{
/* VEX_W_0F385A_M_0_L_0 */
@@ -7641,11 +7630,11 @@ static const struct dis386 vex_w_table[][2] = {
},
{
/* VEX_W_0F3878 */
- { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
+ { "vpbroadcastb", { XM, EXb }, PREFIX_DATA },
},
{
/* VEX_W_0F3879 */
- { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
+ { "vpbroadcastw", { XM, EXw }, PREFIX_DATA },
},
{
/* VEX_W_0F38CF */
@@ -11107,66 +11096,6 @@ intel_operand_size (int bytemode, int sizeflag)
abort ();
}
break;
- case xmm_mb_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("BYTE PTR ");
- break;
- default:
- abort ();
- }
- break;
- case xmm_mw_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("WORD PTR ");
- break;
- default:
- abort ();
- }
- break;
- case xmm_md_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("DWORD PTR ");
- break;
- default:
- abort ();
- }
- break;
- case xmm_mq_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- case 512:
- oappend ("QWORD PTR ");
- break;
- default:
- abort ();
- }
- break;
case xmmdw_mode:
if (!need_vex)
abort ();
@@ -11424,19 +11353,18 @@ OP_E_memory (int bytemode, int sizeflag)
{
case dqw_mode:
case dw_mode:
- case xmm_mw_mode:
+ case w_mode:
shift = 1;
break;
case dqb_mode:
case db_mode:
- case xmm_mb_mode:
+ case b_mode:
shift = 0;
break;
case dq_mode:
if (address_mode != mode_64bit)
{
case dqd_mode:
- case xmm_md_mode:
case d_mode:
case d_swap_mode:
shift = 2;
@@ -11493,7 +11421,6 @@ OP_E_memory (int bytemode, int sizeflag)
case xmm_mode:
shift = 4;
break;
- case xmm_mq_mode:
case q_mode:
case q_swap_mode:
shift = 3;
@@ -12566,10 +12493,10 @@ print_vector_reg (unsigned int reg, int bytemode)
&& bytemode != scalar_mode
&& bytemode != xmmdw_mode
&& bytemode != xmmqd_mode
- && bytemode != xmm_mb_mode
- && bytemode != xmm_mw_mode
- && bytemode != xmm_md_mode
- && bytemode != xmm_mq_mode
+ && bytemode != b_mode
+ && bytemode != w_mode
+ && bytemode != d_mode
+ && bytemode != q_mode
&& bytemode != vex_scalar_w_dq_mode)
{
switch (vex.length)
--
2.33.0

302
0012-x86-drop-vex_scalar_w_dq_mode.patch Normal file
View File

@ -0,0 +1,302 @@
From eb34d29be8766b7466becebdd94e8121e88a44d4 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:09:03 +0200
Subject: [PATCH] x86: drop vex_scalar_w_dq_mode
It has only a single use and can easily be represented by dq_mode
instead. Plus its handling in intel_operand_size() was duplicating
that of vex_vsib_{d,q}_w_dq_mode anyway.
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 417eb1bfbff..5c24618bec4 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -358,7 +358,7 @@
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
+ { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
{ "v4fmaddss", { XMScalar, VexScalar, Mxmm }, 0 },
},
/* PREFIX_EVEX_0F38AA */
@@ -372,6 +372,6 @@
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
+ { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
{ "v4fnmaddss", { XMScalar, VexScalar, Mxmm }, 0 },
},
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 5f1ebaded85..287c7a84635 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -343,7 +343,7 @@ static const struct dis386 evex_table[][256] = {
{ PREFIX_TABLE (PREFIX_EVEX_0F382A) },
{ VEX_W_TABLE (EVEX_W_0F382B) },
{ "vscalefp%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vscalefs%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vscalefs%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
/* 30 */
@@ -368,7 +368,7 @@ static const struct dis386 evex_table[][256] = {
{ "vpmull%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ Bad_Opcode },
{ "vgetexpp%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
- { "vgetexps%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS }, PREFIX_DATA },
+ { "vgetexps%XW", { XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
{ "vplzcnt%DQ", { XM, EXx }, PREFIX_DATA },
{ "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpsrav%DQ", { XM, Vex, EXx }, PREFIX_DATA },
@@ -379,9 +379,9 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ "vrcp14p%XW", { XM, EXx }, PREFIX_DATA },
- { "vrcp14s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vrcp14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vrsqrt14p%XW", { XM, EXx }, 0 },
- { "vrsqrt14s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vrsqrt14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
/* 50 */
{ "vpdpbusd", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpdpbusds", { XM, Vex, EXx }, PREFIX_DATA },
@@ -465,13 +465,13 @@ static const struct dis386 evex_table[][256] = {
{ "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
/* 98 */
{ "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ PREFIX_TABLE (PREFIX_EVEX_0F389A) },
{ PREFIX_TABLE (PREFIX_EVEX_0F389B) },
{ "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
/* A0 */
{ "vpscatterd%DQ", { MVexVSIBDWpX, XM }, PREFIX_DATA },
{ "vpscatterq%DQ", { MVexVSIBQWpX, XMGatherQ }, PREFIX_DATA },
@@ -483,13 +483,13 @@ static const struct dis386 evex_table[][256] = {
{ "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
/* A8 */
{ "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ PREFIX_TABLE (PREFIX_EVEX_0F38AA) },
{ PREFIX_TABLE (PREFIX_EVEX_0F38AB) },
{ "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -501,13 +501,13 @@ static const struct dis386 evex_table[][256] = {
{ "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
/* B8 */
{ "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
/* C0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -521,9 +521,9 @@ static const struct dis386 evex_table[][256] = {
{ "vexp2p%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
{ Bad_Opcode },
{ "vrcp28p%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
- { "vrcp28s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS }, PREFIX_DATA },
+ { "vrcp28s%XW", { XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
{ "vrsqrt28p%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
- { "vrsqrt28s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS }, PREFIX_DATA },
+ { "vrsqrt28s%XW", { XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F38CF) },
/* D0 */
@@ -627,7 +627,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ "vpternlog%DQ", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ "vgetmantp%XW", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- { "vgetmants%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vgetmants%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, PREFIX_DATA },
/* 28 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -675,13 +675,13 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
/* 50 */
{ "vrangep%XW", { XM, Vex, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- { "vranges%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vranges%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ "vfixupimmp%XW", { XM, Vex, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- { "vfixupimms%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vfixupimms%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, PREFIX_DATA },
{ "vreducep%XW", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- { "vreduces%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexS, Ib }, PREFIX_DATA },
+ { "vreduces%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, PREFIX_DATA },
/* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -699,7 +699,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ "vfpclassp%XW%XZ", { MaskG, EXx, Ib }, PREFIX_DATA },
- { "vfpclasss%XW", { MaskG, EXVexWdqScalar, Ib }, PREFIX_DATA },
+ { "vfpclasss%XW", { MaskG, EXdq, Ib }, PREFIX_DATA },
/* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 27b6b8e8f44..6efc15b851b 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -358,6 +358,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define EXdS { OP_EX, d_swap_mode }
#define EXq { OP_EX, q_mode }
#define EXqS { OP_EX, q_swap_mode }
+#define EXdq { OP_EX, dq_mode }
#define EXx { OP_EX, x_mode }
#define EXxS { OP_EX, x_swap_mode }
#define EXxmm { OP_EX, xmm_mode }
@@ -368,7 +369,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define EXxmmdw { OP_EX, xmmdw_mode }
#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
-#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
#define MS { OP_MS, v_mode }
@@ -507,7 +507,7 @@ enum
v_bnd_mode,
/* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
v_bndmk_mode,
- /* operand size depends on REX prefixes. */
+ /* operand size depends on REX.W / VEX.W. */
dq_mode,
/* registers like dq_mode, memory like w_mode, displacements like
v_mode without considering Intel64 ISA. */
@@ -545,8 +545,6 @@ enum
/* scalar, ignore vector length. */
scalar_mode,
- /* Operand size depends on the VEX.W bit, ignore vector length. */
- vex_scalar_w_dq_mode,
/* Static rounding. */
evex_rounding_mode,
@@ -6300,13 +6298,13 @@ static const struct dis386 vex_table[][256] = {
{ "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
/* 98 */
{ "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
/* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -6318,13 +6316,13 @@ static const struct dis386 vex_table[][256] = {
{ "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
/* a8 */
{ "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
/* b0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -6336,13 +6334,13 @@ static const struct dis386 vex_table[][256] = {
{ "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
/* b8 */
{ "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
- { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
/* c0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -11170,15 +11168,6 @@ intel_operand_size (int bytemode, int sizeflag)
case o_mode:
oappend ("OWORD PTR ");
break;
- case vex_scalar_w_dq_mode:
- if (!need_vex)
- abort ();
-
- if (vex.w)
- oappend ("QWORD PTR ");
- else
- oappend ("DWORD PTR ");
- break;
case vex_vsib_d_w_dq_mode:
case vex_vsib_q_w_dq_mode:
if (!need_vex)
@@ -11371,7 +11360,6 @@ OP_E_memory (int bytemode, int sizeflag)
break;
}
/* fall through */
- case vex_scalar_w_dq_mode:
case vex_vsib_d_w_dq_mode:
case vex_vsib_q_w_dq_mode:
case evex_x_gscat_mode:
@@ -12496,8 +12484,7 @@ print_vector_reg (unsigned int reg, int bytemode)
&& bytemode != b_mode
&& bytemode != w_mode
&& bytemode != d_mode
- && bytemode != q_mode
- && bytemode != vex_scalar_w_dq_mode)
+ && bytemode != q_mode)
{
switch (vex.length)
{
@@ -12627,6 +12614,9 @@ OP_EX (int bytemode, int sizeflag)
MODRM_CHECK;
codep++;
+ if (bytemode == dq_mode)
+ bytemode = vex.w ? q_mode : d_mode;
+
if (modrm.mod != 3)
{
OP_E_memory (bytemode, sizeflag);
--
2.33.0

528
0013-x86-drop-dq-b-d-_mode.patch Normal file
View File

@ -0,0 +1,528 @@
From 5fbe0f28ae6dec9736e504cf79cdb76a9fa09dc9 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Thu, 22 Jul 2021 13:09:21 +0200
Subject: [PATCH] x86: drop dq{b,d}_mode
Their sole use is for {,V}EXTRACTPS / {,V}P{EXT,INS}RB respectively; for
consistency also limit use of dqw_mode to Jdqw. 64-bit disassembly
reflecting REX.W / VEX.W is not in line with the assembler's opcode
table having NoRex64 / VexWIG in all respective templates, i.e. assembly
input isn't being honored there either. Obviously the 0FC5 encodings of
{,V}PEXTRW then also need adjustment for consistency reasons.
diff --git a/gas/testsuite/gas/i386/x86-64-avx-wig.d b/gas/testsuite/gas/i386/x86-64-avx-wig.d
index 14edfb3de7d..2144746bdf0 100644
--- a/gas/testsuite/gas/i386/x86-64-avx-wig.d
+++ b/gas/testsuite/gas/i386/x86-64-avx-wig.d
@@ -58,7 +58,7 @@ Disassembly of section .text:
+[a-f0-9]+: c4 e1 ca 5e d4 vdivss %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e3 c9 41 d4 07 vdppd \$0x7,%xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e3 cd 40 d4 07 vdpps \$0x7,%ymm4,%ymm6,%ymm2
- +[a-f0-9]+: c4 e3 f9 17 e1 07 vextractps \$0x7,%xmm4,%rcx
+ +[a-f0-9]+: c4 e3 f9 17 e1 07 vextractps \$0x7,%xmm4,%ecx
+[a-f0-9]+: c4 e1 cd 7c d4 vhaddpd %ymm4,%ymm6,%ymm2
+[a-f0-9]+: c4 e1 cf 7c d4 vhaddps %ymm4,%ymm6,%ymm2
+[a-f0-9]+: c4 e1 cd 7d d4 vhsubpd %ymm4,%ymm6,%ymm2
@@ -157,10 +157,10 @@ Disassembly of section .text:
+[a-f0-9]+: c4 e1 c9 65 d4 vpcmpgtw %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e3 f9 63 f4 07 vpcmpistri \$0x7,%xmm4,%xmm6
+[a-f0-9]+: c4 e3 f9 62 f4 07 vpcmpistrm \$0x7,%xmm4,%xmm6
- +[a-f0-9]+: c4 e3 f9 14 c0 00 vpextrb \$0x0,%xmm0,%rax
+ +[a-f0-9]+: c4 e3 f9 14 c0 00 vpextrb \$0x0,%xmm0,%eax
+[a-f0-9]+: c4 e3 f9 14 00 00 vpextrb \$0x0,%xmm0,\(%rax\)
- +[a-f0-9]+: c4 e1 f9 c5 c0 00 vpextrw \$0x0,%xmm0,%rax
- +[a-f0-9]+: c4 e3 f9 15 c0 00 vpextrw \$0x0,%xmm0,%rax
+ +[a-f0-9]+: c4 e1 f9 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+: c4 e3 f9 15 c0 00 vpextrw \$0x0,%xmm0,%eax
+[a-f0-9]+: c4 e3 f9 15 00 00 vpextrw \$0x0,%xmm0,\(%rax\)
+[a-f0-9]+: c4 e2 c9 02 d4 vphaddd %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e2 c9 03 d4 vphaddsw %xmm4,%xmm6,%xmm2
@@ -169,9 +169,9 @@ Disassembly of section .text:
+[a-f0-9]+: c4 e2 c9 06 d4 vphsubd %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e2 c9 07 d4 vphsubsw %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e2 c9 05 d4 vphsubw %xmm4,%xmm6,%xmm2
- +[a-f0-9]+: c4 e3 f9 20 c0 00 vpinsrb \$0x0,%rax,%xmm0,%xmm0
+ +[a-f0-9]+: c4 e3 f9 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
+[a-f0-9]+: c4 e3 f9 20 00 00 vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
- +[a-f0-9]+: c4 e1 f9 c4 c0 00 vpinsrw \$0x0,%rax,%xmm0,%xmm0
+ +[a-f0-9]+: c4 e1 f9 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
+[a-f0-9]+: c4 e1 f9 c4 00 00 vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
+[a-f0-9]+: c4 e2 c9 04 d4 vpmaddubsw %xmm4,%xmm6,%xmm2
+[a-f0-9]+: c4 e1 c9 f5 d4 vpmaddwd %xmm4,%xmm6,%xmm2
diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
index 79b0fdc6a1f..3a1141866aa 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
@@ -159,9 +159,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa 00 20 00 00[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx\+0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 6a 80[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa c0 df ff ff[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2040\]
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb rax,xmm29,0xab
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb rax,xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb r8,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb eax,xmm29,0xab
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb eax,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb r8d,xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 29 7b[ ]*vpextrb BYTE PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 23 fd 08 14 ac f0 23 01 00 00 7b[ ]*vpextrb BYTE PTR \[rax\+r14\*8\+0x123\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 6a 7f 7b[ ]*vpextrb BYTE PTR \[rdx\+0x7f\],xmm29,0x7b
@@ -174,23 +174,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa 00 01 00 00 7b[ ]*vpextrw WORD PTR \[rdx\+0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 6a 80 7b[ ]*vpextrw WORD PTR \[rdx-0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa fe fe ff ff 7b[ ]*vpextrw WORD PTR \[rdx-0x102\],xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw rax,xmm30,0xab
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw rax,xmm30,0x7b
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw r8,xmm30,0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb xmm30,xmm29,rax,0xab
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb xmm30,xmm29,rax,0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,rbp,0x7b
-[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,r13,0x7b
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw eax,xmm30,0xab
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw eax,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw r8d,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb xmm30,xmm29,eax,0xab
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb xmm30,xmm29,eax,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,ebp,0x7b
+[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,r13d,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 31 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rcx\],0x7b
[ ]*[a-f0-9]+:[ ]*62 23 95 00 20 b4 f0 23 01 00 00 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rax\+r14\*8\+0x123\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 7f 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x7f\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 80 00 00 00 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x80\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 80 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x80\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 7f ff ff ff 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x81\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw xmm30,xmm29,rax,0xab
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw xmm30,xmm29,rax,0x7b
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,rbp,0x7b
-[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,r13,0x7b
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw xmm30,xmm29,eax,0xab
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw xmm30,xmm29,eax,0x7b
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,ebp,0x7b
+[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,r13d,0x7b
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 31 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rcx\],0x7b
[ ]*[a-f0-9]+:[ ]*62 21 95 00 c4 b4 f0 23 01 00 00 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rax\+r14\*8\+0x123\],0x7b
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 72 7f 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rdx\+0xfe\],0x7b
@@ -690,9 +690,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa 00 20 00 00[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx\+0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 6a 80[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa c0 df ff ff[ ]*vpcmpgtw k5,zmm30,ZMMWORD PTR \[rdx-0x2040\]
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb rax,xmm29,0xab
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb rax,xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb r8,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb eax,xmm29,0xab
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb eax,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb r8d,xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 29 7b[ ]*vpextrb BYTE PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 23 fd 08 14 ac f0 34 12 00 00 7b[ ]*vpextrb BYTE PTR \[rax\+r14\*8\+0x1234\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 6a 7f 7b[ ]*vpextrb BYTE PTR \[rdx\+0x7f\],xmm29,0x7b
@@ -705,23 +705,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa 00 01 00 00 7b[ ]*vpextrw WORD PTR \[rdx\+0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 6a 80 7b[ ]*vpextrw WORD PTR \[rdx-0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa fe fe ff ff 7b[ ]*vpextrw WORD PTR \[rdx-0x102\],xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw rax,xmm30,0xab
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw rax,xmm30,0x7b
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw r8,xmm30,0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb xmm30,xmm29,rax,0xab
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb xmm30,xmm29,rax,0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,rbp,0x7b
-[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,r13,0x7b
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw eax,xmm30,0xab
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw eax,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw r8d,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb xmm30,xmm29,eax,0xab
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb xmm30,xmm29,eax,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,ebp,0x7b
+[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,r13d,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 31 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rcx\],0x7b
[ ]*[a-f0-9]+:[ ]*62 23 95 00 20 b4 f0 34 12 00 00 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rax\+r14\*8\+0x1234\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 7f 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x7f\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 80 00 00 00 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x80\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 80 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x80\],0x7b
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 7f ff ff ff 7b[ ]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x81\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw xmm30,xmm29,rax,0xab
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw xmm30,xmm29,rax,0x7b
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,rbp,0x7b
-[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,r13,0x7b
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw xmm30,xmm29,eax,0xab
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw xmm30,xmm29,eax,0x7b
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,ebp,0x7b
+[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw xmm30,xmm29,r13d,0x7b
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 31 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rcx\],0x7b
[ ]*[a-f0-9]+:[ ]*62 21 95 00 c4 b4 f0 34 12 00 00 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rax\+r14\*8\+0x1234\],0x7b
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 72 7f 7b[ ]*vpinsrw xmm30,xmm29,WORD PTR \[rdx\+0xfe\],0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
index f48e5e6ff85..d2687009a24 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
@@ -159,9 +159,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa 00 20 00 00[ ]*vpcmpgtw 0x2000\(%rdx\),%zmm30,%k5
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 6a 80[ ]*vpcmpgtw -0x2000\(%rdx\),%zmm30,%k5
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa c0 df ff ff[ ]*vpcmpgtw -0x2040\(%rdx\),%zmm30,%k5
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 29 7b[ ]*vpextrb \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+:[ ]*62 23 fd 08 14 ac f0 23 01 00 00 7b[ ]*vpextrb \$0x7b,%xmm29,0x123\(%rax,%r14,8\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 6a 7f 7b[ ]*vpextrb \$0x7b,%xmm29,0x7f\(%rdx\)
@@ -174,23 +174,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa 00 01 00 00 7b[ ]*vpextrw \$0x7b,%xmm29,0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 6a 80 7b[ ]*vpextrw \$0x7b,%xmm29,-0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa fe fe ff ff 7b[ ]*vpextrw \$0x7b,%xmm29,-0x102\(%rdx\)
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb \$0xab,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb \$0x7b,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%rbp,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%r13,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8d
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb \$0xab,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb \$0x7b,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%ebp,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%r13d,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 31 7b[ ]*vpinsrb \$0x7b,\(%rcx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 23 95 00 20 b4 f0 23 01 00 00 7b[ ]*vpinsrb \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 7f 7b[ ]*vpinsrb \$0x7b,0x7f\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 80 00 00 00 7b[ ]*vpinsrb \$0x7b,0x80\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 80 7b[ ]*vpinsrb \$0x7b,-0x80\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 7f ff ff ff 7b[ ]*vpinsrb \$0x7b,-0x81\(%rdx\),%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw \$0xab,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw \$0x7b,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%rbp,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%r13,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw \$0xab,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw \$0x7b,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%ebp,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%r13d,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 31 7b[ ]*vpinsrw \$0x7b,\(%rcx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 21 95 00 c4 b4 f0 23 01 00 00 7b[ ]*vpinsrw \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 72 7f 7b[ ]*vpinsrw \$0x7b,0xfe\(%rdx\),%xmm29,%xmm30
@@ -690,9 +690,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa 00 20 00 00[ ]*vpcmpgtw 0x2000\(%rdx\),%zmm30,%k5
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 6a 80[ ]*vpcmpgtw -0x2000\(%rdx\),%zmm30,%k5
[ ]*[a-f0-9]+:[ ]*62 f1 8d 40 65 aa c0 df ff ff[ ]*vpcmpgtw -0x2040\(%rdx\),%zmm30,%k5
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 29 7b[ ]*vpextrb \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+:[ ]*62 23 fd 08 14 ac f0 34 12 00 00 7b[ ]*vpextrb \$0x7b,%xmm29,0x1234\(%rax,%r14,8\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 6a 7f 7b[ ]*vpextrb \$0x7b,%xmm29,0x7f\(%rdx\)
@@ -705,23 +705,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa 00 01 00 00 7b[ ]*vpextrw \$0x7b,%xmm29,0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 6a 80 7b[ ]*vpextrw \$0x7b,%xmm29,-0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 aa fe fe ff ff 7b[ ]*vpextrw \$0x7b,%xmm29,-0x102\(%rdx\)
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb \$0xab,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb \$0x7b,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%rbp,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%r13,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8d
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 ab[ ]*vpinsrb \$0xab,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f0 7b[ ]*vpinsrb \$0x7b,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%ebp,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 43 95 00 20 f5 7b[ ]*vpinsrb \$0x7b,%r13d,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 31 7b[ ]*vpinsrb \$0x7b,\(%rcx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 23 95 00 20 b4 f0 34 12 00 00 7b[ ]*vpinsrb \$0x7b,0x1234\(%rax,%r14,8\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 7f 7b[ ]*vpinsrb \$0x7b,0x7f\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 80 00 00 00 7b[ ]*vpinsrb \$0x7b,0x80\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 72 80 7b[ ]*vpinsrb \$0x7b,-0x80\(%rdx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 95 00 20 b2 7f ff ff ff 7b[ ]*vpinsrb \$0x7b,-0x81\(%rdx\),%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw \$0xab,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw \$0x7b,%rax,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%rbp,%xmm29,%xmm30
-[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%r13,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 ab[ ]*vpinsrw \$0xab,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f0 7b[ ]*vpinsrw \$0x7b,%eax,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%ebp,%xmm29,%xmm30
+[ ]*[a-f0-9]+:[ ]*62 41 95 00 c4 f5 7b[ ]*vpinsrw \$0x7b,%r13d,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 31 7b[ ]*vpinsrw \$0x7b,\(%rcx\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 21 95 00 c4 b4 f0 34 12 00 00 7b[ ]*vpinsrw \$0x7b,0x1234\(%rax,%r14,8\),%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 61 95 00 c4 72 7f 7b[ ]*vpinsrw \$0x7b,0xfe\(%rdx\),%xmm29,%xmm30
diff --git a/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d b/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
index f6031f27968..e1abc7ecb35 100644
--- a/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
@@ -9,23 +9,23 @@
Disassembly of section .text:
0+ <_start>:
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps rax,xmm29,0xab
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps rax,xmm29,0x7b
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps eax,xmm29,0xab
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps eax,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8d,xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps DWORD PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 23 01 00 00 7b vextractps DWORD PTR \[rax\+r14\*8\+0x123\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps DWORD PTR \[rdx\+0x200\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps DWORD PTR \[rdx-0x200\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps DWORD PTR \[rdx-0x204\],xmm29,0x7b
-[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb rax,xmm0,0x0
+[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb eax,xmm0,0x0
[ ]*[a-f0-9]+: 62 f3 fd 08 14 00 00 vpextrb BYTE PTR \[rax\],xmm0,0x0
-[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw rax,xmm0,0x0
-[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw rax,xmm0,0x0
+[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw eax,xmm0,0x0
+[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw eax,xmm0,0x0
[ ]*[a-f0-9]+: 62 f3 fd 08 15 00 00 vpextrw WORD PTR \[rax\],xmm0,0x0
-[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb xmm0,xmm0,rax,0x0
+[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb xmm0,xmm0,eax,0x0
[ ]*[a-f0-9]+: 62 f3 fd 08 20 00 00 vpinsrb xmm0,xmm0,BYTE PTR \[rax\],0x0
-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw xmm0,xmm0,rax,0x0
+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw xmm0,xmm0,eax,0x0
[ ]*[a-f0-9]+: 62 f1 fd 08 c4 00 00 vpinsrw xmm0,xmm0,WORD PTR \[rax\],0x0
[ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd zmm30\{k7\},xmm29
[ ]*[a-f0-9]+: 62 02 fd cf 21 f5 vpmovsxbd zmm30\{k7\}\{z\},xmm29
@@ -91,9 +91,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 00 08 00 00 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 80 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps rax,xmm29,0xab
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps rax,xmm29,0x7b
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps eax,xmm29,0xab
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps eax,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8d,xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps DWORD PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 34 12 00 00 7b vextractps DWORD PTR \[rax\+r14\*8\+0x1234\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-evex-wig1.d b/gas/testsuite/gas/i386/x86-64-evex-wig1.d
index 9c49f1c7105..e62e8f4405f 100644
--- a/gas/testsuite/gas/i386/x86-64-evex-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-wig1.d
@@ -9,23 +9,23 @@
Disassembly of section .text:
0+ <_start>:
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 23 01 00 00 7b vextractps \$0x7b,%xmm29,0x123\(%rax,%r14,8\)
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps \$0x7b,%xmm29,0x1fc\(%rdx\)
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps \$0x7b,%xmm29,0x200\(%rdx\)
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps \$0x7b,%xmm29,-0x200\(%rdx\)
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps \$0x7b,%xmm29,-0x204\(%rdx\)
-[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb \$0x0,%xmm0,%rax
+[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb \$0x0,%xmm0,%eax
[ ]*[a-f0-9]+: 62 f3 fd 08 14 00 00 vpextrb \$0x0,%xmm0,\(%rax\)
-[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw \$0x0,%xmm0,%rax
-[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw \$0x0,%xmm0,%rax
+[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
+[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw \$0x0,%xmm0,%eax
[ ]*[a-f0-9]+: 62 f3 fd 08 15 00 00 vpextrw \$0x0,%xmm0,\(%rax\)
-[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb \$0x0,%rax,%xmm0,%xmm0
+[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 f3 fd 08 20 00 00 vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw \$0x0,%rax,%xmm0,%xmm0
+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 f1 fd 08 c4 00 00 vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}
[ ]*[a-f0-9]+: 62 02 fd cf 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}\{z\}
@@ -91,9 +91,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 00 08 00 00 vpmovzxwq 0x800\(%rdx\),%zmm30\{%k7\}
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 80 vpmovzxwq -0x800\(%rdx\),%zmm30\{%k7\}
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq -0x810\(%rdx\),%zmm30\{%k7\}
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 34 12 00 00 7b vextractps \$0x7b,%xmm29,0x1234\(%rax,%r14,8\)
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps \$0x7b,%xmm29,0x1fc\(%rdx\)
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 6efc15b851b..521d6899338 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -240,11 +240,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define EvS { OP_E, v_swap_mode }
#define Ed { OP_E, d_mode }
#define Edq { OP_E, dq_mode }
-#define Edqw { OP_E, dqw_mode }
-#define Edqb { OP_E, dqb_mode }
#define Edb { OP_E, db_mode }
#define Edw { OP_E, dw_mode }
-#define Edqd { OP_E, dqd_mode }
#define Eq { OP_E, q_mode }
#define indirEv { OP_indirE, indir_v_mode }
#define indirEp { OP_indirE, f_mode }
@@ -509,8 +506,7 @@ enum
v_bndmk_mode,
/* operand size depends on REX.W / VEX.W. */
dq_mode,
- /* registers like dq_mode, memory like w_mode, displacements like
- v_mode without considering Intel64 ISA. */
+ /* Displacements like v_mode without considering Intel64 ISA. */
dqw_mode,
/* bounds operand */
bnd_mode,
@@ -527,14 +523,10 @@ enum
z_mode,
/* 16-byte operand */
o_mode,
- /* registers like dq_mode, memory like b_mode. */
- dqb_mode,
/* registers like d_mode, memory like b_mode. */
db_mode,
/* registers like d_mode, memory like w_mode. */
dw_mode,
- /* registers like dq_mode, memory like d_mode. */
- dqd_mode,
/* Operand size depends on the VEX.W bit, with VSIB dword indices. */
vex_vsib_d_w_dq_mode,
@@ -2182,8 +2174,8 @@ static const struct dis386 dis386_twobyte[] = {
{ "xaddS", { Evh1, Gv }, 0 },
{ PREFIX_TABLE (PREFIX_0FC2) },
{ MOD_TABLE (MOD_0FC3) },
- { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
- { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
+ { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
+ { "pextrw", { Gd, MS, Ib }, PREFIX_OPCODE },
{ "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
{ REG_TABLE (REG_0FC7) },
/* c8 */
@@ -4687,10 +4679,10 @@ static const struct dis386 three_byte_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
- { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
+ { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
+ { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
{ "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
- { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
+ { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
/* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -4701,7 +4693,7 @@ static const struct dis386 three_byte_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
- { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
+ { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
{ "insertps", { XM, EXd, Ib }, PREFIX_DATA },
{ "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
{ Bad_Opcode },
@@ -6850,12 +6842,12 @@ static const struct dis386 vex_len_table[][2] = {
/* VEX_LEN_0FC4 */
{
- { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
+ { "vpinsrw", { XM, Vex, Edw, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0FC5 */
{
- { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
+ { "vpextrw", { Gd, XS, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0FD6 */
@@ -7012,12 +7004,12 @@ static const struct dis386 vex_len_table[][2] = {
/* VEX_LEN_0F3A14 */
{
- { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
+ { "vpextrb", { Edb, XM, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A15 */
{
- { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
+ { "vpextrw", { Edw, XM, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A16 */
@@ -7027,7 +7019,7 @@ static const struct dis386 vex_len_table[][2] = {
/* VEX_LEN_0F3A17 */
{
- { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
+ { "vextractps", { Ed, XM, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A18 */
@@ -7044,7 +7036,7 @@ static const struct dis386 vex_len_table[][2] = {
/* VEX_LEN_0F3A20 */
{
- { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
+ { "vpinsrb", { XM, Vex, Edb, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A21 */
@@ -10957,13 +10949,11 @@ intel_operand_size (int bytemode, int sizeflag)
{
case b_mode:
case b_swap_mode:
- case dqb_mode:
case db_mode:
oappend ("BYTE PTR ");
break;
case w_mode:
case dw_mode:
- case dqw_mode:
oappend ("WORD PTR ");
break;
case indir_v_mode:
@@ -11020,7 +11010,6 @@ intel_operand_size (int bytemode, int sizeflag)
break;
case d_mode:
case d_swap_mode:
- case dqd_mode:
oappend ("DWORD PTR ");
break;
case q_mode:
@@ -11263,9 +11252,6 @@ print_register (unsigned int reg, unsigned int rexmask, int bytemode, int sizefl
case v_mode:
case v_swap_mode:
case dq_mode:
- case dqb_mode:
- case dqd_mode:
- case dqw_mode:
USED_REX (REX_W);
if (rex & REX_W)
names = names64;
@@ -11340,12 +11326,10 @@ OP_E_memory (int bytemode, int sizeflag)
}
switch (bytemode)
{
- case dqw_mode:
case dw_mode:
case w_mode:
shift = 1;
break;
- case dqb_mode:
case db_mode:
case b_mode:
shift = 0;
@@ -11353,7 +11337,6 @@ OP_E_memory (int bytemode, int sizeflag)
case dq_mode:
if (address_mode != mode_64bit)
{
- case dqd_mode:
case d_mode:
case d_swap_mode:
shift = 2;
--
2.33.0

304
0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch Normal file
View File

@ -0,0 +1,304 @@
From 0e4cc77316732e67cff33e493eff2aa7feed4587 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 23 Jul 2021 08:03:21 +0200
Subject: [PATCH] x86: express unduly set rounding control bits in disassembly
While EVEX.L'L are indeed ignored when EVEX.b stands for just SAE,
EVEX.b itself is not ignored when an insn permits neither rounding
control nor SAE.
While changing this aspect of EVEX.b handling, also alter unduly set
embedded broadcast: Don't call BadOp(), screwing up subsequent
disassembly, but emit "{bad}" instead.
diff --git a/gas/testsuite/gas/i386/avx512f-nondef.d b/gas/testsuite/gas/i386/avx512f-nondef.d
index f19edceb6bb..07ffe60e177 100644
--- a/gas/testsuite/gas/i386/avx512f-nondef.d
+++ b/gas/testsuite/gas/i386/avx512f-nondef.d
@@ -10,12 +10,11 @@ Disassembly of section .text:
0+ <.text>:
[ ]*[a-f0-9]+: 62 f3 d5 1f 0b f4 7b vrndscalesd \$0x7b,\{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+: 62 f3 d5 5f 0b f4 7b vrndscalesd \$0x7b,\{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
-[ ]*[a-f0-9]+: 62 f2 55 1f 3b f4 vpminud %zmm4,%zmm5,%zmm6\{%k7\}
-[ ]*[a-f0-9]+: 62 c2 55 1f 3b f4 vpminud %zmm4,%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 55 4f 3b f4 vpminud %zmm4,%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 c2 55 4f 3b f4 vpminud %zmm4,%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 55 1f 3b f4 vpminud \{rn-bad\},%zmm4,%zmm5,%zmm6\{%k7\}
[ ]*[a-f0-9]+: 62 f2 7e 48 31 72 7f vpmovdb %zmm6,0x7f0\(%edx\)
-[ ]*[a-f0-9]+: 62 vpmovdb %zmm6,\(bad\)
-[ ]*[a-f0-9]+: f2 7e 58 bnd jle (0x7d|7d <.text\+0x7d>)
-[ ]*[a-f0-9]+: 31 72 7f xor %esi,0x7f\(%edx\)
+[ ]*[a-f0-9]+: 62 f2 7e 58 31 72 7f vpmovdb %zmm6,0x7f0\(%edx\)\{bad\}
[ ]*[a-f0-9]+: 62 f1 7c 88 58 \(bad\)
[ ]*[a-f0-9]+: c3 ret *
[ ]*[a-f0-9]+: 62 f2 7d 4f 92 01 vgatherdps \(bad\),%zmm0\{%k7\}
diff --git a/gas/testsuite/gas/i386/avx512f-nondef.s b/gas/testsuite/gas/i386/avx512f-nondef.s
index 676c4e0fe4b..96d04666248 100644
--- a/gas/testsuite/gas/i386/avx512f-nondef.s
+++ b/gas/testsuite/gas/i386/avx512f-nondef.s
@@ -5,13 +5,15 @@
.byte 0x62, 0xf3, 0xd5, 0x1f, 0x0b, 0xf4, 0x7b
# vrndscalesd {sae}, $123, %xmm4, %xmm5, %xmm6{%k7} # with not-null RC
.byte 0x62, 0xf3, 0xd5, 0x5f, 0x0b, 0xf4, 0x7b
-# vpminud %zmm4, %zmm5, %zmm6{%k7} # with 111 REX
+# vpminud %zmm4, %zmm5, %zmm6{%k7} # with 11 EVEX.{B,R'}
+.byte 0x62, 0xf2, 0x55, 0x4f, 0x3b, 0xf4
+# vpminud %zmm4, %zmm5, %zmm6{%k7} # with not-11 EVEX.{B,R'}
+.byte 0x62, 0xc2, 0x55, 0x4f, 0x3b, 0xf4
+# vpminud %zmm4, %zmm5, %zmm6{%k7} # with set EVEX.b bit
.byte 0x62, 0xf2, 0x55, 0x1f, 0x3b, 0xf4
-# vpminud %zmm4, %zmm5, %zmm6{%k7} # with not-111 REX
-.byte 0x62, 0xc2, 0x55, 0x1f, 0x3b, 0xf4
-# vpmovdb %zmm6, 2032(%rdx) # with unset EVEX.B bit
+# vpmovdb %zmm6, 2032(%rdx) # with unset EVEX.b bit
.byte 0x62, 0xf2, 0x7e, 0x48, 0x31, 0x72, 0x7f
-# vpmovdb %zmm6, 2032(%rdx) # with set EVEX.B bit - we should get (bad) operand
+# vpmovdb %zmm6, 2032(%rdx) # with set EVEX.b bit - we should get (bad) operand
.byte 0x62, 0xf2, 0x7e, 0x58, 0x31, 0x72, 0x7f
# vaddps xmm0, xmm0, xmm3 # with EVEX.z set
.byte 0x62, 0xf1, 0x7c, 0x88, 0x58, 0xc3
diff --git a/gas/testsuite/gas/i386/evex.d b/gas/testsuite/gas/i386/evex.d
index 367b2eb1321..4afcc6db728 100644
--- a/gas/testsuite/gas/i386/evex.d
+++ b/gas/testsuite/gas/i386/evex.d
@@ -8,14 +8,14 @@ Disassembly of section .text:
0+ <_start>:
+[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
- +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sdl %eax,\(bad\),%xmm5,%xmm6
- +[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sdl %eax,\(bad\),%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sdl %eax,\{rd-bad\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sdl %eax,\{rd-bad\},%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ssl %eax,%xmm5,%xmm6
+[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
- +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
- +[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl %eax,\{rd-bad\},%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,\{rd-bad\},%xmm5,%xmm6
+[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,%eax
+[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,%k0
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f-nondef.d b/gas/testsuite/gas/i386/x86-64-avx512f-nondef.d
index bce2d80588d..e8ddfd58870 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512f-nondef.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512f-nondef.d
@@ -10,10 +10,9 @@ Disassembly of section .text:
0+ <.text>:
[ ]*[a-f0-9]+: 62 f3 d5 1f 0b f4 7b vrndscalesd \$0x7b,\{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+: 62 f3 d5 5f 0b f4 7b vrndscalesd \$0x7b,\{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
-[ ]*[a-f0-9]+: 62 f2 55 1f 3b f4 vpminud %zmm4,%zmm5,%zmm6\{%k7\}
-[ ]*[a-f0-9]+: 62 c2 55 1f 3b f4 vpminud %zmm12,%zmm5,%zmm22\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 55 4f 3b f4 vpminud %zmm4,%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 c2 55 4f 3b f4 vpminud %zmm12,%zmm5,%zmm22\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 55 1f 3b f4 vpminud \{rn-bad\},%zmm4,%zmm5,%zmm6\{%k7\}
[ ]*[a-f0-9]+: 62 f2 7e 48 31 72 7f vpmovdb %zmm6,0x7f0\(%rdx\)
-[ ]*[a-f0-9]+: 62 vpmovdb %zmm6,\(bad\)
-[ ]*[a-f0-9]+: f2 7e 58 bnd jle (0x7d|7d <.text\+0x7d>)
-[ ]*[a-f0-9]+: 31 72 7f xor %esi,0x7f\(%rdx\)
+[ ]*[a-f0-9]+: 62 f2 7e 58 31 72 7f vpmovdb %zmm6,0x7f0\(%rdx\)\{bad\}
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f-nondef.s b/gas/testsuite/gas/i386/x86-64-avx512f-nondef.s
index 255d2c931f1..952f2db76b3 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512f-nondef.s
+++ b/gas/testsuite/gas/i386/x86-64-avx512f-nondef.s
@@ -5,11 +5,13 @@
.byte 0x62, 0xf3, 0xd5, 0x1f, 0x0b, 0xf4, 0x7b
# vrndscalesd {sae}, $123, %xmm4, %xmm5, %xmm6{%k7} # with not-null RC
.byte 0x62, 0xf3, 0xd5, 0x5f, 0x0b, 0xf4, 0x7b
-# vpminud %zmm4, %zmm5, %zmm6{%k7} # with 111 REX
+# vpminud %zmm4, %zmm5, %zmm6{%k7} # with 11 EVEX.{B,R'}
+.byte 0x62, 0xf2, 0x55, 0x4f, 0x3b, 0xf4
+# vpminud %zmm4, %zmm5, %zmm6{%k7} # with not-11 EVEX.{B,R'}
+.byte 0x62, 0xc2, 0x55, 0x4f, 0x3b, 0xf4
+# vpminud %zmm4, %zmm5, %zmm6{%k7} # with set EVEX.b bit
.byte 0x62, 0xf2, 0x55, 0x1f, 0x3b, 0xf4
-# vpminud %zmm4, %zmm5, %zmm6{%k7} # with not-111 REX
-.byte 0x62, 0xc2, 0x55, 0x1f, 0x3b, 0xf4
-# vpmovdb %zmm6, 2032(%rdx) # with unset EVEX.B bit
+# vpmovdb %zmm6, 2032(%rdx) # with unset EVEX.b bit
.byte 0x62, 0xf2, 0x7e, 0x48, 0x31, 0x72, 0x7f
-# vpmovdb %zmm6, 2032(%rdx) # with set EVEX.B bit - we should get (bad) operand
+# vpmovdb %zmm6, 2032(%rdx) # with set EVEX.b bit - we should get (bad) operand
.byte 0x62, 0xf2, 0x7e, 0x58, 0x31, 0x72, 0x7f
diff --git a/gas/testsuite/gas/i386/x86-64-evex.d b/gas/testsuite/gas/i386/x86-64-evex.d
index 3a7b48e0bf9..041747db892 100644
--- a/gas/testsuite/gas/i386/x86-64-evex.d
+++ b/gas/testsuite/gas/i386/x86-64-evex.d
@@ -9,13 +9,13 @@ Disassembly of section .text:
0+ <_start>:
+[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ss %rax,\{rd-sae\},%xmm5,%xmm6
- +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sd %eax,\(bad\),%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sd %eax,\{rd-bad\},%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sd %rax,\{rd-sae\},%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ss %rax,%xmm5,%xmm6
+[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sd %rax,%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ss %rax,\{rd-sae\},%xmm5,%xmm6
- +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd %eax,\(bad\),%xmm5,%xmm6
+ +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd %eax,\{rd-bad\},%xmm5,%xmm6
+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sd %rax,\{rd-sae\},%xmm5,%xmm6
+[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,\(bad\)
+[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,\(bad\)
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 521d6899338..b25a9f324c0 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -159,6 +159,11 @@ static int rex_used;
current instruction. */
static int used_prefixes;
+/* Flags for EVEX bits which we somehow handled when printing the
+ current instruction. */
+#define EVEX_b_used 1
+static int evex_used;
+
/* Flags stored in PREFIXES. */
#define PREFIX_REPZ 1
#define PREFIX_REPNZ 2
@@ -2524,12 +2529,12 @@ static const char *att_names_mask[] = {
"%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
};
-static const char *names_rounding[] =
+static const char *const names_rounding[] =
{
- "{rn-sae}",
- "{rd-sae}",
- "{ru-sae}",
- "{rz-sae}"
+ "{rn-",
+ "{rd-",
+ "{ru-",
+ "{rz-"
};
static const struct dis386 reg_table[][8] = {
@@ -8578,6 +8583,7 @@ ckprefix (void)
prefixes = 0;
used_prefixes = 0;
rex_used = 0;
+ evex_used = 0;
last_lock_prefix = -1;
last_repz_prefix = -1;
last_repnz_prefix = -1;
@@ -9661,6 +9667,21 @@ print_insn (bfd_vma pc, disassemble_info *info)
oappend ("/(bad)");
}
}
+
+ /* Check whether rounding control was enabled for an insn not
+ supporting it. */
+ if (modrm.mod == 3 && vex.b && !(evex_used & EVEX_b_used))
+ {
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ {
+ obufp = op_out[i];
+ if (*obufp)
+ continue;
+ oappend (names_rounding[vex.ll]);
+ oappend ("bad}");
+ break;
+ }
+ }
}
}
@@ -11316,14 +11337,6 @@ OP_E_memory (int bytemode, int sizeflag)
if (vex.evex)
{
- /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
- if (vex.b
- && bytemode != x_mode
- && bytemode != evex_half_bcst_xmmq_mode)
- {
- BadOp ();
- return;
- }
switch (bytemode)
{
case dw_mode:
@@ -11764,10 +11777,9 @@ OP_E_memory (int bytemode, int sizeflag)
oappend (scratchbuf);
}
}
- if (vex.b
- && (bytemode == x_mode
- || bytemode == evex_half_bcst_xmmq_mode))
+ if (vex.b)
{
+ evex_used |= EVEX_b_used;
if (vex.w
|| bytemode == evex_half_bcst_xmmq_mode)
{
@@ -11786,7 +11798,7 @@ OP_E_memory (int bytemode, int sizeflag)
abort ();
}
}
- else
+ else if (bytemode == x_mode)
{
switch (vex.length)
{
@@ -11803,6 +11815,9 @@ OP_E_memory (int bytemode, int sizeflag)
abort ();
}
}
+ else
+ /* If operand doesn't allow broadcast, vex.b should be 0. */
+ oappend ("{bad}");
}
}
@@ -13495,24 +13510,25 @@ MOVSXD_Fixup (int bytemode, int sizeflag)
static void
OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- if (modrm.mod == 3 && vex.b)
- switch (bytemode)
- {
- case evex_rounding_64_mode:
- if (address_mode != mode_64bit || !vex.w)
- {
- oappend ("(bad)");
- break;
- }
- /* Fall through. */
- case evex_rounding_mode:
- oappend (names_rounding[vex.ll]);
- break;
- case evex_sae_mode:
- oappend ("{sae}");
- break;
- default:
- abort ();
- break;
- }
+ if (modrm.mod != 3 || !vex.b)
+ return;
+
+ switch (bytemode)
+ {
+ case evex_rounding_64_mode:
+ if (address_mode != mode_64bit || !vex.w)
+ return;
+ /* Fall through. */
+ case evex_rounding_mode:
+ evex_used |= EVEX_b_used;
+ oappend (names_rounding[vex.ll]);
+ break;
+ case evex_sae_mode:
+ evex_used |= EVEX_b_used;
+ oappend ("{");
+ break;
+ default:
+ abort ();
+ }
+ oappend ("sae}");
}
--
2.33.0

52
0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch Normal file
View File

@ -0,0 +1,52 @@
From fc141319027485a7cfcbae2451b048ddc6c33b48 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Wed, 28 Jul 2021 10:42:47 -0700
Subject: [PATCH] x86: Simplify check for distinct TMM register operands
If any pair of operands in AMX instructions with 3 TMM register operands
are the same, the instruction will UD. Don't call register_number to
check for distinct TMM register operands since all TMM register operands
have the same size.
* config/tc-i386.c (check_VecOperands): Remove register_number
call when checking for distinct TMM register operands.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d98c6c4e949..1235c3e7733 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6076,21 +6076,16 @@ check_VecOperands (const insn_template *t)
}
}
- /* For AMX instructions with three tmmword operands, all tmmword operand must be
- distinct */
- if (t->operand_types[0].bitfield.tmmword
- && i.reg_operands == 3)
- {
- if (register_number (i.op[0].regs)
- == register_number (i.op[1].regs)
- || register_number (i.op[0].regs)
- == register_number (i.op[2].regs)
- || register_number (i.op[1].regs)
- == register_number (i.op[2].regs))
- {
- i.error = invalid_tmm_register_set;
- return 1;
- }
+ /* For AMX instructions with 3 TMM register operands, all operands
+ must be distinct. */
+ if (i.reg_operands == 3
+ && t->operand_types[0].bitfield.tmmword
+ && (i.op[0].regs == i.op[1].regs
+ || i.op[0].regs == i.op[2].regs
+ || i.op[1].regs == i.op[2].regs))
+ {
+ i.error = invalid_tmm_register_set;
+ return 1;
}
/* Check if broadcast is supported by the instruction and is applied
--
2.33.0

90788
0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch Normal file
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26295
0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch Normal file
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204
0018-x86-ELF-fix-.tfloat-output.patch Normal file
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@ -0,0 +1,204 @@
From e2295dade838ad296e1e1cd1096177058139b6b3 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Wed, 11 Aug 2021 08:30:26 +0200
Subject: [PATCH] x86/ELF: fix .tfloat output
The ELF psABI-s are quite clear here: On 32-bit the data type is 12
bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16
bytes long (with 6 bytes of padding). Make ieee_md_atof() capable of
handling such padding, and specify the needed padding for x86 (leaving
non-ELF targets alone for now). Split the existing x86 testcase.
diff --git a/gas/config/atof-ieee.c b/gas/config/atof-ieee.c
index fa988aa36ee..e6e8879b51b 100644
--- a/gas/config/atof-ieee.c
+++ b/gas/config/atof-ieee.c
@@ -30,7 +30,13 @@ extern FLONUM_TYPE generic_floating_point_number;
#define F_PRECISION 2
#define D_PRECISION 4
#define X_PRECISION 5
+#ifndef X_PRECISION_PAD
+#define X_PRECISION_PAD 0
+#endif
#define P_PRECISION 5
+#ifndef P_PRECISION_PAD
+#define P_PRECISION_PAD X_PRECISION_PAD
+#endif
/* Length in LittleNums of guard bits. */
#define GUARD 2
@@ -760,7 +766,7 @@ ieee_md_atof (int type,
LITTLENUM_TYPE words[MAX_LITTLENUMS];
LITTLENUM_TYPE *wordP;
char *t;
- int prec = 0;
+ int prec = 0, pad = 0;
if (strchr (FLT_CHARS, type) != NULL)
{
@@ -788,6 +794,7 @@ ieee_md_atof (int type,
case 't':
case 'T':
prec = X_PRECISION;
+ pad = X_PRECISION_PAD;
type = 'x'; /* This is what atof_ieee() understands. */
break;
@@ -803,6 +810,7 @@ ieee_md_atof (int type,
#else
prec = P_PRECISION;
#endif
+ pad = P_PRECISION_PAD;
break;
default:
@@ -835,7 +843,7 @@ ieee_md_atof (int type,
if (t)
input_line_pointer = t;
- *sizeP = prec * sizeof (LITTLENUM_TYPE);
+ *sizeP = (prec + pad) * sizeof (LITTLENUM_TYPE);
if (big_wordian)
{
@@ -854,5 +862,8 @@ ieee_md_atof (int type,
}
}
+ memset (litP, 0, pad * sizeof (LITTLENUM_TYPE));
+ litP += pad * sizeof (LITTLENUM_TYPE);
+
return NULL;
}
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index cdc660f79a4..0fa8b0d5a04 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -10229,6 +10229,19 @@ x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
fix_new_exp (frag, off, len, exp, 0, r);
}
+/* Return the number of padding LITTLENUMs following a tbyte floating
+ point value. */
+
+int
+x86_tfloat_pad (void)
+{
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+ if (IS_ELF)
+ return object_64bit ? 3 : 1;
+#endif
+ return 0;
+}
+
/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
purpose of the `.dc.a' internal pseudo-op. */
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index 90d23da7d91..f94226edf78 100644
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -134,6 +134,9 @@ extern bfd_reloc_code_real_type x86_cons (expressionS *, int);
extern void x86_cons_fix_new
(fragS *, unsigned int, unsigned int, expressionS *, bfd_reloc_code_real_type);
+#define X_PRECISION_PAD x86_tfloat_pad ()
+extern int x86_tfloat_pad (void);
+
#define TC_ADDRESS_BYTES x86_address_bytes
extern int x86_address_bytes (void);
diff --git a/gas/testsuite/gas/i386/fp-elf32.d b/gas/testsuite/gas/i386/fp-elf32.d
new file mode 100644
index 00000000000..6ef9c83ac54
--- /dev/null
+++ b/gas/testsuite/gas/i386/fp-elf32.d
@@ -0,0 +1,12 @@
+#objdump: -s -j .data
+#name: i386 fp (ELF)
+#source: fp.s
+
+.*: file format .*
+
+Contents of section .data:
+ 0000 00881bcd 4b789ad4 00400000 71a37909 .*
+ 0010 4f930a40 789a5440 789a5440 00000000 .*
+ 0020 e65e1710 20395e3b e65e1710 20395e3b .*
+ 0030 00000000 0000a044 01000000 0000a044 .*
+ 0040 00000000 0000f03f .*
diff --git a/gas/testsuite/gas/i386/fp-elf64.d b/gas/testsuite/gas/i386/fp-elf64.d
new file mode 100644
index 00000000000..2e68ac8ebca
--- /dev/null
+++ b/gas/testsuite/gas/i386/fp-elf64.d
@@ -0,0 +1,12 @@
+#objdump: -s -j .data
+#name: x86-64 fp (ELF)
+#source: fp.s
+
+.*: file format .*
+
+Contents of section .data:
+ 0000 00881bcd 4b789ad4 00400000 00000000 .*
+ 0010 71a37909 4f930a40 789a5440 789a5440 .*
+ 0020 e65e1710 20395e3b e65e1710 20395e3b .*
+ 0030 00000000 0000a044 01000000 0000a044 .*
+ 0040 00000000 0000f03f .*
diff --git a/gas/testsuite/gas/i386/fp.s b/gas/testsuite/gas/i386/fp.s
index 11a50cf2683..fca56f29ac1 100644
--- a/gas/testsuite/gas/i386/fp.s
+++ b/gas/testsuite/gas/i386/fp.s
@@ -7,10 +7,10 @@
# .byte 0x71, 0xa3, 0x79, 0x09, 0x4f, 0x93, 0x0a, 0x40
# The next two are 32-bit floating point format.
.float 3.32192809488736218171e0
-# .byte 0x78, 0x9a, 0x54, 0x40, 0, 0, 0, 0
+# .byte 0x78, 0x9a, 0x54, 0x40
.single 3.32192809488736218171e0
-# .byte 0x78, 0x9a, 0x54, 0x40, 0, 0, 0, 0
- .byte 0, 0, 0, 0, 0, 0
+# .byte 0x78, 0x9a, 0x54, 0x40
+ .p2align 4,0
# The assembler used to treat the next value as zero instead of 1e-22.
.double .0000000000000000000001
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3464bc2702b..122da6a2315 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -118,7 +118,6 @@ if [gas_32_check] then {
run_list_test "lockbad-1" "-al"
run_dump_test "long-1"
run_dump_test "long-1-intel"
- run_dump_test "fp"
run_dump_test "nops"
run_dump_test "nops16-1"
run_dump_test "nops-1"
@@ -624,6 +623,7 @@ if [gas_32_check] then {
run_dump_test "intel-movs16"
run_dump_test "intel-cmps32"
run_dump_test "intel-cmps16"
+ run_dump_test "fp-elf32"
run_list_test "inval-equ-1" "-al"
run_list_test "inval-equ-2" "-al"
run_dump_test "ifunc"
@@ -697,6 +697,8 @@ if [gas_32_check] then {
run_dump_test "iamcu-5"
run_list_test "iamcu-inval-1" "-march=iamcu -al"
}
+ } else {
+ run_dump_test "fp"
}
# This is a PE specific test.
@@ -1274,6 +1276,7 @@ if [gas_64_check] then {
run_list_test "reloc64" "--defsym _bad_=1"
run_dump_test "mixed-mode-reloc64"
run_dump_test "rela"
+ run_dump_test "fp-elf64"
run_dump_test "x86-64-ifunc"
run_dump_test "x86-64-opcode-inval"
run_dump_test "x86-64-opcode-inval-intel"
--
2.33.0

155
0019-x86-ELF-fix-.ds.x-output.patch Normal file
View File

@ -0,0 +1,155 @@
From e74e2b4c336fad993b0dd31b859af919ad52ec9e Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Wed, 11 Aug 2021 08:31:03 +0200
Subject: [PATCH] x86/ELF: fix .ds.x output
The ELF psABI-s are quite clear here: On 32-bit the underlying data type
is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it
is 16 bytes long (with 6 bytes of padding). Make s_space() capable of
handling 'x' (and 'p') type floating point being other than 12 bytes
wide (also adjusting documentation). This requires duplicating the
definition of X_PRECISION in the target speciifc header; the compiler
would complain if this was out of sync with config/atof-ieee.c.
Note that for now padding space doesn't get separated from actual
storage, which means that things will work correctly only for little-
endian cases, and which also means that by specifying large enough
numbers padding space can be set to non-zero. Since the logic is needed
for a single little-endian architecture only for now, I'm hoping that
this might be acceptable for the time being; otherwise the change will
become more intrusive.
Note also that this brings the emitted data size of .ds.x vs .tfloat in
line for non-ELF targets as well; the issue will be even more obvious
when further taking into account a subsequent patch fixing .dc.x/.dcb.x
(where output sizes currently differ depending on input format).
Extend existing x86 testcases.
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index f94226edf78..2dc6312f28e 100644
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -134,6 +134,7 @@ extern bfd_reloc_code_real_type x86_cons (expressionS *, int);
extern void x86_cons_fix_new
(fragS *, unsigned int, unsigned int, expressionS *, bfd_reloc_code_real_type);
+#define X_PRECISION 5
#define X_PRECISION_PAD x86_tfloat_pad ()
extern int x86_tfloat_pad (void);
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 292c4af2bb6..b8d5b9be15e 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -5125,13 +5125,13 @@ Emits 8-byte values.
@item @samp{.l}
Emits 4-byte values.
@item @samp{.p}
-Emits 12-byte values.
+Emits values with size matching packed-decimal floating-point ones.
@item @samp{.s}
Emits 4-byte values.
@item @samp{.w}
Emits 2-byte values.
@item @samp{.x}
-Emits 12-byte values.
+Emits values with size matching long double precision floating-point ones.
@end table
Note - unlike the @code{.dcb} directive the @samp{.d}, @samp{.s} and @samp{.x}
diff --git a/gas/read.c b/gas/read.c
index ea9261e639b..6bba696cebc 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -382,10 +382,10 @@ static const pseudo_typeS potable[] = {
{"ds.b", s_space, 1},
{"ds.d", s_space, 8},
{"ds.l", s_space, 4},
- {"ds.p", s_space, 12},
+ {"ds.p", s_space, 'p'},
{"ds.s", s_space, 4},
{"ds.w", s_space, 2},
- {"ds.x", s_space, 12},
+ {"ds.x", s_space, 'x'},
{"debug", s_ignore, 0},
#ifdef S_SET_DESC
{"desc", s_desc, 0},
@@ -3327,6 +3327,29 @@ s_space (int mult)
md_flush_pending_output ();
#endif
+ switch (mult)
+ {
+ case 'x':
+#ifdef X_PRECISION
+# ifndef P_PRECISION
+# define P_PRECISION X_PRECISION
+# define P_PRECISION_PAD X_PRECISION_PAD
+# endif
+ mult = (X_PRECISION + X_PRECISION_PAD) * sizeof (LITTLENUM_TYPE);
+ if (!mult)
+#endif
+ mult = 12;
+ break;
+
+ case 'p':
+#ifdef P_PRECISION
+ mult = (P_PRECISION + P_PRECISION_PAD) * sizeof (LITTLENUM_TYPE);
+ if (!mult)
+#endif
+ mult = 12;
+ break;
+ }
+
#ifdef md_cons_align
md_cons_align (1);
#endif
diff --git a/gas/testsuite/gas/i386/fp-elf32.d b/gas/testsuite/gas/i386/fp-elf32.d
index 6ef9c83ac54..9e1254615ec 100644
--- a/gas/testsuite/gas/i386/fp-elf32.d
+++ b/gas/testsuite/gas/i386/fp-elf32.d
@@ -9,4 +9,5 @@ Contents of section .data:
0010 4f930a40 789a5440 789a5440 00000000 .*
0020 e65e1710 20395e3b e65e1710 20395e3b .*
0030 00000000 0000a044 01000000 0000a044 .*
- 0040 00000000 0000f03f .*
+ 0040 00000000 0000f03f 00000000 00000000 .*
+ 0050 ffffffff ffffffff ffffffff cccccccc .*
diff --git a/gas/testsuite/gas/i386/fp-elf64.d b/gas/testsuite/gas/i386/fp-elf64.d
index 2e68ac8ebca..0314929cf9c 100644
--- a/gas/testsuite/gas/i386/fp-elf64.d
+++ b/gas/testsuite/gas/i386/fp-elf64.d
@@ -9,4 +9,5 @@ Contents of section .data:
0010 71a37909 4f930a40 789a5440 789a5440 .*
0020 e65e1710 20395e3b e65e1710 20395e3b .*
0030 00000000 0000a044 01000000 0000a044 .*
- 0040 00000000 0000f03f .*
+ 0040 00000000 0000f03f 00000000 00000000 .*
+ 0050 ffffffff ffffffff ffffffff ffffffff .*
diff --git a/gas/testsuite/gas/i386/fp.d b/gas/testsuite/gas/i386/fp.d
index edf79ff9996..dd7e028b44b 100644
--- a/gas/testsuite/gas/i386/fp.d
+++ b/gas/testsuite/gas/i386/fp.d
@@ -8,4 +8,5 @@ Contents of section .data:
0010 0a40789a 5440789a 54400000 00000000 .*
0020 e65e1710 20395e3b e65e1710 20395e3b .*
0030 00000000 0000a044 01000000 0000a044 .*
- 0040 00000000 0000f03f .*
+ 0040 00000000 0000f03f 00000000 00000000 .*
+ 0050 ffffffff ffffffff ffffcccc cccccccc .*
diff --git a/gas/testsuite/gas/i386/fp.s b/gas/testsuite/gas/i386/fp.s
index fca56f29ac1..601709c2196 100644
--- a/gas/testsuite/gas/i386/fp.s
+++ b/gas/testsuite/gas/i386/fp.s
@@ -20,3 +20,7 @@
.double 37778931862957165903873.0
# Ensure we handle a crazy number of digits
.double 1.000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
+ .p2align 4,0
+
+ .ds.x 1, -1
+ .p2align 4,0xcc
--
2.33.0

113
0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch Normal file
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@ -0,0 +1,113 @@
From 8f2200fe8e7f17295ed6d9bbc908da533c95e089 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Wed, 11 Aug 2021 08:31:41 +0200
Subject: [PATCH] x86/ELF: fix .tfloat output with hex input
The ELF psABI-s are quite clear here: On 32-bit the data type is 12
bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16
bytes long (with 6 bytes of padding). Make hex_float() capable of
handling such padding.
Note that this brings the emitted data size of .dc.x / .dcb.x in line
also for non-ELF targets; so far they were different depending on input
format (dec vs hex).
Extend the existing x86 testcases.
diff --git a/gas/read.c b/gas/read.c
index 6bba696cebc..b8e845dd569 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -4847,7 +4847,7 @@ parse_repeat_cons (expressionS *exp, unsigned int nbytes)
static int
hex_float (int float_type, char *bytes)
{
- int length;
+ int length, pad = 0;
int i;
switch (float_type)
@@ -4868,12 +4868,22 @@ hex_float (int float_type, char *bytes)
case 'x':
case 'X':
- length = 12;
+#ifdef X_PRECISION
+ length = X_PRECISION * sizeof (LITTLENUM_TYPE);
+ pad = X_PRECISION_PAD * sizeof (LITTLENUM_TYPE);
+ if (!length)
+#endif
+ length = 12;
break;
case 'p':
case 'P':
- length = 12;
+#ifdef P_PRECISION
+ length = P_PRECISION * sizeof (LITTLENUM_TYPE);
+ pad = P_PRECISION_PAD * sizeof (LITTLENUM_TYPE);
+ if (!length)
+#endif
+ length = 12;
break;
default:
@@ -4926,7 +4936,9 @@ hex_float (int float_type, char *bytes)
memset (bytes, 0, length - i);
}
- return length;
+ memset (bytes + length, 0, pad);
+
+ return length + pad;
}
/* float_cons()
diff --git a/gas/testsuite/gas/i386/fp-elf32.d b/gas/testsuite/gas/i386/fp-elf32.d
index 9e1254615ec..eefe84db310 100644
--- a/gas/testsuite/gas/i386/fp-elf32.d
+++ b/gas/testsuite/gas/i386/fp-elf32.d
@@ -11,3 +11,6 @@ Contents of section .data:
0030 00000000 0000a044 01000000 0000a044 .*
0040 00000000 0000f03f 00000000 00000000 .*
0050 ffffffff ffffffff ffffffff cccccccc .*
+ 0060 00000000 00000080 fe3f0000 00000000 .*
+ 0070 00000080 fdbf0000 00000000 00000080 .*
+ 0080 ff030000 aaaaaaaa aaaaaaaa aaaaaaaa .*
diff --git a/gas/testsuite/gas/i386/fp-elf64.d b/gas/testsuite/gas/i386/fp-elf64.d
index 0314929cf9c..0756aa1e36a 100644
--- a/gas/testsuite/gas/i386/fp-elf64.d
+++ b/gas/testsuite/gas/i386/fp-elf64.d
@@ -11,3 +11,6 @@ Contents of section .data:
0030 00000000 0000a044 01000000 0000a044 .*
0040 00000000 0000f03f 00000000 00000000 .*
0050 ffffffff ffffffff ffffffff ffffffff .*
+ 0060 00000000 00000080 fe3f0000 00000000 .*
+ 0070 00000000 00000080 fdbf0000 00000000 .*
+ 0080 00000000 00000080 ff030000 00000000 .*
diff --git a/gas/testsuite/gas/i386/fp.d b/gas/testsuite/gas/i386/fp.d
index dd7e028b44b..b93595ac8c3 100644
--- a/gas/testsuite/gas/i386/fp.d
+++ b/gas/testsuite/gas/i386/fp.d
@@ -10,3 +10,5 @@ Contents of section .data:
0030 00000000 0000a044 01000000 0000a044 .*
0040 00000000 0000f03f 00000000 00000000 .*
0050 ffffffff ffffffff ffffcccc cccccccc .*
+ 0060 00000000 00000080 fe3f0000 00000000 .*
+ 0070 0080fdbf 00000000 00000080 ff03aaaa .*
diff --git a/gas/testsuite/gas/i386/fp.s b/gas/testsuite/gas/i386/fp.s
index 601709c2196..7fe642e5180 100644
--- a/gas/testsuite/gas/i386/fp.s
+++ b/gas/testsuite/gas/i386/fp.s
@@ -24,3 +24,8 @@
.ds.x 1, -1
.p2align 4,0xcc
+
+ .tfloat 0x:3ffe80
+ .dc.x 0x:bffd80
+ .dcb.x 1, 0x:03ff80
+ .p2align 4,0xaa
--
2.33.0

121
0021-x86-introduce-.hfloat-directive.patch Normal file
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@ -0,0 +1,121 @@
From 7d19d096292acac01d0fde4d99c3e49d69688e03 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Wed, 11 Aug 2021 08:32:54 +0200
Subject: [PATCH] x86: introduce .hfloat directive
This is to be able to generate data passed to {,V}CVTPH2PS and acted
upon by AVX512-FP16 insns. To be able to also use the hex forms
supported for other floating point formats, a small addition to the
generic hex_float() is needed.
Extend existing x86 testcases.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 0fa8b0d5a04..a9e36213390 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -512,7 +512,7 @@ const char EXP_CHARS[] = "eE";
/* Chars that mean this number is a floating point constant
As in 0f12.456
or 0d1.2345e12. */
-const char FLT_CHARS[] = "fFdDxX";
+const char FLT_CHARS[] = "fFdDxXhH";
/* Tables for lexical analysis. */
static char mnemonic_chars[256];
@@ -1356,6 +1356,7 @@ const pseudo_typeS md_pseudo_table[] =
{"ffloat", float_cons, 'f'},
{"dfloat", float_cons, 'd'},
{"tfloat", float_cons, 'x'},
+ {"hfloat", float_cons, 'h'},
{"value", cons, 2},
{"slong", signed_cons, 4},
{"noopt", s_ignore, 0},
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 9058ad444b0..664237c75c9 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -1313,18 +1313,21 @@ data type. Constructors build these data types into memory.
@cindex @code{single} directive, i386
@cindex @code{double} directive, i386
@cindex @code{tfloat} directive, i386
+@cindex @code{hfloat} directive, i386
@cindex @code{float} directive, x86-64
@cindex @code{single} directive, x86-64
@cindex @code{double} directive, x86-64
@cindex @code{tfloat} directive, x86-64
+@cindex @code{hfloat} directive, x86-64
@itemize @bullet
@item
Floating point constructors are @samp{.float} or @samp{.single},
-@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
-These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
-and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
-only supports this format via the @samp{fldt} (load 80-bit real to stack
-top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
+@samp{.double}, @samp{.tfloat}, and @samp{.hfloat} for 32-, 64-, 80-, and
+16-bit formats respectively. The former three correspond to instruction
+mnemonic suffixes @samp{s}, @samp{l}, and @samp{t}. @samp{t} stands for
+80-bit (ten byte) real. The 80387 only supports this format via the
+@samp{fldt} (load 80-bit real to stack top) and @samp{fstpt} (store 80-bit
+real and pop stack) instructions.
@cindex @code{word} directive, i386
@cindex @code{long} directive, i386
diff --git a/gas/read.c b/gas/read.c
index b8e845dd569..4170a254030 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -4852,6 +4852,11 @@ hex_float (int float_type, char *bytes)
switch (float_type)
{
+ case 'h':
+ case 'H':
+ length = 2;
+ break;
+
case 'f':
case 'F':
case 's':
diff --git a/gas/testsuite/gas/i386/fp-elf32.d b/gas/testsuite/gas/i386/fp-elf32.d
index eefe84db310..d25eed8b8ef 100644
--- a/gas/testsuite/gas/i386/fp-elf32.d
+++ b/gas/testsuite/gas/i386/fp-elf32.d
@@ -14,3 +14,4 @@ Contents of section .data:
0060 00000000 00000080 fe3f0000 00000000 .*
0070 00000080 fdbf0000 00000000 00000080 .*
0080 ff030000 aaaaaaaa aaaaaaaa aaaaaaaa .*
+ 0090 003c00c0 003c5555 55555555 55555555 .*
diff --git a/gas/testsuite/gas/i386/fp-elf64.d b/gas/testsuite/gas/i386/fp-elf64.d
index 0756aa1e36a..bdc8f86662e 100644
--- a/gas/testsuite/gas/i386/fp-elf64.d
+++ b/gas/testsuite/gas/i386/fp-elf64.d
@@ -14,3 +14,4 @@ Contents of section .data:
0060 00000000 00000080 fe3f0000 00000000 .*
0070 00000000 00000080 fdbf0000 00000000 .*
0080 00000000 00000080 ff030000 00000000 .*
+ 0090 003c00c0 003c5555 55555555 55555555 .*
diff --git a/gas/testsuite/gas/i386/fp.d b/gas/testsuite/gas/i386/fp.d
index b93595ac8c3..65a5fccd6ee 100644
--- a/gas/testsuite/gas/i386/fp.d
+++ b/gas/testsuite/gas/i386/fp.d
@@ -12,3 +12,4 @@ Contents of section .data:
0050 ffffffff ffffffff ffffcccc cccccccc .*
0060 00000000 00000080 fe3f0000 00000000 .*
0070 0080fdbf 00000000 00000080 ff03aaaa .*
+ 0080 003c00c0 003c5555 55555555 55555555 .*
diff --git a/gas/testsuite/gas/i386/fp.s b/gas/testsuite/gas/i386/fp.s
index 7fe642e5180..8976dd82f60 100644
--- a/gas/testsuite/gas/i386/fp.s
+++ b/gas/testsuite/gas/i386/fp.s
@@ -29,3 +29,6 @@
.dc.x 0x:bffd80
.dcb.x 1, 0x:03ff80
.p2align 4,0xaa
+
+ .hfloat 1, -2, 0x:3c00
+ .p2align 4,0x55
--
2.33.0

103
0022-x86-Avoid-abort-on-invalid-broadcast.patch Normal file
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@ -0,0 +1,103 @@
From 7e40d574be8b8bc01d3726b90556cff0081e9dd9 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 19 Aug 2021 06:38:21 -0700
Subject: [PATCH] x86: Avoid abort on invalid broadcast
Print "{bad}" on invalid broadcast instead of abort.
gas/
PR binutils/28247
* testsuite/gas/i386/bad-bcast.d: New file.
* testsuite/gas/i386/bad-bcast.s: Likewise.
* testsuite/gas/i386/i386.exp: Run bad-bcast.
opcodes/
PR binutils/28247
* i386-dis.c (OP_E_memory): Print "{bad}" on invalid broadcast
instead of abort.
diff --git a/gas/testsuite/gas/i386/bad-bcast.d b/gas/testsuite/gas/i386/bad-bcast.d
new file mode 100644
index 00000000000..9fc474a42ff
--- /dev/null
+++ b/gas/testsuite/gas/i386/bad-bcast.d
@@ -0,0 +1,14 @@
+#objdump: -dw
+#name: Disassemble bad broadcast
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <.text>:
+ +[a-f0-9]+: 62 .byte 0x62
+ +[a-f0-9]+: c3 ret
+ +[a-f0-9]+: 8c 1d 66 90 66 90 mov %ds,0x90669066
+ +[a-f0-9]+: 66 90 xchg %ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/bad-bcast.s b/gas/testsuite/gas/i386/bad-bcast.s
new file mode 100644
index 00000000000..e09c3aae5de
--- /dev/null
+++ b/gas/testsuite/gas/i386/bad-bcast.s
@@ -0,0 +1,2 @@
+ .text
+ .byte 0x62, 0xc3, 0x8c, 0x1d, 0x66, 0x90, 0x66, 0x90, 0x66, 0x90
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index f5eda2cf331..80959726d0e 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -646,6 +646,7 @@ if [gas_32_check] then {
run_dump_test "dw2-compress-2"
run_dump_test "dw2-compressed-2"
+ run_dump_test "bad-bcast"
run_dump_test "bad-size"
run_dump_test "size-1"
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 2c7027ca6f1..acb5a0faa88 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11912,7 +11912,7 @@ OP_E_memory (int bytemode, int sizeflag)
{
if (vex.w)
{
- abort ();
+ oappend ("{bad}");
}
else
{
@@ -11928,7 +11928,7 @@ OP_E_memory (int bytemode, int sizeflag)
oappend ("{1to32}");
break;
default:
- abort ();
+ oappend ("{bad}");
}
}
}
@@ -11948,7 +11948,7 @@ OP_E_memory (int bytemode, int sizeflag)
oappend ("{1to8}");
break;
default:
- abort ();
+ oappend ("{bad}");
}
}
else if (bytemode == x_mode
@@ -11966,7 +11966,7 @@ OP_E_memory (int bytemode, int sizeflag)
oappend ("{1to16}");
break;
default:
- abort ();
+ oappend ("{bad}");
}
}
else
--
2.33.0

59
0023-x86-Put-back-3-aborts-in-OP_E_memory.patch Normal file
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@ -0,0 +1,59 @@
From ca22cf5ed52c1b4c40dbadf893f558ef09d0c66b Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 19 Aug 2021 07:39:10 -0700
Subject: [PATCH] x86: Put back 3 aborts in OP_E_memory
Put back 3 aborts where invalid lengths should have been filtered out.
gas/
PR binutils/28247
* testsuite/gas/i386/bad-bcast.s: Add a comment.
opcodes/
PR binutils/28247
* * i386-dis.c (OP_E_memory): Put back 3 aborts.
diff --git a/gas/testsuite/gas/i386/bad-bcast.s b/gas/testsuite/gas/i386/bad-bcast.s
index e09c3aae5de..3e49b2238ed 100644
--- a/gas/testsuite/gas/i386/bad-bcast.s
+++ b/gas/testsuite/gas/i386/bad-bcast.s
@@ -1,2 +1,3 @@
.text
+# Invalid 16-bit broadcast with EVEX.W == 1.
.byte 0x62, 0xc3, 0x8c, 0x1d, 0x66, 0x90, 0x66, 0x90, 0x66, 0x90
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index acb5a0faa88..aa292233d4d 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11928,7 +11928,7 @@ OP_E_memory (int bytemode, int sizeflag)
oappend ("{1to32}");
break;
default:
- oappend ("{bad}");
+ abort ();
}
}
}
@@ -11948,7 +11948,7 @@ OP_E_memory (int bytemode, int sizeflag)
oappend ("{1to8}");
break;
default:
- oappend ("{bad}");
+ abort ();
}
}
else if (bytemode == x_mode
@@ -11966,7 +11966,7 @@ OP_E_memory (int bytemode, int sizeflag)
oappend ("{1to16}");
break;
default:
- oappend ("{bad}");
+ abort ();
}
}
else
--
2.33.0

279
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@ -0,0 +1,279 @@
From 2c02075a8ec5223bc4cbcc9561eb91e28d46a9e5 Mon Sep 17 00:00:00 2001
From: "Cui,Lili" <lili.cui@intel.com>
Date: Tue, 28 Sep 2021 11:13:33 +0800
Subject: [PATCH] x86: Print {bad} on invalid broadcast in OP_E_memory
Don't print broadcast for scalar_mode, and print {bad} for invalid broadcast.
gas/
PR binutils/28381
* testsuite/gas/i386/bad-bcast.s: Add a new testcase.
* testsuite/gas/i386/bad-bcast.d: Likewise.
* testsuite/gas/i386/bad-bcast-intel.d: New.
opcodes/
PR binutils/28381
* i386-dis.c (static struct): Add no_broadcast.
(OP_E_memory): Mark invalid broadcast with no_broadcast=1 and Print "{bad}"for it.
(intel_operand_size): mark invalid broadcast with no_broadcast=1.
(OP_XMM): Mark scalar_mode with no_broadcast=1.
diff --git a/gas/testsuite/gas/i386/bad-bcast-intel.d b/gas/testsuite/gas/i386/bad-bcast-intel.d
new file mode 100644
index 00000000000..29de3de299c
--- /dev/null
+++ b/gas/testsuite/gas/i386/bad-bcast-intel.d
@@ -0,0 +1,15 @@
+#source: bad-bcast.s
+#objdump: -dw -Mintel
+#name: Disassemble bad broadcast (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ ]*[a-f0-9]+:[ ]*62 c3 8c 1d 66\s*\(bad\)
+[ ]*[a-f0-9]+:[ ]*90\s*nop
+[ ]*[a-f0-9]+:[ ]*66 90\s*xchg ax,ax
+[ ]*[a-f0-9]+:[ ]*66 90\s*xchg ax,ax
+[ ]*[a-f0-9]+:[ ]*62 c1 ff 38 2a 20\s*vcvtsi2sd xmm4,xmm0,\[eax\]{bad}
+#pass
diff --git a/gas/testsuite/gas/i386/bad-bcast.d b/gas/testsuite/gas/i386/bad-bcast.d
index 9fc474a42ff..4f829259994 100644
--- a/gas/testsuite/gas/i386/bad-bcast.d
+++ b/gas/testsuite/gas/i386/bad-bcast.d
@@ -7,8 +7,8 @@
Disassembly of section .text:
0+ <.text>:
- +[a-f0-9]+: 62 .byte 0x62
- +[a-f0-9]+: c3 ret
- +[a-f0-9]+: 8c 1d 66 90 66 90 mov %ds,0x90669066
- +[a-f0-9]+: 66 90 xchg %ax,%ax
-#pass
+ +[a-f0-9]+: 62 c3 8c 1d 66\s+\(bad\)
+ +[a-f0-9]+: 90\s+nop
+ +[a-f0-9]+: 66 90\s+xchg %ax,%ax
+ +[a-f0-9]+: 66 90\s+xchg %ax,%ax
+ +[a-f0-9]+: 62 c1 ff 38 2a 20\s+vcvtsi2sd \(%eax\){bad},%xmm0,%xmm4
diff --git a/gas/testsuite/gas/i386/bad-bcast.s b/gas/testsuite/gas/i386/bad-bcast.s
index 3e49b2238ed..6c55dcbbbd8 100644
--- a/gas/testsuite/gas/i386/bad-bcast.s
+++ b/gas/testsuite/gas/i386/bad-bcast.s
@@ -1,3 +1,5 @@
.text
# Invalid 16-bit broadcast with EVEX.W == 1.
.byte 0x62, 0xc3, 0x8c, 0x1d, 0x66, 0x90, 0x66, 0x90, 0x66, 0x90
+# Invalid vcvtsi2sd with EVEX.b == 1.
+ .byte 0x62,0xc1,0xff,0x38,0x2a,0x20
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 80959726d0e..680259b1c4e 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -646,6 +646,7 @@ if [gas_32_check] then {
run_dump_test "dw2-compress-2"
run_dump_test "dw2-compressed-2"
+ run_dump_test "bad-bcast-intel"
run_dump_test "bad-bcast"
run_dump_test "bad-size"
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index aa292233d4d..926f776de88 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -2422,6 +2422,7 @@ static struct
int zeroing;
int ll;
int b;
+ int no_broadcast;
}
vex;
static unsigned char need_vex;
@@ -11059,23 +11060,25 @@ intel_operand_size (int bytemode, int sizeflag)
{
if (vex.b)
{
- switch (bytemode)
- {
- case x_mode:
- case evex_half_bcst_xmmq_mode:
- if (vex.w)
- oappend ("QWORD PTR ");
- else
- oappend ("DWORD PTR ");
- break;
- case xh_mode:
- case evex_half_bcst_xmmqh_mode:
- case evex_half_bcst_xmmqdh_mode:
- oappend ("WORD PTR ");
- break;
- default:
- abort ();
- }
+ if (!vex.no_broadcast)
+ switch (bytemode)
+ {
+ case x_mode:
+ case evex_half_bcst_xmmq_mode:
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ break;
+ case xh_mode:
+ case evex_half_bcst_xmmqh_mode:
+ case evex_half_bcst_xmmqdh_mode:
+ oappend ("WORD PTR ");
+ break;
+ default:
+ vex.no_broadcast = 1;
+ break;
+ }
return;
}
switch (bytemode)
@@ -11908,69 +11911,71 @@ OP_E_memory (int bytemode, int sizeflag)
if (vex.b)
{
evex_used |= EVEX_b_used;
- if (bytemode == xh_mode)
- {
- if (vex.w)
- {
- oappend ("{bad}");
- }
- else
- {
- switch (vex.length)
- {
- case 128:
- oappend ("{1to8}");
- break;
- case 256:
- oappend ("{1to16}");
- break;
- case 512:
- oappend ("{1to32}");
- break;
- default:
- abort ();
- }
- }
- }
- else if (vex.w
- || bytemode == evex_half_bcst_xmmqdh_mode
- || bytemode == evex_half_bcst_xmmq_mode)
+ if (!vex.no_broadcast)
{
- switch (vex.length)
+ if (bytemode == xh_mode)
{
- case 128:
- oappend ("{1to2}");
- break;
- case 256:
- oappend ("{1to4}");
- break;
- case 512:
- oappend ("{1to8}");
- break;
- default:
- abort ();
+ if (vex.w)
+ oappend ("{bad}");
+ else
+ {
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("{1to8}");
+ break;
+ case 256:
+ oappend ("{1to16}");
+ break;
+ case 512:
+ oappend ("{1to32}");
+ break;
+ default:
+ abort ();
+ }
+ }
}
- }
- else if (bytemode == x_mode
- || bytemode == evex_half_bcst_xmmqh_mode)
- {
- switch (vex.length)
+ else if (vex.w
+ || bytemode == evex_half_bcst_xmmqdh_mode
+ || bytemode == evex_half_bcst_xmmq_mode)
{
- case 128:
- oappend ("{1to4}");
- break;
- case 256:
- oappend ("{1to8}");
- break;
- case 512:
- oappend ("{1to16}");
- break;
- default:
- abort ();
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("{1to2}");
+ break;
+ case 256:
+ oappend ("{1to4}");
+ break;
+ case 512:
+ oappend ("{1to8}");
+ break;
+ default:
+ abort ();
+ }
+ }
+ else if (bytemode == x_mode
+ || bytemode == evex_half_bcst_xmmqh_mode)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("{1to4}");
+ break;
+ case 256:
+ oappend ("{1to8}");
+ break;
+ case 512:
+ oappend ("{1to16}");
+ break;
+ default:
+ abort ();
+ }
}
+ else
+ vex.no_broadcast = 1;
}
- else
- /* If operand doesn't allow broadcast, vex.b should be 0. */
+ if (vex.no_broadcast)
oappend ("{bad}");
}
}
@@ -12685,6 +12690,8 @@ OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
if (bytemode == tmm_mode)
modrm.reg = reg;
+ else if (bytemode == scalar_mode)
+ vex.no_broadcast = 1;
print_vector_reg (reg, bytemode);
}
--
2.33.0

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6257
0026-opcodes-Make-i386-dis.c-thread-safe.patch Normal file
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0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch Normal file
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@ -0,0 +1,423 @@
From 2235ecb8afebeb56baf29eb98de34cfa1b95f697 Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 14 Jan 2022 10:54:21 +0100
Subject: [PATCH] x86: reduce AVX512-FP16 set of insns decoded through
vex_w_table[]
Like already indicated during review of the original submission, there's
really only very few insns where going through this table is easier /
cheaper than using suitable macros. Utilize %XH more and introduce
similar %XS and %XD (which subsequently can be used for further table
size reduction).
While there also switch to using oappend() in 'XH' macro processing.
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 9c8156ac11e..64a43ce02a1 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -375,17 +375,17 @@
{ "vfmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
{ "v4fnmaddss", { XMScalar, VexScalar, Mxmm }, 0 },
},
- /* PREFIX_EVEX_0F3A08_W_0 */
+ /* PREFIX_EVEX_0F3A08 */
{
- { "vrndscaleph", { XM, EXxh, EXxEVexS, Ib }, 0 },
+ { "vrndscalep%XH", { XM, EXxh, EXxEVexS, Ib }, 0 },
{ Bad_Opcode },
- { "vrndscaleps", { XM, EXx, EXxEVexS, Ib }, 0 },
+ { "vrndscalep%XS", { XM, EXx, EXxEVexS, Ib }, 0 },
},
- /* PREFIX_EVEX_0F3A0A_W_0 */
+ /* PREFIX_EVEX_0F3A0A */
{
- { "vrndscalesh", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 },
+ { "vrndscales%XH", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 },
{ Bad_Opcode },
- { "vrndscaless", { XMScalar, VexScalar, EXd, EXxEVexS, Ib }, 0 },
+ { "vrndscales%XS", { XMScalar, VexScalar, EXd, EXxEVexS, Ib }, 0 },
},
/* PREFIX_EVEX_0F3A26 */
{
@@ -482,27 +482,18 @@
{ "vmulp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
{ "vmuls%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
},
- /* PREFIX_EVEX_MAP5_5A_W_0 */
+ /* PREFIX_EVEX_MAP5_5A */
{
- { "vcvtph2pd", { XM, EXxmmqdh, EXxEVexS }, 0 },
- { "vcvtsh2sd", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vcvtp%XH2pd", { XM, EXxmmqdh, EXxEVexS }, 0 },
+ { "vcvts%XH2sd", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vcvtp%XD2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
+ { "vcvts%XD2sh", { XMM, VexScalar, EXq, EXxEVexR }, 0 },
},
- /* PREFIX_EVEX_MAP5_5A_W_1 */
+ /* PREFIX_EVEX_MAP5_5B */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "vcvtpd2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
- { "vcvtsd2sh", { XMM, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* PREFIX_EVEX_MAP5_5B_W_0 */
- {
- { "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
- { "vcvttph2dq", { XM, EXxmmqh, EXxEVexS }, 0 },
- { "vcvtph2dq", { XM, EXxmmqh, EXxEVexR }, 0 },
- },
- /* PREFIX_EVEX_MAP5_5B_W_1 */
- {
- { "vcvtqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
+ { VEX_W_TABLE (EVEX_W_MAP5_5B_P_0) },
+ { "vcvttp%XH2dq", { XM, EXxmmqh, EXxEVexS }, 0 },
+ { "vcvtp%XH2dq", { XM, EXxmmqh, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_5C */
{
@@ -526,47 +517,47 @@
},
/* PREFIX_EVEX_MAP5_78 */
{
- { VEX_W_TABLE (EVEX_W_MAP5_78_P_0) },
+ { "vcvttp%XH2udq", { XM, EXxmmqh, EXxEVexS }, 0 },
{ "vcvttsh2usi", { Gdq, EXw, EXxEVexS }, 0 },
- { VEX_W_TABLE (EVEX_W_MAP5_78_P_2) },
+ { "vcvttp%XH2uqq", { XM, EXxmmqdh, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_MAP5_79 */
{
- { VEX_W_TABLE (EVEX_W_MAP5_79_P_0) },
+ { "vcvtp%XH2udq", { XM, EXxmmqh, EXxEVexR }, 0 },
{ "vcvtsh2usi", { Gdq, EXw, EXxEVexR }, 0 },
- { VEX_W_TABLE (EVEX_W_MAP5_79_P_2) },
+ { "vcvtp%XH2uqq", { XM, EXxmmqdh, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_7A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_MAP5_7A_P_2) },
+ { "vcvttp%XH2qq", { XM, EXxmmqdh, EXxEVexS }, 0 },
{ VEX_W_TABLE (EVEX_W_MAP5_7A_P_3) },
},
/* PREFIX_EVEX_MAP5_7B */
{
{ Bad_Opcode },
{ "vcvtusi2sh{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
- { VEX_W_TABLE (EVEX_W_MAP5_7B_P_2) },
+ { "vcvtp%XH2qq", { XM, EXxmmqdh, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_7C */
{
- { VEX_W_TABLE (EVEX_W_MAP5_7C_P_0) },
+ { "vcvttp%XH2uw", { XM, EXxh, EXxEVexS }, 0 },
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_MAP5_7C_P_2) },
+ { "vcvttp%XH2w", { XM, EXxh, EXxEVexS }, 0 },
},
- /* PREFIX_EVEX_MAP5_7D_W_0 */
+ /* PREFIX_EVEX_MAP5_7D */
{
- { "vcvtph2uw", { XM, EXxh, EXxEVexR }, 0 },
- { "vcvtw2ph", { XM, EXxh, EXxEVexR }, 0 },
- { "vcvtph2w", { XM, EXxh, EXxEVexR }, 0 },
- { "vcvtuw2ph", { XM, EXxh, EXxEVexR }, 0 },
+ { "vcvtp%XH2uw", { XM, EXxh, EXxEVexR }, 0 },
+ { "vcvtw2p%XH", { XM, EXxh, EXxEVexR }, 0 },
+ { "vcvtp%XH2w", { XM, EXxh, EXxEVexR }, 0 },
+ { "vcvtuw2p%XH", { XM, EXxh, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP6_13 */
{
- { VEX_W_TABLE (EVEX_W_MAP6_13_P_0) },
+ { "vcvts%XH2ss", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_MAP6_13_P_2) },
+ { "vcvtp%XH2psx", { XM, EXxmmqh, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_MAP6_56 */
{
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index 62c3d3b9afb..fc0a0791d1d 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -550,19 +550,11 @@
{ Bad_Opcode },
{ "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
},
- /* EVEX_W_0F3A08 */
- {
- { PREFIX_TABLE (PREFIX_EVEX_0F3A08_W_0) },
- },
/* EVEX_W_0F3A09 */
{
{ Bad_Opcode },
{ "vrndscalepd", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
},
- /* EVEX_W_0F3A0A */
- {
- { PREFIX_TABLE (PREFIX_EVEX_0F3A0A_W_0) },
- },
/* EVEX_W_0F3A0B */
{
{ Bad_Opcode },
@@ -636,62 +628,13 @@
{ Bad_Opcode },
{ "vpshrdw", { XM, Vex, EXx, Ib }, 0 },
},
- /* EVEX_W_MAP5_5A */
- {
- { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A_W_0) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A_W_1) },
- },
- /* EVEX_W_MAP5_5B */
- {
- { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B_W_0) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B_W_1) },
- },
- /* EVEX_W_MAP5_78_P_0 */
- {
- { "vcvttph2udq", { XM, EXxmmqh, EXxEVexS }, 0 },
- },
- /* EVEX_W_MAP5_78_P_2 */
- {
- { "vcvttph2uqq", { XM, EXxmmqdh, EXxEVexS }, 0 },
- },
- /* EVEX_W_MAP5_79_P_0 */
- {
- { "vcvtph2udq", { XM, EXxmmqh, EXxEVexR }, 0 },
- },
- /* EVEX_W_MAP5_79_P_2 */
+ /* EVEX_W_MAP5_5B_P_0 */
{
- { "vcvtph2uqq", { XM, EXxmmqdh, EXxEVexR }, 0 },
- },
- /* EVEX_W_MAP5_7A_P_2 */
- {
- { "vcvttph2qq", { XM, EXxmmqdh, EXxEVexS }, 0 },
+ { "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
+ { "vcvtqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
},
/* EVEX_W_MAP5_7A_P_3 */
{
{ "vcvtudq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
{ "vcvtuqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_MAP5_7B_P_2 */
- {
- { "vcvtph2qq", { XM, EXxmmqdh, EXxEVexR }, 0 },
- },
- /* EVEX_W_MAP5_7C_P_0 */
- {
- { "vcvttph2uw", { XM, EXxh, EXxEVexS }, 0 },
- },
- /* EVEX_W_MAP5_7C_P_2 */
- {
- { "vcvttph2w", { XM, EXxh, EXxEVexS }, 0 },
- },
- /* EVEX_W_MAP5_7D */
- {
- { PREFIX_TABLE (PREFIX_EVEX_MAP5_7D_W_0) },
- },
- /* EVEX_W_MAP6_13_P_0 */
- {
- { "vcvtsh2ss", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
- },
- /* EVEX_W_MAP6_13_P_2 */
- {
- { "vcvtph2psx", { XM, EXxmmqh, EXxEVexS }, 0 },
- },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index d79c78c1793..11cc257bb2e 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -593,9 +593,9 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
- { VEX_W_TABLE (EVEX_W_0F3A08) },
+ { PREFIX_TABLE (PREFIX_EVEX_0F3A08) },
{ VEX_W_TABLE (EVEX_W_0F3A09) },
- { VEX_W_TABLE (EVEX_W_0F3A0A) },
+ { PREFIX_TABLE (PREFIX_EVEX_0F3A0A) },
{ VEX_W_TABLE (EVEX_W_0F3A0B) },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -976,8 +976,8 @@ static const struct dis386 evex_table[][256] = {
/* 58 */
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_58) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_59) },
- { VEX_W_TABLE (EVEX_W_MAP5_5A) },
- { VEX_W_TABLE (EVEX_W_MAP5_5B) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5C) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5D) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5E) },
@@ -1015,7 +1015,7 @@ static const struct dis386 evex_table[][256] = {
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7A) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7B) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7C) },
- { VEX_W_TABLE (EVEX_W_MAP5_7D) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP5_7D) },
{ "vmovw", { Edw, XMScalar }, PREFIX_DATA },
{ Bad_Opcode },
/* 80 */
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 4e0e1559339..afc3743e4e8 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1212,8 +1212,8 @@ enum
PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB,
- PREFIX_EVEX_0F3A08_W_0,
- PREFIX_EVEX_0F3A0A_W_0,
+ PREFIX_EVEX_0F3A08,
+ PREFIX_EVEX_0F3A0A,
PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A27,
PREFIX_EVEX_0F3A56,
@@ -1233,10 +1233,8 @@ enum
PREFIX_EVEX_MAP5_51,
PREFIX_EVEX_MAP5_58,
PREFIX_EVEX_MAP5_59,
- PREFIX_EVEX_MAP5_5A_W_0,
- PREFIX_EVEX_MAP5_5A_W_1,
- PREFIX_EVEX_MAP5_5B_W_0,
- PREFIX_EVEX_MAP5_5B_W_1,
+ PREFIX_EVEX_MAP5_5A,
+ PREFIX_EVEX_MAP5_5B,
PREFIX_EVEX_MAP5_5C,
PREFIX_EVEX_MAP5_5D,
PREFIX_EVEX_MAP5_5E,
@@ -1246,7 +1244,7 @@ enum
PREFIX_EVEX_MAP5_7A,
PREFIX_EVEX_MAP5_7B,
PREFIX_EVEX_MAP5_7C,
- PREFIX_EVEX_MAP5_7D_W_0,
+ PREFIX_EVEX_MAP5_7D,
PREFIX_EVEX_MAP6_13,
PREFIX_EVEX_MAP6_56,
@@ -1746,9 +1744,7 @@ enum
EVEX_W_0F3883,
EVEX_W_0F3A05,
- EVEX_W_0F3A08,
EVEX_W_0F3A09,
- EVEX_W_0F3A0A,
EVEX_W_0F3A0B,
EVEX_W_0F3A18_L_n,
EVEX_W_0F3A19_L_n,
@@ -1765,21 +1761,8 @@ enum
EVEX_W_0F3A70,
EVEX_W_0F3A72,
- EVEX_W_MAP5_5A,
- EVEX_W_MAP5_5B,
- EVEX_W_MAP5_78_P_0,
- EVEX_W_MAP5_78_P_2,
- EVEX_W_MAP5_79_P_0,
- EVEX_W_MAP5_79_P_2,
- EVEX_W_MAP5_7A_P_2,
+ EVEX_W_MAP5_5B_P_0,
EVEX_W_MAP5_7A_P_3,
- EVEX_W_MAP5_7B_P_2,
- EVEX_W_MAP5_7C_P_0,
- EVEX_W_MAP5_7C_P_2,
- EVEX_W_MAP5_7D,
-
- EVEX_W_MAP6_13_P_0,
- EVEX_W_MAP6_13_P_2,
};
typedef void (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
@@ -1840,7 +1823,9 @@ struct dis386 {
"XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
register operands and no broadcast.
"XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
+ "XD" => print 'd' if EVEX.W=1, EVEX.W=0 is not a valid encoding
"XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
+ "XS" => print 's' if EVEX.W=0, EVEX.W=1 is not a valid encoding
"XV" => print "{vex3}" pseudo prefix
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
being false, or no operand at all in 64bit mode, or if suffix_always
@@ -10496,6 +10481,23 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
}
break;
case 'D':
+ if (l == 1)
+ {
+ switch (last[0])
+ {
+ case 'X':
+ if (ins->vex.w)
+ *ins->obufp++ = 'd';
+ else
+ oappend (ins, "{bad}");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ }
+ if (l)
+ abort ();
if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
break;
USED_REX (REX_W);
@@ -10582,13 +10584,7 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
if (ins->vex.w == 0)
*ins->obufp++ = 'h';
else
- {
- *ins->obufp++ = '{';
- *ins->obufp++ = 'b';
- *ins->obufp++ = 'a';
- *ins->obufp++ = 'd';
- *ins->obufp++ = '}';
- }
+ oappend (ins, "{bad}");
}
else
abort ();
@@ -10752,9 +10748,13 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
}
}
+ break;
}
- else if (l == 1 && last[0] == 'L')
+ if (l != 1)
+ abort ();
+ switch (last[0])
{
+ case 'L':
if (ins->address_mode == mode_64bit
&& !(ins->prefixes & PREFIX_ADDR))
{
@@ -10764,9 +10764,15 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
}
goto case_S;
+ case 'X':
+ if (!ins->vex.w)
+ *ins->obufp++ = 's';
+ else
+ oappend (ins, "{bad}");
+ break;
+ default:
+ abort ();
}
- else
- abort ();
break;
case 'V':
if (l == 0)
--
2.33.0

600
0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch Normal file
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@ -0,0 +1,600 @@
From 740a1e791175987e28cc39dbd11e3fc152ffc40b Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 14 Jan 2022 10:54:55 +0100
Subject: [PATCH] x86: reduce AVX512 FP set of insns decoded through
vex_w_table[]
Like for AVX512-FP16, there's not that many FP insns where going through
this table is easier / cheaper than using suitable macros. Utilize %XS
and %XD more to eliminate a fair number of table entries.
While doing this I noticed a few anomalies. Where lines get touched /
moved anyway, these are being addressed right here:
- vmovshdup used EXx for its 2nd operand, thus displaying seemingly
valid broadcast when EVEX.b is set with a memory operand; use
EXEvexXNoBcst instead just like vmovsldup already does
- vmovlhps used EXx for its 3rd operand, when all sibling entries use
EXq; switch to EXq there for consistency (the two differ only for
memory operands)
diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h
index 7a372ce8c0b..2d35bf2a589 100644
--- a/opcodes/i386-dis-evex-mod.h
+++ b/opcodes/i386-dis-evex-mod.h
@@ -1,7 +1,7 @@
{
/* MOD_EVEX_0F12_PREFIX_0 */
{ "vmovlpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F12_P_0_M_1) },
+ { "vmovhlp%XS", { XMM, Vex, EXq }, 0 },
},
{
/* MOD_EVEX_0F12_PREFIX_2 */
@@ -14,7 +14,7 @@
{
/* MOD_EVEX_0F16_PREFIX_0 */
{ "vmovhpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F16_P_0_M_1) },
+ { "vmovlhp%XS", { XMM, Vex, EXq }, 0 },
},
{
/* MOD_EVEX_0F16_PREFIX_2 */
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 64a43ce02a1..fc5439a1fec 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -1,28 +1,28 @@
/* PREFIX_EVEX_0F10 */
{
{ "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F10_P_1) },
+ { "vmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
{ "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F10_P_3) },
+ { "vmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
},
/* PREFIX_EVEX_0F11 */
{
{ "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F11_P_1) },
+ { "vmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
{ "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F11_P_3) },
+ { "vmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
},
/* PREFIX_EVEX_0F12 */
{
{ MOD_TABLE (MOD_EVEX_0F12_PREFIX_0) },
- { VEX_W_TABLE (EVEX_W_0F12_P_1) },
+ { "vmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
{ MOD_TABLE (MOD_EVEX_0F12_PREFIX_2) },
- { VEX_W_TABLE (EVEX_W_0F12_P_3) },
+ { "vmov%XDdup", { XM, EXymmq }, 0 },
},
/* PREFIX_EVEX_0F16 */
{
{ MOD_TABLE (MOD_EVEX_0F16_PREFIX_0) },
- { VEX_W_TABLE (EVEX_W_0F16_P_1) },
+ { "vmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
{ MOD_TABLE (MOD_EVEX_0F16_PREFIX_2) },
},
/* PREFIX_EVEX_0F2A */
@@ -35,64 +35,64 @@
/* PREFIX_EVEX_0F51 */
{
{ "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F51_P_1) },
+ { "vsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F51_P_3) },
+ { "vsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F58 */
{
{ "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F58_P_1) },
+ { "vadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F58_P_3) },
+ { "vadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F59 */
{
{ "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F59_P_1) },
+ { "vmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F59_P_3) },
+ { "vmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5A */
{
- { VEX_W_TABLE (EVEX_W_0F5A_P_0) },
- { VEX_W_TABLE (EVEX_W_0F5A_P_1) },
- { VEX_W_TABLE (EVEX_W_0F5A_P_2) },
- { VEX_W_TABLE (EVEX_W_0F5A_P_3) },
+ { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
+ { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+ { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
+ { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5B */
{
{ VEX_W_TABLE (EVEX_W_0F5B_P_0) },
- { VEX_W_TABLE (EVEX_W_0F5B_P_1) },
- { VEX_W_TABLE (EVEX_W_0F5B_P_2) },
+ { "vcvttp%XS2dq", { XM, EXx, EXxEVexS }, 0 },
+ { "vcvtp%XS2dq", { XM, EXx, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5C */
{
{ "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5C_P_1) },
+ { "vsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5C_P_3) },
+ { "vsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5D */
{
{ "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5D_P_1) },
+ { "vmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
{ "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5D_P_3) },
+ { "vmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F5E */
{
{ "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5E_P_1) },
+ { "vdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5E_P_3) },
+ { "vdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5F */
{
{ "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5F_P_1) },
+ { "vmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
{ "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5F_P_3) },
+ { "vmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F6F */
{
@@ -152,16 +152,16 @@
/* PREFIX_EVEX_0FC2 */
{
{ "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0FC2_P_1) },
+ { "vcmps%XS", { MaskG, VexScalar, EXd, EXxEVexS, CMP }, 0 },
{ "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0FC2_P_3) },
+ { "vcmps%XD", { MaskG, VexScalar, EXq, EXxEVexS, CMP }, 0 },
},
/* PREFIX_EVEX_0FE6 */
{
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0FE6_P_1) },
- { VEX_W_TABLE (EVEX_W_0FE6_P_2) },
- { VEX_W_TABLE (EVEX_W_0FE6_P_3) },
+ { "vcvttp%XD2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
+ { "vcvtp%XD2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F3810 */
{
@@ -185,7 +185,7 @@
{
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F3813_P_1) },
- { VEX_W_TABLE (EVEX_W_0F3813_P_2) },
+ { "vcvtph2p%XS", { XM, EXxmmq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F3814 */
{
@@ -322,7 +322,7 @@
/* PREFIX_EVEX_0F3852 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_0F3852_P_1) },
+ { "vdpbf16p%XS", { XM, Vex, EXx }, 0 },
{ "vpdpwssd", { XM, Vex, EXx }, 0 },
{ "vp4dpwssd", { XM, Vex, EXxmm }, 0 },
},
@@ -343,9 +343,9 @@
/* PREFIX_EVEX_0F3872 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_0F3872_P_1) },
+ { "vcvtnep%XS2bf16%XY", { XMxmmq, EXx }, 0 },
{ VEX_W_TABLE (EVEX_W_0F3872_P_2) },
- { VEX_W_TABLE (EVEX_W_0F3872_P_3) },
+ { "vcvtne2p%XS2bf16", { XM, Vex, EXx}, 0 },
},
/* PREFIX_EVEX_0F389A */
{
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index fc0a0791d1d..9b4bb6a2924 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -1,136 +1,8 @@
- /* EVEX_W_0F10_P_1 */
- {
- { "vmovss", { XMScalar, VexScalarR, EXd }, 0 },
- },
- /* EVEX_W_0F10_P_3 */
- {
- { Bad_Opcode },
- { "vmovsd", { XMScalar, VexScalarR, EXq }, 0 },
- },
- /* EVEX_W_0F11_P_1 */
- {
- { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
- },
- /* EVEX_W_0F11_P_3 */
- {
- { Bad_Opcode },
- { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
- },
- /* EVEX_W_0F12_P_0_M_1 */
- {
- { "vmovhlps", { XMM, Vex, EXq }, 0 },
- },
- /* EVEX_W_0F12_P_1 */
- {
- { "vmovsldup", { XM, EXEvexXNoBcst }, 0 },
- },
- /* EVEX_W_0F12_P_3 */
- {
- { Bad_Opcode },
- { "vmovddup", { XM, EXymmq }, 0 },
- },
- /* EVEX_W_0F16_P_0_M_1 */
- {
- { "vmovlhps", { XMM, Vex, EXx }, 0 },
- },
- /* EVEX_W_0F16_P_1 */
- {
- { "vmovshdup", { XM, EXx }, 0 },
- },
- /* EVEX_W_0F51_P_1 */
- {
- { "vsqrtss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F51_P_3 */
- {
- { Bad_Opcode },
- { "vsqrtsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F58_P_1 */
- {
- { "vaddss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F58_P_3 */
- {
- { Bad_Opcode },
- { "vaddsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F59_P_1 */
- {
- { "vmulss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F59_P_3 */
- {
- { Bad_Opcode },
- { "vmulsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5A_P_0 */
- {
- { "vcvtps2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5A_P_1 */
- {
- { "vcvtss2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5A_P_2 */
- {
- { Bad_Opcode },
- { "vcvtpd2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5A_P_3 */
- {
- { Bad_Opcode },
- { "vcvtsd2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
/* EVEX_W_0F5B_P_0 */
{
{ "vcvtdq2ps", { XM, EXx, EXxEVexR }, 0 },
{ "vcvtqq2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_0F5B_P_1 */
- {
- { "vcvttps2dq", { XM, EXx, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5B_P_2 */
- {
- { "vcvtps2dq", { XM, EXx, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5C_P_1 */
- {
- { "vsubss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5C_P_3 */
- {
- { Bad_Opcode },
- { "vsubsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5D_P_1 */
- {
- { "vminss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5D_P_3 */
- {
- { Bad_Opcode },
- { "vminsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5E_P_1 */
- {
- { "vdivss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5E_P_3 */
- {
- { Bad_Opcode },
- { "vdivsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5F_P_1 */
- {
- { "vmaxss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5F_P_3 */
- {
- { Bad_Opcode },
- { "vmaxsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
- },
/* EVEX_W_0F62 */
{
{ "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
@@ -258,15 +130,6 @@
{ "vmovdqu8", { EXxS, XM }, 0 },
{ "vmovdqu16", { EXxS, XM }, 0 },
},
- /* EVEX_W_0FC2_P_1 */
- {
- { "vcmpss", { MaskG, VexScalar, EXd, EXxEVexS, CMP }, 0 },
- },
- /* EVEX_W_0FC2_P_3 */
- {
- { Bad_Opcode },
- { "vcmpsd", { MaskG, VexScalar, EXq, EXxEVexS, CMP }, 0 },
- },
/* EVEX_W_0FD2 */
{
{ "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
@@ -291,16 +154,6 @@
{ "vcvtdq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
{ "vcvtqq2pd", { XM, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_0FE6_P_2 */
- {
- { Bad_Opcode },
- { "vcvttpd2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
- },
- /* EVEX_W_0FE6_P_3 */
- {
- { Bad_Opcode },
- { "vcvtpd2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
- },
/* EVEX_W_0FE7 */
{
{ "vmovntdq", { EXEvexXNoBcst, XM }, PREFIX_DATA },
@@ -332,11 +185,6 @@
{
{ "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
},
- /* EVEX_W_0F380D */
- {
- { Bad_Opcode },
- { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
- },
/* EVEX_W_0F3810_P_1 */
{
{ "vpmovuswb", { EXxmmq, XM }, 0 },
@@ -368,10 +216,6 @@
{
{ "vpmovusdw", { EXxmmq, XM }, 0 },
},
- /* EVEX_W_0F3813_P_2 */
- {
- { "vcvtph2ps", { XM, EXxmmq, EXxEVexS }, 0 },
- },
/* EVEX_W_0F3814_P_1 */
{
{ "vpmovusqw", { EXxmmqd, XM }, 0 },
@@ -492,11 +336,6 @@
{
{ MOD_TABLE (MOD_EVEX_0F383A_P_1_W_0) },
},
- /* EVEX_W_0F3852_P_1 */
- {
- { "vdpbf16ps", { XM, Vex, EXx }, 0 },
- { Bad_Opcode },
- },
/* EVEX_W_0F3859 */
{
{ "vbroadcasti32x2", { XM, EXq }, PREFIX_DATA },
@@ -517,21 +356,11 @@
{ Bad_Opcode },
{ "vpshldvw", { XM, Vex, EXx }, PREFIX_DATA },
},
- /* EVEX_W_0F3872_P_1 */
- {
- { "vcvtneps2bf16%XY", { XMxmmq, EXx }, 0 },
- { Bad_Opcode },
- },
/* EVEX_W_0F3872_P_2 */
{
{ Bad_Opcode },
{ "vpshrdvw", { XM, Vex, EXx }, 0 },
},
- /* EVEX_W_0F3872_P_3 */
- {
- { "vcvtne2ps2bf16", { XM, Vex, EXx}, 0 },
- { Bad_Opcode },
- },
/* EVEX_W_0F387A */
{
{ MOD_TABLE (MOD_EVEX_0F387A_W_0) },
@@ -545,21 +374,6 @@
{ Bad_Opcode },
{ "vpmultishiftqb", { XM, Vex, EXx }, PREFIX_DATA },
},
- /* EVEX_W_0F3A05 */
- {
- { Bad_Opcode },
- { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
- },
- /* EVEX_W_0F3A09 */
- {
- { Bad_Opcode },
- { "vrndscalepd", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- },
- /* EVEX_W_0F3A0B */
- {
- { Bad_Opcode },
- { "vrndscalesd", { XMScalar, VexScalar, EXq, EXxEVexS, Ib }, PREFIX_DATA },
- },
/* EVEX_W_0F3A18_L_n */
{
{ "vinsertf32x4", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 11cc257bb2e..5d621cf1557 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -307,7 +307,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
{ VEX_W_TABLE (VEX_W_0F380C) },
- { VEX_W_TABLE (EVEX_W_0F380D) },
+ { "vpermilp%XD", { XM, Vex, EXx }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
@@ -589,14 +589,14 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ "valign%DQ", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ VEX_W_TABLE (VEX_W_0F3A04) },
- { VEX_W_TABLE (EVEX_W_0F3A05) },
+ { "vpermilp%XD", { XM, EXx, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
{ PREFIX_TABLE (PREFIX_EVEX_0F3A08) },
- { VEX_W_TABLE (EVEX_W_0F3A09) },
+ { "vrndscalep%XD", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
{ PREFIX_TABLE (PREFIX_EVEX_0F3A0A) },
- { VEX_W_TABLE (EVEX_W_0F3A0B) },
+ { "vrndscales%XD", { XMScalar, VexScalar, EXq, EXxEVexS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index afc3743e4e8..ad560b1899c 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1621,36 +1621,7 @@ enum
VEX_W_0FXOP_09_E2_L_0,
VEX_W_0FXOP_09_E3_L_0,
- EVEX_W_0F10_P_1,
- EVEX_W_0F10_P_3,
- EVEX_W_0F11_P_1,
- EVEX_W_0F11_P_3,
- EVEX_W_0F12_P_0_M_1,
- EVEX_W_0F12_P_1,
- EVEX_W_0F12_P_3,
- EVEX_W_0F16_P_0_M_1,
- EVEX_W_0F16_P_1,
- EVEX_W_0F51_P_1,
- EVEX_W_0F51_P_3,
- EVEX_W_0F58_P_1,
- EVEX_W_0F58_P_3,
- EVEX_W_0F59_P_1,
- EVEX_W_0F59_P_3,
- EVEX_W_0F5A_P_0,
- EVEX_W_0F5A_P_1,
- EVEX_W_0F5A_P_2,
- EVEX_W_0F5A_P_3,
EVEX_W_0F5B_P_0,
- EVEX_W_0F5B_P_1,
- EVEX_W_0F5B_P_2,
- EVEX_W_0F5C_P_1,
- EVEX_W_0F5C_P_3,
- EVEX_W_0F5D_P_1,
- EVEX_W_0F5D_P_3,
- EVEX_W_0F5E_P_1,
- EVEX_W_0F5E_P_3,
- EVEX_W_0F5F_P_1,
- EVEX_W_0F5F_P_3,
EVEX_W_0F62,
EVEX_W_0F66,
EVEX_W_0F6A,
@@ -1678,15 +1649,11 @@ enum
EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2,
EVEX_W_0F7F_P_3,
- EVEX_W_0FC2_P_1,
- EVEX_W_0FC2_P_3,
EVEX_W_0FD2,
EVEX_W_0FD3,
EVEX_W_0FD4,
EVEX_W_0FD6,
EVEX_W_0FE6_P_1,
- EVEX_W_0FE6_P_2,
- EVEX_W_0FE6_P_3,
EVEX_W_0FE7,
EVEX_W_0FF2,
EVEX_W_0FF3,
@@ -1694,7 +1661,7 @@ enum
EVEX_W_0FFA,
EVEX_W_0FFB,
EVEX_W_0FFE,
- EVEX_W_0F380D,
+
EVEX_W_0F3810_P_1,
EVEX_W_0F3810_P_2,
EVEX_W_0F3811_P_1,
@@ -1702,7 +1669,6 @@ enum
EVEX_W_0F3812_P_1,
EVEX_W_0F3812_P_2,
EVEX_W_0F3813_P_1,
- EVEX_W_0F3813_P_2,
EVEX_W_0F3814_P_1,
EVEX_W_0F3815_P_1,
EVEX_W_0F3819_L_n,
@@ -1731,21 +1697,15 @@ enum
EVEX_W_0F3835_P_2,
EVEX_W_0F3837,
EVEX_W_0F383A_P_1,
- EVEX_W_0F3852_P_1,
EVEX_W_0F3859,
EVEX_W_0F385A_M_0_L_n,
EVEX_W_0F385B_M_0_L_2,
EVEX_W_0F3870,
- EVEX_W_0F3872_P_1,
EVEX_W_0F3872_P_2,
- EVEX_W_0F3872_P_3,
EVEX_W_0F387A,
EVEX_W_0F387B,
EVEX_W_0F3883,
- EVEX_W_0F3A05,
- EVEX_W_0F3A09,
- EVEX_W_0F3A0B,
EVEX_W_0F3A18_L_n,
EVEX_W_0F3A19_L_n,
EVEX_W_0F3A1A_L_2,
--
2.33.0

204
0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch Normal file
View File

@ -0,0 +1,204 @@
From 928c8d70c82feea45683b43e324cd2079d4ee31d Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 14 Jan 2022 10:55:42 +0100
Subject: [PATCH] x86: consistently use scalar_mode for AVX512-FP16 scalar
insns
For some reason the original AVFX512F insns were not taken as a basis
here, causing unnecessary divergence. While not an active issue, it is
still relevant to note that OP_XMM() has special treatment of e.g.
scalar_mode (marking broadcast as invalid). Such would better be
consistent for all sufficiently similar insns.
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index fc5439a1fec..140c4e850b4 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -440,7 +440,7 @@
},
/* PREFIX_EVEX_MAP5_1D */
{
- { "vcvtss2s%XH", { XMM, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vcvtss2s%XH", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ Bad_Opcode },
{ "vcvtps2p%XHx%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
},
@@ -470,24 +470,24 @@
/* PREFIX_EVEX_MAP5_51 */
{
{ "vsqrtp%XH", { XM, EXxh, EXxEVexR }, 0 },
- { "vsqrts%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
+ { "vsqrts%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_58 */
{
{ "vaddp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
- { "vadds%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
+ { "vadds%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_59 */
{
{ "vmulp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
- { "vmuls%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
+ { "vmuls%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_5A */
{
{ "vcvtp%XH2pd", { XM, EXxmmqdh, EXxEVexS }, 0 },
- { "vcvts%XH2sd", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vcvts%XH2sd", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
{ "vcvtp%XD2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
- { "vcvts%XD2sh", { XMM, VexScalar, EXq, EXxEVexR }, 0 },
+ { "vcvts%XD2sh", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_5B */
{
@@ -498,22 +498,22 @@
/* PREFIX_EVEX_MAP5_5C */
{
{ "vsubp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
- { "vsubs%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
+ { "vsubs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_5D */
{
{ "vminp%XH", { XM, Vex, EXxh, EXxEVexS }, 0 },
- { "vmins%XH", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vmins%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_MAP5_5E */
{
{ "vdivp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
- { "vdivs%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
+ { "vdivs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_5F */
{
{ "vmaxp%XH", { XM, Vex, EXxh, EXxEVexS }, 0 },
- { "vmaxs%XH", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vmaxs%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_MAP5_78 */
{
@@ -555,7 +555,7 @@
},
/* PREFIX_EVEX_MAP6_13 */
{
- { "vcvts%XH2ss", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vcvts%XH2ss", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
{ Bad_Opcode },
{ "vcvtp%XH2psx", { XM, EXxmmqh, EXxEVexS }, 0 },
},
@@ -569,9 +569,9 @@
/* PREFIX_EVEX_MAP6_57 */
{
{ Bad_Opcode },
- { "vfmaddcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vfmaddcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
{ Bad_Opcode },
- { "vfcmaddcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vfcmaddcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP6_D6 */
{
@@ -583,7 +583,7 @@
/* PREFIX_EVEX_MAP6_D7 */
{
{ Bad_Opcode },
- { "vfmulcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vfmulcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
{ Bad_Opcode },
- { "vfcmulcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vfcmulcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
},
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 5d621cf1557..fe39026a871 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -1216,7 +1216,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ "vscalefp%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vscalefs%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vscalefs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
/* 30 */
@@ -1241,7 +1241,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ "vgetexpp%XH", { XM, EXxh, EXxEVexS }, PREFIX_DATA },
- { "vgetexps%XH", { XMM, VexScalar, EXw, EXxEVexS }, PREFIX_DATA },
+ { "vgetexps%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1252,9 +1252,9 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ "vrcpp%XH", { XM, EXxh }, PREFIX_DATA },
- { "vrcps%XH", { XMM, VexScalar, EXw }, PREFIX_DATA },
+ { "vrcps%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA },
{ "vrsqrtp%XH", { XM, EXxh }, PREFIX_DATA },
- { "vrsqrts%XH", { XMM, VexScalar, EXw }, PREFIX_DATA },
+ { "vrsqrts%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA },
/* 50 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1338,13 +1338,13 @@ static const struct dis386 evex_table[][256] = {
{ "vfmsubadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
/* 98 */
{ "vfmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmadd132s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmsub132s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd132s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub132s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
/* A0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1356,13 +1356,13 @@ static const struct dis386 evex_table[][256] = {
{ "vfmsubadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
/* A8 */
{ "vfmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmadd213s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmsub213s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd213s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub213s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1374,13 +1374,13 @@ static const struct dis386 evex_table[][256] = {
{ "vfmsubadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
/* B8 */
{ "vfmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmadd231s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmsub231s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd231s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub231s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
/* C0 */
{ Bad_Opcode },
{ Bad_Opcode },
--
2.33.0

38
binutils.spec
View File

@ -1,7 +1,7 @@
Summary: Binary utilities
Name: binutils
Version: 2.37
Release: 8
Release: 9
License: GPLv3+
URL: https://sourceware.org/binutils
@ -33,6 +33,36 @@ Patch10: bfd-Close-the-file-descriptor-if-there-is-no-archive.patch
Patch11: binutils-AArch64-EFI.patch
Patch12: backport-0001-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch
Patch13: 0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch
Patch14: 0002-x86-drop-OP_Mask.patch
Patch15: 0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch
Patch16: 0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch
Patch17: 0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch
Patch18: 0006-x86-fold-duplicate-register-printing-code.patch
Patch19: 0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch
Patch20: 0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch
Patch21: 0009-x86-drop-vex_mode-and-vex_scalar_mode.patch
Patch22: 0010-x86-fold-duplicate-vector-register-printing-code.patch
Patch23: 0011-x86-drop-xmm_m-b-w-d-q-_mode.patch
Patch24: 0012-x86-drop-vex_scalar_w_dq_mode.patch
Patch25: 0013-x86-drop-dq-b-d-_mode.patch
Patch26: 0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch
Patch27: 0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch
Patch28: 0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch
Patch29: 0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch
Patch30: 0018-x86-ELF-fix-.tfloat-output.patch
Patch31: 0019-x86-ELF-fix-.ds.x-output.patch
Patch32: 0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch
Patch33: 0021-x86-introduce-.hfloat-directive.patch
Patch34: 0022-x86-Avoid-abort-on-invalid-broadcast.patch
Patch35: 0023-x86-Put-back-3-aborts-in-OP_E_memory.patch
Patch36: 0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch
Patch37: 0025-x86-Terminate-mnemonicendp-in-swap_operand.patch
Patch38: 0026-opcodes-Make-i386-dis.c-thread-safe.patch
Patch39: 0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch
Patch40: 0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch
Patch41: 0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch
Provides: bundled(libiberty)
@ -355,6 +385,12 @@ fi
%{_infodir}/bfd*info*
%changelog
* Tue Aug 11 2022 dingguangya <dingguangya1@huawei.com> - 2.37-9
- Type:requirements
- ID:NA
- SUG:NA
- DESC:Enable Intel AVX512_FP16 instructions
* Fri Aug 05 2022 maminjie <maminjie8@163.com> - 2.37-8
- Fix preserve_dates: cannot set time