!3 Add new patch: Accelerate adler32 by SVE instructions
From: @liqiang9102 Reviewed-by: @xiezhipeng1 Signed-off-by: @xiezhipeng1
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0005-Accelerate-Adler32-using-arm64-SVE-instructions.patch
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0005-Accelerate-Adler32-using-arm64-SVE-instructions.patch
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From 41ebac8b7d7485a5396ae25ce2412cafcd03f1a2 Mon Sep 17 00:00:00 2001
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From: liqiang <liqiang64@huawei.com>
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Date: Thu, 2 Sep 2021 17:31:48 +0800
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Subject: [PATCH] Accelerate Adler32 using arm64 SVE instructions
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This patch uses the SVE instruction set to rewrite the Adler32
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algorithm (checksum algorithm in libz). By dividing the data into
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blocks, a vector operation can complete a data block in parallel.
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Measured on a Taishan 1951 machine that supports 256bit width SVE,
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this algorithm is about 3~5 times faster than the algorithm implemented
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in C language in libz. The wider the bit width, the better the
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acceleration effect. Below are the results of my measured random
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data of 1M and 10M:
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[root@xxx adler32]# ./benchmark 1000000
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Libz alg: Time used: 608 us, 1644.7 Mb/s.
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SVE alg: Time used: 166 us, 6024.1 Mb/s.
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[root@xxx adler32]# ./benchmark 10000000
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Libz alg: Time used: 6484 us, 1542.3 Mb/s.
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SVE alg: Time used: 2034 us, 4916.4 Mb/s.
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On machines that support ARM64 sve instructions, this algorithm can
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effectively accelerate adler32, thereby achieving the effect of improving
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the performance of the basic compression algorithm libz.
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In the implementation of this patch, blocks can be of any size, so the
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algorithm can automatically adapt to SVE hardware with different bit
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widths without modifying the code.
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Signed-off-by: liqiang <liqiang64@huawei.com>
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---
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contrib/arm/adler32_sve.S | 129 ++++++++++++++++++++++++++++++++++++++
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1 file changed, 129 insertions(+)
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create mode 100644 contrib/arm/adler32_sve.S
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diff --git a/contrib/arm/adler32_sve.S b/contrib/arm/adler32_sve.S
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new file mode 100644
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index 0000000..97c5930
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--- /dev/null
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+++ b/contrib/arm/adler32_sve.S
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@@ -0,0 +1,129 @@
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+/******************************************************************************
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+ * Copyright (c) Huawei Technologies Co., Ltd. 2018-2020. All rights reserved.
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+ * iSulad licensed under the Mulan PSL v2.
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+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
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+ * You may obtain a copy of Mulan PSL v2 at:
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+ * http://license.coscl.org.cn/MulanPSL2
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+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
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+ * PURPOSE.
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+ * See the Mulan PSL v2 for more details.
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+ * Author: liqiang
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+ * Create: 2020-07-13
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+ * Description: Use SVE instruction to optimize adler32 algorithm.
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+ * Enhancement: 2020-10-13
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+ Automatically support different SVE vector length(128~2048).
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+ ******************************************************************************/
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+
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+.file "adler32_sve.S"
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+.text
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+.align 4
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+
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+//The supported sve vector length range is 128~2048 by this Adler_sequence
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+.Adler_sequence:
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+ .short 256,255,254,253,252,251,250,249,248,247,246,245,244,243,242,241,240,239,238,237,236,235,234,233,232,231,230,229,228,227,226,225,224,223,222,221,220,219,218,217,216,215,214,213,212,211,210,209,208,207,206,205,204,203,202,201,200,199,198,197,196,195,194,193,192,191,190,189,188,187,186,185,184,183,182,181,180,179,178,177,176,175,174,173,172,171,170,169,168,167,166,165,164,163,162,161,160,159,158,157,156,155,154,153,152,151,150,149,148,147,146,145,144,143,142,141,140,139,138,137,136,135,134,133,132,131,130,129,128,127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112,111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96,95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80,79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1
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+
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+.global adler32_sve
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+.type adler32_sve, %function
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+adler32_sve:
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+ // x0: unsigned long adler
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+ // x1: const unsigned char *buf
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+ // x2: unsigned long len
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+
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+ // w10 : A = adler & 0xffff
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+ // w11 : B = (adler >> 16) & 0xffff
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+ // first byte A = 1, B = 0
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+ and w10, w0, #0xffff
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+ lsr w11, w0, #16
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+ // less than and equal 63byte, jumper to normal proc
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+ cmp x2, #0x3f
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+ b.le Lnormal_proc
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+
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+ // Get the length of the sve vector to x6.
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+ mov x6, #0
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+ addvl x6, x6, #1
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+ adr x12, .Adler_sequence
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+ ptrue p0.h
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+
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+ // Get the starting position of the required sequence.
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+ mov x9, #256
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+ sub x9, x9, x6
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+ ld1h z24.h, p0/z, [x12, x9, lsl #1] // taps1 to z24.h
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+ inch x9
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+ ld1h z25.h, p0/z, [x12, x9, lsl #1] // taps2 to z25.h
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+ // must bigger than 64byte
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+ ptrue p0.b
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+ ptrue p1.h
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+ mov x9, #0
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+.align 4
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+LBig_loop:
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+ // x is SVE vector length.
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+ // Bn = Bn-1 + An-1 * x + x * D1 + (x-1) * D2 + ... + 1 * Dx
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+ // An = An-1 + D1 + D2 + D3 + ... + Dx
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+
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+ .macro ADLER_BLOCK_32
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+ ld1b z0.b, p0/z, [x1, x9]
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+
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+ uaddv d20, p0, z0.b // D1 + D2 + ... + D32
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+ mov x12, v20.2d[0] // mov sum to w12
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+ madd x11, x10, x6, x11 // Bn = An-1 * 32 + Bn-1
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+
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+ uunpklo z26.h, z0.b
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+ uunpkhi z27.h, z0.b
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+ mul z26.h, p1/m, z26.h, z24.h // x * D1 + (x-1) * D2 + ... + (x/2 + 1) * D(x/2)
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+ mul z27.h, p1/m, z27.h, z25.h // (x/2) * D(x/2 + 1) + (x/2 - 1) * D(x/2 + 2) + ... + 1 * Dx
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+
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+ uaddv d21, p1, z26.h
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+ uaddv d22, p1, z27.h
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+ mov x13, v21.2d[0]
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+ mov x14, v22.2d[0]
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+
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+ add x11, x13, x11
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+ add x11, x14, x11 // Bn += x * D1 + (x-1) * D2 + ... + 1 * Dx
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+ add x10, x12, x10 // An += D1 + D2 + ... + Dx
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+ incb x9
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+ .endm
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+ mov x15, #4
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+ ADLER_BLOCK_32
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+ ADLER_BLOCK_32
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+ ADLER_BLOCK_32
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+ ADLER_BLOCK_32
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+
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+ // calc = reg0 % 65521
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+ .macro mod65521, reg0, reg1, reg2
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+ mov w\reg1, #0x8071
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+ mov w\reg2, #0xfff1
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+ movk w\reg1, #0x8007, lsl #16
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+ umull x\reg1, w\reg0, w\reg1
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+ lsr x\reg1, x\reg1, #47
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+ msub w\reg0, w\reg1, w\reg2, w\reg0
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+ .endm
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+
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+ mod65521 10, 14, 16
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+ mod65521 11, 14, 16
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+
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+Lloop_cond:
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+ mul x12, x6, x15
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+ sub x2, x2, x12
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+ cmp x2, x12
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+ b.ge LBig_loop
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+
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+Lnormal_proc:
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+ cmp x2, #0
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+ b.eq Lret
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+
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+ ldrb w15, [x1, x9]
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+ add x9, x9, #1
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+ add x10, x15, x10
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+ add x11, x10, x11
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+ sub x2, x2, #1
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+ b Lnormal_proc
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+
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+Lret:
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+ mod65521 10, 14, 5
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+ mod65521 11, 14, 5
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+ lsl x11, x11, #16
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+ orr x0, x10, x11
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+ ret
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+
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+.size adler32_sve, .-adler32_sve
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--
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2.17.1
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@ -1,6 +1,6 @@
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Name: zlib
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Version: 1.2.11
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Release: 18
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Release: 19
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Summary: A lossless data-compression library
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License: zlib and Boost
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URL: http://www.zlib.net
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@ -15,6 +15,7 @@ Patch2: 0002-Porting-optimized-longest_match.patch
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Patch3: 0003-arm64-specific-build-patch.patch
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Patch4: 0004-zlib-Optimize-CRC32.patch
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Patch5: zlib-1.2.11-SIMD.patch
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Patch6: 0005-Accelerate-Adler32-using-arm64-SVE-instructions.patch
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%endif
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Patch6000: fix-undefined-buffer-detected-by-oss-fuzz.patch
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@ -118,6 +119,9 @@ make test
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%{_libdir}/pkgconfig/minizip.pc
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%changelog
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* Thu Sep 2 2021 liqiang <liqiang64@huawei.com> - 1.2.11-19
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- Optimize Adler32 by SVE instructions.
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* Mon Sep 14 2020 noah <hedongbo@huawei.com> - 1.2.11-18
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- add zlib-1.2.11-SIMD.patch
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