Add RISC-V support
This commit is contained in:
YukariChiba
laokz
parent
d59da9614b
commit
b41e0ac5e6
106
0003-RISC-V-support.patch
Normal file
106
0003-RISC-V-support.patch
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@ -0,0 +1,106 @@
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diff --git a/utils/uds/atomicDefs.h b/utils/uds/atomicDefs.h
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index f468369..673f974 100644
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--- a/utils/uds/atomicDefs.h
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+++ b/utils/uds/atomicDefs.h
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@@ -98,6 +98,8 @@ static INLINE void smp_mb(void)
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__asm__ __volatile__("sync" : : : "memory");
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#elif defined __loongarch64
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__asm__ __volatile__("dbar 0" : : : "memory");
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+#elif defined __riscv
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+ __asm__ __volatile__("fence rw,rw" : : : "memory");
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#else
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#error "no fence defined"
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#endif
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@@ -125,6 +127,8 @@ static INLINE void smp_rmb(void)
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__asm__ __volatile__("lwsync" : : : "memory");
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#elif defined __loongarch64
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__asm__ __volatile__("dbar 0" : : : "memory");
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+#elif defined __riscv
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+ __asm__ __volatile__("fence r,r" : : : "memory");
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#else
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#error "no fence defined"
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#endif
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@@ -152,6 +156,8 @@ static INLINE void smp_wmb(void)
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__asm__ __volatile__("lwsync" : : : "memory");
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#elif defined __loongarch64
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__asm__ __volatile__("dbar 0" : : : "memory");
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+#elif defined __riscv
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+ __asm__ __volatile__("fence w,w" : : : "memory");
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#else
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#error "no fence defined"
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#endif
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@@ -178,7 +184,7 @@ static INLINE void smp_mb__before_atomic(void)
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static INLINE void smp_read_barrier_depends(void)
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{
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#if defined(__x86_64__) || defined(__PPC__) || defined(__s390__) \
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- || defined(__aarch64__) || defined(__loongarch64)
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+ || defined(__aarch64__) || defined(__loongarch64) || defined(__riscv)
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// Nothing needed for these architectures.
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#else
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// Default to playing it safe.
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diff --git a/utils/uds/cpu.h b/utils/uds/cpu.h
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index e26d653..f3fd61f 100644
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--- a/utils/uds/cpu.h
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+++ b/utils/uds/cpu.h
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@@ -36,7 +36,7 @@
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#define CACHE_LINE_BYTES 128
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#elif defined(__s390x__)
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#define CACHE_LINE_BYTES 256
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-#elif defined(__x86_64__) || defined(__aarch64__) || defined(__loongarch64)
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+#elif defined(__x86_64__) || defined(__aarch64__) || defined(__loongarch64) || defined(__riscv)
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#define CACHE_LINE_BYTES 64
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#else
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#error "unknown cache line size"
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diff --git a/utils/uds/Makefile b/utils/uds/Makefile
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index e33d682..ff6ece0 100644
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--- a/utils/uds/Makefile
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+++ b/utils/uds/Makefile
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@@ -32,8 +32,11 @@ ifeq ($(origin CC), default)
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CC=gcc
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endif
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+ifeq ($(filter riscv64%,$(MAKE_HOST)),)
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+Wcast-align = -Wcast-align
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+endif
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WARNS = -Wall \
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- -Wcast-align \
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+ $(Wcast-align) \
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-Werror \
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-Wextra \
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-Winit-self \
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diff --git a/utils/vdo/base/Makefile b/utils/vdo/base/Makefile
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index fb009a7..26a8e28 100644
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--- a/utils/vdo/base/Makefile
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+++ b/utils/vdo/base/Makefile
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@@ -22,9 +22,12 @@ VDO_VERSION = 6.2.6.14
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UDS_DIR = ../../uds
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+ifeq ($(filter riscv64%,$(MAKE_HOST)),)
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+Wcast-align = -Wcast-align
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+endif
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WARNS = \
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-Wall \
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- -Wcast-align \
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+ $(Wcast-align) \
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-Werror \
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-Wextra \
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-Winit-self \
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diff --git a/utils/vdo/user/Makefile b/utils/vdo/user/Makefile
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index 8946fb3..698dede 100644
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--- a/utils/vdo/user/Makefile
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+++ b/utils/vdo/user/Makefile
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@@ -24,9 +24,12 @@ VDO_VERSION = 6.2.6.14
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UDS_DIR = ../../uds
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VDO_BASE_DIR = ../base
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+ifeq ($(filter riscv64%,$(MAKE_HOST)),)
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+Wcast-align = -Wcast-align
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+endif
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WARNS = \
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-Wall \
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- -Wcast-align \
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+ $(Wcast-align) \
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-Werror \
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-Wextra \
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-Winit-self \
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12
vdo.spec
12
vdo.spec
@ -1,12 +1,13 @@
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Name: vdo
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Version: 6.2.6.14
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Release: 2
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Release: 3
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Summary: Management tools for Virtual Data Optimizer
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License: GPLv2
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URL: http://github.com/dm-vdo/vdo
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Source0: https://github.com/dm-vdo/vdo/archive/refs/tags/%{version}.tar.gz
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Patch0002: 0002-Ignore-misaligned-pointers.patch
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Patch0003: 0001-Add-loongarch64-support.patch
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Patch0004: 0003-RISC-V-support.patch
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BuildRequires: gcc libuuid-devel device-mapper-devel device-mapper-event-devel
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BuildRequires: valgrind-devel python3 python3-devel zlib-devel systemd
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@ -26,9 +27,8 @@ This package provides the user-space management tools for VDO.
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%prep
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%setup -q
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%patch0002 -p1
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%ifarch loongarch64
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%patch0003 -p1
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%endif
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%patch0004 -p1
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%build
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%make_build
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@ -85,6 +85,12 @@ done
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%{_mandir}/man8/*
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%changelog
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* Fri Mar 17 2023 laokz <zhangkai@iscas.ac.cn> - 6.2.6.14-3
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- Add RISC-V support (Patch by YukariChiba<i@0x7f.cc>)
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- Source of fence commands: RISC-V ISA Spec from riscv.org
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- Remove -Wcast-align flag, since it causes error in RISC-V gcc
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- Remove error-prone patch isolation macro
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* Tue Mar 7 2023 doupengda <doupengda@loongson.cn> - 6.2.6.14-2
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- Add loongarch64 support
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