Add RISC-V support

0003-RISC-V-support.patch

@@ -0,0 +1,106 @@
+diff --git a/utils/uds/atomicDefs.h b/utils/uds/atomicDefs.h
+index f468369..673f974 100644
+--- a/utils/uds/atomicDefs.h
++++ b/utils/uds/atomicDefs.h
+@@ -98,6 +98,8 @@ static INLINE void smp_mb(void)
+   __asm__ __volatile__("sync" : : : "memory");
+ #elif defined __loongarch64
+   __asm__ __volatile__("dbar 0" : : : "memory");
++#elif defined __riscv
++  __asm__ __volatile__("fence rw,rw" : : : "memory");
+ #else
+ #error "no fence defined"
+ #endif
+@@ -125,6 +127,8 @@ static INLINE void smp_rmb(void)
+   __asm__ __volatile__("lwsync" : : : "memory");
+ #elif defined __loongarch64
+   __asm__ __volatile__("dbar 0" : : : "memory");
++#elif defined __riscv
++  __asm__ __volatile__("fence r,r" : : : "memory");
+ #else
+ #error "no fence defined"
+ #endif
+@@ -152,6 +156,8 @@ static INLINE void smp_wmb(void)
+   __asm__ __volatile__("lwsync" : : : "memory");
+ #elif defined __loongarch64
+   __asm__ __volatile__("dbar 0" : : : "memory");
++#elif defined __riscv
++  __asm__ __volatile__("fence w,w" : : : "memory");
+ #else
+ #error "no fence defined"
+ #endif
+@@ -178,7 +184,7 @@ static INLINE void smp_mb__before_atomic(void)
+ static INLINE void smp_read_barrier_depends(void)
+ {
+ #if defined(__x86_64__) || defined(__PPC__) || defined(__s390__) \
+-  || defined(__aarch64__)  || defined(__loongarch64)
++  || defined(__aarch64__)  || defined(__loongarch64)  || defined(__riscv)
+   // Nothing needed for these architectures.
+ #else
+   // Default to playing it safe.
+diff --git a/utils/uds/cpu.h b/utils/uds/cpu.h
+index e26d653..f3fd61f 100644
+--- a/utils/uds/cpu.h
++++ b/utils/uds/cpu.h
+@@ -36,7 +36,7 @@
+ #define CACHE_LINE_BYTES 128
+ #elif defined(__s390x__)
+ #define CACHE_LINE_BYTES 256
+-#elif defined(__x86_64__) || defined(__aarch64__) || defined(__loongarch64)
++#elif defined(__x86_64__) || defined(__aarch64__) || defined(__loongarch64)  || defined(__riscv)
+ #define CACHE_LINE_BYTES  64
+ #else
+ #error "unknown cache line size"
+diff --git a/utils/uds/Makefile b/utils/uds/Makefile
+index e33d682..ff6ece0 100644
+--- a/utils/uds/Makefile
++++ b/utils/uds/Makefile
+@@ -32,8 +32,11 @@ ifeq ($(origin CC), default)
+   CC=gcc
+ endif
+ 
++ifeq ($(filter riscv64%,$(MAKE_HOST)),)
++Wcast-align = -Wcast-align
++endif
+ WARNS =	-Wall			\
+-	-Wcast-align		\
++	$(Wcast-align)		\
+ 	-Werror			\
+ 	-Wextra			\
+ 	-Winit-self		\
+diff --git a/utils/vdo/base/Makefile b/utils/vdo/base/Makefile
+index fb009a7..26a8e28 100644
+--- a/utils/vdo/base/Makefile
++++ b/utils/vdo/base/Makefile
+@@ -22,9 +22,12 @@ VDO_VERSION = 6.2.6.14
+ UDS_DIR      = ../../uds
+ 
+ 
++ifeq ($(filter riscv64%,$(MAKE_HOST)),)
++Wcast-align = -Wcast-align
++endif
+ WARNS            =				\
+ 		   -Wall			\
+-		   -Wcast-align			\
++		   $(Wcast-align)			\
+ 		   -Werror			\
+ 		   -Wextra			\
+ 		   -Winit-self			\
+diff --git a/utils/vdo/user/Makefile b/utils/vdo/user/Makefile
+index 8946fb3..698dede 100644
+--- a/utils/vdo/user/Makefile
++++ b/utils/vdo/user/Makefile
+@@ -24,9 +24,12 @@ VDO_VERSION = 6.2.6.14
+ UDS_DIR      = ../../uds
+ VDO_BASE_DIR = ../base
+ 
++ifeq ($(filter riscv64%,$(MAKE_HOST)),)
++Wcast-align = -Wcast-align
++endif
+ WARNS            =				\
+ 		   -Wall			\
+-		   -Wcast-align			\
++		   $(Wcast-align)			\
+ 		   -Werror			\
+ 		   -Wextra			\
+ 		   -Winit-self			\

vdo.spec

@@ -1,12 +1,13 @@
 Name:           vdo
 Version:        6.2.6.14
-Release:        2
+Release:        3
 Summary:        Management tools for Virtual Data Optimizer
 License:        GPLv2
 URL:            http://github.com/dm-vdo/vdo
 Source0:	https://github.com/dm-vdo/vdo/archive/refs/tags/%{version}.tar.gz
 Patch0002:      0002-Ignore-misaligned-pointers.patch
 Patch0003:      0001-Add-loongarch64-support.patch
+Patch0004:      0003-RISC-V-support.patch
 
 BuildRequires:  gcc libuuid-devel device-mapper-devel device-mapper-event-devel
 BuildRequires:  valgrind-devel python3 python3-devel zlib-devel systemd
@@ -26,9 +27,8 @@ This package provides the user-space management tools for VDO.
 %prep
 %setup -q
 %patch0002 -p1
-%ifarch loongarch64
 %patch0003 -p1
-%endif
+%patch0004 -p1
 
 %build
 %make_build
@@ -85,6 +85,12 @@ done
 %{_mandir}/man8/*
 
 %changelog
+* Fri Mar 17 2023 laokz <zhangkai@iscas.ac.cn> - 6.2.6.14-3
+- Add RISC-V support (Patch by YukariChiba<i@0x7f.cc>)
+- Source of fence commands: RISC-V ISA Spec from riscv.org
+- Remove -Wcast-align flag, since it causes error in RISC-V gcc
+- Remove error-prone patch isolation macro
+
 * Tue Mar 7 2023 doupengda <doupengda@loongson.cn> - 6.2.6.14-2
 - Add loongarch64 support