From 957c59b751202c6235da4c00389dce67fd5730e8 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Thu, 19 May 2022 10:18:14 +0800 Subject: [PATCH] Add LoongArch64 Linux support --- Makefile.all.am | 7 + Makefile.in | 9 +- Makefile.tool.am | 12 + Makefile.vex.am | 14 +- Makefile.vex.in | 199 +- README | 1 + README.loongarch64 | 51 + VEX/auxprogs/genoffsets.c | 36 + VEX/priv/guest_loongarch64_defs.h | 131 + VEX/priv/guest_loongarch64_helpers.c | 905 + VEX/priv/guest_loongarch64_toIR.c | 12086 ++++ VEX/priv/host_loongarch64_defs.c | 3929 ++ VEX/priv/host_loongarch64_defs.h | 919 + VEX/priv/host_loongarch64_isel.c | 3748 ++ VEX/priv/ir_defs.c | 55 +- VEX/priv/main_main.c | 109 + VEX/pub/libvex.h | 22 + VEX/pub/libvex_basictypes.h | 4 + VEX/pub/libvex_guest_loongarch64.h | 172 + VEX/pub/libvex_guest_offsets.h | 33 + VEX/pub/libvex_ir.h | 36 +- VEX/pub/libvex_trc_values.h | 1 + auxprogs/Makefile.in | 7 + cachegrind/Makefile.in | 19 + cachegrind/cg_arch.c | 7 + cachegrind/cg_branchpred.c | 2 +- cachegrind/tests/Makefile.in | 7 + cachegrind/tests/x86/Makefile.in | 7 + callgrind/Makefile.in | 19 + callgrind/tests/Makefile.in | 7 + config.h | 2 +- configure | 56 +- configure.ac | 28 +- coregrind/Makefile.am | 15 +- coregrind/Makefile.in | 252 +- coregrind/launcher-linux.c | 11 +- coregrind/m_aspacemgr/aspacemgr-common.c | 9 +- coregrind/m_aspacemgr/aspacemgr-linux.c | 3 +- coregrind/m_cache.c | 233 + coregrind/m_coredump/coredump-elf.c | 42 + coregrind/m_debuginfo/d3basics.c | 3 + coregrind/m_debuginfo/debuginfo.c | 30 +- coregrind/m_debuginfo/priv_storage.h | 19 +- coregrind/m_debuginfo/readdwarf.c | 47 +- coregrind/m_debuginfo/readelf.c | 6 +- coregrind/m_debuginfo/storage.c | 9 + coregrind/m_debuglog.c | 35 + .../m_dispatch/dispatch-loongarch64-linux.S | 314 + .../loongarch-base64-valgrind-s1.xml | 45 + .../loongarch-base64-valgrind-s2.xml | 45 + coregrind/m_gdbserver/loongarch-base64.xml | 45 + .../loongarch-fpu64-valgrind-s1.xml | 57 + .../loongarch-fpu64-valgrind-s2.xml | 57 + coregrind/m_gdbserver/loongarch-fpu64.xml | 57 + .../loongarch64-linux-valgrind.xml | 18 + coregrind/m_gdbserver/loongarch64-linux.xml | 14 + coregrind/m_gdbserver/target.c | 2 + .../m_gdbserver/valgrind-low-loongarch64.c | 272 + coregrind/m_gdbserver/valgrind_low.h | 1 + coregrind/m_initimg/initimg-linux.c | 17 +- coregrind/m_libcassert.c | 20 + coregrind/m_libcfile.c | 63 +- coregrind/m_libcproc.c | 11 +- coregrind/m_libcsetjmp.c | 66 + coregrind/m_machine.c | 194 +- coregrind/m_main.c | 37 +- coregrind/m_options.c | 3 +- coregrind/m_redir.c | 17 + coregrind/m_scheduler/scheduler.c | 8 + .../m_sigframe/sigframe-loongarch64-linux.c | 285 + coregrind/m_signals.c | 75 +- coregrind/m_stacktrace.c | 94 + coregrind/m_syscall.c | 32 + coregrind/m_syswrap/priv_syswrap-linux.h | 7 + coregrind/m_syswrap/priv_types_n_macros.h | 3 +- .../m_syswrap/syscall-loongarch64-linux.S | 143 + coregrind/m_syswrap/syswrap-generic.c | 2 +- coregrind/m_syswrap/syswrap-linux.c | 36 +- .../m_syswrap/syswrap-loongarch64-linux.c | 644 + coregrind/m_syswrap/syswrap-main.c | 93 +- coregrind/m_trampoline.S | 48 + coregrind/m_translate.c | 5 + coregrind/m_vki.c | 6 +- coregrind/pub_core_aspacemgr.h | 3 +- coregrind/pub_core_basics.h | 8 +- coregrind/pub_core_debuginfo.h | 4 + coregrind/pub_core_machine.h | 13 + coregrind/pub_core_mallocfree.h | 1 + coregrind/pub_core_signals.h | 1 + coregrind/pub_core_syscall.h | 1 + coregrind/pub_core_trampoline.h | 6 + coregrind/pub_core_transtab.h | 3 +- coregrind/pub_core_transtab_asm.h | 2 +- coregrind/vgdb-invoker-ptrace.c | 19 +- dhat/Makefile.in | 19 + dhat/tests/Makefile.in | 7 + drd/Makefile.in | 19 + drd/drd_bitmap.h | 2 +- drd/drd_load_store.c | 4 + drd/tests/Makefile.in | 7 + drd/tests/pth_barrier_thr_cr.supp | 11 + exp-bbv/Makefile.in | 19 + exp-bbv/tests/Makefile.in | 7 + exp-bbv/tests/amd64-linux/Makefile.in | 7 + exp-bbv/tests/arm-linux/Makefile.in | 7 + exp-bbv/tests/ppc32-linux/Makefile.in | 7 + exp-bbv/tests/x86-linux/Makefile.in | 7 + exp-bbv/tests/x86/Makefile.in | 7 + gdbserver_tests/Makefile.am | 1 + gdbserver_tests/Makefile.in | 8 + gdbserver_tests/filter_helgrind_monitor | 2 + .../filter_helgrind_monitor_loongarch64 | 43 + gdbserver_tests/solaris/Makefile.in | 7 + helgrind/Makefile.in | 19 + helgrind/hg_main.c | 1 + helgrind/tests/Makefile.in | 7 + helgrind/tests/annotate_hbefore.c | 30 + helgrind/tests/tc07_hbl1.c | 17 + helgrind/tests/tc08_hbl2.c | 17 + helgrind/tests/tc11_XCHG.c | 18 + include/Makefile.am | 3 + include/Makefile.in | 3 + include/pub_tool_basics.h | 6 +- include/pub_tool_guest.h | 3 + include/pub_tool_libcsetjmp.h | 8 + include/pub_tool_machine.h | 6 + include/pub_tool_redir.h | 2 + include/pub_tool_vkiscnums_asm.h | 4 + include/valgrind.h | 525 +- include/valgrind.h.in | 525 +- include/vki/vki-linux.h | 5 + include/vki/vki-loongarch64-linux.h | 811 + .../vki/vki-posixtypes-loongarch64-linux.h | 76 + include/vki/vki-scnums-loongarch64-linux.h | 356 + lackey/Makefile.in | 19 + massif/Makefile.in | 19 + massif/tests/Makefile.am | 1 + massif/tests/Makefile.in | 8 + massif/tests/big-alloc.post.exp-loongarch64 | 54 + memcheck/Makefile.in | 19 + memcheck/mc_machine.c | 119 + memcheck/mc_translate.c | 17 + memcheck/tests/Makefile.am | 5 +- memcheck/tests/Makefile.in | 65 +- memcheck/tests/amd64-freebsd/Makefile.in | 7 + memcheck/tests/amd64-linux/Makefile.in | 7 + memcheck/tests/amd64-solaris/Makefile.in | 7 + memcheck/tests/amd64/Makefile.in | 7 + memcheck/tests/arm64-linux/Makefile.in | 7 + memcheck/tests/atomic_incs.c | 84 +- memcheck/tests/common/Makefile.in | 7 + memcheck/tests/darwin/Makefile.in | 7 + memcheck/tests/freebsd/Makefile.in | 7 + memcheck/tests/leak-segv-jmp.c | 15 +- memcheck/tests/leak-segv-jmp.stderr.exp | 20 +- memcheck/tests/leak.h | 21 + memcheck/tests/linux/Makefile.in | 7 + memcheck/tests/loongarch64-linux/Makefile.am | 17 + .../tests/loongarch64-linux/filter_stderr | 3 + memcheck/tests/loongarch64-linux/scalar.c | 1296 + memcheck/tests/loongarch64-linux/scalar.h | 62 + .../tests/loongarch64-linux/scalar.stderr.exp | 2716 + .../tests/loongarch64-linux/scalar.vgtest | 5 + memcheck/tests/mips32/Makefile.in | 7 + memcheck/tests/mips64/Makefile.in | 7 + memcheck/tests/ppc32/Makefile.in | 7 + memcheck/tests/ppc64/Makefile.in | 7 + memcheck/tests/s390x/Makefile.in | 7 + memcheck/tests/solaris/Makefile.in | 7 + memcheck/tests/unit_libcbase.c | 4 +- memcheck/tests/vbit-test/Makefile.in | 7 + memcheck/tests/vbit-test/irops.c | 526 +- memcheck/tests/vbit-test/vtest.h | 19 +- memcheck/tests/x86-freebsd/Makefile.in | 7 + memcheck/tests/x86-linux/Makefile.in | 7 + memcheck/tests/x86-solaris/Makefile.in | 7 + memcheck/tests/x86/Makefile.in | 7 + mpi/Makefile.in | 7 + nightly/conf/loongarch64.conf | 3 + nightly/conf/loongarch64.sendemail | 7 + none/Makefile.in | 19 + none/tests/Makefile.am | 9 +- none/tests/Makefile.in | 56 +- none/tests/allexec_prepare_prereq | 13 +- none/tests/amd64-darwin/Makefile.in | 7 + none/tests/amd64-linux/Makefile.in | 7 + none/tests/amd64-solaris/Makefile.in | 7 + none/tests/amd64/Makefile.in | 7 + none/tests/arm/Makefile.in | 7 + none/tests/arm64/Makefile.in | 7 + none/tests/darwin/Makefile.in | 7 + none/tests/freebsd/Makefile.in | 7 + none/tests/libvex_test.c | 7 +- none/tests/linux/Makefile.in | 7 + none/tests/loongarch64/Makefile.am | 43 + none/tests/loongarch64/allexec.c | 56 + none/tests/loongarch64/atomic.c | 75 + none/tests/loongarch64/atomic.stderr.exp | 0 none/tests/loongarch64/atomic.stdout.exp | 72 + none/tests/loongarch64/atomic.vgtest | 3 + none/tests/loongarch64/branch.c | 148 + none/tests/loongarch64/branch.stderr.exp | 0 none/tests/loongarch64/branch.stdout.exp | 64 + none/tests/loongarch64/branch.vgtest | 2 + none/tests/loongarch64/cpucfg.c | 24 + none/tests/loongarch64/cpucfg.stderr.exp | 0 none/tests/loongarch64/cpucfg.stdout.exp | 72 + none/tests/loongarch64/cpucfg.vgtest | 3 + none/tests/loongarch64/fault.c | 234 + none/tests/loongarch64/fault.stderr.exp | 138 + none/tests/loongarch64/fault.stdout.exp | 267 + none/tests/loongarch64/fault.vgtest | 2 + none/tests/loongarch64/fault_fp.c | 163 + none/tests/loongarch64/fault_fp.stderr.exp | 64 + none/tests/loongarch64/fault_fp.stdout.exp | 189 + none/tests/loongarch64/fault_fp.vgtest | 3 + none/tests/loongarch64/filter_stderr | 3 + none/tests/loongarch64/float.c | 804 + none/tests/loongarch64/float.stderr.exp | 0 none/tests/loongarch64/float.stdout.exp | 54240 ++++++++++++++++ none/tests/loongarch64/float.vgtest | 3 + none/tests/loongarch64/integer.c | 1311 + none/tests/loongarch64/integer.stderr.exp | 0 none/tests/loongarch64/integer.stdout.exp | 2748 + none/tests/loongarch64/integer.vgtest | 2 + none/tests/loongarch64/llsc.c | 69 + none/tests/loongarch64/llsc.stderr.exp | 0 none/tests/loongarch64/llsc.stdout.exp | 6 + none/tests/loongarch64/llsc.vgtest | 2 + none/tests/loongarch64/memory.c | 345 + none/tests/loongarch64/memory.stderr.exp | 0 none/tests/loongarch64/memory.stdout.exp | 109 + none/tests/loongarch64/memory.vgtest | 2 + none/tests/loongarch64/move.c | 112 + none/tests/loongarch64/move.stderr.exp | 0 none/tests/loongarch64/move.stdout.exp | 156 + none/tests/loongarch64/move.vgtest | 3 + none/tests/loongarch64/pc.c | 66 + none/tests/loongarch64/pc.stderr.exp | 0 none/tests/loongarch64/pc.stdout.exp | 28 + none/tests/loongarch64/pc.vgtest | 2 + none/tests/loongarch64/special.c | 112 + none/tests/loongarch64/special.stderr.exp | 0 none/tests/loongarch64/special.stdout.exp | 48 + none/tests/loongarch64/special.vgtest | 2 + none/tests/loongarch64/vector128.c | 12 + none/tests/loongarch64/vector128.stderr.exp | 0 none/tests/loongarch64/vector128.stdout.exp | 0 none/tests/loongarch64/vector128.vgtest | 3 + none/tests/loongarch64/vector256.c | 12 + none/tests/loongarch64/vector256.stderr.exp | 0 none/tests/loongarch64/vector256.stdout.exp | 0 none/tests/loongarch64/vector256.vgtest | 3 + none/tests/mips32/Makefile.in | 7 + none/tests/mips64/Makefile.in | 7 + none/tests/nanomips/Makefile.in | 7 + none/tests/ppc32/Makefile.in | 7 + none/tests/ppc64/Makefile.in | 7 + none/tests/s390x/Makefile.in | 7 + none/tests/scripts/Makefile.in | 7 + none/tests/solaris/Makefile.in | 7 + none/tests/x86-darwin/Makefile.in | 7 + none/tests/x86-freebsd/Makefile.in | 7 + none/tests/x86-linux/Makefile.in | 7 + none/tests/x86-solaris/Makefile.in | 7 + none/tests/x86/Makefile.in | 7 + perf/Makefile.in | 7 + tests/Makefile.am | 3 +- tests/Makefile.in | 30 +- tests/arch_test.c | 5 + tests/loongarch64_features.c | 81 + tests/platform_test | 1 + 272 files changed, 95890 insertions(+), 475 deletions(-) create mode 100644 README.loongarch64 create mode 100644 VEX/priv/guest_loongarch64_defs.h create mode 100644 VEX/priv/guest_loongarch64_helpers.c create mode 100644 VEX/priv/guest_loongarch64_toIR.c create mode 100644 VEX/priv/host_loongarch64_defs.c create mode 100644 VEX/priv/host_loongarch64_defs.h create mode 100644 VEX/priv/host_loongarch64_isel.c create mode 100644 VEX/pub/libvex_guest_loongarch64.h create mode 100644 coregrind/m_dispatch/dispatch-loongarch64-linux.S create mode 100644 coregrind/m_gdbserver/loongarch-base64-valgrind-s1.xml create mode 100644 coregrind/m_gdbserver/loongarch-base64-valgrind-s2.xml create mode 100644 coregrind/m_gdbserver/loongarch-base64.xml create mode 100644 coregrind/m_gdbserver/loongarch-fpu64-valgrind-s1.xml create mode 100644 coregrind/m_gdbserver/loongarch-fpu64-valgrind-s2.xml create mode 100644 coregrind/m_gdbserver/loongarch-fpu64.xml create mode 100644 coregrind/m_gdbserver/loongarch64-linux-valgrind.xml create mode 100644 coregrind/m_gdbserver/loongarch64-linux.xml create mode 100644 coregrind/m_gdbserver/valgrind-low-loongarch64.c create mode 100644 coregrind/m_sigframe/sigframe-loongarch64-linux.c create mode 100644 coregrind/m_syswrap/syscall-loongarch64-linux.S create mode 100644 coregrind/m_syswrap/syswrap-loongarch64-linux.c create mode 100755 gdbserver_tests/filter_helgrind_monitor_loongarch64 create mode 100644 include/vki/vki-loongarch64-linux.h create mode 100644 include/vki/vki-posixtypes-loongarch64-linux.h create mode 100644 include/vki/vki-scnums-loongarch64-linux.h create mode 100644 massif/tests/big-alloc.post.exp-loongarch64 create mode 100644 memcheck/tests/loongarch64-linux/Makefile.am create mode 100755 memcheck/tests/loongarch64-linux/filter_stderr create mode 100644 memcheck/tests/loongarch64-linux/scalar.c create mode 100644 memcheck/tests/loongarch64-linux/scalar.h create mode 100644 memcheck/tests/loongarch64-linux/scalar.stderr.exp create mode 100644 memcheck/tests/loongarch64-linux/scalar.vgtest create mode 100644 nightly/conf/loongarch64.conf create mode 100644 nightly/conf/loongarch64.sendemail create mode 100644 none/tests/loongarch64/Makefile.am create mode 100644 none/tests/loongarch64/allexec.c create mode 100644 none/tests/loongarch64/atomic.c create mode 100644 none/tests/loongarch64/atomic.stderr.exp create mode 100644 none/tests/loongarch64/atomic.stdout.exp create mode 100644 none/tests/loongarch64/atomic.vgtest create mode 100644 none/tests/loongarch64/branch.c create mode 100644 none/tests/loongarch64/branch.stderr.exp create mode 100644 none/tests/loongarch64/branch.stdout.exp create mode 100644 none/tests/loongarch64/branch.vgtest create mode 100644 none/tests/loongarch64/cpucfg.c create mode 100644 none/tests/loongarch64/cpucfg.stderr.exp create mode 100644 none/tests/loongarch64/cpucfg.stdout.exp create mode 100644 none/tests/loongarch64/cpucfg.vgtest create mode 100644 none/tests/loongarch64/fault.c create mode 100644 none/tests/loongarch64/fault.stderr.exp create mode 100644 none/tests/loongarch64/fault.stdout.exp create mode 100644 none/tests/loongarch64/fault.vgtest create mode 100644 none/tests/loongarch64/fault_fp.c create mode 100644 none/tests/loongarch64/fault_fp.stderr.exp create mode 100644 none/tests/loongarch64/fault_fp.stdout.exp create mode 100644 none/tests/loongarch64/fault_fp.vgtest create mode 100755 none/tests/loongarch64/filter_stderr create mode 100644 none/tests/loongarch64/float.c create mode 100644 none/tests/loongarch64/float.stderr.exp create mode 100644 none/tests/loongarch64/float.stdout.exp create mode 100644 none/tests/loongarch64/float.vgtest create mode 100644 none/tests/loongarch64/integer.c create mode 100644 none/tests/loongarch64/integer.stderr.exp create mode 100644 none/tests/loongarch64/integer.stdout.exp create mode 100644 none/tests/loongarch64/integer.vgtest create mode 100644 none/tests/loongarch64/llsc.c create mode 100644 none/tests/loongarch64/llsc.stderr.exp create mode 100644 none/tests/loongarch64/llsc.stdout.exp create mode 100644 none/tests/loongarch64/llsc.vgtest create mode 100644 none/tests/loongarch64/memory.c create mode 100644 none/tests/loongarch64/memory.stderr.exp create mode 100644 none/tests/loongarch64/memory.stdout.exp create mode 100644 none/tests/loongarch64/memory.vgtest create mode 100644 none/tests/loongarch64/move.c create mode 100644 none/tests/loongarch64/move.stderr.exp create mode 100644 none/tests/loongarch64/move.stdout.exp create mode 100644 none/tests/loongarch64/move.vgtest create mode 100644 none/tests/loongarch64/pc.c create mode 100644 none/tests/loongarch64/pc.stderr.exp create mode 100644 none/tests/loongarch64/pc.stdout.exp create mode 100644 none/tests/loongarch64/pc.vgtest create mode 100644 none/tests/loongarch64/special.c create mode 100644 none/tests/loongarch64/special.stderr.exp create mode 100644 none/tests/loongarch64/special.stdout.exp create mode 100644 none/tests/loongarch64/special.vgtest create mode 100644 none/tests/loongarch64/vector128.c create mode 100644 none/tests/loongarch64/vector128.stderr.exp create mode 100644 none/tests/loongarch64/vector128.stdout.exp create mode 100644 none/tests/loongarch64/vector128.vgtest create mode 100644 none/tests/loongarch64/vector256.c create mode 100644 none/tests/loongarch64/vector256.stderr.exp create mode 100644 none/tests/loongarch64/vector256.stdout.exp create mode 100644 none/tests/loongarch64/vector256.vgtest create mode 100644 tests/loongarch64_features.c diff --git a/Makefile.all.am b/Makefile.all.am index 94d65f2..eca59dc 100755 --- a/Makefile.all.am +++ b/Makefile.all.am @@ -290,6 +290,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g + AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -350,6 +356,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ diff --git a/Makefile.in b/Makefile.in index 56751f4..81dcc71 100644 --- a/Makefile.in +++ b/Makefile.in @@ -219,7 +219,7 @@ am__DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/config.h.in \ $(top_srcdir)/docs/xml/vg-entities.xml.in \ $(top_srcdir)/drd/scripts/download-and-build-splash2.in \ AUTHORS COPYING NEWS README compile config.guess config.sub \ - install-sh missing + depcomp install-sh missing DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) distdir = $(PACKAGE)-$(VERSION) top_distdir = $(distdir) @@ -635,6 +635,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -682,6 +688,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ TOOLS = \ diff --git a/Makefile.tool.am b/Makefile.tool.am index 4ce6d5a..7dbfbd8 100644 --- a/Makefile.tool.am +++ b/Makefile.tool.am @@ -99,6 +99,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -167,6 +171,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -239,6 +246,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/Makefile.vex.am b/Makefile.vex.am index 98d8483..009d93b 100644 --- a/Makefile.vex.am +++ b/Makefile.vex.am @@ -26,6 +26,7 @@ pkginclude_HEADERS = \ pub/libvex_guest_s390x.h \ pub/libvex_guest_mips32.h \ pub/libvex_guest_mips64.h \ + pub/libvex_guest_loongarch64.h \ pub/libvex_s390x_common.h \ pub/libvex_ir.h \ pub/libvex_trc_values.h \ @@ -49,6 +50,7 @@ noinst_HEADERS = \ priv/guest_mips_defs.h \ priv/mips_defs.h \ priv/guest_nanomips_defs.h \ + priv/guest_loongarch64_defs.h \ priv/host_generic_regs.h \ priv/host_generic_simd64.h \ priv/host_generic_simd128.h \ @@ -64,7 +66,8 @@ noinst_HEADERS = \ priv/s390_defs.h \ priv/host_mips_defs.h \ priv/host_nanomips_defs.h \ - priv/common_nanomips_defs.h + priv/common_nanomips_defs.h \ + priv/host_loongarch64_defs.h BUILT_SOURCES = pub/libvex_guest_offsets.h CLEANFILES = pub/libvex_guest_offsets.h @@ -93,7 +96,8 @@ pub/libvex_guest_offsets.h: auxprogs/genoffsets.c \ pub/libvex_guest_arm64.h \ pub/libvex_guest_s390x.h \ pub/libvex_guest_mips32.h \ - pub/libvex_guest_mips64.h + pub/libvex_guest_mips64.h \ + pub/libvex_guest_loongarch64.h rm -f auxprogs/genoffsets.s $(mkdir_p) auxprogs pub $(CC) $(CFLAGS_FOR_GENOFFSETS) \ @@ -151,6 +155,8 @@ LIBVEX_SOURCES_COMMON = \ priv/guest_mips_toIR.c \ priv/guest_nanomips_helpers.c \ priv/guest_nanomips_toIR.c \ + priv/guest_loongarch64_helpers.c \ + priv/guest_loongarch64_toIR.c \ priv/host_generic_regs.c \ priv/host_generic_simd64.c \ priv/host_generic_simd128.c \ @@ -174,7 +180,9 @@ LIBVEX_SOURCES_COMMON = \ priv/host_mips_defs.c \ priv/host_nanomips_defs.c \ priv/host_mips_isel.c \ - priv/host_nanomips_isel.c + priv/host_nanomips_isel.c \ + priv/host_loongarch64_defs.c \ + priv/host_loongarch64_isel.c LIBVEXMULTIARCH_SOURCES = priv/multiarch_main_main.c diff --git a/Makefile.vex.in b/Makefile.vex.in index b0380a6..61f439b 100644 --- a/Makefile.vex.in +++ b/Makefile.vex.in @@ -188,6 +188,8 @@ am__objects_1 = priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main_globals.$(OBJEX priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mips_toIR.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_nanomips_helpers.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_nanomips_toIR.$(OBJEXT) \ + priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_loongarch64_helpers.$(OBJEXT) \ + priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_loongarch64_toIR.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.$(OBJEXT) \ @@ -211,7 +213,9 @@ am__objects_1 = priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main_globals.$(OBJEX priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_defs.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_nanomips_defs.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_isel.$(OBJEXT) \ - priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_nanomips_isel.$(OBJEXT) + priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_nanomips_isel.$(OBJEXT) \ + priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_loongarch64_defs.$(OBJEXT) \ + priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_loongarch64_isel.$(OBJEXT) am_libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS = $(am__objects_1) libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS = \ $(am_libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS) @@ -229,7 +233,8 @@ am__libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST = \ priv/guest_s390_helpers.c priv/guest_s390_toIR.c \ priv/guest_mips_helpers.c priv/guest_mipsdsp_toIR.c \ priv/guest_mips_toIR.c priv/guest_nanomips_helpers.c \ - priv/guest_nanomips_toIR.c priv/host_generic_regs.c \ + priv/guest_nanomips_toIR.c priv/guest_loongarch64_helpers.c \ + priv/guest_loongarch64_toIR.c priv/host_generic_regs.c \ priv/host_generic_simd64.c priv/host_generic_simd128.c \ priv/host_generic_simd256.c priv/host_generic_maddf.c \ priv/host_generic_reg_alloc2.c priv/host_generic_reg_alloc3.c \ @@ -240,7 +245,8 @@ am__libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST = \ priv/host_arm64_isel.c priv/host_s390_defs.c \ priv/host_s390_isel.c priv/s390_disasm.c priv/host_mips_defs.c \ priv/host_nanomips_defs.c priv/host_mips_isel.c \ - priv/host_nanomips_isel.c + priv/host_nanomips_isel.c priv/host_loongarch64_defs.c \ + priv/host_loongarch64_isel.c am__objects_2 = priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_globals.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_main.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_util.$(OBJEXT) \ @@ -267,6 +273,8 @@ am__objects_2 = priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_globals.$(OBJEX priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mips_toIR.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_nanomips_helpers.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_nanomips_toIR.$(OBJEXT) \ + priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_loongarch64_helpers.$(OBJEXT) \ + priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_loongarch64_toIR.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.$(OBJEXT) \ @@ -290,7 +298,9 @@ am__objects_2 = priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_globals.$(OBJEX priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_defs.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_nanomips_defs.$(OBJEXT) \ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_isel.$(OBJEXT) \ - priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_nanomips_isel.$(OBJEXT) + priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_nanomips_isel.$(OBJEXT) \ + priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.$(OBJEXT) \ + priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.$(OBJEXT) @VGCONF_HAVE_PLATFORM_SEC_TRUE@am_libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS = \ @VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_2) libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS = \ @@ -334,6 +344,8 @@ am__depfiles_remade = priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-gues priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_arm_toIR.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_generic_bb_to_IR.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_generic_x87.Po \ + priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_loongarch64_helpers.Po \ + priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_loongarch64_toIR.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mips_helpers.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mips_toIR.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mipsdsp_toIR.Po \ @@ -358,6 +370,8 @@ am__depfiles_remade = priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-gues priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.Po \ + priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_loongarch64_defs.Po \ + priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_loongarch64_isel.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_defs.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_isel.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_nanomips_defs.Po \ @@ -384,6 +398,8 @@ am__depfiles_remade = priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-gues priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_arm_toIR.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_generic_bb_to_IR.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_generic_x87.Po \ + priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_loongarch64_helpers.Po \ + priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_loongarch64_toIR.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mips_helpers.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mips_toIR.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mipsdsp_toIR.Po \ @@ -408,6 +424,8 @@ am__depfiles_remade = priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-gues priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.Po \ + priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.Po \ + priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_defs.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_isel.Po \ priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_nanomips_defs.Po \ @@ -851,6 +869,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -898,6 +922,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -924,6 +949,7 @@ pkginclude_HEADERS = \ pub/libvex_guest_s390x.h \ pub/libvex_guest_mips32.h \ pub/libvex_guest_mips64.h \ + pub/libvex_guest_loongarch64.h \ pub/libvex_s390x_common.h \ pub/libvex_ir.h \ pub/libvex_trc_values.h \ @@ -947,6 +973,7 @@ noinst_HEADERS = \ priv/guest_mips_defs.h \ priv/mips_defs.h \ priv/guest_nanomips_defs.h \ + priv/guest_loongarch64_defs.h \ priv/host_generic_regs.h \ priv/host_generic_simd64.h \ priv/host_generic_simd128.h \ @@ -962,7 +989,8 @@ noinst_HEADERS = \ priv/s390_defs.h \ priv/host_mips_defs.h \ priv/host_nanomips_defs.h \ - priv/common_nanomips_defs.h + priv/common_nanomips_defs.h \ + priv/host_loongarch64_defs.h BUILT_SOURCES = pub/libvex_guest_offsets.h CLEANFILES = pub/libvex_guest_offsets.h @@ -1006,6 +1034,8 @@ LIBVEX_SOURCES_COMMON = \ priv/guest_mips_toIR.c \ priv/guest_nanomips_helpers.c \ priv/guest_nanomips_toIR.c \ + priv/guest_loongarch64_helpers.c \ + priv/guest_loongarch64_toIR.c \ priv/host_generic_regs.c \ priv/host_generic_simd64.c \ priv/host_generic_simd128.c \ @@ -1029,7 +1059,9 @@ LIBVEX_SOURCES_COMMON = \ priv/host_mips_defs.c \ priv/host_nanomips_defs.c \ priv/host_mips_isel.c \ - priv/host_nanomips_isel.c + priv/host_nanomips_isel.c \ + priv/host_loongarch64_defs.c \ + priv/host_loongarch64_isel.c LIBVEXMULTIARCH_SOURCES = priv/multiarch_main_main.c LIBVEX_CFLAGS_NO_LTO = \ @@ -1195,6 +1227,10 @@ priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_nanomips_helpers.$(OBJEXT): \ priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_nanomips_toIR.$(OBJEXT): \ priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) +priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_loongarch64_helpers.$(OBJEXT): \ + priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) +priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_loongarch64_toIR.$(OBJEXT): \ + priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT): \ priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT): \ @@ -1243,6 +1279,10 @@ priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_isel.$(OBJEXT): \ priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_nanomips_isel.$(OBJEXT): \ priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) +priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_loongarch64_defs.$(OBJEXT): \ + priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) +priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_loongarch64_isel.$(OBJEXT): \ + priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a: $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_DEPENDENCIES) $(EXTRA_libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_DEPENDENCIES) $(AM_V_at)-rm -f libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a @@ -1300,6 +1340,10 @@ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_nanomips_helpers.$(OBJEXT): \ priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_nanomips_toIR.$(OBJEXT): \ priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) +priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_loongarch64_helpers.$(OBJEXT): \ + priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) +priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_loongarch64_toIR.$(OBJEXT): \ + priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT): \ priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT): \ @@ -1348,6 +1392,10 @@ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_isel.$(OBJEXT): \ priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_nanomips_isel.$(OBJEXT): \ priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) +priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.$(OBJEXT): \ + priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) +priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.$(OBJEXT): \ + priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp) libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a: $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS) 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priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.Po @@ -2900,6 +3040,34 @@ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_nanomips_isel.obj: priv/host_na @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_nanomips_isel.obj `if test -f 'priv/host_nanomips_isel.c'; then $(CYGPATH_W) 'priv/host_nanomips_isel.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_nanomips_isel.c'; fi` +priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.o: priv/host_loongarch64_defs.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.o -MD -MP -MF priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.Tpo -c -o priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.o `test -f 'priv/host_loongarch64_defs.c' || echo '$(srcdir)/'`priv/host_loongarch64_defs.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.Tpo priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='priv/host_loongarch64_defs.c' object='priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.o `test -f 'priv/host_loongarch64_defs.c' || echo '$(srcdir)/'`priv/host_loongarch64_defs.c + +priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.obj: priv/host_loongarch64_defs.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.obj -MD -MP -MF priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.Tpo -c -o priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.obj `if test -f 'priv/host_loongarch64_defs.c'; then $(CYGPATH_W) 'priv/host_loongarch64_defs.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_loongarch64_defs.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.Tpo priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='priv/host_loongarch64_defs.c' object='priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.obj `if test -f 'priv/host_loongarch64_defs.c'; then $(CYGPATH_W) 'priv/host_loongarch64_defs.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_loongarch64_defs.c'; fi` + +priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.o: priv/host_loongarch64_isel.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.o -MD -MP -MF priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.Tpo -c -o priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.o `test -f 'priv/host_loongarch64_isel.c' || echo '$(srcdir)/'`priv/host_loongarch64_isel.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.Tpo priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='priv/host_loongarch64_isel.c' object='priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.o `test -f 'priv/host_loongarch64_isel.c' || echo '$(srcdir)/'`priv/host_loongarch64_isel.c + +priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.obj: priv/host_loongarch64_isel.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.obj -MD -MP -MF priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.Tpo -c -o priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.obj `if test -f 'priv/host_loongarch64_isel.c'; then $(CYGPATH_W) 'priv/host_loongarch64_isel.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_loongarch64_isel.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.Tpo priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='priv/host_loongarch64_isel.c' object='priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.obj `if test -f 'priv/host_loongarch64_isel.c'; then $(CYGPATH_W) 'priv/host_loongarch64_isel.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_loongarch64_isel.c'; fi` + priv/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.o: priv/multiarch_main_main.c @am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT priv/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.o -MD -MP -MF priv/$(DEPDIR)/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.Tpo -c -o priv/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.o `test -f 'priv/multiarch_main_main.c' || echo '$(srcdir)/'`priv/multiarch_main_main.c @am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) priv/$(DEPDIR)/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.Tpo priv/$(DEPDIR)/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.Po @@ -3090,6 +3258,8 @@ distclean: distclean-am -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_arm_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_generic_bb_to_IR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_generic_x87.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_loongarch64_helpers.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_loongarch64_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mips_helpers.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mips_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mipsdsp_toIR.Po @@ -3114,6 +3284,8 @@ distclean: distclean-am -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_loongarch64_defs.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_loongarch64_isel.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_defs.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_isel.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_nanomips_defs.Po @@ -3140,6 +3312,8 @@ distclean: distclean-am -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_arm_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_generic_bb_to_IR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_generic_x87.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_loongarch64_helpers.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_loongarch64_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mips_helpers.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mips_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mipsdsp_toIR.Po @@ -3164,6 +3338,8 @@ distclean: distclean-am -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_defs.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_isel.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_nanomips_defs.Po @@ -3237,6 +3413,8 @@ maintainer-clean: maintainer-clean-am -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_arm_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_generic_bb_to_IR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_generic_x87.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_loongarch64_helpers.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_loongarch64_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mips_helpers.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mips_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mipsdsp_toIR.Po @@ -3261,6 +3439,8 @@ maintainer-clean: maintainer-clean-am -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd256.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_loongarch64_defs.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_loongarch64_isel.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_defs.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_isel.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_nanomips_defs.Po @@ -3287,6 +3467,8 @@ maintainer-clean: maintainer-clean-am -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_arm_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_generic_bb_to_IR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_generic_x87.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_loongarch64_helpers.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_loongarch64_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mips_helpers.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mips_toIR.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mipsdsp_toIR.Po @@ -3311,6 +3493,8 @@ maintainer-clean: maintainer-clean-am -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd256.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_defs.Po + -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_loongarch64_isel.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_defs.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_isel.Po -rm -f priv/$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_nanomips_defs.Po @@ -3461,7 +3645,8 @@ pub/libvex_guest_offsets.h: auxprogs/genoffsets.c \ pub/libvex_guest_arm64.h \ pub/libvex_guest_s390x.h \ pub/libvex_guest_mips32.h \ - pub/libvex_guest_mips64.h + pub/libvex_guest_mips64.h \ + pub/libvex_guest_loongarch64.h rm -f auxprogs/genoffsets.s $(mkdir_p) auxprogs pub $(CC) $(CFLAGS_FOR_GENOFFSETS) \ diff --git a/README b/README index 8423880..1a88d1d 100644 --- a/README +++ b/README @@ -41,6 +41,7 @@ platforms: - MIPS32/Linux - MIPS64/Linux - nanoMIPS/Linux +- LOONGARCH64/Linux - X86/Solaris - AMD64/Solaris - X86/FreeBSD diff --git a/README.loongarch64 b/README.loongarch64 new file mode 100644 index 0000000..742bca0 --- /dev/null +++ b/README.loongarch64 @@ -0,0 +1,51 @@ +Status +~~~~~~ + +A port to LoongArch64 Linux platform. + +Some new IROps: + +* Iop_ScaleBF64 +* Iop_ScaleBF32 +* Iop_RSqrtF64 +* Iop_RSqrtF32 +* Iop_LogBF64 +* Iop_LogBF32 +* Iop_MaxNumAbsF64 +* Iop_MinNumAbsF64 +* Iop_MaxNumF32 +* Iop_MinNumF32 +* Iop_MaxNumAbsF32 +* Iop_MinNumAbsF32 +* Iop_Max64Sx4 +* Iop_Max64Ux4 +* Iop_Min64Sx4 +* Iop_Min64Ux4 + +A new IRMBusEvent: + +* Imbe_InsnFence + +A new IRJumpKind: + +* Ijk_SigSYS + + +Limitations +~~~~~~~~~~~ + +* Only the fallback LLSC implementation is supported. +* Not all vector instructions are supported. +* Tests need to be added for vector instructions. + + +Reading Material +~~~~~~~~~~~~~~~~ + +* LoongArch Reference Manual + https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html +* LoongArch ELF ABI specification: + https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html +* LoongArch Toolchain Conventions: + https://loongson.github.io/LoongArch-Documentation/LoongArch-toolchain-conventions-EN.html + diff --git a/VEX/auxprogs/genoffsets.c b/VEX/auxprogs/genoffsets.c index 54376dc..89edf52 100644 --- a/VEX/auxprogs/genoffsets.c +++ b/VEX/auxprogs/genoffsets.c @@ -53,6 +53,7 @@ #include "../pub/libvex_guest_s390x.h" #include "../pub/libvex_guest_mips32.h" #include "../pub/libvex_guest_mips64.h" +#include "../pub/libvex_guest_loongarch64.h" #define VG_STRINGIFZ(__str) #__str #define VG_STRINGIFY(__str) VG_STRINGIFZ(__str) @@ -262,6 +263,41 @@ void foo ( void ) GENOFFSET(MIPS64,mips64,PC); GENOFFSET(MIPS64,mips64,HI); GENOFFSET(MIPS64,mips64,LO); + + // LOONGARCH64 + GENOFFSET(LOONGARCH64,loongarch64,R0); + GENOFFSET(LOONGARCH64,loongarch64,R1); + GENOFFSET(LOONGARCH64,loongarch64,R2); + GENOFFSET(LOONGARCH64,loongarch64,R3); + GENOFFSET(LOONGARCH64,loongarch64,R4); + GENOFFSET(LOONGARCH64,loongarch64,R5); + GENOFFSET(LOONGARCH64,loongarch64,R6); + GENOFFSET(LOONGARCH64,loongarch64,R7); + GENOFFSET(LOONGARCH64,loongarch64,R8); + GENOFFSET(LOONGARCH64,loongarch64,R9); + GENOFFSET(LOONGARCH64,loongarch64,R10); + GENOFFSET(LOONGARCH64,loongarch64,R11); + GENOFFSET(LOONGARCH64,loongarch64,R12); + GENOFFSET(LOONGARCH64,loongarch64,R13); + GENOFFSET(LOONGARCH64,loongarch64,R14); + GENOFFSET(LOONGARCH64,loongarch64,R15); + GENOFFSET(LOONGARCH64,loongarch64,R16); + GENOFFSET(LOONGARCH64,loongarch64,R17); + GENOFFSET(LOONGARCH64,loongarch64,R18); + GENOFFSET(LOONGARCH64,loongarch64,R19); + GENOFFSET(LOONGARCH64,loongarch64,R20); + GENOFFSET(LOONGARCH64,loongarch64,R21); + GENOFFSET(LOONGARCH64,loongarch64,R22); + GENOFFSET(LOONGARCH64,loongarch64,R23); + GENOFFSET(LOONGARCH64,loongarch64,R24); + GENOFFSET(LOONGARCH64,loongarch64,R25); + GENOFFSET(LOONGARCH64,loongarch64,R26); + GENOFFSET(LOONGARCH64,loongarch64,R27); + GENOFFSET(LOONGARCH64,loongarch64,R28); + GENOFFSET(LOONGARCH64,loongarch64,R29); + GENOFFSET(LOONGARCH64,loongarch64,R30); + GENOFFSET(LOONGARCH64,loongarch64,R31); + GENOFFSET(LOONGARCH64,loongarch64,PC); } /*--------------------------------------------------------------------*/ diff --git a/VEX/priv/guest_loongarch64_defs.h b/VEX/priv/guest_loongarch64_defs.h new file mode 100644 index 0000000..c3b572c --- /dev/null +++ b/VEX/priv/guest_loongarch64_defs.h @@ -0,0 +1,131 @@ + +/*---------------------------------------------------------------*/ +/*--- begin guest_loongarch64_defs.h ---*/ +/*---------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +/* Only to be used within the guest-loongarch64 directory. */ + +#ifndef __VEX_GUEST_LOONGARCH64_DEFS_H +#define __VEX_GUEST_LOONGARCH64_DEFS_H + +#include "libvex_basictypes.h" +#include "guest_generic_bb_to_IR.h" /* DisResult */ + + +/*---------------------------------------------------------*/ +/*--- loongarch64 to IR conversion ---*/ +/*---------------------------------------------------------*/ + +/* Convert one LOONGARCH64 insn to IR. See the type DisOneInstrFn in + guest_generic_bb_to_IR.h. */ +extern DisResult disInstr_LOONGARCH64 ( IRSB* irsb_IN, + const UChar* guest_code_IN, + Long delta, + Addr guest_IP, + VexArch guest_arch, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo, + VexEndness host_endness_IN, + Bool sigill_diag_IN ); + +/* Used by the optimiser to specialise calls to helpers. */ +extern IRExpr* guest_loongarch64_spechelper ( const HChar* function_name, + IRExpr** args, + IRStmt** precedingStmts, + Int n_precedingStmts ); + +/* Describes to the optimser which part of the guest state require + precise memory exceptions. This is logically part of the guest + state description. */ +extern Bool guest_loongarch64_state_requires_precise_mem_exns ( Int minoff, + Int maxoff, + VexRegisterUpdates pxControl ); + +extern VexGuestLayout loongarch64Guest_layout; + + +/*---------------------------------------------------------*/ +/*--- loongarch64 guest helpers ---*/ +/*---------------------------------------------------------*/ + +enum fpop { + FADD_S, FADD_D, FSUB_S, FSUB_D, + FMUL_S, FMUL_D, FDIV_S, FDIV_D, + FMADD_S, FMADD_D, FMSUB_S, FMSUB_D, + FNMADD_S, FNMADD_D, FNMSUB_S, FNMSUB_D, + FMAX_S, FMAX_D, FMIN_S, FMIN_D, + FMAXA_S, FMAXA_D, FMINA_S, FMINA_D, + FABS_S, FABS_D, FNEG_S, FNEG_D, + FSQRT_S, FSQRT_D, + FRECIP_S, FRECIP_D, + FRSQRT_S, FRSQRT_D, + FSCALEB_S, FSCALEB_D, + FLOGB_S, FLOGB_D, + FCMP_CAF_S, FCMP_CAF_D, FCMP_SAF_S, FCMP_SAF_D, + FCMP_CLT_S, FCMP_CLT_D, FCMP_SLT_S, FCMP_SLT_D, + FCMP_CEQ_S, FCMP_CEQ_D, FCMP_SEQ_S, FCMP_SEQ_D, + FCMP_CLE_S, FCMP_CLE_D, FCMP_SLE_S, FCMP_SLE_D, + FCMP_CUN_S, FCMP_CUN_D, FCMP_SUN_S, FCMP_SUN_D, + FCMP_CULT_S, FCMP_CULT_D, FCMP_SULT_S, FCMP_SULT_D, + FCMP_CUEQ_S, FCMP_CUEQ_D, FCMP_SUEQ_S, FCMP_SUEQ_D, + FCMP_CULE_S, FCMP_CULE_D, FCMP_SULE_S, FCMP_SULE_D, + FCMP_CNE_S, FCMP_CNE_D, FCMP_SNE_S, FCMP_SNE_D, + FCMP_COR_S, FCMP_COR_D, FCMP_SOR_S, FCMP_SOR_D, + FCMP_CUNE_S, FCMP_CUNE_D, FCMP_SUNE_S, FCMP_SUNE_D, + FCVT_S_D, FCVT_D_S, + FTINTRM_W_S, FTINTRM_W_D, FTINTRM_L_S, FTINTRM_L_D, + FTINTRP_W_S, FTINTRP_W_D, FTINTRP_L_S, FTINTRP_L_D, + FTINTRZ_W_S, FTINTRZ_W_D, FTINTRZ_L_S, FTINTRZ_L_D, + FTINTRNE_W_S, FTINTRNE_W_D, FTINTRNE_L_S, FTINTRNE_L_D, + FTINT_W_S, FTINT_W_D, FTINT_L_S, FTINT_L_D, + FFINT_S_W, FFINT_D_W, FFINT_S_L, FFINT_D_L, + FRINT_S, FRINT_D +}; + +extern ULong loongarch64_calculate_cpucfg ( ULong src ); +extern ULong loongarch64_calculate_revb_2h ( ULong src ); +extern ULong loongarch64_calculate_revb_4h ( ULong src ); +extern ULong loongarch64_calculate_revb_2w ( ULong src ); +extern ULong loongarch64_calculate_revb_d ( ULong src ); +extern ULong loongarch64_calculate_revh_2w ( ULong src ); +extern ULong loongarch64_calculate_revh_d ( ULong src ); +extern ULong loongarch64_calculate_bitrev_4b ( ULong src ); +extern ULong loongarch64_calculate_bitrev_8b ( ULong src ); +extern ULong loongarch64_calculate_bitrev_w ( ULong src ); +extern ULong loongarch64_calculate_bitrev_d ( ULong src ); +extern ULong loongarch64_calculate_crc ( ULong old, ULong msg, ULong len ); +extern ULong loongarch64_calculate_crcc ( ULong old, ULong msg, ULong len ); +extern ULong loongarch64_calculate_fclass_s ( ULong src ); +extern ULong loongarch64_calculate_fclass_d ( ULong src ); +extern ULong loongarch64_calculate_FCSR ( enum fpop op, ULong src1, + ULong src2, ULong src3 ); +extern ULong loongarch64_calculate_negative_id ( ULong insSz, ULong sHi, ULong sLo ); + +#endif /* ndef __VEX_GUEST_LOONGARCH64_DEFS_H */ + + +/*---------------------------------------------------------------*/ +/*--- end guest_loongarch64_defs.h ---*/ +/*---------------------------------------------------------------*/ diff --git a/VEX/priv/guest_loongarch64_helpers.c b/VEX/priv/guest_loongarch64_helpers.c new file mode 100644 index 0000000..e761539 --- /dev/null +++ b/VEX/priv/guest_loongarch64_helpers.c @@ -0,0 +1,905 @@ + +/*---------------------------------------------------------------*/ +/*--- begin guest_loongarch64_helpers.c ---*/ +/*---------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#include "libvex_basictypes.h" +#include "libvex_emnote.h" +#include "libvex_guest_loongarch64.h" +#include "libvex_ir.h" +#include "libvex.h" + +#include "main_util.h" +#include "main_globals.h" +#include "guest_generic_bb_to_IR.h" +#include "guest_loongarch64_defs.h" + + +/* This file contains helper functions for loongarch64 guest code. + Calls to these functions are generated by the back end. */ + +IRExpr* guest_loongarch64_spechelper ( const HChar * function_name, + IRExpr ** args, + IRStmt ** precedingStmts, + Int n_precedingStmts ) +{ + return NULL; +} + +/* VISIBLE TO LIBVEX CLIENT */ +void LibVEX_GuestLOONGARCH64_initialise ( /*OUT*/ + VexGuestLOONGARCH64State* vex_state ) +{ + UInt i; + + /* Event check fail addr and counter. */ + vex_state->host_EvC_FAILADDR = 0; + vex_state->host_EvC_COUNTER = 0; + + /* CPU Registers */ + vex_state->guest_R0 = 0; /* Constant zero */ + vex_state->guest_R1 = 0; /* Return address */ + vex_state->guest_R2 = 0; /* Thread pointer */ + vex_state->guest_R3 = 0; /* Stack pointer */ + vex_state->guest_R4 = 0; /* Argument registers / Return value */ + vex_state->guest_R5 = 0; + vex_state->guest_R6 = 0; /* Argument registers */ + vex_state->guest_R7 = 0; + vex_state->guest_R8 = 0; + vex_state->guest_R9 = 0; + vex_state->guest_R10 = 0; + vex_state->guest_R11 = 0; + vex_state->guest_R12 = 0; /* Temporary registers */ + vex_state->guest_R13 = 0; + vex_state->guest_R14 = 0; + vex_state->guest_R15 = 0; + vex_state->guest_R16 = 0; + vex_state->guest_R17 = 0; + vex_state->guest_R18 = 0; + vex_state->guest_R19 = 0; + vex_state->guest_R20 = 0; + vex_state->guest_R21 = 0; /* Reserved */ + vex_state->guest_R22 = 0; /* Frame pointer / Static register */ + vex_state->guest_R23 = 0; /* Static registers */ + vex_state->guest_R24 = 0; + vex_state->guest_R25 = 0; + vex_state->guest_R26 = 0; + vex_state->guest_R27 = 0; + vex_state->guest_R28 = 0; + vex_state->guest_R29 = 0; + vex_state->guest_R30 = 0; + vex_state->guest_R31 = 0; + + vex_state->guest_PC = 0; /* Program counter */ + + /* FPU/SIMD Registers */ + for (i = 0; i < 8; i++) { + vex_state->guest_X0[i] = 0xffffffff; + vex_state->guest_X1[i] = 0xffffffff; + vex_state->guest_X2[i] = 0xffffffff; + vex_state->guest_X3[i] = 0xffffffff; + vex_state->guest_X4[i] = 0xffffffff; + vex_state->guest_X5[i] = 0xffffffff; + vex_state->guest_X6[i] = 0xffffffff; + vex_state->guest_X7[i] = 0xffffffff; + vex_state->guest_X8[i] = 0xffffffff; + vex_state->guest_X9[i] = 0xffffffff; + vex_state->guest_X10[i] = 0xffffffff; + vex_state->guest_X11[i] = 0xffffffff; + vex_state->guest_X12[i] = 0xffffffff; + vex_state->guest_X13[i] = 0xffffffff; + vex_state->guest_X14[i] = 0xffffffff; + vex_state->guest_X15[i] = 0xffffffff; + vex_state->guest_X16[i] = 0xffffffff; + vex_state->guest_X17[i] = 0xffffffff; + vex_state->guest_X18[i] = 0xffffffff; + vex_state->guest_X19[i] = 0xffffffff; + vex_state->guest_X20[i] = 0xffffffff; + vex_state->guest_X21[i] = 0xffffffff; + vex_state->guest_X22[i] = 0xffffffff; + vex_state->guest_X23[i] = 0xffffffff; + vex_state->guest_X24[i] = 0xffffffff; + vex_state->guest_X25[i] = 0xffffffff; + vex_state->guest_X26[i] = 0xffffffff; + vex_state->guest_X27[i] = 0xffffffff; + vex_state->guest_X28[i] = 0xffffffff; + vex_state->guest_X29[i] = 0xffffffff; + vex_state->guest_X30[i] = 0xffffffff; + vex_state->guest_X31[i] = 0xffffffff; + } + + vex_state->guest_FCC0 = 0; /* Condition Flag Registers */ + vex_state->guest_FCC1 = 0; + vex_state->guest_FCC2 = 0; + vex_state->guest_FCC3 = 0; + vex_state->guest_FCC4 = 0; + vex_state->guest_FCC5 = 0; + vex_state->guest_FCC6 = 0; + vex_state->guest_FCC7 = 0; + vex_state->guest_FCSR = 0; /* FP Control and Status Register */ + + /* Various pseudo-regs mandated by Vex or Valgrind. */ + /* Emulation notes */ + vex_state->guest_EMNOTE = 0; + + /* For clflush: record start and length of area to invalidate */ + vex_state->guest_CMSTART = 0; + vex_state->guest_CMLEN = 0; + + /* Used to record the unredirected guest address at the start of + a translation whose start has been redirected. By reading + this pseudo-register shortly afterwards, the translation can + find out what the corresponding no-redirection address was. + Note, this is only set for wrap-style redirects, not for + replace-style ones. */ + vex_state->guest_NRADDR = 0; +} + + +/*-----------------------------------------------------------*/ +/*--- Describing the loongarch64 guest state, for the ---*/ +/*--- benefit of iropt and instrumenters ---*/ +/*-----------------------------------------------------------*/ + +/* Figure out if any part of the guest state contained in minoff + .. maxoff requires precise memory exceptions. If in doubt return + True (but this generates significantly slower code). + + We enforce precise exns for guest SP, PC and FP. + + Only SP is needed in mode VexRegUpdSpAtMemAccess. +*/ + +Bool guest_loongarch64_state_requires_precise_mem_exns ( Int minoff, + Int maxoff, + VexRegisterUpdates pxControl ) +{ + Int sp_min = offsetof(VexGuestLOONGARCH64State, guest_R3); + Int sp_max = sp_min + 8 - 1; + if ( maxoff < sp_min || minoff > sp_max ) { + /* no overlap with sp */ + if (pxControl == VexRegUpdSpAtMemAccess) + return False; /* We only need to check stack pointer. */ + } else { + return True; + } + + Int pc_min = offsetof(VexGuestLOONGARCH64State, guest_PC); + Int pc_max = pc_min + 8 - 1; + if ( maxoff < pc_min || minoff > pc_max ) { + /* no overlap with pc */ + } else { + return True; + } + + Int fp_min = offsetof(VexGuestLOONGARCH64State, guest_R22); + Int fp_max = fp_min + 8 - 1; + if ( maxoff < fp_min || minoff > fp_max ) { + /* no overlap with fp */ + } else { + return True; + } + + return False; +} + +#define ALWAYSDEFD64(field) \ + { offsetof(VexGuestLOONGARCH64State, field), \ + (sizeof ((VexGuestLOONGARCH64State*)0)->field) } + +VexGuestLayout loongarch64Guest_layout = { + /* Total size of the guest state, in bytes. */ + .total_sizeB = sizeof(VexGuestLOONGARCH64State), + /* Describe the stack pointer. */ + .offset_SP = offsetof(VexGuestLOONGARCH64State, guest_R3), + .sizeof_SP = 8, + /* Describe the frame pointer. */ + .offset_FP = offsetof(VexGuestLOONGARCH64State, guest_R22), + .sizeof_FP = 8, + /* Describe the instruction pointer. */ + .offset_IP = offsetof(VexGuestLOONGARCH64State, guest_PC), + .sizeof_IP = 8, + /* Describe any sections to be regarded by Memcheck as + 'always-defined'. */ + .n_alwaysDefd = 6, + /* ? :( */ + .alwaysDefd = { + /* 0 */ ALWAYSDEFD64(guest_R0), + /* 1 */ ALWAYSDEFD64(guest_PC), + /* 2 */ ALWAYSDEFD64(guest_EMNOTE), + /* 3 */ ALWAYSDEFD64(guest_CMSTART), + /* 4 */ ALWAYSDEFD64(guest_CMLEN), + /* 5 */ ALWAYSDEFD64(guest_NRADDR), + } +}; + + +/*-----------------------------------------------------------*/ +/*--- loongarch64 guest helpers ---*/ +/*-----------------------------------------------------------*/ + +/* Claim to be the following CPU, which is probably representative of + the earliest loongarch64 offerings. + + CPU Family : Loongson-64bit + Model Name : Loongson-3A5000LL + CPU Revision : 0x10 + FPU Revision : 0x00 + CPU MHz : 2300.00 + BogoMIPS : 4600.00 + TLB Entries : 2112 + Address Sizes : 48 bits physical, 48 bits virtual + ISA : loongarch32 loongarch64 + Features : cpucfg lam ual fpu lsx lasx complex crypto lvz + Hardware Watchpoint : yes, iwatch count: 8, dwatch count: 8 +*/ +ULong loongarch64_calculate_cpucfg ( ULong src ) +{ + ULong res; + switch (src) { + case 0x0: + res = 0x0014c010; + break; + case 0x1: + res = 0x03f2f2fe; + break; + case 0x2: + res = 0x007ccfc7; + break; + case 0x3: + res = 0x0000fcff; + break; + case 0x4: + res = 0x05f5e100; + break; + case 0x5: + res = 0x00010001; + break; + case 0x6: + res = 0x00007f33; + break; + case 0x10: + res = 0x00002c3d; + break; + case 0x11: + res = 0x06080003; + break; + case 0x12: + res = 0x06080003; + break; + case 0x13: + res = 0x0608000f; + break; + case 0x14: + res = 0x060e000f; + break; + default: + res = 0x00000000; + break; + } + return (ULong)(Long)(Int)res; +} + +static void swap_UChar ( UChar* a, UChar* b ) +{ + UChar t = *a; + *a = *b; + *b = t; +} + +ULong loongarch64_calculate_revb_2h ( ULong src ) +{ + UChar* s = (UChar*)&src; + swap_UChar(&s[0], &s[1]); + swap_UChar(&s[2], &s[3]); + return (ULong)(Long)(Int)src; +} + +ULong loongarch64_calculate_revb_4h ( ULong src ) +{ + UChar* s = (UChar*)&src; + swap_UChar(&s[0], &s[1]); + swap_UChar(&s[2], &s[3]); + swap_UChar(&s[4], &s[5]); + swap_UChar(&s[6], &s[7]); + return src; +} + +ULong loongarch64_calculate_revb_2w ( ULong src ) +{ + UChar* s = (UChar*)&src; + swap_UChar(&s[0], &s[3]); + swap_UChar(&s[1], &s[2]); + swap_UChar(&s[4], &s[7]); + swap_UChar(&s[5], &s[6]); + return src; +} + +ULong loongarch64_calculate_revb_d ( ULong src ) +{ + UChar* s = (UChar*)&src; + swap_UChar(&s[0], &s[7]); + swap_UChar(&s[1], &s[6]); + swap_UChar(&s[2], &s[5]); + swap_UChar(&s[3], &s[4]); + return src; +} + +static void swap_UShort ( UShort* a, UShort* b ) +{ + UShort t = *a; + *a = *b; + *b = t; +} + +ULong loongarch64_calculate_revh_2w ( ULong src ) +{ + UShort* s = (UShort*)&src; + swap_UShort(&s[0], &s[1]); + swap_UShort(&s[2], &s[3]); + return src; +} + +ULong loongarch64_calculate_revh_d ( ULong src ) +{ + UShort* s = (UShort*)&src; + swap_UShort(&s[0], &s[3]); + swap_UShort(&s[1], &s[2]); + return src; +} + +static ULong bitrev ( ULong src, ULong start, ULong end ) +{ + int i, j; + ULong res = 0; + for (i = start, j = 1; i < end; i++, j++) + res |= ((src >> i) & 1) << (end - j); + return res; +} + +ULong loongarch64_calculate_bitrev_4b ( ULong src ) +{ + ULong res = bitrev(src, 0, 8); + res |= bitrev(src, 8, 16); + res |= bitrev(src, 16, 24); + res |= bitrev(src, 24, 32); + return (ULong)(Long)(Int)res; +} + +ULong loongarch64_calculate_bitrev_8b ( ULong src ) +{ + ULong res = bitrev(src, 0, 8); + res |= bitrev(src, 8, 16); + res |= bitrev(src, 16, 24); + res |= bitrev(src, 24, 32); + res |= bitrev(src, 32, 40); + res |= bitrev(src, 40, 48); + res |= bitrev(src, 48, 56); + res |= bitrev(src, 56, 64); + return res; +} + +ULong loongarch64_calculate_bitrev_w ( ULong src ) +{ + ULong res = bitrev(src, 0, 32); + return (ULong)(Long)(Int)res; +} + +ULong loongarch64_calculate_bitrev_d ( ULong src ) +{ + return bitrev(src, 0, 64); +} + +static ULong crc32 ( ULong old, ULong msg, ULong width, ULong poly ) +{ + int i; + ULong new; + if (width == 8) + msg &= 0xff; + else if (width == 16) + msg &= 0xffff; + else if (width == 32) + msg &= 0xffffffff; + new = (old & 0xffffffff) ^ msg; + for (i = 0; i < width; i++) { + if (new & 1) + new = (new >> 1) ^ poly; + else + new >>= 1; + } + return new; +} + +ULong loongarch64_calculate_crc ( ULong old, ULong msg, ULong len ) +{ + ULong res = crc32(old, msg, len, 0xedb88320); + return (ULong)(Long)(Int)res; +} + +ULong loongarch64_calculate_crcc ( ULong old, ULong msg, ULong len ) +{ + ULong res = crc32(old, msg, len, 0x82f63b78); + return (ULong)(Long)(Int)res; +} + +ULong loongarch64_calculate_fclass_s ( ULong src ) +{ + UInt f = src; + Bool sign = toBool(f >> 31); + if ((f & 0x7fffffff) == 0x7f800000) { + return sign ? 1 << 2 : 1 << 6; + } else if ((f & 0x7fffffff) == 0) { + return sign ? 1 << 5 : 1 << 9; + } else if ((f & 0x7f800000) == 0) { + return sign ? 1 << 4 : 1 << 8; + } else if ((f & ~(1 << 31)) > 0x7f800000) { + return ((UInt)(f << 1) >= 0xff800000) ? 1 << 1 : 1 << 0; + } else { + return sign ? 1 << 3 : 1 << 7; + } +} + +ULong loongarch64_calculate_fclass_d ( ULong src ) +{ + ULong f = src; + Bool sign = toBool(f >> 63); + if ((f & 0x7fffffffffffffffULL) == 0x7ff0000000000000ULL) { + return sign ? 1 << 2 : 1 << 6; + } else if ((f & 0x7fffffffffffffffULL) == 0) { + return sign ? 1 << 5 : 1 << 9; + } else if ((f & 0x7ff0000000000000ULL) == 0) { + return sign ? 1 << 4 : 1 << 8; + } else if ((f & ~(1ULL << 63)) > 0x7ff0000000000000ULL) { + return ((f << 1) >= 0xfff0000000000000ULL) ? 1 << 1 : 1 << 0; + } else { + return sign ? 1 << 3 : 1 << 7; + } +} + +ULong loongarch64_calculate_negative_id ( ULong insSz, ULong sHi, ULong sLo ) +{ + V128 src; + UInt i; + + src.w64[1] = sHi; + src.w64[0] = sLo; + + switch (insSz) { + case 0b00: { + for (i = 0; i < 16; i++) { + if ((Char)src.w8[i] < 0) + break; + } + break; + } + case 0b01: { + for (i = 0; i < 8; i++) { + if ((Short)src.w16[i] < 0) + break; + } + break; + } + default: + vassert(0); + break; + } + + return (ULong)i; +} + +#if defined(__loongarch__) +#define ASM_VOLATILE_UNARY(inst) \ + __asm__ volatile("movfcsr2gr $s0, $r0 \n\t" \ + "movgr2fcsr $r2, $zero \n\t" \ + #inst" $f24, %1 \n\t" \ + "movfcsr2gr %0, $r2 \n\t" \ + "movgr2fcsr $r0, $s0 \n\t" \ + : "=r" (fcsr2) \ + : "f" (src1) \ + : "$s0", "$f24" \ + ) + +#define ASM_VOLATILE_BINARY(inst) \ + __asm__ volatile("movfcsr2gr $s0, $r0 \n\t" \ + "movgr2fcsr $r2, $zero \n\t" \ + #inst" $f24, %1, %2 \n\t" \ + "movfcsr2gr %0, $r2 \n\t" \ + "movgr2fcsr $r0, $s0 \n\t" \ + : "=r" (fcsr2) \ + : "f" (src1), "f" (src2) \ + : "$s0", "$f24" \ + ) + +#define ASM_VOLATILE_TRINARY(inst) \ + __asm__ volatile("movfcsr2gr $s0, $r0 \n\t" \ + "movgr2fcsr $r2, $zero \n\t" \ + #inst" $f24, %1, %2, %3 \n\t" \ + "movfcsr2gr %0, $r2 \n\t" \ + "movgr2fcsr $r0, $s0 \n\t" \ + : "=r" (fcsr2) \ + : "f" (src1), "f" (src2), "f" (src3) \ + : "$s0", "$f24" \ + ) + +#define ASM_VOLATILE_FCMP(inst) \ + __asm__ volatile("movfcsr2gr $s0, $r0 \n\t" \ + "movgr2fcsr $r2, $zero \n\t" \ + #inst" $fcc0, %1, %2 \n\t" \ + "movfcsr2gr %0, $r0 \n\t" \ + "movgr2fcsr $r0, $s0 \n\t" \ + : "=r" (fcsr2) \ + : "f" (src1), "f" (src2) \ + : "$s0", "$fcc0" \ + ) +#endif + +/* Calculate FCSR and return whether an exception needs to be thrown */ +ULong loongarch64_calculate_FCSR ( enum fpop op, ULong src1, + ULong src2, ULong src3 ) +{ + UInt fcsr2 = 0; +#if defined(__loongarch__) + switch (op) { + case FADD_S: + ASM_VOLATILE_BINARY(fadd.s); + break; + case FADD_D: + ASM_VOLATILE_BINARY(fadd.d); + break; + case FSUB_S: + ASM_VOLATILE_BINARY(fsub.s); + break; + case FSUB_D: + ASM_VOLATILE_BINARY(fsub.d); + break; + case FMUL_S: + ASM_VOLATILE_BINARY(fmul.s); + break; + case FMUL_D: + ASM_VOLATILE_BINARY(fmul.d); + break; + case FDIV_S: + ASM_VOLATILE_BINARY(fdiv.s); + break; + case FDIV_D: + ASM_VOLATILE_BINARY(fdiv.d); + break; + case FMADD_S: + ASM_VOLATILE_TRINARY(fmadd.s); + break; + case FMADD_D: + ASM_VOLATILE_TRINARY(fmadd.d); + break; + case FMSUB_S: + ASM_VOLATILE_TRINARY(fmsub.s); + break; + case FMSUB_D: + ASM_VOLATILE_TRINARY(fmsub.d); + break; + case FNMADD_S: + ASM_VOLATILE_TRINARY(fnmadd.s); + break; + case FNMADD_D: + ASM_VOLATILE_TRINARY(fnmadd.d); + break; + case FNMSUB_S: + ASM_VOLATILE_TRINARY(fnmsub.s); + break; + case FNMSUB_D: + ASM_VOLATILE_TRINARY(fnmsub.s); + break; + case FMAX_S: + ASM_VOLATILE_BINARY(fmax.s); + break; + case FMAX_D: + ASM_VOLATILE_BINARY(fmax.d); + break; + case FMIN_S: + ASM_VOLATILE_BINARY(fmin.s); + break; + case FMIN_D: + ASM_VOLATILE_BINARY(fmin.d); + break; + case FMAXA_S: + ASM_VOLATILE_BINARY(fmaxa.s); + break; + case FMAXA_D: + ASM_VOLATILE_BINARY(fmaxa.d); + break; + case FMINA_S: + ASM_VOLATILE_BINARY(fmina.s); + break; + case FMINA_D: + ASM_VOLATILE_BINARY(fmina.s); + break; + case FABS_S: + ASM_VOLATILE_UNARY(fabs.s); + break; + case FABS_D: + ASM_VOLATILE_UNARY(fabs.d); + break; + case FNEG_S: + ASM_VOLATILE_UNARY(fneg.s); + break; + case FNEG_D: + ASM_VOLATILE_UNARY(fneg.d); + break; + case FSQRT_S: + ASM_VOLATILE_UNARY(fsqrt.s); + break; + case FSQRT_D: + ASM_VOLATILE_UNARY(fsqrt.d); + break; + case FRECIP_S: + ASM_VOLATILE_UNARY(frecip.s); + break; + case FRECIP_D: + ASM_VOLATILE_UNARY(frecip.d); + break; + case FRSQRT_S: + ASM_VOLATILE_UNARY(frsqrt.s); + break; + case FRSQRT_D: + ASM_VOLATILE_UNARY(frsqrt.d); + break; + case FSCALEB_S: + ASM_VOLATILE_BINARY(fscaleb.s); + break; + case FSCALEB_D: + ASM_VOLATILE_BINARY(fscaleb.d); + break; + case FLOGB_S: + ASM_VOLATILE_UNARY(flogb.s); + break; + case FLOGB_D: + ASM_VOLATILE_UNARY(flogb.d); + break; + case FCMP_CAF_S: + ASM_VOLATILE_FCMP(fcmp.caf.s); + break; + case FCMP_CAF_D: + ASM_VOLATILE_FCMP(fcmp.caf.d); + break; + case FCMP_SAF_S: + ASM_VOLATILE_FCMP(fcmp.saf.s); + break; + case FCMP_SAF_D: + ASM_VOLATILE_FCMP(fcmp.saf.d); + break; + case FCMP_CLT_S: + ASM_VOLATILE_FCMP(fcmp.clt.s); + break; + case FCMP_CLT_D: + ASM_VOLATILE_FCMP(fcmp.clt.d); + break; + case FCMP_SLT_S: + ASM_VOLATILE_FCMP(fcmp.slt.s); + break; + case FCMP_SLT_D: + ASM_VOLATILE_FCMP(fcmp.slt.d); + break; + case FCMP_CEQ_S: + ASM_VOLATILE_FCMP(fcmp.ceq.s); + break; + case FCMP_CEQ_D: + ASM_VOLATILE_FCMP(fcmp.ceq.d); + break; + case FCMP_SEQ_S: + ASM_VOLATILE_FCMP(fcmp.seq.s); + break; + case FCMP_SEQ_D: + ASM_VOLATILE_FCMP(fcmp.seq.d); + break; + case FCMP_CLE_S: + ASM_VOLATILE_FCMP(fcmp.cle.s); + break; + case FCMP_CLE_D: + ASM_VOLATILE_FCMP(fcmp.cle.d); + break; + case FCMP_SLE_S: + ASM_VOLATILE_FCMP(fcmp.sle.s); + break; + case FCMP_SLE_D: + ASM_VOLATILE_FCMP(fcmp.sle.d); + break; + case FCMP_CUN_S: + ASM_VOLATILE_FCMP(fcmp.cun.s); + break; + case FCMP_CUN_D: + ASM_VOLATILE_FCMP(fcmp.cun.d); + break; + case FCMP_SUN_S: + ASM_VOLATILE_FCMP(fcmp.sun.s); + break; + case FCMP_SUN_D: + ASM_VOLATILE_FCMP(fcmp.sun.d); + break; + case FCMP_CULT_S: + ASM_VOLATILE_FCMP(fcmp.cult.s); + break; + case FCMP_CULT_D: + ASM_VOLATILE_FCMP(fcmp.cult.d); + break; + case FCMP_SULT_S: + ASM_VOLATILE_FCMP(fcmp.sult.s); + break; + case FCMP_SULT_D: + ASM_VOLATILE_FCMP(fcmp.sult.d); + break; + case FCMP_CUEQ_S: + ASM_VOLATILE_FCMP(fcmp.cueq.s); + break; + case FCMP_CUEQ_D: + ASM_VOLATILE_FCMP(fcmp.cueq.d); + break; + case FCMP_SUEQ_S: + ASM_VOLATILE_FCMP(fcmp.sueq.s); + break; + case FCMP_SUEQ_D: + ASM_VOLATILE_FCMP(fcmp.sueq.d); + break; + case FCMP_CULE_S: + ASM_VOLATILE_FCMP(fcmp.cule.s); + break; + case FCMP_CULE_D: + ASM_VOLATILE_FCMP(fcmp.cule.d); + break; + case FCMP_SULE_S: + ASM_VOLATILE_FCMP(fcmp.sule.s); + break; + case FCMP_SULE_D: + ASM_VOLATILE_FCMP(fcmp.sule.d); + break; + case FCMP_CNE_S: + ASM_VOLATILE_FCMP(fcmp.cne.s); + break; + case FCMP_CNE_D: + ASM_VOLATILE_FCMP(fcmp.cne.d); + break; + case FCMP_SNE_S: + ASM_VOLATILE_FCMP(fcmp.sne.s); + break; + case FCMP_SNE_D: + ASM_VOLATILE_FCMP(fcmp.sne.d); + break; + case FCMP_COR_S: + ASM_VOLATILE_FCMP(fcmp.cor.s); + break; + case FCMP_COR_D: + ASM_VOLATILE_FCMP(fcmp.cor.d); + break; + case FCMP_SOR_S: + ASM_VOLATILE_FCMP(fcmp.sor.s); + break; + case FCMP_SOR_D: + ASM_VOLATILE_FCMP(fcmp.sor.d); + break; + case FCMP_CUNE_S: + ASM_VOLATILE_FCMP(fcmp.cune.s); + break; + case FCMP_CUNE_D: + ASM_VOLATILE_FCMP(fcmp.cune.d); + break; + case FCMP_SUNE_S: + ASM_VOLATILE_FCMP(fcmp.sune.s); + break; + case FCMP_SUNE_D: + ASM_VOLATILE_FCMP(fcmp.sune.d); + break; + case FCVT_S_D: + ASM_VOLATILE_UNARY(fcvt.s.d); + break; + case FCVT_D_S: + ASM_VOLATILE_UNARY(fcvt.d.s); + break; + case FTINTRM_W_S: + ASM_VOLATILE_UNARY(ftintrm.w.s); + break; + case FTINTRM_W_D: + ASM_VOLATILE_UNARY(ftintrm.w.d); + break; + case FTINTRM_L_S: + ASM_VOLATILE_UNARY(ftintrm.l.s); + break; + case FTINTRM_L_D: + ASM_VOLATILE_UNARY(ftintrm.l.d); + break; + case FTINTRP_W_S: + ASM_VOLATILE_UNARY(ftintrp.w.s); + break; + case FTINTRP_W_D: + ASM_VOLATILE_UNARY(ftintrp.w.d); + break; + case FTINTRP_L_S: + ASM_VOLATILE_UNARY(ftintrp.l.s); + break; + case FTINTRP_L_D: + ASM_VOLATILE_UNARY(ftintrp.l.d); + break; + case FTINTRZ_W_S: + ASM_VOLATILE_UNARY(ftintrz.w.s); + break; + case FTINTRZ_W_D: + ASM_VOLATILE_UNARY(ftintrz.w.d); + break; + case FTINTRZ_L_S: + ASM_VOLATILE_UNARY(ftintrz.l.s); + break; + case FTINTRZ_L_D: + ASM_VOLATILE_UNARY(ftintrz.l.d); + break; + case FTINTRNE_W_S: + ASM_VOLATILE_UNARY(ftintrne.w.s); + break; + case FTINTRNE_W_D: + ASM_VOLATILE_UNARY(ftintrne.w.d); + break; + case FTINTRNE_L_S: + ASM_VOLATILE_UNARY(ftintrne.l.s); + break; + case FTINTRNE_L_D: + ASM_VOLATILE_UNARY(ftintrne.l.d); + break; + case FTINT_W_S: + ASM_VOLATILE_UNARY(ftint.w.s); + break; + case FTINT_W_D: + ASM_VOLATILE_UNARY(ftint.w.d); + break; + case FTINT_L_S: + ASM_VOLATILE_UNARY(ftint.l.s); + break; + case FTINT_L_D: + ASM_VOLATILE_UNARY(ftint.l.d); + break; + case FFINT_S_W: + ASM_VOLATILE_UNARY(ffint.s.w); + break; + case FFINT_D_W: + ASM_VOLATILE_UNARY(ffint.d.w); + break; + case FFINT_S_L: + ASM_VOLATILE_UNARY(ffint.s.l); + break; + case FFINT_D_L: + ASM_VOLATILE_UNARY(ffint.d.l); + break; + case FRINT_S: + ASM_VOLATILE_UNARY(frint.s); + break; + case FRINT_D: + ASM_VOLATILE_UNARY(frint.d); + break; + default: + break; + } +#endif + return (ULong)fcsr2; +} + + +/*---------------------------------------------------------------*/ +/*--- end guest_loongarch64_helpers.c ---*/ +/*---------------------------------------------------------------*/ diff --git a/VEX/priv/guest_loongarch64_toIR.c b/VEX/priv/guest_loongarch64_toIR.c new file mode 100644 index 0000000..50c24f1 --- /dev/null +++ b/VEX/priv/guest_loongarch64_toIR.c @@ -0,0 +1,12086 @@ + +/*--------------------------------------------------------------------*/ +/*--- begin guest_loongarch64_toIR.c ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +/* "Special" instructions. + + This instruction decoder can decode four special instructions + which mean nothing natively (are no-ops as far as regs/mem are + concerned) but have meaning for supporting Valgrind. A special + instruction is flagged by a 16-byte preamble: + + 00450c00 (srli.d $zero, $zero, 3 + 00453400 srli.d $zero, $zero, 13 + 00457400 srli.d $zero, $zero, 29 + 00454c00 srli.d $zero, $zero, 19) + + Following that, one of the following 3 are allowed + (standard interpretation in parentheses): + + 001535ad (or $t1, $t1, $t1) $a7 = client_request ( $t0 ) + 001539ce (or $t2, $t2, $t2) $a7 = guest_NRADDR + 00153def (or $t3, $t3, $t3) call-noredir $t8 + 00154210 (or $t4, $t4, $t4) IR injection + + Any other bytes following the 16-byte preamble are illegal and + constitute a failure in instruction decoding. This all assumes + that the preamble will never occur except in specific code + fragments designed for Valgrind to catch. +*/ + +/* Translates LOONGARCH64 code to IR. */ + +#include "libvex_basictypes.h" +#include "libvex_ir.h" +#include "libvex.h" +#include "libvex_guest_loongarch64.h" + +#include "main_util.h" +#include "main_globals.h" +#include "guest_generic_bb_to_IR.h" +#include "guest_loongarch64_defs.h" + + +/*------------------------------------------------------------*/ +/*--- Globals ---*/ +/*------------------------------------------------------------*/ + +/* These are set at the start of the translation of a instruction, so + that we don't have to pass them around endlessly. CONST means does + not change during translation of the instruction. */ + +/* CONST: what is the host's endianness? We need to know this in + order to do sub-register accesses to the SIMD/FP registers + correctly. */ +static VexEndness host_endness; + +/* CONST: The guest address for the instruction currently being + translated. */ +static Addr64 guest_PC_curr_instr; + +/* MOD: The IRSB* into which we're generating code. */ +static IRSB* irsb; + + +/*------------------------------------------------------------*/ +/*--- Debugging output ---*/ +/*------------------------------------------------------------*/ + +#define DIP(format, args...) \ + if (vex_traceflags & VEX_TRACE_FE) \ + vex_printf(format, ## args) + +static const HChar* nameIReg( UInt reg ) +{ + vassert(reg < 32); + static const HChar* reg_names[32] = { + "$zero", + "$ra", + "$tp", + "$sp", + "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", + "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8", + "$r21", /* Reserved */ + "$fp", + "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", "$s8" + }; + return reg_names[reg]; +} + +static const HChar* nameFReg( UInt reg ) +{ + vassert(reg < 32); + static const HChar* reg_names[32] = { + "$fa0", "$fa1", "$fa2", "$fa3", "$fa4", "$fa5", "$fa6", "$fa7", + "$ft0", "$ft1", "$ft2", "$ft3", "$ft4", "$ft5", "$ft6", "$ft7", + "$ft8", "$ft9", "$ft10", "$ft11", "$ft12", "$ft13", "$ft14", "$ft15", + "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", "$fs6", "$fs7" + }; + return reg_names[reg]; +} + +static const HChar* nameVReg( UInt reg ) +{ + vassert(reg < 32); + static const HChar* reg_names[32] = { + "$vr0", "$vr1", "$vr2", "$vr3", "$vr4", "$vr5", "$vr6", "$vr7", + "$vr8", "$vr9", "$vr10", "$vr11", "$vr12", "$vr13", "$vr14", "$vr15", + "$vr16", "$vr17", "$vr18", "$vr19", "$vr20", "$vr21", "$vr22", "$vr23", + "$vr24", "$vr25", "$vr26", "$vr27", "$vr28", "$vr29", "$vr30", "$vr31" + }; + return reg_names[reg]; +} + +static const HChar* nameXReg( UInt reg ) +{ + vassert(reg < 32); + static const HChar* reg_names[32] = { + "$xr0", "$xr1", "$xr2", "$xr3", "$xr4", "$xr5", "$xr6", "$xr7", + "$xr8", "$xr9", "$xr10", "$xr11", "$xr12", "$xr13", "$xr14", "$xr15", + "$xr16", "$xr17", "$xr18", "$xr19", "$xr20", "$xr21", "$xr22", "$xr23", + "$xr24", "$xr25", "$xr26", "$xr27", "$xr28", "$xr29", "$xr30", "$xr31" + }; + return reg_names[reg]; +} + +static const HChar* nameFCC( UInt reg ) +{ + vassert(reg < 8); + static const HChar* reg_names[8] = { + "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fcc7" + }; + return reg_names[reg]; +} + +static const HChar* nameFCSR( UInt reg ) +{ + vassert(reg < 4); + static const HChar* reg_names[4] = { + "$fcsr0", "$fcsr1", "$fcsr2", "$fcsr3" + }; + return reg_names[reg]; +} + + +/*------------------------------------------------------------*/ +/*--- Helper bits and pieces for deconstructing the ---*/ +/*--- loongarch64 insn stream. ---*/ +/*------------------------------------------------------------*/ + +/* Get insn[max:min] */ +#define SLICE(insn, max, min) \ + ((((UInt)(insn)) >> (min)) & (UInt)((1ULL << ((max) - (min) + 1)) - 1ULL)) + +/* Do a little-endian load of a 32-bit word, regardless of the + endianness of the underlying host. */ +static inline UInt getUInt ( const UChar* p ) +{ + UInt w = 0; + w = (w << 8) | p[3]; + w = (w << 8) | p[2]; + w = (w << 8) | p[1]; + w = (w << 8) | p[0]; + return w; +} + +/* Sign extend to 32-bit */ +static inline UInt extend32 ( UInt imm, UInt size ) +{ + UInt shift = 32 - size; + return (UInt)(((Int)imm << shift) >> shift); +} + +/* Sign extend to 64-bit */ +static inline ULong extend64 ( ULong imm, UInt size ) +{ + UInt shift = 64 - size; + return (ULong)(((Long)imm << shift) >> shift); +} + +/* Get the suffix of the insn */ +static const HChar *mkInsSize ( UInt size ) { + const HChar *insSize[8] + = { "b", "h", "w", "d", "bu", "hu", "wu", "du" }; + vassert(size < 8); + return insSize[size]; +} + + +/*------------------------------------------------------------*/ +/*--- Helper bits and pieces for creating IR fragments. ---*/ +/*------------------------------------------------------------*/ + +static inline IRExpr* mkU64 ( ULong i ) +{ + return IRExpr_Const(IRConst_U64(i)); +} + +static inline IRExpr* mkU32 ( UInt i ) +{ + return IRExpr_Const(IRConst_U32(i)); +} + +static inline IRExpr* mkU16 ( UShort i ) +{ + return IRExpr_Const(IRConst_U16(i)); +} + +static inline IRExpr* mkU8 ( UChar i ) +{ + return IRExpr_Const(IRConst_U8(i)); +} + +static inline IRExpr* mkU1 ( Bool i ) +{ + return IRExpr_Const(IRConst_U1(i)); +} + +static inline IRExpr* mkF64i ( ULong i ) +{ + return IRExpr_Const(IRConst_F64i(i)); +} + +static inline IRExpr* mkF32i ( UInt i ) +{ + return IRExpr_Const(IRConst_F32i(i)); +} + +static inline IRExpr* mkV128 ( UShort i ) +{ + return IRExpr_Const(IRConst_V128(i)); +} + +static inline IRExpr* mkexpr ( IRTemp tmp ) +{ + return IRExpr_RdTmp(tmp); +} + +static inline IRExpr* unop ( IROp op, IRExpr* a ) +{ + return IRExpr_Unop(op, a); +} + +static inline IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) +{ + return IRExpr_Binop(op, a1, a2); +} + +static inline IRExpr* triop ( IROp op, IRExpr* a1, IRExpr* a2, IRExpr* a3 ) +{ + return IRExpr_Triop(op, a1, a2, a3); +} + +static inline IRExpr* qop ( IROp op, IRExpr* a1, IRExpr* a2, + IRExpr* a3, IRExpr* a4 ) +{ + return IRExpr_Qop(op, a1, a2, a3, a4); +} + +static inline IRExpr* load ( IRType ty, IRExpr* addr ) +{ + return IRExpr_Load(Iend_LE, ty, addr); +} + +/* Add a statement to the list held by "irbb". */ +static inline void stmt ( IRStmt* st ) +{ + addStmtToIRSB(irsb, st); +} + +static inline void store ( IRExpr* addr, IRExpr* data ) +{ + stmt(IRStmt_Store(Iend_LE, addr, data)); +} + +static inline void assign ( IRTemp dst, IRExpr* e ) +{ + stmt(IRStmt_WrTmp(dst, e)); +} + +static inline void exit ( IRExpr* e, IRJumpKind jk, ULong offs ) +{ + stmt(IRStmt_Exit(e, jk, IRConst_U64(guest_PC_curr_instr + offs), + offsetof(VexGuestLOONGARCH64State, guest_PC))); +} + +/* Generate an expression to check if addr is aligned. */ +static inline IRExpr* check_align ( IRExpr* addr, IRExpr* align ) +{ + return binop(Iop_CmpNE64, binop(Iop_And64, addr, align), + IRExpr_Get(offsetof(VexGuestLOONGARCH64State, guest_R0), + Ity_I64)); +} + +/* Generate a SIGSYS if the expression evaluates to true. */ +static inline void gen_SIGSYS ( IRExpr* cond ) +{ + exit(cond, Ijk_SigSYS, 4); +} + +/* Generate a SIGBUS if the expression evaluates to true. */ +static inline void gen_SIGBUS ( IRExpr* cond ) +{ + exit(cond, Ijk_SigBUS, 4); +} + +static inline void cas ( IRTemp old, IRExpr* addr, IRExpr* expd, IRExpr* new ) +{ + IRCAS* c = mkIRCAS(IRTemp_INVALID, old, Iend_LE, addr, + NULL, expd, NULL, new); + stmt(IRStmt_CAS(c)); +} + +/* Generate a new temporary of the given type. */ +static inline IRTemp newTemp ( IRType ty ) +{ + vassert(isPlausibleIRType(ty)); + return newIRTemp(irsb->tyenv, ty); +} + +/* S-extend 8/16/32 bit int expr to 64. */ +static IRExpr* extendS ( IRType ty, IRExpr* e ) +{ + switch (ty) { + case Ity_I1: return unop(Iop_1Sto64, e); + case Ity_I8: return unop(Iop_8Sto64, e); + case Ity_I16: return unop(Iop_16Sto64, e); + case Ity_I32: return unop(Iop_32Sto64, e); + default: vassert(0); + } +} + +/* Z-extend 8/16/32 bit int expr to 64. */ +static IRExpr* extendU ( IRType ty, IRExpr* e ) +{ + switch (ty) { + case Ity_I1: return unop(Iop_1Uto64, e); + case Ity_I8: return unop(Iop_8Uto64, e); + case Ity_I16: return unop(Iop_16Uto64, e); + case Ity_I32: return unop(Iop_32Uto64, e); + default: vassert(0); + } +} + +/* Break a V128-bit value up into four 32-bit ints. */ +static void breakupV128to32s ( IRTemp t128, + IRTemp* t3, IRTemp* t2, + IRTemp* t1, IRTemp* t0 ) +{ + IRTemp hi64 = newTemp(Ity_I64); + IRTemp lo64 = newTemp(Ity_I64); + assign(hi64, unop(Iop_V128HIto64, mkexpr(t128))); + assign(lo64, unop(Iop_V128to64, mkexpr(t128))); + + vassert(t0 && *t0 == IRTemp_INVALID); + vassert(t1 && *t1 == IRTemp_INVALID); + vassert(t2 && *t2 == IRTemp_INVALID); + vassert(t3 && *t3 == IRTemp_INVALID); + *t0 = newTemp(Ity_I32); + *t1 = newTemp(Ity_I32); + *t2 = newTemp(Ity_I32); + *t3 = newTemp(Ity_I32); + assign(*t0, unop(Iop_64to32, mkexpr(lo64))); + assign(*t1, unop(Iop_64HIto32, mkexpr(lo64))); + assign(*t2, unop(Iop_64to32, mkexpr(hi64))); + assign(*t3, unop(Iop_64HIto32, mkexpr(hi64))); +} + +/* Break a V256-bit value up into four 64-bit ints. */ +static void breakupV256to64s ( IRTemp t256, + IRTemp* t3, IRTemp* t2, + IRTemp* t1, IRTemp* t0 ) +{ + vassert(t0 && *t0 == IRTemp_INVALID); + vassert(t1 && *t1 == IRTemp_INVALID); + vassert(t2 && *t2 == IRTemp_INVALID); + vassert(t3 && *t3 == IRTemp_INVALID); + *t0 = newTemp(Ity_I64); + *t1 = newTemp(Ity_I64); + *t2 = newTemp(Ity_I64); + *t3 = newTemp(Ity_I64); + assign(*t0, unop(Iop_V256to64_0, mkexpr(t256))); + assign(*t1, unop(Iop_V256to64_1, mkexpr(t256))); + assign(*t2, unop(Iop_V256to64_2, mkexpr(t256))); + assign(*t3, unop(Iop_V256to64_3, mkexpr(t256))); +} + +/* Break a V256-bit value up into two V128s. */ +static void breakupV256toV128s ( IRTemp t256, + IRTemp* hi, IRTemp* lo ) +{ + vassert(hi && *hi == IRTemp_INVALID); + vassert(lo && *lo == IRTemp_INVALID); + *hi = newTemp(Ity_V128); + *lo = newTemp(Ity_V128); + assign(*hi, unop(Iop_V256toV128_1, mkexpr(t256))); + assign(*lo, unop(Iop_V256toV128_0, mkexpr(t256))); +} + +/* Break a V256-bit value up into eight 32-bit ints. */ +static void breakupV256to32s ( IRTemp t256, + IRTemp* t7, IRTemp* t6, + IRTemp* t5, IRTemp* t4, + IRTemp* t3, IRTemp* t2, + IRTemp* t1, IRTemp* t0 ) +{ + IRTemp t128_1 = IRTemp_INVALID; + IRTemp t128_0 = IRTemp_INVALID; + breakupV256toV128s(t256, &t128_1, &t128_0); + breakupV128to32s(t128_1, t7, t6, t5, t4); + breakupV128to32s(t128_0, t3, t2, t1, t0); +} + +/* Construct a V256-bit value from four 64-bit ints. */ +static IRExpr* mkV256from64s ( IRTemp t3, IRTemp t2, + IRTemp t1, IRTemp t0 ) +{ + return binop(Iop_V128HLtoV256, + binop(Iop_64HLtoV128, mkexpr(t3), mkexpr(t2)), + binop(Iop_64HLtoV128, mkexpr(t1), mkexpr(t0))); +} + +/* Construct a V256-bit value from eight 32-bit ints. */ +static IRExpr* mkV256from32s ( IRTemp t7, IRTemp t6, + IRTemp t5, IRTemp t4, + IRTemp t3, IRTemp t2, + IRTemp t1, IRTemp t0 ) +{ + return binop(Iop_V128HLtoV256, + binop(Iop_64HLtoV128, + binop(Iop_32HLto64, mkexpr(t7), mkexpr(t6)), + binop(Iop_32HLto64, mkexpr(t5), mkexpr(t4))), + binop(Iop_64HLtoV128, + binop(Iop_32HLto64, mkexpr(t3), mkexpr(t2)), + binop(Iop_32HLto64, mkexpr(t1), mkexpr(t0))) + ); +} + +static IROp mkVecGetElem ( UInt size ) { + const IROp ops[4] + = { Iop_GetElem8x16, Iop_GetElem16x8, + Iop_GetElem32x4, Iop_GetElem64x2 }; + vassert(size < 4); + return ops[size]; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for accessing guest registers. ---*/ +/*------------------------------------------------------------*/ + +/* ---------------- Integer registers ---------------- */ + +static Int offsetIReg ( UInt iregNo ) +{ + switch (iregNo) { + case 0: return offsetof(VexGuestLOONGARCH64State, guest_R0); + case 1: return offsetof(VexGuestLOONGARCH64State, guest_R1); + case 2: return offsetof(VexGuestLOONGARCH64State, guest_R2); + case 3: return offsetof(VexGuestLOONGARCH64State, guest_R3); + case 4: return offsetof(VexGuestLOONGARCH64State, guest_R4); + case 5: return offsetof(VexGuestLOONGARCH64State, guest_R5); + case 6: return offsetof(VexGuestLOONGARCH64State, guest_R6); + case 7: return offsetof(VexGuestLOONGARCH64State, guest_R7); + case 8: return offsetof(VexGuestLOONGARCH64State, guest_R8); + case 9: return offsetof(VexGuestLOONGARCH64State, guest_R9); + case 10: return offsetof(VexGuestLOONGARCH64State, guest_R10); + case 11: return offsetof(VexGuestLOONGARCH64State, guest_R11); + case 12: return offsetof(VexGuestLOONGARCH64State, guest_R12); + case 13: return offsetof(VexGuestLOONGARCH64State, guest_R13); + case 14: return offsetof(VexGuestLOONGARCH64State, guest_R14); + case 15: return offsetof(VexGuestLOONGARCH64State, guest_R15); + case 16: return offsetof(VexGuestLOONGARCH64State, guest_R16); + case 17: return offsetof(VexGuestLOONGARCH64State, guest_R17); + case 18: return offsetof(VexGuestLOONGARCH64State, guest_R18); + case 19: return offsetof(VexGuestLOONGARCH64State, guest_R19); + case 20: return offsetof(VexGuestLOONGARCH64State, guest_R20); + case 21: return offsetof(VexGuestLOONGARCH64State, guest_R21); + case 22: return offsetof(VexGuestLOONGARCH64State, guest_R22); + case 23: return offsetof(VexGuestLOONGARCH64State, guest_R23); + case 24: return offsetof(VexGuestLOONGARCH64State, guest_R24); + case 25: return offsetof(VexGuestLOONGARCH64State, guest_R25); + case 26: return offsetof(VexGuestLOONGARCH64State, guest_R26); + case 27: return offsetof(VexGuestLOONGARCH64State, guest_R27); + case 28: return offsetof(VexGuestLOONGARCH64State, guest_R28); + case 29: return offsetof(VexGuestLOONGARCH64State, guest_R29); + case 30: return offsetof(VexGuestLOONGARCH64State, guest_R30); + case 31: return offsetof(VexGuestLOONGARCH64State, guest_R31); + default: vassert(0); + } +} + +static IRExpr* getIReg8 ( UInt iregNo ) +{ + return IRExpr_Get(offsetIReg(iregNo), Ity_I8); +} + +static IRExpr* getIReg16 ( UInt iregNo ) +{ + return IRExpr_Get(offsetIReg(iregNo), Ity_I16); +} + +static IRExpr* getIReg32 ( UInt iregNo ) +{ + return IRExpr_Get(offsetIReg(iregNo), Ity_I32); +} + +static IRExpr* getIReg64 ( UInt iregNo ) +{ + return IRExpr_Get(offsetIReg(iregNo), Ity_I64); +} + +static void putIReg ( UInt iregNo, IRExpr* e ) +{ + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); + if (iregNo != 0) /* $r0 - constant zero */ + stmt(IRStmt_Put(offsetIReg(iregNo), e)); +} + +static void putPC ( IRExpr* e ) +{ + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); + stmt(IRStmt_Put(offsetof(VexGuestLOONGARCH64State, guest_PC), e)); +} + +/* ---------------- Floating point / vector registers ---------------- */ + +static Int offsetXReg ( UInt iregNo ) +{ + switch (iregNo) { + case 0: return offsetof(VexGuestLOONGARCH64State, guest_X0); + case 1: return offsetof(VexGuestLOONGARCH64State, guest_X1); + case 2: return offsetof(VexGuestLOONGARCH64State, guest_X2); + case 3: return offsetof(VexGuestLOONGARCH64State, guest_X3); + case 4: return offsetof(VexGuestLOONGARCH64State, guest_X4); + case 5: return offsetof(VexGuestLOONGARCH64State, guest_X5); + case 6: return offsetof(VexGuestLOONGARCH64State, guest_X6); + case 7: return offsetof(VexGuestLOONGARCH64State, guest_X7); + case 8: return offsetof(VexGuestLOONGARCH64State, guest_X8); + case 9: return offsetof(VexGuestLOONGARCH64State, guest_X9); + case 10: return offsetof(VexGuestLOONGARCH64State, guest_X10); + case 11: return offsetof(VexGuestLOONGARCH64State, guest_X11); + case 12: return offsetof(VexGuestLOONGARCH64State, guest_X12); + case 13: return offsetof(VexGuestLOONGARCH64State, guest_X13); + case 14: return offsetof(VexGuestLOONGARCH64State, guest_X14); + case 15: return offsetof(VexGuestLOONGARCH64State, guest_X15); + case 16: return offsetof(VexGuestLOONGARCH64State, guest_X16); + case 17: return offsetof(VexGuestLOONGARCH64State, guest_X17); + case 18: return offsetof(VexGuestLOONGARCH64State, guest_X18); + case 19: return offsetof(VexGuestLOONGARCH64State, guest_X19); + case 20: return offsetof(VexGuestLOONGARCH64State, guest_X20); + case 21: return offsetof(VexGuestLOONGARCH64State, guest_X21); + case 22: return offsetof(VexGuestLOONGARCH64State, guest_X22); + case 23: return offsetof(VexGuestLOONGARCH64State, guest_X23); + case 24: return offsetof(VexGuestLOONGARCH64State, guest_X24); + case 25: return offsetof(VexGuestLOONGARCH64State, guest_X25); + case 26: return offsetof(VexGuestLOONGARCH64State, guest_X26); + case 27: return offsetof(VexGuestLOONGARCH64State, guest_X27); + case 28: return offsetof(VexGuestLOONGARCH64State, guest_X28); + case 29: return offsetof(VexGuestLOONGARCH64State, guest_X29); + case 30: return offsetof(VexGuestLOONGARCH64State, guest_X30); + case 31: return offsetof(VexGuestLOONGARCH64State, guest_X31); + default: vassert(0); + } +} + +static Int offsetFCC ( UInt iregNo ) +{ + switch (iregNo) { + case 0: return offsetof(VexGuestLOONGARCH64State, guest_FCC0); + case 1: return offsetof(VexGuestLOONGARCH64State, guest_FCC1); + case 2: return offsetof(VexGuestLOONGARCH64State, guest_FCC2); + case 3: return offsetof(VexGuestLOONGARCH64State, guest_FCC3); + case 4: return offsetof(VexGuestLOONGARCH64State, guest_FCC4); + case 5: return offsetof(VexGuestLOONGARCH64State, guest_FCC5); + case 6: return offsetof(VexGuestLOONGARCH64State, guest_FCC6); + case 7: return offsetof(VexGuestLOONGARCH64State, guest_FCC7); + default: vassert(0); + } +} + +/* Find the offset of the laneNo'th lane of type laneTy in the given + Xreg. Since the host is little-endian, the least significant lane + has the lowest offset. */ +static Int offsetXRegLane ( UInt xregNo, IRType laneTy, UInt laneNo ) +{ + vassert(host_endness == VexEndnessLE); + Int laneSzB; + /* Since the host is little-endian, the least significant lane + will be at the lowest address. */ + switch (laneTy) { + case Ity_F32: laneSzB = 4; break; + case Ity_F64: laneSzB = 8; break; + case Ity_V128: laneSzB = 16; break; + case Ity_V256: laneSzB = 32; break; + default: vassert(0); break; + } + return offsetXReg(xregNo) + laneNo * laneSzB; +} + +static IRExpr* getXReg ( UInt xregNo ) +{ + return IRExpr_Get(offsetXRegLane(xregNo, Ity_V256, 0), Ity_V256); +} + +static IRExpr* getVReg ( UInt vregNo ) +{ + return IRExpr_Get(offsetXRegLane(vregNo, Ity_V128, 0), Ity_V128); +} + +static IRExpr* getFReg64 ( UInt fregNo ) +{ + return IRExpr_Get(offsetXRegLane(fregNo, Ity_F64, 0), Ity_F64); +} + +static IRExpr* getFReg32 ( UInt fregNo ) +{ + /* Get FReg32 from FReg64. + We could probably use IRExpr_Get(offsetXRegLane(fregNo, Ity_F32, 0), Ity_F32), + but that would cause Memcheck to report some errors. + */ + IRExpr* i = unop(Iop_ReinterpF64asI64, getFReg64(fregNo)); + return unop(Iop_ReinterpI32asF32, unop(Iop_64to32, i)); +} + +static IRExpr* getFCC ( UInt iregNo ) +{ + return IRExpr_Get(offsetFCC(iregNo), Ity_I8); +} + +static IRExpr* getFCSR ( UInt iregNo ) +{ + /* + bits | name + --------------- + 4:0 | Enables + 7:5 | 0 + 9:8 | RM + 15:10 | 0 + 20:16 | Flags + 23:21 | 0 + 28:24 | Cause + 31:29 | 0 + */ + Int offs = offsetof(VexGuestLOONGARCH64State, guest_FCSR); + IRExpr* fcsr0 = IRExpr_Get(offs, Ity_I32); + switch (iregNo) { + case 0: + return fcsr0; + case 1: + /* FCSR1 is Enables of FCSR0. It seems that the hardware + implementation is that the 7th bit belongs to FCSR1. */ + return binop(Iop_And32, fcsr0, mkU32(0x0000009f)); + case 2: + /* FCSR2 is Cause and Flags of FCSR0. */ + return binop(Iop_And32, fcsr0, mkU32(0x1f1f0000)); + case 3: + /* FCSR3 is RM of FCSR0. */ + return binop(Iop_And32, fcsr0, mkU32(0x00000300)); + default: + vassert(0); + } +} + +static void putFReg32 ( UInt iregNo, IRExpr* e ) +{ + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F32); + stmt(IRStmt_Put(offsetXReg(iregNo), e)); +} + +static void putFReg64 ( UInt iregNo, IRExpr* e ) +{ + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64); + stmt(IRStmt_Put(offsetXReg(iregNo), e)); +} + +static void putVReg ( UInt iregNo, IRExpr* e ) +{ + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128); + stmt(IRStmt_Put(offsetXReg(iregNo), e)); +} + +static void putXReg ( UInt iregNo, IRExpr* e ) +{ + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V256); + stmt(IRStmt_Put(offsetXReg(iregNo), e)); +} + +static void putFCC ( UInt iregNo, IRExpr* e ) +{ + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8); + stmt(IRStmt_Put(offsetFCC(iregNo), e)); +} + +static void putFCSR ( UInt iregNo, IRExpr* e ) +{ + vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); + IRExpr* fcsr0 = getFCSR(0); + IRExpr* and1; + IRExpr* and2; + switch (iregNo) { + case 0: + /* It seems that the hardware implementation allows the 6th + bit and the 7th bit to be non-zero. */ + and1 = getIReg32(0); + and2 = binop(Iop_And32, e, mkU32(0x1f1f03df)); + break; + case 1: + /* FCSR1 is Enables of FCSR0. It seems that the hardware + implementation is that the 7th bit belongs to FCSR1. */ + and1 = binop(Iop_And32, fcsr0, mkU32(0xffffff60)); + and2 = binop(Iop_And32, e, mkU32(0x0000009f)); + break; + case 2: + /* FCSR2 is Cause and Flags of FCSR0. */ + and1 = binop(Iop_And32, fcsr0, mkU32(0xe0e0ffff)); + and2 = binop(Iop_And32, e, mkU32(0x1f1f0000)); + break; + case 3: + /* FCSR3 is RM of FCSR0. */ + and1 = binop(Iop_And32, fcsr0, mkU32(0xfffffcff)); + and2 = binop(Iop_And32, e, mkU32(0x00000300)); + break; + default: + vassert(0); + } + Int offs = offsetof(VexGuestLOONGARCH64State, guest_FCSR); + stmt(IRStmt_Put(offs, binop(Iop_Or32, and1, and2))); +} + +static IRExpr* get_rounding_mode ( void ) +{ + /* + rounding mode | LOONGARCH | IR + ------------------------------ + to nearest | 00 | 00 + to zero | 01 | 11 + to +infinity | 10 | 10 + to -infinity | 11 | 01 + */ + + /* Bits 8 to 9 in FCSR are rounding mode. */ + IRExpr* fcsr = getFCSR(0); + IRExpr* shr = binop(Iop_Shr32, fcsr, mkU8(8)); + IRTemp rm = newTemp(Ity_I32); + assign(rm, binop(Iop_And32, shr, mkU32(0x3))); + + /* rm = XOR(rm, (rm << 1) & 2) */ + IRExpr* shl = binop(Iop_Shl32, mkexpr(rm), mkU8(1)); + IRExpr* and = binop(Iop_And32, shl, mkU32(2)); + return binop(Iop_Xor32, mkexpr(rm), and); +} + +static void calculateFCSR ( enum fpop op, UInt nargs, + UInt src1, UInt src2, UInt src3 ) +{ + IRExpr* s1 = NULL; + IRExpr* s2 = NULL; + IRExpr* s3 = NULL; + switch (nargs) { + case 3: s3 = unop(Iop_ReinterpF64asI64, getFReg64(src3)); /* fallthrough */ + case 2: s2 = unop(Iop_ReinterpF64asI64, getFReg64(src2)); /* fallthrough */ + case 1: s1 = unop(Iop_ReinterpF64asI64, getFReg64(src1)); break; + default: vassert(0); + } + IRExpr** arg = mkIRExprVec_4(mkU64(op), s1, s2, s3); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_FCSR", + &loongarch64_calculate_FCSR, + arg); + IRTemp fcsr2 = newTemp(Ity_I32); + assign(fcsr2, unop(Iop_64to32, call)); + putFCSR(2, mkexpr(fcsr2)); +} + +static IRExpr* gen_round_to_nearest ( void ) +{ + return mkU32(0x0); +} + +static IRExpr* gen_round_down ( void ) +{ + return mkU32(0x1); +} + +static IRExpr* gen_round_up ( void ) +{ + return mkU32(0x2); +} + +static IRExpr* gen_round_to_zero ( void ) +{ + return mkU32(0x3); +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for fixed point arithmetic insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_add_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("add.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* add = binop(Iop_Add32, getIReg32(rj), getIReg32(rk)); + putIReg(rd, extendS(Ity_I32, add)); + + return True; +} + +static Bool gen_add_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("add.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_Add64, getIReg64(rj), getIReg64(rk))); + + return True; +} + +static Bool gen_sub_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("sub.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* sub = binop(Iop_Sub32, getIReg32(rj), getIReg32(rk)); + putIReg(rd, extendS(Ity_I32, sub)); + + return True; +} + +static Bool gen_sub_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("sub.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_Sub64, getIReg64(rj), getIReg64(rk))); + + return True; +} + +static Bool gen_slt ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("slt %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* cond = binop(Iop_CmpLT64S, getIReg64(rj), getIReg64(rk)); + putIReg(rd, extendU(Ity_I1, cond)); + + return True; +} + +static Bool gen_sltu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("sltu %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* cond = binop(Iop_CmpLT64U, getIReg64(rj), getIReg64(rk)); + putIReg(rd, extendU(Ity_I1, cond)); + + return True; +} + +static Bool gen_slti ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("slti %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* cond = binop(Iop_CmpLT64S, getIReg64(rj), + mkU64(extend64(si12, 12))); + putIReg(rd, extendU(Ity_I1, cond)); + + return True; +} + +static Bool gen_sltui ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("sltui %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* cond = binop(Iop_CmpLT64U, getIReg64(rj), + mkU64(extend64(si12, 12))); + putIReg(rd, extendU(Ity_I1, cond)); + + return True; +} + +static Bool gen_nor ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("nor %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* or = binop(Iop_Or64, getIReg64(rj), getIReg64(rk)); + putIReg(rd, unop(Iop_Not64, or)); + + return True; +} + +static Bool gen_and ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("and %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_And64, getIReg64(rj), getIReg64(rk))); + + return True; +} + +static Bool gen_or ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("or %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_Or64, getIReg64(rj), getIReg64(rk))); + + return True; +} + +static Bool gen_xor ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("xor %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_Xor64, getIReg64(rj), getIReg64(rk))); + + return True; +} + +static Bool gen_orn ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("orn %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* not = unop(Iop_Not64, getIReg64(rk)); + putIReg(rd, binop(Iop_Or64, getIReg64(rj), not)); + + return True; +} + +static Bool gen_andn ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("andn %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* not = unop(Iop_Not64, getIReg64(rk)); + putIReg(rd, binop(Iop_And64, getIReg64(rj), not)); + + return True; +} + +static Bool gen_mul_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mul.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* mul = binop(Iop_MullS32, getIReg32(rj), getIReg32(rk)); + putIReg(rd, extendS(Ity_I32, unop(Iop_64to32, mul))); + + return True; +} + +static Bool gen_mulh_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mulh.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* mul = binop(Iop_MullS32, getIReg32(rj), getIReg32(rk)); + putIReg(rd, extendS(Ity_I32, unop(Iop_64HIto32, mul))); + + return True; +} + +static Bool gen_mulh_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mulh.wu %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* mul = binop(Iop_MullU32, getIReg32(rj), getIReg32(rk)); + putIReg(rd, extendS(Ity_I32, unop(Iop_64HIto32, mul))); + + return True; +} + +static Bool gen_mul_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mul.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* mul = binop(Iop_MullS64, getIReg64(rj), getIReg64(rk)); + putIReg(rd, unop(Iop_128to64, mul)); + + return True; +} + +static Bool gen_mulh_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mulh.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* mul = binop(Iop_MullS64, getIReg64(rj), getIReg64(rk)); + putIReg(rd, unop(Iop_128HIto64, mul)); + + return True; +} + +static Bool gen_mulh_du ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mulh.du %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* mul = binop(Iop_MullU64, getIReg64(rj), getIReg64(rk)); + putIReg(rd, unop(Iop_128HIto64, mul)); + + return True; +} + +static Bool gen_mulw_d_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mulw.d.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_MullS32, getIReg32(rj), getIReg32(rk))); + + return True; +} + +static Bool gen_mulw_d_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mulw.d.wu %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_MullU32, getIReg32(rj), getIReg32(rk))); + + return True; +} + +static Bool gen_div_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("div.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* div = binop(Iop_DivS32, getIReg32(rj), getIReg32(rk)); + putIReg(rd, extendS(Ity_I32, div)); + + return True; +} + +static Bool gen_mod_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mod.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* mod = binop(Iop_DivModS32to32, getIReg32(rj), getIReg32(rk)); + putIReg(rd, extendS(Ity_I32, unop(Iop_64HIto32, mod))); + + return True; +} + +static Bool gen_div_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("div.wu %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* div = binop(Iop_DivU32, getIReg32(rj), getIReg32(rk)); + putIReg(rd, extendS(Ity_I32, div)); + + return True; +} + +static Bool gen_mod_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mod.wu %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* mod = binop(Iop_DivModU32to32, getIReg32(rj), getIReg32(rk)); + putIReg(rd, extendS(Ity_I32, unop(Iop_64HIto32, mod))); + + return True; +} + +static Bool gen_div_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("div.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_DivS64, getIReg64(rj), getIReg64(rk))); + + return True; +} + +static Bool gen_mod_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mod.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* mod = binop(Iop_DivModS64to64, getIReg64(rj), getIReg64(rk)); + putIReg(rd, unop(Iop_128HIto64, mod)); + + return True; +} + +static Bool gen_div_du ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("div.du %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_DivU64, getIReg64(rj), getIReg64(rk))); + + return True; +} + +static Bool gen_mod_du ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("mod.du %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* mod = binop(Iop_DivModU64to64, getIReg64(rj), getIReg64(rk)); + putIReg(rd, unop(Iop_128HIto64, mod)); + + return True; +} + +static Bool gen_alsl_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt sa2 = SLICE(insn, 16, 15); + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("alsl.w %s, %s, %s, %u\n", nameIReg(rd), nameIReg(rj), + nameIReg(rk), sa2); + + IRExpr* shl = binop(Iop_Shl32, getIReg32(rj), mkU8(sa2 + 1)); + IRExpr* add = binop(Iop_Add32, shl, getIReg32(rk)); + putIReg(rd, extendS(Ity_I32, add)); + + return True; +} + +static Bool gen_alsl_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt sa2 = SLICE(insn, 16, 15); + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("alsl.wu %s, %s, %s, %u\n", nameIReg(rd), nameIReg(rj), + nameIReg(rk), sa2); + + IRExpr* shl = binop(Iop_Shl32, getIReg32(rj), mkU8(sa2 + 1)); + IRExpr* add = binop(Iop_Add32, shl, getIReg32(rk)); + putIReg(rd, extendU(Ity_I32, add)); + + return True; +} + +static Bool gen_alsl_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt sa2 = SLICE(insn, 16, 15); + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("alsl.d %s, %s, %s, %u\n", nameIReg(rd), nameIReg(rj), + nameIReg(rk), sa2); + + IRExpr* shl = binop(Iop_Shl64, getIReg64(rj), mkU8(sa2 + 1)); + putIReg(rd, binop(Iop_Add64, shl, getIReg64(rk))); + + return True; +} + +static Bool gen_lu12i_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si20 = SLICE(insn, 24, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("lu12i.w %s, %d\n", nameIReg(rd), (Int)extend32(si20, 20)); + + IRExpr* imm = mkU32(si20 << 12); + putIReg(rd, extendS(Ity_I32, imm)); + + return True; +} + +static Bool gen_lu32i_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si20 = SLICE(insn, 24, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("lu32i.d %s, %d\n", nameIReg(rd), (Int)extend32(si20, 20)); + + IRExpr* imm = mkU64((ULong)extend32(si20, 20) << 32); + IRExpr* shl = binop(Iop_Shl64, getIReg64(rd), mkU8(32)); + IRExpr* shr = binop(Iop_Shr64, shl, mkU8(32)); + putIReg(rd, binop(Iop_Or64, imm, shr)); + + return True; +} + +static Bool gen_lu52i_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("lu52i.d %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* imm = mkU64((ULong)si12 << 52); + IRExpr* shl = binop(Iop_Shl64, getIReg64(rj), mkU8(12)); + IRExpr* shr = binop(Iop_Shr64, shl, mkU8(12)); + putIReg(rd, binop(Iop_Or64, imm, shr)); + + return True; +} + +static Bool gen_pcaddi ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si20 = SLICE(insn, 24, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("pcaddi %s, %d\n", nameIReg(rd), (Int)extend32(si20, 20)); + + putIReg(rd, mkU64(guest_PC_curr_instr + extend64(si20 << 2, 22))); + + return True; +} + +static Bool gen_pcalau12i ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si20 = SLICE(insn, 24, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("pcalau12i %s, %d\n", nameIReg(rd), (Int)extend32(si20, 20)); + + IRExpr* imm = mkU64(guest_PC_curr_instr + extend64(si20 << 12, 32)); + IRExpr* shr = binop(Iop_Shr64, imm, mkU8(12)); + putIReg(rd, binop(Iop_Shl64, shr, mkU8(12))); + + return True; +} + +static Bool gen_pcaddu12i ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si20 = SLICE(insn, 24, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("pcaddu12i %s, %d\n", nameIReg(rd), (Int)extend32(si20, 20)); + + putIReg(rd, mkU64(guest_PC_curr_instr + extend64(si20 << 12, 32))); + + return True; +} + +static Bool gen_pcaddu18i ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si20 = SLICE(insn, 24, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("pcaddu18i %s, %d\n", nameIReg(rd), (Int)extend32(si20, 20)); + + putIReg(rd, mkU64(guest_PC_curr_instr + extend64((ULong)si20 << 18, 38))); + + return True; +} + +static Bool gen_addi_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("addi.w %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* imm = mkU32(extend32(si12, 12)); + IRExpr* add = binop(Iop_Add32, getIReg32(rj), imm); + putIReg(rd, extendS(Ity_I32, add)); + + return True; +} + +static Bool gen_addi_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("addi.d %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* imm = mkU64(extend64(si12, 12)); + putIReg(rd, binop(Iop_Add64, getIReg64(rj), imm)); + + return True; +} + +static Bool gen_addu16i_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si16 = SLICE(insn, 25, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("addu16i.d %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si16, 16)); + + IRExpr* imm = mkU64(extend64(si16 << 16, 32)); + putIReg(rd, binop(Iop_Add64, getIReg64(rj), imm)); + + return True; +} + +static Bool gen_andi ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("andi %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui12); + + IRExpr* imm = mkU64((ULong)ui12); + putIReg(rd, binop(Iop_And64, getIReg64(rj), imm)); + + return True; +} + +static Bool gen_ori ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ori %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui12); + + IRExpr* imm = mkU64((ULong)ui12); + putIReg(rd, binop(Iop_Or64, getIReg64(rj), imm)); + + return True; +} + +static Bool gen_xori ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("xori %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui12); + + IRExpr* imm = mkU64((ULong)ui12); + putIReg(rd, binop(Iop_Xor64, getIReg64(rj), imm)); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for fixed point shift insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_sll_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("sll.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* shl = binop(Iop_Shl32, getIReg32(rj), getIReg8(rk)); + putIReg(rd, extendS(Ity_I32, shl)); + + return True; +} + +static Bool gen_srl_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("srl.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* shr = binop(Iop_Shr32, getIReg32(rj), getIReg8(rk)); + putIReg(rd, extendS(Ity_I32, shr)); + + return True; +} + +static Bool gen_sra_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("sra.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* sar = binop(Iop_Sar32, getIReg32(rj), getIReg8(rk)); + putIReg(rd, extendS(Ity_I32, sar)); + + return True; +} + +static Bool gen_sll_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("sll.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_Shl64, getIReg64(rj), getIReg8(rk))); + + return True; +} + +static Bool gen_srl_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("srl.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_Shr64, getIReg64(rj), getIReg8(rk))); + + return True; +} + +static Bool gen_sra_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("sra.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + putIReg(rd, binop(Iop_Sar64, getIReg64(rj), getIReg8(rk))); + + return True; +} + +static Bool gen_rotr_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("rotr.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp tmp1 = newTemp(Ity_I32); + assign(tmp1, getIReg32(rj)); + IRTemp tmp2 = newTemp(Ity_I8); + assign(tmp2, getIReg8(rk)); + IRExpr* shr = binop(Iop_Shr32, mkexpr(tmp1), mkexpr(tmp2)); + IRExpr* imm = unop(Iop_8Uto32, mkexpr(tmp2)); + IRExpr* sub = binop(Iop_Sub32, mkU32(32), imm); + IRExpr* imm2 = unop(Iop_32to8, sub); + IRExpr* shl = binop(Iop_Shl32, mkexpr(tmp1), imm2); + IRExpr* or = binop(Iop_Or32, shr, shl); + putIReg(rd, extendS(Ity_I32, or)); + + return True; +} + +static Bool gen_rotr_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("rotr.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp tmp1 = newTemp(Ity_I64); + assign(tmp1, getIReg64(rj)); + IRTemp tmp2 = newTemp(Ity_I8); + assign(tmp2, getIReg8(rk)); + IRExpr* shr = binop(Iop_Shr64, mkexpr(tmp1), mkexpr(tmp2)); + IRExpr* imm = unop(Iop_8Uto64, mkexpr(tmp2)); + IRExpr* sub = binop(Iop_Sub64, mkU64(64), imm); + IRExpr* imm2 = unop(Iop_64to8, sub); + IRExpr* shl = binop(Iop_Shl64, mkexpr(tmp1), imm2); + putIReg(rd, binop(Iop_Or64, shr, shl)); + + return True; +} + +static Bool gen_slli_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui5 = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("slli.w %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui5); + + IRExpr* shl = binop(Iop_Shl32, getIReg32(rj), mkU8(ui5)); + putIReg(rd, extendS(Ity_I32, shl)); + + return True; +} + +static Bool gen_slli_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui6 = SLICE(insn, 15, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("slli.d %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui6); + + putIReg(rd, binop(Iop_Shl64, getIReg64(rj), mkU8(ui6))); + + return True; +} + +static Bool gen_srli_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui5 = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("srli.w %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui5); + + IRExpr* shr = binop(Iop_Shr32, getIReg32(rj), mkU8(ui5)); + putIReg(rd, extendS(Ity_I32, shr)); + + return True; +} + +static Bool gen_srli_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui6 = SLICE(insn, 15, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("srli.d %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui6); + + putIReg(rd, binop(Iop_Shr64, getIReg64(rj), mkU8(ui6))); + + return True; +} + +static Bool gen_srai_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui5 = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("srai.w %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui5); + + IRExpr* sar = binop(Iop_Sar32, getIReg32(rj), mkU8(ui5)); + putIReg(rd, extendS(Ity_I32, sar)); + + return True; +} + +static Bool gen_srai_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui6 = SLICE(insn, 15, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("srai.d %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui6); + + putIReg(rd, binop(Iop_Sar64, getIReg64(rj), mkU8(ui6))); + + return True; +} + +static Bool gen_rotri_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui5 = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("rotri.w %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui5); + + IRTemp tmp = newTemp(Ity_I32); + assign(tmp, getIReg32(rj)); + IRExpr* shr = binop(Iop_Shr32, mkexpr(tmp), mkU8(ui5)); + IRExpr* shl = binop(Iop_Shl32, mkexpr(tmp), mkU8(32 - ui5)); + if (32 - ui5 == 32) + shl = mkU32(0); + IRExpr* or = binop(Iop_Or32, shr, shl); + putIReg(rd, extendS(Ity_I32, or)); + + return True; +} + +static Bool gen_rotri_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ui6 = SLICE(insn, 15, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("rotri.d %s, %s, %u\n", nameIReg(rd), nameIReg(rj), ui6); + + IRTemp tmp = newTemp(Ity_I64); + assign(tmp, getIReg64(rj)); + IRExpr* shr = binop(Iop_Shr64, mkexpr(tmp), mkU8(ui6)); + IRExpr* shl = binop(Iop_Shl64, mkexpr(tmp), mkU8(64 - ui6)); + if (64 - ui6 == 64) + shl = mkU64(0); + putIReg(rd, binop(Iop_Or64, shr, shl)); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for fixed point bit insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_ext_w_h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ext.w.h %s, %s\n", nameIReg(rd), nameIReg(rj)); + + putIReg(rd, extendS(Ity_I16, getIReg16(rj))); + + return True; +} + +static Bool gen_ext_w_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ext.w.b %s, %s\n", nameIReg(rd), nameIReg(rj)); + + putIReg(rd, extendS(Ity_I8, getIReg8(rj))); + + return True; +} + +static Bool gen_clo_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("clo.w %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr* not = unop(Iop_Not32, getIReg32(rj)); + IRExpr* clz = unop(Iop_Clz32, not); + putIReg(rd, extendU(Ity_I32, clz)); + + return True; +} + +static Bool gen_clz_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("clz.w %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr* clz = unop(Iop_Clz32, getIReg32(rj)); + putIReg(rd, extendU(Ity_I32, clz)); + + return True; +} + +static Bool gen_cto_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("cto.w %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr* not = unop(Iop_Not32, getIReg32(rj)); + IRExpr* clz = unop(Iop_Ctz32, not); + putIReg(rd, extendU(Ity_I32, clz)); + + return True; +} + +static Bool gen_ctz_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ctz.w %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr* clz = unop(Iop_Ctz32, getIReg32(rj)); + putIReg(rd, extendU(Ity_I32, clz)); + + return True; +} + +static Bool gen_clo_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("clo.d %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr* not = unop(Iop_Not64, getIReg64(rj)); + putIReg(rd, unop(Iop_Clz64, not)); + + return True; +} + +static Bool gen_clz_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("clz.d %s, %s\n", nameIReg(rd), nameIReg(rj)); + + putIReg(rd, unop(Iop_Clz64, getIReg64(rj))); + + return True; +} + +static Bool gen_cto_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("cto.d %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr* not = unop(Iop_Not64, getIReg64(rj)); + putIReg(rd, unop(Iop_Ctz64, not)); + + return True; +} + +static Bool gen_ctz_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ctz.d %s, %s\n", nameIReg(rd), nameIReg(rj)); + + putIReg(rd, unop(Iop_Ctz64, getIReg64(rj))); + + return True; +} + +static Bool gen_revb_2h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("revb.2h %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_revb_2h", + &loongarch64_calculate_revb_2h, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_revb_4h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("revb.4h %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_revb_4h", + &loongarch64_calculate_revb_4h, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_revb_2w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("revb.2w %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_revb_2w", + &loongarch64_calculate_revb_2w, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_revb_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("revb.d %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_revb_d", + &loongarch64_calculate_revb_d, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_revh_2w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("revh.2w %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_revh_2w", + &loongarch64_calculate_revh_2w, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_revh_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("revh.d %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_revh_d", + &loongarch64_calculate_revh_d, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_bitrev_4b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bitrev.4b %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_bitrev_4b", + &loongarch64_calculate_bitrev_4b, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_bitrev_8b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bitrev.8b %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_bitrev_8b", + &loongarch64_calculate_bitrev_8b, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_bitrev_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bitrev.w %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_bitrev_w", + &loongarch64_calculate_bitrev_w, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_bitrev_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bitrev.d %s, %s\n", nameIReg(rd), nameIReg(rj)); + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_bitrev_d", + &loongarch64_calculate_bitrev_d, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_bytepick_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt sa2 = SLICE(insn, 16, 15); + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bytepick.w %s, %s, %s, %u\n", nameIReg(rd), nameIReg(rj), + nameIReg(rk), sa2); + + UInt shift = 8 * (4 - sa2); + IRExpr* shl = binop(Iop_Shl32, getIReg32(rk), mkU8(32 - shift)); + if (32 - shift == 32) + shl = mkU32(0); + IRExpr* shr = binop(Iop_Shr32, getIReg32(rj), mkU8(shift)); + if (shift == 32) + shr = mkU32(0); + IRExpr* or = binop(Iop_Or32, shl, shr); + putIReg(rd, extendS(Ity_I32, or)); + + return True; +} + +static Bool gen_bytepick_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt sa3 = SLICE(insn, 17, 15); + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bytepick.d %s, %s, %s, %u\n", nameIReg(rd), nameIReg(rj), + nameIReg(rk), sa3); + + UInt shift = 8 * (8 - sa3); + IRExpr* shl = binop(Iop_Shl64, getIReg64(rk), mkU8(64 - shift)); + if (64 - shift == 64) + shl = mkU64(0); + IRExpr* shr = binop(Iop_Shr64, getIReg64(rj), mkU8(shift)); + if (shift == 64) + shr = mkU64(0); + putIReg(rd, binop(Iop_Or64, shl, shr)); + + return True; +} + +static Bool gen_maskeqz ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("maskeqz %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* cond = binop(Iop_CmpNE64, getIReg64(rk), mkU64(0)); + putIReg(rd, binop(Iop_And64, extendS(Ity_I1, cond), getIReg64(rj))); + + return True; +} + +static Bool gen_masknez ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("masknez %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* cond = binop(Iop_CmpEQ64, getIReg64(rk), mkU64(0)); + putIReg(rd, binop(Iop_And64, extendS(Ity_I1, cond), getIReg64(rj))); + + return True; +} + +static Bool gen_bstrins_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt msb = SLICE(insn, 20, 16); + UInt lsb = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bstrins.w %s, %s, %u, %u\n", nameIReg(rd), nameIReg(rj), msb, lsb); + + IRTemp tmp = newTemp(Ity_I32); + assign(tmp, getIReg32(rd)); + IRExpr* shl1; + if (msb == 31) { + shl1 = mkU32(0); + } else { + IRExpr* shr1 = binop(Iop_Shr32, mkexpr(tmp), mkU8(msb + 1)); + shl1 = binop(Iop_Shl32, shr1, mkU8(msb + 1)); + } + IRExpr* shl2 = binop(Iop_Shl32, getIReg32(rj), mkU8(31 - msb + lsb)); + IRExpr* shr2 = binop(Iop_Shr32, shl2, mkU8(31 - msb)); + IRExpr* shr3; + if (lsb == 0) { + shr3 = mkU32(0); + } else { + IRExpr* shl3 = binop(Iop_Shl32, mkexpr(tmp), mkU8(32 - lsb)); + shr3 = binop(Iop_Shr32, shl3, mkU8(32 - lsb)); + } + IRExpr* or1 = binop(Iop_Or32, shl1, shr2); + IRExpr* or2 = binop(Iop_Or32, or1, shr3); + putIReg(rd, extendS(Ity_I32, or2)); + + return True; +} + +static Bool gen_bstrpick_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt msb = SLICE(insn, 20, 16); + UInt lsb = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bstrpick.w %s, %s, %u, %u\n", nameIReg(rd), nameIReg(rj), msb, lsb); + + IRExpr* shl = binop(Iop_Shl32, getIReg32(rj), mkU8(31 - msb)); + IRExpr* shr = binop(Iop_Shr32, shl, mkU8(31 - msb + lsb)); + putIReg(rd, extendS(Ity_I32, shr)); + + return True; +} + +static Bool gen_bstrins_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt msb = SLICE(insn, 21, 16); + UInt lsb = SLICE(insn, 15, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bstrins.d %s, %s, %u, %u\n", nameIReg(rd), nameIReg(rj), msb, lsb); + + IRTemp tmp = newTemp(Ity_I64); + assign(tmp, getIReg64(rd)); + IRExpr* shl1; + if (msb == 63) { + shl1 = mkU64(0); + } else { + IRExpr* shr1 = binop(Iop_Shr64, mkexpr(tmp), mkU8(msb + 1)); + shl1 = binop(Iop_Shl64, shr1, mkU8(msb + 1)); + } + IRExpr* shl2 = binop(Iop_Shl64, getIReg64(rj), mkU8(63 - msb + lsb)); + IRExpr* shr2 = binop(Iop_Shr64, shl2, mkU8(63 - msb)); + IRExpr* shr3; + if (lsb == 0) { + shr3 = mkU64(0); + } else { + IRExpr* shl3 = binop(Iop_Shl64, mkexpr(tmp), mkU8(64 - lsb)); + shr3 = binop(Iop_Shr64, shl3, mkU8(64 - lsb)); + } + IRExpr* or = binop(Iop_Or64, shl1, shr2); + putIReg(rd, binop(Iop_Or64, or, shr3)); + + return True; +} + +static Bool gen_bstrpick_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt msb = SLICE(insn, 21, 16); + UInt lsb = SLICE(insn, 15, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bstrpick.d %s, %s, %u, %u\n", nameIReg(rd), nameIReg(rj), msb, lsb); + + IRExpr* shl = binop(Iop_Shl64, getIReg64(rj), mkU8(63 - msb)); + putIReg(rd, binop(Iop_Shr64, shl, mkU8(63 - msb + lsb))); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for fixed point load/store insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_ld_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ld.b %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + putIReg(rd, extendS(Ity_I8, load(Ity_I8, addr))); + + return True; +} + +static Bool gen_ld_h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ld.h %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x1))); + putIReg(rd, extendS(Ity_I16, load(Ity_I16, addr))); + + return True; +} + +static Bool gen_ld_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ld.w %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + putIReg(rd, extendS(Ity_I32, load(Ity_I32, addr))); + + return True; +} + +static Bool gen_ld_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ld.d %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x7))); + putIReg(rd, load(Ity_I64, addr)); + + return True; +} + +static Bool gen_st_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("st.b %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + store(addr, getIReg8(rd)); + + return True; +} + +static Bool gen_st_h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("st.h %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x1))); + store(addr, getIReg16(rd)); + + return True; +} + +static Bool gen_st_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("st.w %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + store(addr, getIReg32(rd)); + + return True; +} + +static Bool gen_st_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("st.d %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x7))); + store(addr, getIReg64(rd)); + + return True; +} + +static Bool gen_ld_bu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ld.bu %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + putIReg(rd, extendU(Ity_I8, load(Ity_I8, addr))); + + return True; +} + +static Bool gen_ld_hu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ld.hu %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x1))); + putIReg(rd, extendU(Ity_I16, load(Ity_I16, addr))); + + return True; +} + +static Bool gen_ld_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ld.wu %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si12, 12)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + putIReg(rd, extendU(Ity_I32, load(Ity_I32, addr))); + + return True; +} + +static Bool gen_ldx_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldx.b %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + putIReg(rd, extendS(Ity_I8, load(Ity_I8, addr))); + + return True; +} + +static Bool gen_ldx_h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldx.h %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x1))); + putIReg(rd, extendS(Ity_I16, load(Ity_I16, addr))); + + return True; +} + +static Bool gen_ldx_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldx.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + putIReg(rd, extendS(Ity_I32, load(Ity_I32, addr))); + + return True; +} + +static Bool gen_ldx_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldx.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x7))); + putIReg(rd, load(Ity_I64, addr)); + + return True; +} + +static Bool gen_stx_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stx.b %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + store(addr, getIReg8(rd)); + + return True; +} + +static Bool gen_stx_h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stx.h %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x1))); + store(addr, getIReg16(rd)); + + return True; +} + +static Bool gen_stx_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stx.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + store(addr, getIReg32(rd)); + + return True; +} + +static Bool gen_stx_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stx.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x7))); + store(addr, getIReg64(rd)); + + return True; +} + +static Bool gen_ldx_bu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldx.bu %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + putIReg(rd, extendU(Ity_I8, load(Ity_I8, addr))); + + return True; +} + +static Bool gen_ldx_hu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldx.hu %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x1))); + putIReg(rd, extendU(Ity_I16, load(Ity_I16, addr))); + + return True; +} + +static Bool gen_ldx_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldx.wu %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + putIReg(rd, extendU(Ity_I32, load(Ity_I32, addr))); + + return True; +} + +static Bool gen_preld ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt hint = SLICE(insn, 4, 0); + + DIP("preld %u, %s, %d\n", hint, nameIReg(rj), (Int)extend32(si12, 12)); + + return True; +} + +static Bool gen_preldx ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt hint = SLICE(insn, 4, 0); + + DIP("preldx %u, %s, %d\n", hint, nameIReg(rj), (Int)extend32(si12, 12)); + + return True; +} + +static Bool gen_dbar ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt hint = SLICE(insn, 14, 0); + + DIP("dbar %u\n", hint); + + stmt(IRStmt_MBE(Imbe_Fence)); + + return True; +} + +static Bool gen_ibar ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt hint = SLICE(insn, 14, 0); + + DIP("ibar %u\n", hint); + + stmt(IRStmt_MBE(Imbe_InsnFence)); + + return True; +} + +static Bool gen_ldptr_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si14 = SLICE(insn, 23, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldptr.w %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si14, 14)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), + mkU64(extend64(si14 << 2, 16))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + putIReg(rd, extendS(Ity_I32, load(Ity_I32, addr))); + + return True; +} + +static Bool gen_stptr_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si14 = SLICE(insn, 23, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stptr.w %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si14, 14)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), + mkU64(extend64(si14 << 2, 16))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + store(addr, getIReg32(rd)); + + return True; +} + +static Bool gen_ldptr_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si14 = SLICE(insn, 23, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldptr.d %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si14, 14)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), + mkU64(extend64(si14 << 2, 16))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x7))); + putIReg(rd, load(Ity_I64, addr)); + + return True; +} + +static Bool gen_stptr_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si14 = SLICE(insn, 23, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stptr.d %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si14, 14)); + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), + mkU64(extend64(si14 << 2, 16))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x7))); + store(addr, getIReg64(rd)); + + return True; +} + +static Bool gen_ldgt_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldgt.b %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + putIReg(rd, extendS(Ity_I8, load(Ity_I8, mkexpr(addr)))); + + return True; +} + +static Bool gen_ldgt_h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldgt.h %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x1))); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + putIReg(rd, extendS(Ity_I16, load(Ity_I16, mkexpr(addr)))); + + return True; +} + +static Bool gen_ldgt_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldgt.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + putIReg(rd, extendS(Ity_I32, load(Ity_I32, mkexpr(addr)))); + + return True; +} + +static Bool gen_ldgt_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldgt.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + putIReg(rd, load(Ity_I64, mkexpr(addr))); + + return True; +} + +static Bool gen_ldle_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldle.b %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + putIReg(rd, extendS(Ity_I8, load(Ity_I8, mkexpr(addr)))); + + return True; +} + +static Bool gen_ldle_h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldle.h %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x1))); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + putIReg(rd, extendS(Ity_I16, load(Ity_I16, mkexpr(addr)))); + + return True; +} + +static Bool gen_ldle_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldle.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + putIReg(rd, extendS(Ity_I32, load(Ity_I32, mkexpr(addr)))); + + return True; +} + +static Bool gen_ldle_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ldle.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + putIReg(rd, load(Ity_I64, mkexpr(addr))); + + return True; +} + +static Bool gen_stgt_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stgt.b %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + store(mkexpr(addr), getIReg8(rd)); + + return True; +} + +static Bool gen_stgt_h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stgt.h %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x1))); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + store(mkexpr(addr), getIReg16(rd)); + + return True; +} + +static Bool gen_stgt_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stgt.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + store(mkexpr(addr), getIReg32(rd)); + + return True; +} + +static Bool gen_stgt_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stgt.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + store(mkexpr(addr), getIReg64(rd)); + + return True; +} + +static Bool gen_stle_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stle.b %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + store(mkexpr(addr), getIReg8(rd)); + + return True; +} + +static Bool gen_stle_h ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stle.h %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x1))); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + store(mkexpr(addr), getIReg16(rd)); + + return True; +} + +static Bool gen_stle_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stle.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + store(mkexpr(addr), getIReg32(rd)); + + return True; +} + +static Bool gen_stle_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("stle.d %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + store(mkexpr(addr), getIReg64(rd)); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for fixed point atomic insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_ll_helper ( UInt rd, UInt rj, UInt si14, Bool size64 ) +{ + Int offs_size = offsetof(VexGuestLOONGARCH64State, guest_LLSC_SIZE); + Int offs_addr = offsetof(VexGuestLOONGARCH64State, guest_LLSC_ADDR); + Int offs_data = offsetof(VexGuestLOONGARCH64State, guest_LLSC_DATA); + + /* Get address of the load. */ + IRTemp addr = newTemp(Ity_I64); + assign(addr, binop(Iop_Add64, getIReg64(rj), + mkU64(extend64(si14 << 2, 16)))); + if (size64) + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + else + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + + /* Load the value. */ + IRTemp res = newTemp(Ity_I64); + if (size64) + assign(res, load(Ity_I64, mkexpr(addr))); + else + assign(res, extendS(Ity_I32, load(Ity_I32, mkexpr(addr)))); + + /* Set up the LLSC fallback data. */ + if (size64) + stmt(IRStmt_Put(offs_size, mkU64(8))); + else + stmt(IRStmt_Put(offs_size, mkU64(4))); + stmt(IRStmt_Put(offs_addr, mkexpr(addr))); + stmt(IRStmt_Put(offs_data, mkexpr(res))); + + /* Write the result to the destination register. */ + putIReg(rd, mkexpr(res)); + + return True; +} + +static Bool gen_sc_helper ( UInt rd, UInt rj, UInt si14, Bool size64 ) +{ + Int offs_size = offsetof(VexGuestLOONGARCH64State, guest_LLSC_SIZE); + Int offs_addr = offsetof(VexGuestLOONGARCH64State, guest_LLSC_ADDR); + Int offs_data = offsetof(VexGuestLOONGARCH64State, guest_LLSC_DATA); + + /* Get address of the load. */ + IRTemp addr = newTemp(Ity_I64); + assign(addr, binop(Iop_Add64, getIReg64(rj), + mkU64(extend64(si14 << 2, 16)))); + if (size64) + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + else + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + + /* Get new value. */ + IRTemp new; + if (size64) { + new = newTemp(Ity_I64); + assign(new, getIReg64(rd)); + } else { + new = newTemp(Ity_I32); + assign(new, getIReg32(rd)); + } + + /* Mark the SC initially as failed. */ + putIReg(rd, mkU64(0)); + + /* Set that no transaction is in progress. */ + IRTemp size = newTemp(Ity_I64); + assign(size, IRExpr_Get(offs_size, Ity_I64)); + stmt(IRStmt_Put(offs_size, mkU64(0) /* "no transaction" */)); + + /* Fail if no or wrong-size transaction. */ + if (size64) + exit(binop(Iop_CmpNE64, mkexpr(size), mkU64(8)), Ijk_Boring, 4); + else + exit(binop(Iop_CmpNE64, mkexpr(size), mkU64(4)), Ijk_Boring, 4); + + /* Fail if the address doesn't match the LL address. */ + exit(binop(Iop_CmpNE64, mkexpr(addr), IRExpr_Get(offs_addr, Ity_I64)), + Ijk_Boring, 4); + + /* Fail if the data doesn't match the LL data. */ + IRTemp data; + if (size64) { + data = newTemp(Ity_I64); + assign(data, IRExpr_Get(offs_data, Ity_I64)); + IRExpr* d = load(Ity_I64, mkexpr(addr)); + exit(binop(Iop_CmpNE64, d, mkexpr(data)), Ijk_Boring, 4); + } else { + data = newTemp(Ity_I32); + IRTemp tmp = newTemp(Ity_I64); + assign(tmp, IRExpr_Get(offs_data, Ity_I64)); + assign(data, unop(Iop_64to32, mkexpr(tmp))); + IRExpr* d = extendS(Ity_I32, load(Ity_I32, mkexpr(addr))); + exit(binop(Iop_CmpNE64, d, mkexpr(tmp)), Ijk_Boring, 4); + } + + /* Try to CAS the new value in. */ + IRTemp old; + if (size64) { + old = newTemp(Ity_I64); + cas(old, mkexpr(addr), mkexpr(data), mkexpr(new)); + } else { + old = newTemp(Ity_I32); + cas(old, mkexpr(addr), mkexpr(data), mkexpr(new)); + } + + /* Fail if the CAS failed (old != expd). */ + if (size64) + exit(binop(Iop_CasCmpNE64, mkexpr(old), mkexpr(data)), Ijk_Boring, 4); + else + exit(binop(Iop_CasCmpNE32, mkexpr(old), mkexpr(data)), Ijk_Boring, 4); + + /* Otherwise mark the operation as successful. */ + putIReg(rd, mkU64(1)); + + return True; +} + +static Bool gen_ll_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si14 = SLICE(insn, 23, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ll.w %s, %s, %d%s\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si14, 14), + abiinfo->guest__use_fallback_LLSC ? + " (fallback implementation)" : ""); + + if (abiinfo->guest__use_fallback_LLSC) { + return gen_ll_helper(rd, rj, si14, False); + } else { + IRTemp res = newTemp(Ity_I32); + IRTemp addr = newTemp(Ity_I64); + assign(addr, binop(Iop_Add64, getIReg64(rj), + mkU64(extend64(si14 << 2, 16)))); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(addr), NULL/*LL*/)); + putIReg(rd, extendS(Ity_I32, mkexpr(res))); + return True; + } +} + +static Bool gen_sc_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si14 = SLICE(insn, 23, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("sc.w %s, %s, %d%s\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si14, 14), + abiinfo->guest__use_fallback_LLSC ? + " (fallback implementation)" : ""); + + if (abiinfo->guest__use_fallback_LLSC) { + return gen_sc_helper(rd, rj, si14, False); + } else { + IRTemp res = newTemp(Ity_I1); + IRTemp addr = newTemp(Ity_I64); + assign(addr, binop(Iop_Add64, getIReg64(rj), + mkU64(extend64(si14 << 2, 16)))); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(addr), getIReg32(rd))); + return True; + } +} + +static Bool gen_ll_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si14 = SLICE(insn, 23, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ll.d %s, %s, %d%s\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si14, 14), + abiinfo->guest__use_fallback_LLSC ? + " (fallback implementation)" : ""); + + if (abiinfo->guest__use_fallback_LLSC) { + return gen_ll_helper(rd, rj, si14, True); + } else { + IRTemp res = newTemp(Ity_I64); + IRTemp addr = newTemp(Ity_I64); + assign(addr, binop(Iop_Add64, getIReg64(rj), + mkU64(extend64(si14 << 2, 16)))); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(addr), NULL/*LL*/)); + putIReg(rd, mkexpr(res)); + return True; + } +} + +static Bool gen_sc_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si14 = SLICE(insn, 23, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("sc.d %s, %s, %d%s\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(si14, 14), + abiinfo->guest__use_fallback_LLSC ? + " (fallback implementation)" : ""); + + if (abiinfo->guest__use_fallback_LLSC) { + return gen_sc_helper(rd, rj, si14, True); + } else { + IRTemp res = newTemp(Ity_I1); + IRTemp addr = newTemp(Ity_I64); + assign(addr, binop(Iop_Add64, getIReg64(rj), + mkU64(extend64(si14 << 2, 16)))); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(addr), getIReg64(rd))); + return True; + } +} + +enum amop { + AMSWAP, AMADD, AMAND, AMOR, AMXOR, AMMAX, AMMIN, AMMAX_U, AMMIN_U +}; + +static Bool gen_am_w_helper ( enum amop op, Bool fence, + UInt rd, UInt rj, UInt rk ) +{ + if (fence) + stmt(IRStmt_MBE(Imbe_Fence)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + + IRTemp o = newTemp(Ity_I32); + assign(o, load(Ity_I32, mkexpr(addr))); + IRTemp n = newTemp(Ity_I32); + assign(n, getIReg32(rk)); + IRExpr* e; + switch (op) { + case AMSWAP: + e = mkexpr(n); + break; + case AMADD: + e = binop(Iop_Add32, mkexpr(o), mkexpr(n)); + break; + case AMAND: + e = binop(Iop_And32, mkexpr(o), mkexpr(n)); + break; + case AMOR: + e = binop(Iop_Or32, mkexpr(o), mkexpr(n)); + break; + case AMXOR: + e = binop(Iop_Xor32, mkexpr(o), mkexpr(n)); + break; + case AMMAX: { + IRExpr* cond = binop(Iop_CmpLT32S, mkexpr(n), mkexpr(o)); + e = IRExpr_ITE(cond, mkexpr(o), mkexpr(n)); + break; + } + case AMMIN: { + IRExpr* cond = binop(Iop_CmpLT32S, mkexpr(o), mkexpr(n)); + e = IRExpr_ITE(cond, mkexpr(o), mkexpr(n)); + break; + } + case AMMAX_U: { + IRExpr* cond = binop(Iop_CmpLT32U, mkexpr(n), mkexpr(o)); + e = IRExpr_ITE(cond, mkexpr(o), mkexpr(n)); + break; + } + case AMMIN_U: { + IRExpr* cond = binop(Iop_CmpLT32U, mkexpr(o), mkexpr(n)); + e = IRExpr_ITE(cond, mkexpr(o), mkexpr(n)); + break; + } + default: + return False; + } + + IRTemp old = newTemp(Ity_I32); + cas(old, mkexpr(addr), mkexpr(o), e); + IRExpr* cond = binop(Iop_CasCmpNE32, mkexpr(old), mkexpr(o)); + exit(cond, Ijk_Boring, 0); /* Loop if failed */ + putIReg(rd, extendS(Ity_I32, mkexpr(o))); + + if (fence) + stmt(IRStmt_MBE(Imbe_Fence)); + + return True; +} + +static Bool gen_am_d_helper ( enum amop op, Bool fence, + UInt rd, UInt rj, UInt rk ) +{ + if (fence) + stmt(IRStmt_MBE(Imbe_Fence)); + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + + IRTemp o = newTemp(Ity_I64); + assign(o, load(Ity_I64, mkexpr(addr))); + IRTemp n = newTemp(Ity_I64); + assign(n, getIReg64(rk)); + IRExpr* e; + switch (op) { + case AMSWAP: + e = mkexpr(n); + break; + case AMADD: + e = binop(Iop_Add64, mkexpr(o), mkexpr(n)); + break; + case AMAND: + e = binop(Iop_And64, mkexpr(o), mkexpr(n)); + break; + case AMOR: + e = binop(Iop_Or64, mkexpr(o), mkexpr(n)); + break; + case AMXOR: + e = binop(Iop_Xor64, mkexpr(o), mkexpr(n)); + break; + case AMMAX: { + IRExpr* cond = binop(Iop_CmpLT64S, mkexpr(n), mkexpr(o)); + e = IRExpr_ITE(cond, mkexpr(o), mkexpr(n)); + break; + } + case AMMIN: { + IRExpr* cond = binop(Iop_CmpLT64S, mkexpr(o), mkexpr(n)); + e = IRExpr_ITE(cond, mkexpr(o), mkexpr(n)); + break; + } + case AMMAX_U: { + IRExpr* cond = binop(Iop_CmpLT64U, mkexpr(n), mkexpr(o)); + e = IRExpr_ITE(cond, mkexpr(o), mkexpr(n)); + break; + } + case AMMIN_U: { + IRExpr* cond = binop(Iop_CmpLT64U, mkexpr(o), mkexpr(n)); + e = IRExpr_ITE(cond, mkexpr(o), mkexpr(n)); + break; + } + default: + return False; + } + + IRTemp old = newTemp(Ity_I64); + cas(old, mkexpr(addr), mkexpr(o), e); + IRExpr* cond = binop(Iop_CasCmpNE64, mkexpr(old), mkexpr(o)); + exit(cond, Ijk_Boring, 0); /* Loop if failed */ + putIReg(rd, mkexpr(o)); + + if (fence) + stmt(IRStmt_MBE(Imbe_Fence)); + + return True; +} + +static Bool gen_amswap_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amswap.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMSWAP, False, rd, rj, rk); +} + +static Bool gen_amswap_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amswap.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMSWAP, False, rd, rj, rk); +} + +static Bool gen_amadd_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amadd.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMADD, False, rd, rj, rk); +} + +static Bool gen_amadd_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amadd.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMADD, False, rd, rj, rk); +} + +static Bool gen_amand_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amand.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMAND, False, rd, rj, rk); +} + +static Bool gen_amand_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amand.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMAND, False, rd, rj, rk); +} + +static Bool gen_amor_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amor.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMOR, False, rd, rj, rk); +} + +static Bool gen_amor_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amor.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMOR, False, rd, rj, rk); +} + +static Bool gen_amxor_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amxor.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMXOR, False, rd, rj, rk); +} + +static Bool gen_amxor_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amxor.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMXOR, False, rd, rj, rk); +} + +static Bool gen_ammax_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammax.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMMAX, False, rd, rj, rk); +} + +static Bool gen_ammax_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammax.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMMAX, False, rd, rj, rk); +} + +static Bool gen_ammin_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammin.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMMIN, False, rd, rj, rk); +} + +static Bool gen_ammin_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammin.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMMIN, False, rd, rj, rk); +} + +static Bool gen_ammax_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammax.wu %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMMAX_U, False, rd, rj, rk); +} + +static Bool gen_ammax_du ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammax.du %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMMAX_U, False, rd, rj, rk); +} + +static Bool gen_ammin_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammin.wu %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMMIN_U, False, rd, rj, rk); +} + +static Bool gen_ammin_du ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammin.du %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMMIN_U, False, rd, rj, rk); +} + +static Bool gen_amswap_db_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amswap_db.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMSWAP, True, rd, rj, rk); +} + +static Bool gen_amswap_db_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amswap_db.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMSWAP, True, rd, rj, rk); +} + +static Bool gen_amadd_db_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amadd_db.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMADD, True, rd, rj, rk); +} + +static Bool gen_amadd_db_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amadd_db.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMADD, True, rd, rj, rk); +} + +static Bool gen_amand_db_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amand_db.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMAND, True, rd, rj, rk); +} + +static Bool gen_amand_db_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amand_db.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMAND, True, rd, rj, rk); +} + +static Bool gen_amor_db_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amor_db.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMOR, True, rd, rj, rk); +} + +static Bool gen_amor_db_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amor_db.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMOR, True, rd, rj, rk); +} + +static Bool gen_amxor_db_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amxor_db.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMXOR, True, rd, rj, rk); +} + +static Bool gen_amxor_db_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("amxor_db.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMXOR, True, rd, rj, rk); +} + +static Bool gen_ammax_db_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammax_db.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMMAX, True, rd, rj, rk); +} + +static Bool gen_ammax_db_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammax_db.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMMAX, True, rd, rj, rk); +} + +static Bool gen_ammin_db_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammin_db.w %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMMIN, True, rd, rj, rk); +} + +static Bool gen_ammin_db_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammin_db.d %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMMIN, True, rd, rj, rk); +} + +static Bool gen_ammax_db_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammax_db.wu %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMMAX_U, True, rd, rj, rk); +} + +static Bool gen_ammax_db_du ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammax_db.du %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMMAX_U, True, rd, rj, rk); +} + +static Bool gen_ammin_db_wu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammin_db.wu %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_w_helper(AMMIN_U, True, rd, rj, rk); +} + +static Bool gen_ammin_db_du ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("ammin_db.du %s, %s, %s\n", nameIReg(rd), nameIReg(rk), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LAM)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_am_d_helper(AMMIN_U, True, rd, rj, rk); +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for fixed point extra insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_crc_w_b_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("crc.w.b.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr** arg = mkIRExprVec_3(getIReg64(rk), getIReg64(rj), mkU64(8)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_crc", + &loongarch64_calculate_crc, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_crc_w_h_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("crc.w.h.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr** arg = mkIRExprVec_3(getIReg64(rk), getIReg64(rj), mkU64(16)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_crc", + &loongarch64_calculate_crc, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_crc_w_w_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("crc.w.w.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr** arg = mkIRExprVec_3(getIReg64(rk), getIReg64(rj), mkU64(32)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_crc", + &loongarch64_calculate_crc, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_crc_w_d_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("crc.w.d.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr** arg = mkIRExprVec_3(getIReg64(rk), getIReg64(rj), mkU64(64)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_crc", + &loongarch64_calculate_crc, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_crcc_w_b_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("crcc.w.b.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr** arg = mkIRExprVec_3(getIReg64(rk), getIReg64(rj), mkU64(8)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_crcc", + &loongarch64_calculate_crcc, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_crcc_w_h_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("crcc.w.h.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr** arg = mkIRExprVec_3(getIReg64(rk), getIReg64(rj), mkU64(16)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_crcc", + &loongarch64_calculate_crcc, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_crcc_w_w_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("crcc.w.w.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr** arg = mkIRExprVec_3(getIReg64(rk), getIReg64(rj), mkU64(32)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_crcc", + &loongarch64_calculate_crcc, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_crcc_w_d_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("crcc.w.d.w %s, %s, %s\n", nameIReg(rd), nameIReg(rj), nameIReg(rk)); + + IRExpr** arg = mkIRExprVec_3(getIReg64(rk), getIReg64(rj), mkU64(64)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_crcc", + &loongarch64_calculate_crcc, + arg); + putIReg(rd, call); + + return True; +} + +static Bool gen_break ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt code = SLICE(insn, 14, 0); + + DIP("break %u\n", code); + + putPC(mkU64(guest_PC_curr_instr + 4)); + + /* On LoongArch, most instructions do not raise exceptions; + instead, gcc notifies the kernel with a trap instruction. + We simulate the behavior of the linux kernel here. + See arch/loongarch/kernel/traps.c. + */ + switch (code) { + case 6: /* BRK_OVERFLOW */ + dres->jk_StopHere = Ijk_SigFPE_IntOvf; + break; + case 7: /* BRK_DIVZERO */ + dres->jk_StopHere = Ijk_SigFPE_IntDiv; + break; + default: + dres->jk_StopHere = Ijk_SigTRAP; + break; + } + dres->whatNext = Dis_StopHere; + + return True; +} + +static Bool gen_syscall ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt hint = SLICE(insn, 14, 0); + + DIP("syscall %u\n", hint); + + putPC(mkU64(guest_PC_curr_instr + 4)); + + dres->jk_StopHere = Ijk_Sys_syscall; + dres->whatNext = Dis_StopHere; + + return True; +} + +static Bool gen_asrtle_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + + DIP("asrtle.d %s, %s\n", nameIReg(rj), nameIReg(rk)); + + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), getIReg64(rj))); + + return True; +} + +static Bool gen_asrtgt_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + + DIP("asrtgt.d %s, %s\n", nameIReg(rj), nameIReg(rk)); + + gen_SIGSYS(binop(Iop_CmpLE64U, getIReg64(rj), getIReg64(rk))); + + return True; +} + +static Bool gen_rdtimel_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("rdtimel.w %s, %s\n", nameIReg(rd), nameIReg(rj)); + + putIReg(rd, mkU64(0)); + + return True; +} + +static Bool gen_rdtimeh_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("rdtimeh.w %s, %s\n", nameIReg(rd), nameIReg(rj)); + + putIReg(rd, mkU64(0)); + + return True; +} + +static Bool gen_rdtime_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("rdtime.d %s, %s\n", nameIReg(rd), nameIReg(rj)); + + putIReg(rd, mkU64(0)); + + return True; +} + +static Bool gen_cpucfg ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("cpucfg %s, %s\n", nameIReg(rd), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_CPUCFG)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr** arg = mkIRExprVec_1(getIReg64(rj)); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_cpucfg", + &loongarch64_calculate_cpucfg, + arg); + putIReg(rd, call); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for floating point arithmetic insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_fadd_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fadd.s %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FADD_S, 2, fj, fk, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, triop(Iop_AddF32, rm, getFReg32(fj), getFReg32(fk))); + + return True; +} + +static Bool gen_fadd_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fadd.d %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FADD_D, 2, fj, fk, 0); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, triop(Iop_AddF64, rm, getFReg64(fj), getFReg64(fk))); + + return True; +} + +static Bool gen_fsub_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fsub.s %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FSUB_S, 2, fj, fk, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, triop(Iop_SubF32, rm, getFReg32(fj), getFReg32(fk))); + + return True; +} + +static Bool gen_fsub_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fsub.d %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FSUB_D, 2, fj, fk, 0); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, triop(Iop_SubF64, rm, getFReg64(fj), getFReg64(fk))); + + return True; +} + +static Bool gen_fmul_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmul.s %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMUL_S, 2, fj, fk, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, triop(Iop_MulF32, rm, getFReg32(fj), getFReg32(fk))); + + return True; +} + +static Bool gen_fmul_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmul.d %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMUL_D, 2, fj, fk, 0); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, triop(Iop_MulF64, rm, getFReg64(fj), getFReg64(fk))); + + return True; +} + +static Bool gen_fdiv_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fdiv.s %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FDIV_S, 2, fj, fk, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, triop(Iop_DivF32, rm, getFReg32(fj), getFReg32(fk))); + + return True; +} + +static Bool gen_fdiv_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fdiv.d %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FDIV_D, 2, fj, fk, 0); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, triop(Iop_DivF64, rm, getFReg64(fj), getFReg64(fk))); + + return True; +} + +static Bool gen_fmadd_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fa = SLICE(insn, 19, 15); + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmadd.s %s, %s, %s, %s\n", nameFReg(fd), nameFReg(fj), + nameFReg(fk), nameFReg(fa)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMADD_S, 3, fj, fk, fa); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, qop(Iop_MAddF32, rm, getFReg32(fj), + getFReg32(fk), getFReg32(fa))); + + return True; +} + +static Bool gen_fmadd_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fa = SLICE(insn, 19, 15); + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmadd.d %s, %s, %s, %s\n", nameFReg(fd), nameFReg(fj), + nameFReg(fk), nameFReg(fa)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMADD_D, 3, fj, fk, fa); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, qop(Iop_MAddF64, rm, getFReg64(fj), + getFReg64(fk), getFReg64(fa))); + + return True; +} + +static Bool gen_fmsub_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fa = SLICE(insn, 19, 15); + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmsub.s %s, %s, %s, %s\n", nameFReg(fd), nameFReg(fj), + nameFReg(fk), nameFReg(fa)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMSUB_S, 3, fj, fk, fa); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, qop(Iop_MSubF32, rm, getFReg32(fj), + getFReg32(fk), getFReg32(fa))); + + return True; +} + +static Bool gen_fmsub_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fa = SLICE(insn, 19, 15); + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmsub.d %s, %s, %s, %s\n", nameFReg(fd), nameFReg(fj), + nameFReg(fk), nameFReg(fa)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMSUB_D, 3, fj, fk, fa); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, qop(Iop_MSubF64, rm, getFReg64(fj), + getFReg64(fk), getFReg64(fa))); + + return True; +} + +static Bool gen_fnmadd_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fa = SLICE(insn, 19, 15); + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fnmadd.s %s, %s, %s, %s\n", nameFReg(fd), nameFReg(fj), + nameFReg(fk), nameFReg(fa)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FNMADD_S, 3, fj, fk, fa); + IRExpr* rm = get_rounding_mode(); + IRExpr* madd = qop(Iop_MAddF32, rm, getFReg32(fj), + getFReg32(fk), getFReg32(fa)); + putFReg32(fd, unop(Iop_NegF32, madd)); + + return True; +} + +static Bool gen_fnmadd_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fa = SLICE(insn, 19, 15); + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fnmadd.d %s, %s, %s, %s\n", nameFReg(fd), nameFReg(fj), + nameFReg(fk), nameFReg(fa)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FNMADD_D, 3, fj, fk, fa); + IRExpr* rm = get_rounding_mode(); + IRExpr* madd = qop(Iop_MAddF64, rm, getFReg64(fj), + getFReg64(fk), getFReg64(fa)); + putFReg64(fd, unop(Iop_NegF64, madd)); + + return True; +} + +static Bool gen_fnmsub_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fa = SLICE(insn, 19, 15); + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fnmsub.s %s, %s, %s, %s\n", nameFReg(fd), nameFReg(fj), + nameFReg(fk), nameFReg(fa)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FNMSUB_S, 3, fj, fk, fa); + IRExpr* rm = get_rounding_mode(); + IRExpr* msub = qop(Iop_MSubF32, rm, getFReg32(fj), + getFReg32(fk), getFReg32(fa)); + putFReg32(fd, unop(Iop_NegF32, msub)); + + return True; +} + +static Bool gen_fnmsub_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fa = SLICE(insn, 19, 15); + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fnmsub.d %s, %s, %s, %s\n", nameFReg(fd), nameFReg(fj), + nameFReg(fk), nameFReg(fa)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FNMSUB_D, 3, fj, fk, fa); + IRExpr* rm = get_rounding_mode(); + IRExpr* msub = qop(Iop_MSubF64, rm, getFReg64(fj), + getFReg64(fk), getFReg64(fa)); + putFReg64(fd, unop(Iop_NegF64, msub)); + + return True; +} + +static Bool gen_fmax_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmax.s %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMAX_S, 2, fj, fk, 0); + putFReg32(fd, binop(Iop_MaxNumF32, getFReg32(fj), getFReg32(fk))); + + return True; +} + +static Bool gen_fmax_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmax.d %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMAX_D, 2, fj, fk, 0); + putFReg64(fd, binop(Iop_MaxNumF64, getFReg64(fj), getFReg64(fk))); + + return True; +} + +static Bool gen_fmin_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmin.s %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMIN_S, 2, fj, fk, 0); + putFReg32(fd, binop(Iop_MinNumF32, getFReg32(fj), getFReg32(fk))); + + return True; +} + +static Bool gen_fmin_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmin.d %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMIN_D, 2, fj, fk, 0); + putFReg64(fd, binop(Iop_MinNumF64, getFReg64(fj), getFReg64(fk))); + + return True; +} + +static Bool gen_fmaxa_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmaxa.s %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMAXA_S, 2, fj, fk, 0); + putFReg32(fd, binop(Iop_MaxNumAbsF32, getFReg32(fj), getFReg32(fk))); + + return True; +} + +static Bool gen_fmaxa_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmaxa.d %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMAXA_D, 2, fj, fk, 0); + putFReg64(fd, binop(Iop_MaxNumAbsF64, getFReg64(fj), getFReg64(fk))); + + return True; +} + +static Bool gen_fmina_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmina.s %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMINA_S, 2, fj, fk, 0); + putFReg32(fd, binop(Iop_MinNumAbsF32, getFReg32(fj), getFReg32(fk))); + + return True; +} + +static Bool gen_fmina_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmina.d %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FMINA_D, 2, fj, fk, 0); + putFReg64(fd, binop(Iop_MinNumAbsF64, getFReg64(fj), getFReg64(fk))); + + return True; +} + +static Bool gen_fabs_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fabs.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FABS_S, 1, fj, 0, 0); + putFReg32(fd, unop(Iop_AbsF32, getFReg32(fj))); + + return True; +} + +static Bool gen_fabs_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fabs.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FABS_D, 1, fj, 0, 0); + putFReg64(fd, unop(Iop_AbsF64, getFReg64(fj))); + + return True; +} + +static Bool gen_fneg_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fneg.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FNEG_S, 1, fj, 0, 0); + putFReg32(fd, unop(Iop_NegF32, getFReg32(fj))); + + return True; +} + +static Bool gen_fneg_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fneg.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FNEG_D, 1, fj, 0, 0); + putFReg64(fd, unop(Iop_NegF64, getFReg64(fj))); + + return True; +} + +static Bool gen_fsqrt_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fsqrt.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FSQRT_S, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, binop(Iop_SqrtF32, rm, getFReg32(fj))); + + return True; +} + +static Bool gen_fsqrt_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fsqrt.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FSQRT_D, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, binop(Iop_SqrtF64, rm, getFReg64(fj))); + + return True; +} + +static Bool gen_frecip_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("frecip.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FRECIP_S, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, triop(Iop_DivF32, rm, mkF32i(1), getFReg32(fj))); + + return True; +} + +static Bool gen_frecip_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("frecip.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FRECIP_D, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, triop(Iop_DivF64, rm, mkF64i(1), getFReg64(fj))); + + return True; +} + +static Bool gen_frsqrt_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("frsqrt.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FRSQRT_S, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, binop(Iop_RSqrtF32, rm, getFReg32(fj))); + + return True; +} + +static Bool gen_frsqrt_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("frsqrt.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FRSQRT_D, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, binop(Iop_RSqrtF64, rm, getFReg64(fj))); + + return True; +} + +static Bool gen_fscaleb_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fscaleb.s %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FSCALEB_S, 2, fj, fk, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, triop(Iop_ScaleBF32, rm, getFReg32(fj), getFReg32(fk))); + + return True; +} + +static Bool gen_fscaleb_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fscaleb.d %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FSCALEB_D, 2, fj, fk, 0); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, triop(Iop_ScaleBF64, rm, getFReg64(fj), getFReg64(fk))); + + return True; +} + +static Bool gen_flogb_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("flogb.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FLOGB_S, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, binop(Iop_LogBF32, rm, getFReg32(fj))); + + return True; +} + +static Bool gen_flogb_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("flogb.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FLOGB_D, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, binop(Iop_LogBF64, rm, getFReg64(fj))); + + return True; +} + +static Bool gen_fcopysign_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fcopysign.s %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* i1 = unop(Iop_ReinterpF32asI32, getFReg32(fj)); + IRExpr* shl1 = binop(Iop_Shl32, i1, mkU8(1)); + IRExpr* shr1 = binop(Iop_Shr32, shl1, mkU8(1)); + IRExpr* i2 = unop(Iop_ReinterpF32asI32, getFReg32(fk)); + IRExpr* shr2 = binop(Iop_Shr32, i2, mkU8(31)); + IRExpr* shl2 = binop(Iop_Shl32, shr2, mkU8(31)); + IRExpr* or = binop(Iop_Or32, shr1, shl2); + putFReg32(fd, unop(Iop_ReinterpI32asF32, or)); + + return True; +} + +static Bool gen_fcopysign_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fcopysign.d %s, %s, %s\n", nameFReg(fd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* i1 = unop(Iop_ReinterpF64asI64, getFReg64(fj)); + IRExpr* shl1 = binop(Iop_Shl64, i1, mkU8(1)); + IRExpr* shr1 = binop(Iop_Shr64, shl1, mkU8(1)); + IRExpr* i2 = unop(Iop_ReinterpF64asI64, getFReg64(fk)); + IRExpr* shr2 = binop(Iop_Shr64, i2, mkU8(63)); + IRExpr* shl2 = binop(Iop_Shl64, shr2, mkU8(63)); + IRExpr* or = binop(Iop_Or64, shr1, shl2); + putFReg64(fd, unop(Iop_ReinterpI64asF64, or)); + + return True; +} + +static Bool gen_fclass_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fclass.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr** arg = mkIRExprVec_1(unop(Iop_ReinterpF64asI64, getFReg64(fj))); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_fclass_s", + &loongarch64_calculate_fclass_s, + arg); + putFReg32(fd, unop(Iop_ReinterpI32asF32, unop(Iop_64to32, call))); + + return True; +} + +static Bool gen_fclass_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fclass.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr** arg = mkIRExprVec_1(unop(Iop_ReinterpF64asI64, getFReg64(fj))); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_fclass_d", + &loongarch64_calculate_fclass_d, + arg); + putFReg64(fd, unop(Iop_ReinterpI64asF64, call)); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for floating point comparison insns ---*/ +/*------------------------------------------------------------*/ + +static inline IRExpr* is_UN ( IRExpr* e ) +{ + return binop(Iop_CmpEQ32, e, mkU32(0x45)); +} + +static inline IRExpr* is_LT ( IRExpr* e ) +{ + return binop(Iop_CmpEQ32, e, mkU32(0x1)); +} + +static inline IRExpr* is_GT ( IRExpr* e ) +{ + return binop(Iop_CmpEQ32, e, mkU32(0x0)); +} + +static inline IRExpr* is_EQ ( IRExpr* e ) +{ + return binop(Iop_CmpEQ32, e, mkU32(0x40)); +} + +static Bool gen_fcmp_cond_helper ( enum fpop op, UInt cc, + UInt fj, UInt fk, Bool size64 ) +{ + /* We have to convert 'irRes' from an IR-convention return result + (IRCmpF32Result / IRCmpF64Result) to a LOONGARCH-encoded group. + + FP cmp result | IR + -------------------- + UN | 0x45 + LT | 0x01 + GT | 0x00 + EQ | 0x40 + */ + IRTemp result = newTemp(Ity_I32); + if (size64) + assign(result, binop(Iop_CmpF64, getFReg64(fj), getFReg64(fk))); + else + assign(result, binop(Iop_CmpF32, getFReg32(fj), getFReg32(fk))); + + IRExpr* e; + switch (op) { + case FCMP_CAF_S: case FCMP_CAF_D: case FCMP_SAF_S: case FCMP_SAF_D: + e = mkU1(False); + break; + case FCMP_CLT_S: case FCMP_CLT_D: case FCMP_SLT_S: case FCMP_SLT_D: + e = is_LT(mkexpr(result)); + break; + case FCMP_CEQ_S: case FCMP_CEQ_D: case FCMP_SEQ_S: case FCMP_SEQ_D: + e = is_EQ(mkexpr(result)); + break; + case FCMP_CLE_S: case FCMP_CLE_D: case FCMP_SLE_S: case FCMP_SLE_D: + e = binop(Iop_Or1, is_LT(mkexpr(result)), is_EQ(mkexpr(result))); + break; + case FCMP_CUN_S: case FCMP_CUN_D: case FCMP_SUN_S: case FCMP_SUN_D: + e = is_UN(mkexpr(result)); + break; + case FCMP_CULT_S: case FCMP_CULT_D: case FCMP_SULT_S: case FCMP_SULT_D: + e = binop(Iop_Or1, is_UN(mkexpr(result)), is_LT(mkexpr(result))); + break; + case FCMP_CUEQ_S: case FCMP_CUEQ_D: case FCMP_SUEQ_S: case FCMP_SUEQ_D: + e = binop(Iop_Or1, is_UN(mkexpr(result)), is_EQ(mkexpr(result))); + break; + case FCMP_CULE_S: case FCMP_CULE_D: case FCMP_SULE_S: case FCMP_SULE_D: + e = binop(Iop_Or1, is_UN(mkexpr(result)), + binop(Iop_Or1, is_LT(mkexpr(result)), + is_EQ(mkexpr(result)))); + break; + case FCMP_CNE_S: case FCMP_CNE_D: case FCMP_SNE_S: case FCMP_SNE_D: + e = binop(Iop_Or1, is_GT(mkexpr(result)), is_LT(mkexpr(result))); + break; + case FCMP_COR_S: case FCMP_COR_D: case FCMP_SOR_S: case FCMP_SOR_D: + e = binop(Iop_Or1, is_GT(mkexpr(result)), + binop(Iop_Or1, is_LT(mkexpr(result)), + is_EQ(mkexpr(result)))); + break; + case FCMP_CUNE_S: case FCMP_CUNE_D: case FCMP_SUNE_S: case FCMP_SUNE_D: + e = binop(Iop_Or1, is_UN(mkexpr(result)), + binop(Iop_Or1, is_GT(mkexpr(result)), + is_LT(mkexpr(result)))); + break; + default: + return False; + } + + calculateFCSR(op, 2, fj, fk, 0); + putFCC(cc, unop(Iop_1Uto8, e)); + + return True; +} + +static Bool gen_fcmp_caf_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.caf.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CAF_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_caf_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.caf.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CAF_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_saf_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.saf.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SAF_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_saf_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.saf.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SAF_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_clt_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.clt.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CLT_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_clt_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.clt.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CLT_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_slt_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.slt.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SLT_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_slt_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.slt.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SLT_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_ceq_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.ceq.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CEQ_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_ceq_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.ceq.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CEQ_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_seq_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.seq.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SEQ_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_seq_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.seq.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SEQ_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_cle_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cle.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CLE_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_cle_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cle.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CLE_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_sle_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sle.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SLE_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_sle_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sle.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SLE_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_cun_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cun.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CUN_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_cun_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cun.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CUN_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_sun_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sun.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SUN_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_sun_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sun.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SUN_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_cult_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cult.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CULT_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_cult_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cult.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CULT_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_sult_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sult.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SULT_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_sult_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sult.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SULT_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_cueq_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cueq.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CUEQ_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_cueq_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cueq.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CUEQ_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_sueq_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sueq.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SUEQ_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_sueq_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sueq.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SUEQ_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_cule_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cule.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CULE_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_cule_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cule.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CULE_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_sule_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sule.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SULE_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_sule_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sule.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SULE_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_cne_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cne.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CNE_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_cne_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cne.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CNE_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_sne_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sne.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SNE_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_sne_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sne.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SNE_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_cor_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cor.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_COR_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_cor_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cor.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_COR_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_sor_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sor.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SOR_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_sor_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sor.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SOR_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_cune_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cune.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CUNE_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_cune_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.cune.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_CUNE_D, cd, fj, fk, True); +} + +static Bool gen_fcmp_sune_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sune.s %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SUNE_S, cd, fj, fk, False); +} + +static Bool gen_fcmp_sune_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("fcmp.sune.d %s, %s, %s\n", nameFCC(cd), nameFReg(fj), nameFReg(fk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_fcmp_cond_helper(FCMP_SUNE_D, cd, fj, fk, True); +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for floating point conversion insns ---*/ +/*------------------------------------------------------------*/ + +static IRExpr* is_Invalid_Overflow ( void ) +{ + /* Bits 16 to 20 in FCSR are flags. + Bit 18 - overflow + Bit 20 - invalid + */ + IRExpr* fcsr = getFCSR(0); + IRExpr* shr = binop(Iop_Shr32, fcsr, mkU8(16)); + IRExpr* and = binop(Iop_And32, shr, mkU32(0x14)); + return binop(Iop_CmpNE32, and, getIReg32(0)); +} + +static Bool gen_convert_s_helper ( enum fpop op, UInt fd, UInt fj ) +{ + IRExpr* e; + IRExpr* rm; + switch (op) { + case FTINTRM_W_S: + rm = gen_round_down(); + e = binop(Iop_F32toI32S, rm, getFReg32(fj)); + break; + case FTINTRM_W_D: + rm = gen_round_down(); + e = binop(Iop_F64toI32S, rm, getFReg64(fj)); + break; + case FTINTRP_W_S: + rm = gen_round_up(); + e = binop(Iop_F32toI32S, rm, getFReg32(fj)); + break; + case FTINTRP_W_D: + rm = gen_round_up(); + e = binop(Iop_F64toI32S, rm, getFReg64(fj)); + break; + case FTINTRZ_W_S: + rm = gen_round_to_zero(); + e = binop(Iop_F32toI32S, rm, getFReg32(fj)); + break; + case FTINTRZ_W_D: + rm = gen_round_to_zero(); + e = binop(Iop_F64toI32S, rm, getFReg64(fj)); + break; + case FTINTRNE_W_S: + rm = gen_round_to_nearest(); + e = binop(Iop_F32toI32S, rm, getFReg32(fj)); + break; + case FTINTRNE_W_D: + rm = gen_round_to_nearest(); + e = binop(Iop_F64toI32S, rm, getFReg64(fj)); + break; + case FTINT_W_S: + rm = get_rounding_mode(); + e = binop(Iop_F32toI32S, rm, getFReg32(fj)); + break; + case FTINT_W_D: + rm = get_rounding_mode(); + e = binop(Iop_F64toI32S, rm, getFReg64(fj)); + break; + default: + return False; + } + + calculateFCSR(op, 1, fj, 0, 0); + IRExpr* ite = IRExpr_ITE(is_Invalid_Overflow(), mkU32(0x7fffffff), e); + putFReg32(fd, unop(Iop_ReinterpI32asF32, ite)); + + return True; +} + +static Bool gen_convert_d_helper ( enum fpop op, UInt fd, UInt fj ) +{ + IRExpr* e; + IRExpr* rm; + switch (op) { + case FTINTRM_L_S: + rm = gen_round_down(); + e = binop(Iop_F32toI64S, rm, getFReg32(fj)); + break; + case FTINTRM_L_D: + rm = gen_round_down(); + e = binop(Iop_F64toI64S, rm, getFReg64(fj)); + break; + case FTINTRP_L_S: + rm = gen_round_up(); + e = binop(Iop_F32toI64S, rm, getFReg32(fj)); + break; + case FTINTRP_L_D: + rm = gen_round_up(); + e = binop(Iop_F64toI64S, rm, getFReg64(fj)); + break; + case FTINTRZ_L_S: + rm = gen_round_to_zero(); + e = binop(Iop_F32toI64S, rm, getFReg32(fj)); + break; + case FTINTRZ_L_D: + rm = gen_round_to_zero(); + e = binop(Iop_F64toI64S, rm, getFReg64(fj)); + break; + case FTINTRNE_L_S: + rm = gen_round_to_nearest(); + e = binop(Iop_F32toI64S, rm, getFReg32(fj)); + break; + case FTINTRNE_L_D: + rm = gen_round_to_nearest(); + e = binop(Iop_F64toI64S, rm, getFReg64(fj)); + break; + case FTINT_L_S: + rm = get_rounding_mode(); + e = binop(Iop_F32toI64S, rm, getFReg32(fj)); + break; + case FTINT_L_D: + rm = get_rounding_mode(); + e = binop(Iop_F64toI64S, rm, getFReg64(fj)); + break; + default: + return False; + } + + calculateFCSR(op, 1, fj, 0, 0); + IRExpr* ite = IRExpr_ITE(is_Invalid_Overflow(), + mkU64(0x7fffffffffffffffULL), e); + putFReg64(fd, unop(Iop_ReinterpI64asF64, ite)); + + return True; +} + +static Bool gen_fcvt_s_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fcvt.s.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FCVT_S_D, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, binop(Iop_F64toF32, rm, getFReg64(fj))); + + return True; +} + +static Bool gen_fcvt_d_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fcvt.d.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FCVT_D_S, 1, fj, 0, 0); + putFReg64(fd, unop(Iop_F32toF64, getFReg32(fj))); + + return True; +} + +static Bool gen_ftintrm_w_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrm.w.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_s_helper(FTINTRM_W_S, fd, fj); +} + +static Bool gen_ftintrm_w_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrm.w.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_s_helper(FTINTRM_W_D, fd, fj); +} + +static Bool gen_ftintrm_l_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrm.l.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_d_helper(FTINTRM_L_S, fd, fj); +} + +static Bool gen_ftintrm_l_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrm.l.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_d_helper(FTINTRM_L_D, fd, fj); +} + +static Bool gen_ftintrp_w_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrp.w.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_s_helper(FTINTRP_W_S, fd, fj); +} + +static Bool gen_ftintrp_w_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrp.w.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_s_helper(FTINTRP_W_D, fd, fj); +} + +static Bool gen_ftintrp_l_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrp.l.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_d_helper(FTINTRP_L_S, fd, fj); +} + +static Bool gen_ftintrp_l_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrp.l.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_d_helper(FTINTRP_L_D, fd, fj); +} + +static Bool gen_ftintrz_w_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrz.w.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_s_helper(FTINTRZ_W_S, fd, fj); +} + +static Bool gen_ftintrz_w_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrz.w.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_s_helper(FTINTRZ_W_D, fd, fj); +} + +static Bool gen_ftintrz_l_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrz.l.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_d_helper(FTINTRZ_L_S, fd, fj); +} + +static Bool gen_ftintrz_l_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrz.l.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_d_helper(FTINTRZ_L_D, fd, fj); +} + +static Bool gen_ftintrne_w_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrne.w.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_s_helper(FTINTRNE_W_S, fd, fj); +} + +static Bool gen_ftintrne_w_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrne.w.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_s_helper(FTINTRNE_W_D, fd, fj); +} + +static Bool gen_ftintrne_l_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrne.l.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_d_helper(FTINTRNE_L_S, fd, fj); +} + +static Bool gen_ftintrne_l_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftintrne.l.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_d_helper(FTINTRNE_L_D, fd, fj); +} + +static Bool gen_ftint_w_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftint.w.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_s_helper(FTINT_W_S, fd, fj); +} + +static Bool gen_ftint_w_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftint.w.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_s_helper(FTINT_W_D, fd, fj); +} + +static Bool gen_ftint_l_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftint.l.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_d_helper(FTINT_L_S, fd, fj); +} + +static Bool gen_ftint_l_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ftint.l.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + return gen_convert_d_helper(FTINT_L_D, fd, fj); +} + +static Bool gen_ffint_s_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ffint.s.w %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FFINT_S_W, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + IRExpr* f = unop(Iop_ReinterpF32asI32, getFReg32(fj)); + putFReg32(fd, binop(Iop_I32StoF32, rm, f)); + + return True; +} + +static Bool gen_ffint_s_l ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ffint.s.l %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FFINT_S_L, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + IRExpr* f = unop(Iop_ReinterpF64asI64, getFReg64(fj)); + putFReg32(fd, binop(Iop_I64StoF32, rm, f)); + + return True; +} + +static Bool gen_ffint_d_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ffint.d.w %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FFINT_D_W, 1, fj, 0, 0); + IRExpr* f = unop(Iop_ReinterpF32asI32, getFReg32(fj)); + putFReg64(fd, unop(Iop_I32StoF64, f)); + + return True; +} + +static Bool gen_ffint_d_l ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("ffint.d.l %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FFINT_D_L, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + IRExpr* f = unop(Iop_ReinterpF64asI64, getFReg64(fj)); + putFReg64(fd, binop(Iop_I64StoF64, rm, f)); + + return True; +} + +static Bool gen_frint_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("frint.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FRINT_S, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg32(fd, binop(Iop_RoundF32toInt, rm, getFReg32(fj))); + + return True; +} + +static Bool gen_frint_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("frint.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + calculateFCSR(FRINT_D, 1, fj, 0, 0); + IRExpr* rm = get_rounding_mode(); + putFReg64(fd, binop(Iop_RoundF64toInt, rm, getFReg64(fj))); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for floating point move insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_fmov_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmov.s %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putFReg32(fd, getFReg32(fj)); + + return True; +} + +static Bool gen_fmov_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fmov.d %s, %s\n", nameFReg(fd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putFReg64(fd, getFReg64(fj)); + + return True; +} + +static Bool gen_fsel ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt ca = SLICE(insn, 17, 15); + UInt fk = SLICE(insn, 14, 10); + UInt fj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fsel %s, %s, %s, %s\n", nameFReg(fd), nameFReg(fj), + nameFReg(fk), nameFCC(ca)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* cc = unop(Iop_8Uto64, getFCC(ca)); + IRExpr* cond = binop(Iop_CmpEQ64, cc, mkU64(0)); + putFReg64(fd, IRExpr_ITE(cond, getFReg64(fj), getFReg64(fk))); + + return True; +} + +static Bool gen_movgr2fr_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("movgr2fr.w %s, %s\n", nameFReg(fd), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + /* The high bits might be undefined, now the hardware implementation + of this instruction is that it is equivalent to movgr2fr.d. */ + putFReg64(fd, unop(Iop_ReinterpI64asF64, getIReg64(rj))); + + return True; +} + +static Bool gen_movgr2fr_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("movgr2fr.d %s, %s\n", nameFReg(fd), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putFReg64(fd, unop(Iop_ReinterpI64asF64, getIReg64(rj))); + + return True; +} + +static Bool gen_movgr2frh_w ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("movgr2frh.w %s, %s\n", nameFReg(fd), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* shl1 = binop(Iop_Shl64, getIReg64(rj), mkU8(32)); + IRExpr* i = unop(Iop_ReinterpF64asI64, getFReg64(fd)); + IRExpr* shl2 = binop(Iop_Shl64, i, mkU8(32)); + IRExpr* shr = binop(Iop_Shr64, shl2, mkU8(32)); + IRExpr* or = binop(Iop_Or64, shl1, shr); + putFReg64(fd, unop(Iop_ReinterpI64asF64, or)); + + return True; +} + +static Bool gen_movfr2gr_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("movfr2gr.s %s, %s\n", nameIReg(rd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* i = unop(Iop_ReinterpF32asI32, getFReg32(fj)); + putIReg(rd, extendS(Ity_I32, i)); + + return True; +} + +static Bool gen_movfr2gr_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("movfr2gr.d %s, %s\n", nameIReg(rd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putIReg(rd, unop(Iop_ReinterpF64asI64, getFReg64(fj))); + + return True; +} + +static Bool gen_movfrh2gr_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("movfrh2gr.s %s, %s\n", nameIReg(rd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* i = unop(Iop_ReinterpF64asI64, getFReg64(fj)); + IRExpr* shr = binop(Iop_Shr64, i, mkU8(32)); + putIReg(rd, extendS(Ity_I32, unop(Iop_64to32, shr))); + + return True; +} + +static Bool gen_movgr2fcsr ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt fcsr = SLICE(insn, 4, 0); + + DIP("movgr2fcsr %s, %s\n", nameFCSR(fcsr), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putFCSR(fcsr, getIReg32(rj)); + + return True; +} + +static Bool gen_movfcsr2gr ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fcsr = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("movfcsr2gr %s, %s\n", nameIReg(rd), nameFCSR(fcsr)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putIReg(rd, extendS(Ity_I32, getFCSR(fcsr))); + + return True; +} + +static Bool gen_movfr2cf ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt fj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("movfr2cf %s, %s\n", nameFCC(cd), nameFReg(fj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* i = unop(Iop_ReinterpF64asI64, getFReg64(fj)); + IRExpr* and = binop(Iop_And64, i, mkU64(0x1)); + putFCC(cd, unop(Iop_64to8, and)); + + return True; +} + +static Bool gen_movcf2fr ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt cj = SLICE(insn, 7, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("movcf2fr %s, %s\n", nameFReg(fd), nameFCC(cj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + /* The hardware implementation of this instruction + does clear the high bits. */ + IRExpr* cc = unop(Iop_8Uto64, getFCC(cj)); + putFReg64(fd, unop(Iop_ReinterpI64asF64, cc)); + + return True; +} + +static Bool gen_movgr2cf ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rj = SLICE(insn, 9, 5); + UInt cd = SLICE(insn, 2, 0); + + DIP("movgr2cf %s, %s\n", nameFCC(cd), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* and = binop(Iop_And64, getIReg64(rj), mkU64(0x1)); + putFCC(cd, unop(Iop_64to8, and)); + + return True; +} + +static Bool gen_movcf2gr ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt cj = SLICE(insn, 7, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("movcf2gr %s, %s\n", nameIReg(rd), nameFCC(cj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + /* The hardware implementation of this instruction + does clear the high bits. */ + putIReg(rd, unop(Iop_8Uto64, getFCC(cj))); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for floating point load/store insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_fld_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fld.s %s, %s, %d\n", nameFReg(fd), nameIReg(rj), + (Int)extend32(si12, 12)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + putFReg32(fd, load(Ity_F32, addr)); + + return True; +} + +static Bool gen_fst_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fst.s %s, %s, %d\n", nameFReg(fd), nameIReg(rj), + (Int)extend32(si12, 12)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + store(addr, getFReg32(fd)); + + return True; +} + +static Bool gen_fld_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fld.d %s, %s, %d\n", nameFReg(fd), nameIReg(rj), + (Int)extend32(si12, 12)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x7))); + putFReg64(fd, load(Ity_F64, addr)); + + return True; +} + +static Bool gen_fst_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fst.d %s, %s, %d\n", nameFReg(fd), nameIReg(rj), + (Int)extend32(si12, 12)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x7))); + store(addr, getFReg64(fd)); + + return True; +} + +static Bool gen_fldx_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fldx.s %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + putFReg32(fd, load(Ity_F32, addr)); + + return True; +} + +static Bool gen_fldx_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fldx.d %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x7))); + putFReg64(fd, load(Ity_F64, addr)); + + return True; +} + +static Bool gen_fstx_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fstx.s %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x3))); + store(addr, getFReg32(fd)); + + return True; +} + +static Bool gen_fstx_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fstx.d %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), getIReg64(rk)); + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_UAL)) + gen_SIGBUS(check_align(addr, mkU64(0x7))); + store(addr, getFReg64(fd)); + + return True; +} + +static Bool gen_fldgt_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fldgt.s %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + putFReg32(fd, load(Ity_F32, mkexpr(addr))); + + return True; +} + +static Bool gen_fldgt_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fldgt.d %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + putFReg64(fd, load(Ity_F64, mkexpr(addr))); + + return True; +} + +static Bool gen_fldle_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fldle.s %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + putFReg32(fd, load(Ity_F32, mkexpr(addr))); + + return True; +} + +static Bool gen_fldle_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fldle.d %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + putFReg64(fd, load(Ity_F64, mkexpr(addr))); + + return True; +} + +static Bool gen_fstgt_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fstgt.s %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + store(mkexpr(addr), getFReg32(fd)); + + return True; +} + +static Bool gen_fstgt_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fstgt.d %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + gen_SIGSYS(binop(Iop_CmpLE64U, mkexpr(addr), getIReg64(rk))); + store(mkexpr(addr), getFReg64(fd)); + + return True; +} + +static Bool gen_fstle_s ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fstle.s %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x3))); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + store(mkexpr(addr), getFReg32(fd)); + + return True; +} + +static Bool gen_fstle_d ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rk = SLICE(insn, 14, 10); + UInt rj = SLICE(insn, 9, 5); + UInt fd = SLICE(insn, 4, 0); + + DIP("fstle.d %s, %s, %s\n", nameFReg(fd), nameIReg(rj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp addr = newTemp(Ity_I64); + assign(addr, getIReg64(rj)); + gen_SIGBUS(check_align(mkexpr(addr), mkU64(0x7))); + gen_SIGSYS(binop(Iop_CmpLT64U, getIReg64(rk), mkexpr(addr))); + store(mkexpr(addr), getFReg64(fd)); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for branch insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_beqz ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs21 = (SLICE(insn, 4, 0) << 16) | SLICE(insn, 25, 10); + UInt rj = SLICE(insn, 9, 5); + + DIP("beqz %s, %d\n", nameIReg(rj), (Int)extend32(offs21, 21)); + + IRExpr* cond = binop(Iop_CmpEQ64, getIReg64(rj), mkU64(0)); + exit(cond, Ijk_Boring, extend64(offs21 << 2, 23)); + + return True; +} + +static Bool gen_bnez ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs21 = (SLICE(insn, 4, 0) << 16) | SLICE(insn, 25, 10); + UInt rj = SLICE(insn, 9, 5); + + DIP("bnez %s, %d\n", nameIReg(rj), (Int)extend32(offs21, 21)); + + IRExpr* cond = binop(Iop_CmpNE64, getIReg64(rj), mkU64(0)); + exit(cond, Ijk_Boring, extend64(offs21 << 2, 23)); + + return True; +} + +static Bool gen_bceqz ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs21 = (SLICE(insn, 4, 0) << 16) | SLICE(insn, 25, 10); + UInt cj = SLICE(insn, 7, 5); + + DIP("bceqz %s, %d\n", nameFCC(cj), (Int)extend32(offs21, 21)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* cc = unop(Iop_8Uto64, getFCC(cj)); + IRExpr* cond = binop(Iop_CmpEQ64, cc, mkU64(0)); + exit(cond, Ijk_Boring, extend64(offs21 << 2, 23)); + + return True; +} + +static Bool gen_bcnez ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs21 = (SLICE(insn, 4, 0) << 16) | SLICE(insn, 25, 10); + UInt cj = SLICE(insn, 7, 5); + + DIP("bcnez %s, %d\n", nameFCC(cj), (Int)extend32(offs21, 21)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_FP)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* cc = unop(Iop_8Uto64, getFCC(cj)); + IRExpr* cond = binop(Iop_CmpNE64, cc, mkU64(0)); + exit(cond, Ijk_Boring, extend64(offs21 << 2, 23)); + + return True; +} + +static Bool gen_jirl ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs16 = SLICE(insn, 25, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("jirl %s, %s, %d\n", nameIReg(rd), nameIReg(rj), + (Int)extend32(offs16, 16)); + + IRTemp tmp = newTemp(Ity_I64); + assign(tmp, getIReg64(rj)); /* This is necessary when rd == rj */ + putIReg(rd, mkU64(guest_PC_curr_instr + 4)); + IRExpr* imm = mkU64(extend64(offs16 << 2, 18)); + putPC(binop(Iop_Add64, mkexpr(tmp), imm)); + + dres->whatNext = Dis_StopHere; + dres->jk_StopHere = Ijk_Boring; + + return True; +} + +static Bool gen_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs26 = (SLICE(insn, 9, 0) << 16) | SLICE(insn, 25, 10); + + DIP("b %d\n", (Int)extend32(offs26, 26)); + + putPC(mkU64(guest_PC_curr_instr + extend64(offs26 << 2, 28))); + + dres->whatNext = Dis_StopHere; + dres->jk_StopHere = Ijk_Boring; + + return True; +} + +static Bool gen_bl ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs26 = (SLICE(insn, 9, 0) << 16) | SLICE(insn, 25, 10); + + DIP("bl %d\n", (Int)extend32(offs26, 26)); + + putIReg(1, mkU64(guest_PC_curr_instr + 4)); + putPC(mkU64(guest_PC_curr_instr + extend64(offs26 << 2, 28))); + + dres->whatNext = Dis_StopHere; + dres->jk_StopHere = Ijk_Boring; + + return True; +} + +static Bool gen_beq ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs16 = SLICE(insn, 25, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("beq %s, %s, %d\n", nameIReg(rj), nameIReg(rd), + (Int)extend32(offs16, 16)); + + IRExpr* cond = binop(Iop_CmpEQ64, getIReg64(rj), getIReg64(rd)); + exit(cond, Ijk_Boring, extend64(offs16 << 2, 18)); + + return True; +} + +static Bool gen_bne ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs16 = SLICE(insn, 25, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bne %s, %s, %d\n", nameIReg(rj), nameIReg(rd), + (Int)extend32(offs16, 16)); + + IRExpr* cond = binop(Iop_CmpNE64, getIReg64(rj), getIReg64(rd)); + exit(cond, Ijk_Boring, extend64(offs16 << 2, 18)); + + return True; +} + +static Bool gen_blt ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs16 = SLICE(insn, 25, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("blt %s, %s, %d\n", nameIReg(rj), nameIReg(rd), + (Int)extend32(offs16, 16)); + + IRExpr* cond = binop(Iop_CmpLT64S, getIReg64(rj), getIReg64(rd)); + exit(cond, Ijk_Boring, extend64(offs16 << 2, 18)); + + return True; +} + +static Bool gen_bge ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs16 = SLICE(insn, 25, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bge %s, %s, %d\n", nameIReg(rj), nameIReg(rd), + (Int)extend32(offs16, 16)); + + IRExpr* cond = binop(Iop_CmpLE64S, getIReg64(rd), getIReg64(rj)); + exit(cond, Ijk_Boring, extend64(offs16 << 2, 18)); + + return True; +} + +static Bool gen_bltu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs16 = SLICE(insn, 25, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bltu %s, %s, %d\n", nameIReg(rj), nameIReg(rd), + (Int)extend32(offs16, 16)); + + IRExpr* cond = binop(Iop_CmpLT64U, getIReg64(rj), getIReg64(rd)); + exit(cond, Ijk_Boring, extend64(offs16 << 2, 18)); + + return True; +} + +static Bool gen_bgeu ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt offs16 = SLICE(insn, 25, 10); + UInt rj = SLICE(insn, 9, 5); + UInt rd = SLICE(insn, 4, 0); + + DIP("bgeu %s, %s, %d\n", nameIReg(rj), nameIReg(rd), + (Int)extend32(offs16, 16)); + + IRExpr* cond = binop(Iop_CmpLE64U, getIReg64(rd), getIReg64(rj)); + exit(cond, Ijk_Boring, extend64(offs16 << 2, 18)); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for vector integer arithmetic insns ---*/ +/*------------------------------------------------------------*/ + +static IROp mkVecADD ( UInt size ) { + const IROp ops[5] + = { Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_Add64x2, Iop_Add128x1 }; + vassert(size < 5); + return ops[size]; +} + +static IROp mkVecSUB ( UInt size ) { + const IROp ops[5] + = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2, Iop_Sub128x1 }; + vassert(size < 5); + return ops[size]; +} + +static IROp mkVecMAXU ( UInt size ) { + const IROp ops[4] + = { Iop_Max8Ux16, Iop_Max16Ux8, Iop_Max32Ux4, Iop_Max64Ux2 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkVecMAXS ( UInt size ) { + const IROp ops[4] + = { Iop_Max8Sx16, Iop_Max16Sx8, Iop_Max32Sx4, Iop_Max64Sx2 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkVecMINU ( UInt size ) { + const IROp ops[4] + = { Iop_Min8Ux16, Iop_Min16Ux8, Iop_Min32Ux4, Iop_Min64Ux2 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkVecMINS ( UInt size ) { + const IROp ops[4] + = { Iop_Min8Sx16, Iop_Min16Sx8, Iop_Min32Sx4, Iop_Min64Sx2 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkV256MAXU ( UInt size ) { + const IROp ops[4] + = { Iop_Max8Ux32, Iop_Max16Ux16, Iop_Max32Ux8, Iop_Max64Ux4 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkV256MAXS ( UInt size ) { + const IROp ops[4] + = { Iop_Max8Sx32, Iop_Max16Sx16, Iop_Max32Sx8, Iop_Max64Sx4 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkV256MINU ( UInt size ) { + const IROp ops[4] + = { Iop_Min8Ux32, Iop_Min16Ux16, Iop_Min32Ux8, Iop_Min64Ux4 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkV256MINS ( UInt size ) { + const IROp ops[4] + = { Iop_Min8Sx32, Iop_Min16Sx16, Iop_Min32Sx8, Iop_Min64Sx4 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkVecCMPGTS ( UInt size ) { + const IROp ops[4] + = { Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, Iop_CmpGT64Sx2 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkVecSHLN ( UInt size ) { + const IROp ops[4] + = { Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkVecSHRN ( UInt size ) { + const IROp ops[4] + = { Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2 }; + vassert(size < 4); + return ops[size]; +} + +static Bool gen_vadd_vsub ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt vk = SLICE(insn, 14, 10); + UInt insSz = SLICE(insn, 16, 15); + UInt isAdd = SLICE(insn, 17, 17); + + const HChar *nm[2] = { "vsub", "vadd" }; + IROp mathOp = isAdd ? mkVecADD(insSz): mkVecSUB(insSz); + + DIP("%s.%s %s, %s, %s\n", nm[isAdd], mkInsSize(insSz), + nameVReg(vd), nameVReg(vj), nameVReg(vk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, binop(mathOp, getVReg(vj), getVReg(vk))); + + return True; +} + +static Bool gen_vaddi_vsubi ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt ui5 = SLICE(insn, 14, 10); + UInt insSz = SLICE(insn, 16, 15); + UInt isAdd = SLICE(insn, 17, 17); + + IRTemp res = newTemp(Ity_V128); + IROp mathOp = isAdd ? mkVecADD(insSz) : mkVecSUB(insSz); + + switch (insSz) { + case 0b00: assign(res, unop(Iop_Dup8x16, mkU8(ui5))); break; + case 0b01: assign(res, unop(Iop_Dup16x8, mkU16(ui5))); break; + case 0b10: assign(res, unop(Iop_Dup32x4, mkU32(ui5))); break; + case 0b11: assign(res, binop(Iop_64HLtoV128, mkU64(ui5), mkU64(ui5))); break; + default: vassert(0); break; + } + + const HChar *nm[2] = { "vsubi", "vaddi" }; + + DIP("%s.%s %s, %s, %u\n", nm[isAdd], mkInsSize(insSz + 4), + nameVReg(vd), nameVReg(vj), ui5); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, binop(mathOp, getVReg(vj), mkexpr(res))); + + return True; +} + +static Bool gen_vmax_vmin ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt vk = SLICE(insn, 14, 10); + UInt insSz = SLICE(insn, 16, 15); + UInt isMin = SLICE(insn, 17, 17); + UInt isU = SLICE(insn, 18, 18); + + IROp op = isMin ? isU ? mkVecMINU(insSz) : mkVecMINS(insSz) : + isU ? mkVecMAXU(insSz) : mkVecMAXS(insSz); + UInt id = isU ? (insSz + 4) : insSz; + const HChar *nm[2] = { "vmax", "vmin" }; + + DIP("%s.%s %s, %s, %s\n", nm[isMin], mkInsSize(id), + nameVReg(vd), nameVReg(vj), nameVReg(vk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, binop(op, getVReg(vj), getVReg(vk))); + + return True; +} + +static Bool gen_xvmax_xvmin ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt xd = SLICE(insn, 4, 0); + UInt xj = SLICE(insn, 9, 5); + UInt xk = SLICE(insn, 14, 10); + UInt insSz = SLICE(insn, 16, 15); + UInt isMin = SLICE(insn, 17, 17); + UInt isU = SLICE(insn, 18, 18); + + IROp op = isMin ? isU ? mkV256MINU(insSz) : mkV256MINS(insSz) : + isU ? mkV256MAXU(insSz) : mkV256MAXS(insSz); + UInt id = isU ? (insSz + 4) : insSz; + const HChar *nm[2] = { "xvmax", "xvmin" }; + + DIP("%s.%s %s, %s, %s\n", nm[isMin], mkInsSize(id), + nameXReg(xd), nameXReg(xj), nameXReg(xk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LASX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putXReg(xd, binop(op, getXReg(xj), getXReg(xk))); + + return True; +} + +static IRTemp gen_vmsk_b ( IRTemp shr ) +{ + UInt i; + IRTemp tmp[16]; + IRTemp tOr = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_V128); + + for (i = 0; i < 16; i++) { + tmp[i] = newTemp(Ity_I32); + assign(tmp[i], binop(Iop_Shl32, + unop(Iop_8Uto32, + binop(Iop_GetElem8x16, + mkexpr(shr), mkU8(i))), + mkU8(i))); + } + + assign(tOr, binop(Iop_Or32, + binop(Iop_Or32, + binop(Iop_Or32, + binop(Iop_Or32, mkexpr(tmp[15]), mkexpr(tmp[14])), + binop(Iop_Or32, mkexpr(tmp[13]), mkexpr(tmp[12]))), + binop(Iop_Or32, + binop(Iop_Or32, mkexpr(tmp[11]), mkexpr(tmp[10])), + binop(Iop_Or32, mkexpr(tmp[9]), mkexpr(tmp[8])))), + binop(Iop_Or32, + binop(Iop_Or32, + binop(Iop_Or32, mkexpr(tmp[7]), mkexpr(tmp[6])), + binop(Iop_Or32, mkexpr(tmp[5]), mkexpr(tmp[4]))), + binop(Iop_Or32, + binop(Iop_Or32, mkexpr(tmp[3]), mkexpr(tmp[2])), + binop(Iop_Or32, mkexpr(tmp[1]), mkexpr(tmp[0])))))); + assign(res, unop(Iop_64UtoV128, extendU(Ity_I32, mkexpr(tOr)))); + + return res; +} + +static IRTemp gen_vmsk_h ( IRTemp shr ) +{ + UInt i; + IRTemp tmp[8]; + IRTemp tOr = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_V128); + + for (i = 0; i < 8; i++) { + tmp[i] = newTemp(Ity_I32); + assign(tmp[i], binop(Iop_Shl32, + unop(Iop_16Uto32, + binop(Iop_GetElem16x8, + mkexpr(shr), mkU8(i))), + mkU8(i))); + } + + assign(tOr, binop(Iop_Or32, + binop(Iop_Or32, + binop(Iop_Or32, mkexpr(tmp[7]), mkexpr(tmp[6])), + binop(Iop_Or32, mkexpr(tmp[5]), mkexpr(tmp[4]))), + binop(Iop_Or32, + binop(Iop_Or32, mkexpr(tmp[3]), mkexpr(tmp[2])), + binop(Iop_Or32, mkexpr(tmp[1]), mkexpr(tmp[0]))))); + assign(res, unop(Iop_64UtoV128, extendU(Ity_I32, mkexpr(tOr)))); + + return res; +} + +static IRTemp gen_vmsk_w ( IRTemp shr ) +{ + UInt i; + IRTemp tmp[4]; + IRTemp tOr = newTemp(Ity_I32); + IRTemp res = newTemp(Ity_V128); + + for (i = 0; i < 4; i++) { + tmp[i] = newTemp(Ity_I32); + assign(tmp[i], binop(Iop_Shl32, + binop(Iop_GetElem32x4, + mkexpr(shr), mkU8(i)), + mkU8(i))); + } + assign(tOr, binop(Iop_Or32, + binop(Iop_Or32, mkexpr(tmp[3]), mkexpr(tmp[2])), + binop(Iop_Or32, mkexpr(tmp[1]), mkexpr(tmp[0])))); + + assign(res, unop(Iop_64UtoV128, extendU(Ity_I32, mkexpr(tOr)))); + + return res; +} + +static IRTemp gen_vmsk_d ( IRTemp shr ) +{ + UInt i; + IRTemp tmp[2]; + IRTemp res = newTemp(Ity_V128); + + for (i = 0; i < 2; i++) { + tmp[i] = newTemp(Ity_I64); + assign(tmp[i], binop(Iop_Shl64, + binop(Iop_GetElem64x2, + mkexpr(shr), mkU8(i)), + mkU8(i))); + } + assign(res, unop(Iop_64UtoV128, + binop(Iop_Or64,mkexpr(tmp[1]), mkexpr(tmp[0])))); + + return res; +} + +static Bool gen_vmsk ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt insSz = SLICE(insn, 11, 10); + UInt insTy = SLICE(insn, 13, 12); + + IRTemp shr = newTemp(Ity_V128); + IRTemp cmp = newTemp(Ity_V128); + IRTemp res = newTemp(Ity_V128); + IRTemp src = newTemp(Ity_V128); + assign(src, getVReg(vj)); + + switch (insTy) { + case 0b00: { + UInt shrNum[4] = {7, 15, 31, 63}; + + DIP("vmskltz.%s %s, %s\n", mkInsSize(insSz), nameVReg(vd), nameVReg(vj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + assign(cmp, binop(mkVecCMPGTS(insSz), mkV128(0x0000), mkexpr(src))); + assign(shr, binop(mkVecSHRN(insSz), mkexpr(cmp), mkU8(shrNum[insSz]))); + + switch(insSz) { + case 0b00: res = gen_vmsk_b(shr); break; + case 0b01: res = gen_vmsk_h(shr); break; + case 0b10: res = gen_vmsk_w(shr); break; + case 0b11: res = gen_vmsk_d(shr); break; + default: vassert(0); break; + } + break; + } + + case 0b01: { + DIP("vmskgez.b %s, %s\n", nameVReg(vd), nameVReg(vj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + assign(cmp, binop(Iop_OrV128, + binop(Iop_CmpGT8Sx16, mkexpr(src), mkV128(0x0000)), + binop(Iop_CmpEQ8x16, mkV128(0x0000), mkexpr(src)))); + assign(shr, binop(Iop_ShrN8x16, mkexpr(cmp), mkU8(7))); + res = gen_vmsk_b(shr); + break; + } + + case 0b10: { + DIP("vmsknz.b %s, %s\n", nameVReg(vd), nameVReg(vj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + assign(cmp, unop(Iop_NotV128, + binop(Iop_CmpEQ8x16, mkV128(0x0000), mkexpr(src)))); + assign(shr, binop(Iop_ShrN8x16, mkexpr(cmp), mkU8(7))); + res = gen_vmsk_b(shr); + break; + } + + default: + return False; + } + + putVReg(vd, mkexpr(res)); + + return True; +} + +static Bool gen_xvmsk ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt xd = SLICE(insn, 4, 0); + UInt xj = SLICE(insn, 9, 5); + UInt insTy = SLICE(insn, 13, 12); + + IRTemp shrHi = newTemp(Ity_V128); + IRTemp shrLo = newTemp(Ity_V128); + IRTemp cmpHi = newTemp(Ity_V128); + IRTemp cmpLo = newTemp(Ity_V128); + IRTemp res = newTemp(Ity_V256); + IRTemp src = newTemp(Ity_V256); + assign(src, getXReg(xj)); + + switch (insTy) { + case 0b10: { + DIP("xvmsknz.b %s, %s\n", nameXReg(xd), nameXReg(xj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp hi, lo; + hi = lo = IRTemp_INVALID; + breakupV256toV128s(src, &hi, &lo); + assign(cmpHi, unop(Iop_NotV128, + binop(Iop_CmpEQ8x16, mkV128(0x0000), mkexpr(hi)))); + assign(shrHi, binop(Iop_ShrN8x16, mkexpr(cmpHi), mkU8(7))); + assign(cmpLo, unop(Iop_NotV128, + binop(Iop_CmpEQ8x16, mkV128(0x0000), mkexpr(lo)))); + assign(shrLo, binop(Iop_ShrN8x16, mkexpr(cmpLo), mkU8(7))); + assign(res, binop(Iop_V128HLtoV256, mkexpr(gen_vmsk_b(shrHi)), mkexpr(gen_vmsk_b(shrLo)))); + break; + } + + default: + return False; + } + + putXReg(xd, mkexpr(res)); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for vector bit operation insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_logical_v ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt vk = SLICE(insn, 14, 10); + UInt insTy = SLICE(insn, 17, 15); + + IRTemp res = newTemp(Ity_V128); + IRTemp srcL = newTemp(Ity_V128); + IRTemp srcR = newTemp(Ity_V128); + assign(srcL, getVReg(vj)); + assign(srcR, getVReg(vk)); + + switch (insTy) { + case 0b100: + assign(res, binop(Iop_AndV128, mkexpr(srcL), mkexpr(srcR))); + break; + case 0b101: + assign(res, binop(Iop_OrV128, mkexpr(srcL), mkexpr(srcR))); + break; + case 0b110: + assign(res, binop(Iop_XorV128, mkexpr(srcL), mkexpr(srcR))); + break; + case 0b111: + assign(res, unop(Iop_NotV128, binop(Iop_OrV128, + mkexpr(srcL), mkexpr(srcR)))); + break; + case 0b000: + assign(res, binop(Iop_AndV128, + unop(Iop_NotV128, mkexpr(srcL)), + mkexpr(srcR))); + break; + case 0b001: + assign(res, binop(Iop_OrV128, + mkexpr(srcL), + unop(Iop_NotV128, mkexpr(srcR)))); + break; + default: + return False; + } + + const HChar *nm[8] = { "vandn.v", "vorn.v", "", "", + "vand.v", "vor.v", "vxor.v", "vnor.v" }; + + DIP("%s %s, %s, %s\n", nm[insTy], nameVReg(vd), nameVReg(vj), nameVReg(vk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, mkexpr(res)); + + return True; +} + +static Bool gen_logical_xv ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt xd = SLICE(insn, 4, 0); + UInt xj = SLICE(insn, 9, 5); + UInt xk = SLICE(insn, 14, 10); + UInt insTy = SLICE(insn, 17, 15); + + IRTemp res = newTemp(Ity_V256); + IRTemp sL = newTemp(Ity_V256); + IRTemp sR = newTemp(Ity_V256); + assign(sL, getXReg(xj)); + assign(sR, getXReg(xk)); + + switch (insTy) { + case 0b110: + assign(res, binop(Iop_XorV256, mkexpr(sL), mkexpr(sR))); + break; + default: + return False; + } + + const HChar *nm[8] = { "xvandn.v", "xvorn.v", "", "", + "xvand.v", "xvor.v", "xvxor.v", "xvnor.v" }; + + DIP("%s %s, %s, %s\n", nm[insTy], nameXReg(xd), nameXReg(xj), nameXReg(xk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LASX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putXReg(xd, mkexpr(res)); + + return True; +} + +static Bool gen_vlogical_u8 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt ui8 = SLICE(insn, 17, 10); + UInt insTy = SLICE(insn, 19, 18); + + IRTemp res = newTemp(Ity_V128); + switch (insTy) { + case 0b00: + assign(res, binop(Iop_AndV128, + getVReg(vj), + unop(Iop_Dup8x16, mkU8(ui8)))); + break; + case 0b01: + assign(res, binop(Iop_OrV128, + getVReg(vj), + unop(Iop_Dup8x16, mkU8(ui8)))); + break; + case 0b10: + assign(res, binop(Iop_XorV128, + getVReg(vj), + unop(Iop_Dup8x16, mkU8(ui8)))); + break; + case 0b11: + assign(res, unop(Iop_NotV128, + binop(Iop_OrV128, + getVReg(vj), + unop(Iop_Dup8x16, mkU8(ui8))))); + break; + default: + vassert(0); + break; + } + + const HChar *nm[4] = { "vandi.b", "vori.b", "vxori.b", "vnori.b" }; + + DIP("%s %s, %s, %u\n", nm[insTy], nameVReg(vd), nameVReg(vj), ui8); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, mkexpr(res)); + + return True; +} + +static Bool gen_vbiti ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt insImm = SLICE(insn, 17, 10); + UInt insTy = SLICE(insn, 19, 18); + + IRTemp c1 = newTemp(Ity_V128); + IRTemp argR = newTemp(Ity_V128); + IRTemp res = newTemp(Ity_V128); + UInt insSz, uImm; + + if ((insImm & 0xf8) == 0x8) { // 00001mmm; b + uImm = insImm & 0x07; + insSz = 0; + } else if ((insImm & 0xf0) == 0x10) { // 0001mmmm; h + uImm = insImm & 0x0f; + insSz = 1; + } else if ((insImm & 0xe0) == 0x20) { // 001mmmmm; w + uImm = insImm & 0x1f; + insSz = 2; + } else if ((insImm & 0xc0) == 0x40) { // 01mmmmmm; d + uImm = insImm & 0x3f; + insSz = 3; + } else { + vassert(0); + } + + switch (insSz) { + case 0b00: + assign(c1, unop(Iop_Dup8x16, mkU8(1))); + break; + case 0b01: + assign(c1, unop(Iop_Dup16x8, mkU16(1))); + break; + case 0b10: + assign(c1, unop(Iop_Dup32x4, mkU32(1))); + break; + case 0b11: + assign(c1, binop(Iop_64HLtoV128, mkU64(1), mkU64(1))); + break; + default: + vassert(0); + break; + } + + assign(argR, binop(mkVecSHLN(insSz), mkexpr(c1), mkU8(uImm))); + switch (insTy) { + case 0b00: + assign(res, binop(Iop_AndV128, + getVReg(vj), unop(Iop_NotV128, mkexpr(argR)))); + break; + case 0b01: + assign(res, binop(Iop_OrV128, getVReg(vj), mkexpr(argR))); + break; + case 0b10: + assign(res, binop(Iop_XorV128, getVReg(vj), mkexpr(argR))); + break; + default: + vassert(0); + break; + } + + const HChar *nm[3] = { "vbitrevi", "vbitclri", "vbitseti" }; + + DIP("%s.%s %s, %u\n", nm[insTy], mkInsSize(insSz), nameVReg(vd), uImm); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, mkexpr(res)); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for vector string processing insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_vfrstpi ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt ui5 = SLICE(insn, 14, 10); + UInt insSz = SLICE(insn, 16, 15); + + UInt i; + IRTemp data[2]; + IRTemp res = newTemp(Ity_V128); + + for (i = 0; i < 2; i++) { + data[i] = newTemp(Ity_I64); + assign(data[i], binop(Iop_GetElem64x2, getVReg(vj), mkU8(i))); + } + + IRExpr** arg = mkIRExprVec_3(mkU64(insSz), mkexpr(data[1]), mkexpr(data[0])); + IRExpr* call = mkIRExprCCall(Ity_I64, 0/*regparms*/, + "loongarch64_calculate_negative_id", + &loongarch64_calculate_negative_id, + arg); + + switch (insSz) { + case 0b00: + assign(res, triop(Iop_SetElem8x16, + getVReg(vd), + mkU8(ui5 % 16), + unop(Iop_64to8, call))); + break; + case 0b01: + assign(res, triop(Iop_SetElem16x8, + getVReg(vd), + mkU8(ui5 % 8), + unop(Iop_64to16, call))); + break; + default: + return False; + } + + DIP("vfrstpi.%s %s, %s, %u\n", mkInsSize(insSz), nameVReg(vd), nameVReg(vj), ui5); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, mkexpr(res)); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for vector comparison and selection insns ---*/ +/*------------------------------------------------------------*/ + +static IROp mkVecCMPEQ ( UInt size ) { + const IROp ops[4] + = { Iop_CmpEQ8x16, Iop_CmpEQ16x8, Iop_CmpEQ32x4, Iop_CmpEQ64x2 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkV256CMPEQ ( UInt size ) { + const IROp ops[4] + = { Iop_CmpEQ8x32, Iop_CmpEQ16x16, Iop_CmpEQ32x8, Iop_CmpEQ64x4 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkVecCMPGTU ( UInt size ) { + const IROp ops[4] + = { Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4, Iop_CmpGT64Ux2 }; + vassert(size < 4); + return ops[size]; +} + +static Bool gen_vcmp_integer ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt vk = SLICE(insn, 14, 10); + UInt insSz = SLICE(insn, 16, 15); + UInt insTy = SLICE(insn, 19, 17); + + UInt szId = insSz; + IRTemp res = newTemp(Ity_V128); + IRTemp argL = newTemp(Ity_V128); + IRTemp argR = newTemp(Ity_V128); + assign(argL, getVReg(vj)); + assign(argR, getVReg(vk)); + + switch (insTy) { + case 0b000: + assign(res, binop(mkVecCMPEQ(insSz), mkexpr(argL), mkexpr(argR))); + break; + case 0b001: + assign(res, binop(Iop_OrV128, + binop(mkVecCMPGTS(insSz), mkexpr(argR), mkexpr(argL)), + binop(mkVecCMPEQ(insSz), mkexpr(argL), mkexpr(argR)))); + break; + case 0b010: + assign(res, binop(Iop_OrV128, + binop(mkVecCMPGTU(insSz), mkexpr(argR), mkexpr(argL)), + binop(mkVecCMPEQ(insSz), mkexpr(argL), mkexpr(argR)))); + szId = insSz + 4; + break; + case 0b011: + assign(res, binop(mkVecCMPGTS(insSz), mkexpr(argR), mkexpr(argL))); + break; + case 0b100: + assign(res, binop(mkVecCMPGTU(insSz), mkexpr(argR), mkexpr(argL))); + szId = insSz + 4; + break; + default: + return False; + } + + const HChar *nm[5] = { "vseq", "vsle", "vsle", "vslt", "vslt" }; + + DIP("%s.%s %s, %s, %s\n", nm[insTy], mkInsSize(szId), + nameVReg(vd), nameVReg(vj), nameVReg(vk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, mkexpr(res)); + + return True; +} + +static Bool gen_vcmpi_integer ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt si5 = SLICE(insn, 14, 10); + UInt insSz = SLICE(insn, 16, 15); + UInt isS = SLICE(insn, 17, 17); + UInt insTy = SLICE(insn, 19, 17); + + UInt szId = insSz; + IRTemp res = newTemp(Ity_V128); + IRTemp argL = newTemp(Ity_V128); + IRTemp argR = newTemp(Ity_V128); + assign(argL, getVReg(vj)); + + IRExpr *si5Expr; + IRTemp s64 = newTemp(Ity_I64); + assign(s64, mkU64(extend64(si5, 5))); + + if (insTy == 0b000) + isS = 1; + + switch (insSz) { + case 0b00: + si5Expr = isS ? unop(Iop_64to8, mkexpr(s64)) : mkU8(si5); + assign(argR, unop(Iop_Dup8x16, si5Expr)); + break; + case 0b01: + si5Expr = isS ? unop(Iop_64to16, mkexpr(s64)) : mkU16(si5); + assign(argR, unop(Iop_Dup16x8, si5Expr)); + break; + case 0b10: + si5Expr = isS ? unop(Iop_64to32, mkexpr(s64)) : mkU32(si5); + assign(argR, unop(Iop_Dup32x4, si5Expr)); + break; + case 0b11: + si5Expr = isS ? mkexpr(s64) : mkU64(si5); + assign(argR, binop(Iop_64HLtoV128, si5Expr, si5Expr)); + break; + default: + vassert(0); + break; + } + + switch (insTy) { + case 0b000: + assign(res, binop(mkVecCMPEQ(insSz), mkexpr(argL), mkexpr(argR))); + break; + case 0b001: + assign(res, binop(Iop_OrV128, + binop(mkVecCMPGTS(insSz), mkexpr(argR), mkexpr(argL)), + binop(mkVecCMPEQ(insSz), mkexpr(argL), mkexpr(argR)))); + break; + case 0b010: + assign(res, binop(Iop_OrV128, + binop(mkVecCMPGTU(insSz), mkexpr(argR), mkexpr(argL)), + binop(mkVecCMPEQ(insSz), mkexpr(argL), mkexpr(argR)))); + szId = insSz + 4; + break; + case 0b011: + assign(res, binop(mkVecCMPGTS(insSz), mkexpr(argR), mkexpr(argL))); + break; + case 0b100: + assign(res, binop(mkVecCMPGTU(insSz), mkexpr(argR), mkexpr(argL))); + szId = insSz + 4; + break; + default: + vassert(0); + break; + } + + const HChar *nm[10] = { "vseqi", "vslei", "vslei", "vslti", "vslti" }; + + DIP("%s.%s %s, %s, %d\n", nm[insTy], mkInsSize(szId), nameVReg(vd), + nameVReg(vj), (Int)extend32(si5, 5)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, mkexpr(res)); + + return True; +} + +static Bool gen_xvcmp_integer ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt xd = SLICE(insn, 4, 0); + UInt xj = SLICE(insn, 9, 5); + UInt xk = SLICE(insn, 14, 10); + UInt insSz = SLICE(insn, 16, 15); + UInt insTy = SLICE(insn, 19, 17); + + UInt szId = insSz; + IRTemp res = newTemp(Ity_V256); + IRTemp argL = newTemp(Ity_V256); + IRTemp argR = newTemp(Ity_V256); + assign(argL, getXReg(xj)); + assign(argR, getXReg(xk)); + + switch (insTy) { + case 0b000: + assign(res, binop(mkV256CMPEQ(insSz), mkexpr(argL), mkexpr(argR))); + break; + default: + return False; + } + + const HChar *nm[5] = { "xvseq", "xvsle", "xvsle", "xvslt", "xvslt" }; + + DIP("%s.%s %s, %s, %s\n", nm[insTy], mkInsSize(szId), + nameXReg(xd), nameXReg(xj), nameXReg(xk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LASX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putXReg(xd, mkexpr(res)); + + return True; +} + +static Bool gen_vset ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt cd = SLICE(insn, 2, 0); + UInt vj = SLICE(insn, 9, 5); + UInt insSz = SLICE(insn, 11, 10); + UInt insTy = SLICE(insn, 13, 12); + + IROp ops64; + IRTemp resHi = newTemp(Ity_I64); + IRTemp resLo = newTemp(Ity_I64); + IRTemp res = newTemp(Ity_V128); + IRTemp eq = newTemp(Ity_V128); + IRTemp z128 = newTemp(Ity_V128); + assign(z128, mkV128(0x0000)); + + switch (insTy) { + case 0b01: { + if (SLICE(insn, 10, 10) == 0b0) { + DIP("vseteqz.v %u, %s", cd, nameVReg(vj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + assign(res, binop(Iop_CmpEQ64x2, getVReg(vj), mkexpr(z128))); + ops64 = Iop_And64; + } else { + DIP("vsetnez.v %u, %s", cd, nameVReg(vj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + assign(res, unop(Iop_NotV128, + binop(Iop_CmpEQ64x2, getVReg(vj), mkexpr(z128)))); + ops64 = Iop_Or64; + } + break; + } + + case 0b10: { + DIP("vsetanyeqz.%s %u, %s", mkInsSize(insSz), cd, nameVReg(vj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + assign(eq, binop(mkVecCMPEQ(insSz), getVReg(vj), mkexpr(z128))); + assign(res, unop(Iop_NotV128, + binop(Iop_CmpEQ64x2, mkexpr(eq), mkexpr(z128)))); + ops64 = Iop_Or64; + break; + } + + case 0b11: { + DIP("vsetqllnez.%s %u, %s", mkInsSize(insSz), cd, nameVReg(vj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + assign(eq, binop(mkVecCMPEQ(insSz), getVReg(vj), mkexpr(z128))); + assign(res, binop(Iop_CmpEQ64x2, mkexpr(eq), mkexpr(z128))); + ops64 = Iop_And64; + break; + } + + default: + return False; + } + + assign(resHi, binop(Iop_GetElem64x2, mkexpr(res), mkU8(1))); + assign(resLo, binop(Iop_GetElem64x2, mkexpr(res), mkU8(0))); + putFCC(cd, unop(Iop_64to8, binop(ops64, mkexpr(resHi), mkexpr(resLo)))); + + return True; +} + +static Bool gen_xvset ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt cd = SLICE(insn, 2, 0); + UInt xj = SLICE(insn, 9, 5); + UInt insSz = SLICE(insn, 11, 10); + UInt insTy = SLICE(insn, 13, 12); + + IROp ops64 = Iop_INVALID; + IRTemp res = newTemp(Ity_V256); + IRTemp z128 = newTemp(Ity_V128); + IRTemp src = newTemp(Ity_V256); + assign(z128, mkV128(0x0000)); + assign(src, getXReg(xj)); + + switch (insTy) { + case 0b01: { + if (SLICE(insn, 10, 10) == 0b0) { + DIP("xvseteqz.v %u, %s", cd, nameXReg(xj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LASX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp hi, lo; + hi = lo = IRTemp_INVALID; + breakupV256toV128s(src, &hi, &lo); + assign(res, binop(Iop_V128HLtoV256, + binop(Iop_CmpEQ64x2, mkexpr(hi), mkexpr(z128)), + binop(Iop_CmpEQ64x2, mkexpr(hi), mkexpr(z128)))); + ops64 = Iop_And64; + } else { + return False; + } + break; + } + + case 0b10: { + DIP("xvsetanyeqz.%s %u, %s", mkInsSize(insSz), cd, nameXReg(xj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LASX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp eqHi = newTemp(Ity_V128); + IRTemp eqLo = newTemp(Ity_V128); + IRTemp hi, lo; + hi = lo = IRTemp_INVALID; + breakupV256toV128s(src, &hi, &lo); + assign(eqHi, binop(mkVecCMPEQ(insSz), mkexpr(hi), mkexpr(z128))); + assign(eqLo, binop(mkVecCMPEQ(insSz), mkexpr(lo), mkexpr(z128))); + assign(res, binop(Iop_V128HLtoV256, + unop(Iop_NotV128, + binop(Iop_CmpEQ64x2, mkexpr(eqHi), mkexpr(z128))), + unop(Iop_NotV128, + binop(Iop_CmpEQ64x2, mkexpr(eqLo), mkexpr(z128))))); + ops64 = Iop_Or64; + break; + } + + default: + return False; + } + + IRTemp r1, r2, r3, r4; + r1 = r2 = r3 = r4 = IRTemp_INVALID; + breakupV256to64s(res, &r1, &r2, &r3, &r4); + putFCC(cd, unop(Iop_64to8, binop(ops64, + binop(ops64, mkexpr(r1), mkexpr(r2)), + binop(ops64, mkexpr(r3), mkexpr(r4))))); + + return True; +} + +/*------------------------------------------------------------*/ +/*--- Helpers for vector moving and shuffling insns ---*/ +/*------------------------------------------------------------*/ + +static IROp mkVecPACKOD ( UInt size ) { + const IROp ops[4] + = { Iop_PackOddLanes8x16, Iop_PackOddLanes16x8, + Iop_PackOddLanes32x4, Iop_InterleaveHI64x2 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkVecPACKEV ( UInt size ) { + const IROp ops[4] + = { Iop_PackEvenLanes8x16, Iop_PackEvenLanes16x8, + Iop_PackEvenLanes32x4, Iop_InterleaveLO64x2 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkVecINTERLEAVELO ( UInt size ) { + const IROp ops[4] + = { Iop_InterleaveLO8x16, Iop_InterleaveLO16x8, + Iop_InterleaveLO32x4, Iop_InterleaveLO64x2 }; + vassert(size < 4); + return ops[size]; +} + +static IROp mkVecINTERLEAVEHI ( UInt size ) { + const IROp ops[4] + = { Iop_InterleaveHI8x16, Iop_InterleaveHI16x8, + Iop_InterleaveHI32x4, Iop_InterleaveHI64x2 }; + vassert(size < 4); + return ops[size]; +} + +static Bool gen_vpickve2gr ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt rd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt insImm = SLICE(insn, 15, 10); + UInt isS = SLICE(insn, 18, 18); + + UInt uImm, insSz; + IRExpr *immExpr; + IRType extTy = Ity_INVALID; + IRTemp res = newTemp(Ity_I64); + + if ((insImm & 0x30) == 0x20) { // 10mmmm; b + uImm = insImm & 0xf; + insSz = 0; + extTy = Ity_I8; + } else if ((insImm & 0x38) == 0x30) { // 110mmm; h + uImm = insImm & 0x7; + insSz = 1; + extTy = Ity_I16; + } else if ((insImm & 0x3c) == 0x38) { // 1110mm; w + uImm = insImm & 0x3; + insSz = 2; + extTy = Ity_I32; + } else if ((insImm & 0x3e) == 0x3c) { // 11110m; d + uImm = insImm & 0x1; + insSz = 3; + } else { + vassert(0); + } + + immExpr = binop(mkVecGetElem(insSz), getVReg(vj), mkU8(uImm)); + if (insSz != 3) + assign(res, isS ? extendS(extTy, immExpr) : + extendU(extTy, immExpr)); + else + assign(res, binop(Iop_Or64, mkU64(0), immExpr)); + + UInt nmId = isS ? insSz : (insSz + 4); + + DIP("vpickve2gr.%s %s, %s", mkInsSize(nmId), + nameIReg(rd), nameVReg(vj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putIReg(rd, mkexpr(res)); + + return True; +} + +static Bool gen_vreplgr2vr ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt rj = SLICE(insn, 9, 5); + UInt insSz = SLICE(insn, 11, 10); + + IRTemp res = newTemp(Ity_V128); + switch (insSz) { + case 0b00: + assign(res, unop(Iop_Dup8x16, getIReg8(rj))); + break; + case 0b01: + assign(res, unop(Iop_Dup16x8, getIReg16(rj))); + break; + case 0b10: + assign(res, unop(Iop_Dup32x4, getIReg32(rj))); + break; + case 0b11: + assign(res, binop(Iop_64HLtoV128, getIReg64(rj), getIReg64(rj))); + break; + default: + vassert(0); + break; + } + + DIP("vreplgr2vr.%s %s, %s", mkInsSize(insSz), + nameVReg(vd), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, mkexpr(res)); + + return True; +} + +static Bool gen_xvreplgr2vr ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt xd = SLICE(insn, 4, 0); + UInt rj = SLICE(insn, 9, 5); + UInt insSz = SLICE(insn, 11, 10); + + IRTemp res = newTemp(Ity_V128); + switch (insSz) { + case 0b00: + assign(res, unop(Iop_Dup8x16, getIReg8(rj))); + break; + case 0b01: + assign(res, unop(Iop_Dup16x8, getIReg16(rj))); + break; + case 0b10: + assign(res, unop(Iop_Dup32x4, getIReg32(rj))); + break; + case 0b11: + assign(res, binop(Iop_64HLtoV128, getIReg64(rj), getIReg64(rj))); + break; + default: + vassert(0); + break; + } + + DIP("xvreplgr2vr.%s %s, %s", mkInsSize(insSz), + nameXReg(xd), nameIReg(rj)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LASX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putXReg(xd, binop(Iop_V128HLtoV256, mkexpr(res), mkexpr(res))); + + return True; +} + +static Bool gen_vreplve ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt rk = SLICE(insn, 14, 10); + UInt insSz = SLICE(insn, 16, 15); + + IRExpr *elem; + IRTemp mod = newTemp(Ity_I8); + IRTemp res = newTemp(Ity_V128); + UInt div[4] = { 0x10, 0x8, 0x4, 0x2 }; + + assign(mod, unop(Iop_64to8, + unop(Iop_128HIto64, + binop(Iop_DivModU64to64, + getIReg64(rk), + mkU64(div[insSz]))))); + + elem = binop(mkVecGetElem(insSz), getVReg(vj), mkexpr(mod)); + switch (insSz) { + case 0b00: + assign(res, unop(Iop_Dup8x16, elem)); + break; + case 0b01: + assign(res, unop(Iop_Dup16x8, elem)); + break; + case 0b10: + assign(res, unop(Iop_Dup32x4, elem)); + break; + case 0b11: + assign(res, binop(Iop_64HLtoV128, elem, elem)); + break; + default: + vassert(0); + break; + } + + DIP("vreplve.%s %s, %s, %s", mkInsSize(insSz), + nameVReg(vd), nameVReg(vj), nameIReg(rk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, mkexpr(res)); + + return True; +} + +static Bool gen_xvpickve ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt xd = SLICE(insn, 4, 0); + UInt xj = SLICE(insn, 9, 5); + UInt insImm = SLICE(insn, 15, 10); + + UInt sImm, insSz; + IRTemp res = newTemp(Ity_I64); + IRTemp z64 = newTemp(Ity_I64); + IRTemp src = newTemp(Ity_V256); + assign(z64, mkU64(0)); + assign(src, getXReg(xj)); + + if ((insImm & 0x38) == 0x30) { // 110ui3; w + IRTemp s[8]; + s[7] = s[6] = s[5] = s[4] = s[3] = s[2] = s[1] = s[0] = IRTemp_INVALID; + breakupV256to32s(src, &s[7], &s[6], &s[5], &s[4], + &s[3], &s[2], &s[1], &s[0]); + sImm = insImm & 0x7; + insSz = 0; + assign(res, extendU(Ity_I32, mkexpr(s[sImm]))); + } else if ((insImm & 0x3c) == 0x38) { // 1110ui2; d + IRTemp s[4]; + s[3] = s[2] = s[1] = s[0] = IRTemp_INVALID; + breakupV256to64s(src, &s[3], &s[2], &s[1], &s[0]); + sImm = insImm & 0x3; + insSz = 1; + assign(res, mkexpr(s[sImm])); + } else { + vassert(0); + } + + const HChar arr = "wd"[insSz]; + DIP("xvpickve.%c %s, %s, %u", arr, nameXReg(xd), nameXReg(xj), sImm); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LASX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putXReg(xd, mkV256from64s(z64, z64, z64, res)); + + return True; +} + +static Bool gen_evod ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt vj = SLICE(insn, 9, 5); + UInt vk = SLICE(insn, 14, 10); + UInt insSz = SLICE(insn, 16, 15); + + const HChar *nm; + IRTemp argL = newTemp(Ity_V128); + IRTemp argR = newTemp(Ity_V128); + IRTemp res = newTemp(Ity_V128); + + switch (SLICE(insn, 19, 17)) { + case 0b011: + nm = "vpackev"; + assign(argL, binop(mkVecPACKEV(insSz), + getVReg(vj), + mkV128(0x0000))); + assign(argR, binop(mkVecPACKEV(insSz), + getVReg(vk), + mkV128(0x0000))); + assign(res, binop(mkVecINTERLEAVEHI(insSz), + mkexpr(argL), + mkexpr(argR))); + break; + case 0b100: + nm = "vpackod"; + assign(argL, binop(mkVecPACKOD(insSz), + getVReg(vj), + mkV128(0x0000))); + assign(argR, binop(mkVecPACKOD(insSz), + getVReg(vk), + mkV128(0x0000))); + assign(res, binop(mkVecINTERLEAVEHI(insSz), + mkexpr(argL), + mkexpr(argR))); + break; + case 0b101: + nm = "vilvl"; + assign(res, binop(mkVecINTERLEAVELO(insSz), + getVReg(vj), + getVReg(vk))); + break; + case 0b110: + nm = "vilvh"; + assign(res, binop(mkVecINTERLEAVEHI(insSz), + getVReg(vj), + getVReg(vk))); + break; + case 0b111: + nm = "vpickev"; + assign(res, binop(mkVecPACKEV(insSz), + getVReg(vj), + getVReg(vk))); + break; + case 0b000: + nm = "vpickod"; + assign(res, binop(mkVecPACKOD(insSz), + getVReg(vj), + getVReg(vk))); + break; + default: + return False; + } + + DIP("%s.%s %s, %s, %s\n", nm, mkInsSize(insSz), + nameVReg(vd), nameVReg(vj), nameVReg(vk)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, mkexpr(res)); + return True; +} + +static Bool gen_vshuf_b ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt va = SLICE(insn, 19, 15); + UInt vk = SLICE(insn, 14, 10); + UInt vj = SLICE(insn, 9, 5); + UInt vd = SLICE(insn, 4, 0); + + DIP("vshuf.b %s, %s, %s, %s\n", nameVReg(vd), nameVReg(vj), nameVReg(vk), + nameVReg(va)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRTemp sHi = newTemp(Ity_V128); + IRTemp sLo = newTemp(Ity_V128); + IRTemp sId = newTemp(Ity_V128); + assign(sHi, getVReg(vj)); + assign(sLo, getVReg(vk)); + assign(sId, getVReg(va)); + UInt i; + IRTemp id[16], res[16]; + + for (i = 0; i < 16; i++) { + id[i] = newTemp(Ity_I8); + res[i] = newTemp(Ity_I8); + + assign(id[i], binop(Iop_GetElem8x16, mkexpr(sId), mkU8(i))); + + assign(res[i], IRExpr_ITE( + binop(Iop_CmpEQ64, + extendU(Ity_I8, binop(Iop_And8, + mkexpr(id[i]), + mkU8(0xC0))), + mkU64(0x0)), + IRExpr_ITE( + binop(Iop_CmpLT64U, + extendU(Ity_I8, binop(Iop_And8, + mkexpr(id[i]), + mkU8(0x1F))), + mkU64(0x10)), + binop(Iop_GetElem8x16, + mkexpr(sLo), + mkexpr(id[i])), + binop(Iop_GetElem8x16, + mkexpr(sHi), + unop(Iop_64to8, + binop(Iop_Sub64, + extendU(Ity_I8, mkexpr(id[i])), + mkU64(0x10))))), + mkU8(0x0))); + } + + putVReg(vd, + binop(Iop_64HLtoV128, + binop(Iop_32HLto64, + binop(Iop_16HLto32, + binop(Iop_8HLto16, mkexpr(res[15]), mkexpr(res[14])), + binop(Iop_8HLto16, mkexpr(res[13]), mkexpr(res[12]))), + binop(Iop_16HLto32, + binop(Iop_8HLto16, mkexpr(res[11]), mkexpr(res[10])), + binop(Iop_8HLto16, mkexpr(res[9]), mkexpr(res[8])))), + binop(Iop_32HLto64, + binop(Iop_16HLto32, + binop(Iop_8HLto16, mkexpr(res[7]), mkexpr(res[6])), + binop(Iop_8HLto16, mkexpr(res[5]), mkexpr(res[4]))), + binop(Iop_16HLto32, + binop(Iop_8HLto16, mkexpr(res[3]), mkexpr(res[2])), + binop(Iop_8HLto16, mkexpr(res[1]), mkexpr(res[0])))))); + + return True; +} + +static Bool gen_xvpermi ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt xd = SLICE(insn, 4, 0); + UInt xj = SLICE(insn, 9, 5); + UInt ui8 = SLICE(insn, 17, 10); + UInt InsSz = SLICE(insn, 19, 18); + + UInt id0 = ui8 & 0x03; + UInt id1 = (ui8 & 0x0c) >> 2; + UInt id2 = (ui8 & 0x30) >> 4; + UInt id3 = (ui8 & 0xc0) >> 6; + + IRTemp res = newTemp(Ity_V256); + IRTemp sJ = newTemp(Ity_V256); + assign(sJ, getXReg(xj)); + IRTemp sD = newTemp(Ity_V256); + assign(sD, getXReg(xd)); + + switch (InsSz) { + case 0b01: { + IRTemp s[16]; + s[7] = s[6] = s[5] = s[4] = s[3] = s[2] = s[1] = s[0] = IRTemp_INVALID; + s[15] = s[14] = s[13] = s[12] = s[11] = s[10] = s[9] = s[8] = IRTemp_INVALID; + breakupV256to32s(sJ, &s[7], &s[6], &s[5], &s[4], + &s[3], &s[2], &s[1], &s[0]); + breakupV256to32s(sD, &s[15], &s[14], &s[13], &s[12], + &s[11], &s[10], &s[9], &s[8]); + assign(res, mkV256from32s(s[id0], s[id1], s[id2], s[id3], + s[id0 + 4], s[id1 + 4], s[id2 + 4], s[id3 + 4])); + break; + } + case 0b10: { + IRTemp s[4]; + s[3] = s[2] = s[1] = s[0] = IRTemp_INVALID; + breakupV256to64s(sJ, &s[3], &s[2], &s[1], &s[0]); + assign(res, mkV256from64s(s[id0], s[id1], s[id2], s[id3])); + break; + } + case 0b11: { + IRTemp s[4]; + s[3] = s[2] = s[1] = s[0] = IRTemp_INVALID; + breakupV256toV128s(sJ, &s[1], &s[0]); + breakupV256toV128s(sD, &s[3], &s[2]); + assign(res, binop(Iop_V128HLtoV256, mkexpr(s[id2]), mkexpr(s[id0]))); + break; + } + default: + vassert(0); + break; + } + + DIP("xvpermi.%s %s, %s, %u\n", mkInsSize(InsSz), nameXReg(xd), nameXReg(xj), ui8); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LASX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putXReg(xd, mkexpr(res)); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Helpers for vector load/store insns ---*/ +/*------------------------------------------------------------*/ + +static Bool gen_vld ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt vd = SLICE(insn, 4, 0); + + DIP("vld %s, %s, %d\n", nameVReg(vd), nameIReg(rj), + (Int)extend32(si12, 12)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + putVReg(vd, load(Ity_V128, addr)); + + return True; +} + +static Bool gen_vldrepl ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt rj = SLICE(insn, 9, 5); + UInt insImm = SLICE(insn, 23, 10); + + UInt sImm, insSz; + IRTemp res = newTemp(Ity_V128); + IRTemp addr = newTemp(Ity_I64); + + if ((insImm & 0x3000) == 0x2000) { // 10si12; b + sImm = insImm & 0xfff; + insSz = 0; + } else if ((insImm & 0x3800) == 0x1000) { // 010si11; h + sImm = insImm & 0x7ff; + insSz = 1; + } else if ((insImm & 0x3c00) == 0x800) { // 0010si10; w + sImm = insImm & 0x3ff; + insSz = 2; + } else if ((insImm & 0x3e00) == 0x400) { // 00010si9; d + sImm = insImm & 0x1ff; + insSz = 3; + } else { + return False; + } + + switch (insSz) { + case 0b00: { + assign(addr, binop(Iop_Add64, + getIReg64(rj), + mkU64(extend64(sImm, 12)))); + assign(res, unop(Iop_Dup8x16, load(Ity_I8, mkexpr(addr)))); + break; + } + case 0b01: { + assign(addr, binop(Iop_Add64, + getIReg64(rj), + mkU64(extend64(sImm << 1, 12)))); + assign(res, unop(Iop_Dup16x8, load(Ity_I16, mkexpr(addr)))); + break; + } + case 0b10: { + assign(addr, binop(Iop_Add64, + getIReg64(rj), + mkU64(extend64(sImm << 2, 12)))); + assign(res, unop(Iop_Dup32x4, load(Ity_I32, mkexpr(addr)))); + break; + } + case 0b11: { + assign(addr, binop(Iop_Add64, + getIReg64(rj), + mkU64(extend64(sImm << 3, 12)))); + assign(res, binop(Iop_64HLtoV128, + load(Ity_I64, mkexpr(addr)), + load(Ity_I64, mkexpr(addr)))); + break; + } + default: + vassert(0); + break; + } + + DIP("vldrepl.%s %s, %s, %u\n", mkInsSize(insSz), + nameVReg(vd), nameIReg(rj), sImm); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + putVReg(vd, mkexpr(res)); + + return True; +} + +static Bool gen_vst ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt vd = SLICE(insn, 4, 0); + + DIP("vst %s, %s, %d\n", nameVReg(vd), nameIReg(rj), + (Int)extend32(si12, 12)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + store(addr, getVReg(vd)); + + return True; +} + +static Bool gen_xvld ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt xd = SLICE(insn, 4, 0); + + DIP("xvld %s, %s, %d\n", nameXReg(xd), nameIReg(rj), + (Int)extend32(si12, 12)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LASX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + putXReg(xd, load(Ity_V256, addr)); + + return True; +} + +static Bool gen_xvst ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt si12 = SLICE(insn, 21, 10); + UInt rj = SLICE(insn, 9, 5); + UInt xd = SLICE(insn, 4, 0); + + DIP("xvst %s, %s, %d\n", nameXReg(xd), nameIReg(rj), + (Int)extend32(si12, 12)); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LASX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + IRExpr* addr = binop(Iop_Add64, getIReg64(rj), mkU64(extend64(si12, 12))); + store(addr, getXReg(xd)); + + return True; +} + +static Bool gen_vstelm ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + UInt vd = SLICE(insn, 4, 0); + UInt rj = SLICE(insn, 9, 5); + UInt si8 = SLICE(insn, 17, 10); + UInt insImm = SLICE(insn, 23, 18); + + IRExpr* addr; + UInt idx, insSz; + + if ((insImm & 0x30) == 0x20) { // 10_idx; b + idx = insImm & 0xf; + insSz = 0; + } else if ((insImm & 0x38) == 0x10) { // 01_idx; h + idx = insImm & 0x7; + insSz = 1; + } else if ((insImm & 0x3c) == 0x8) { // 001_idx; w + idx = insImm & 0x3; + insSz = 2; + } else if ((insImm & 0x3e) == 0x4) { // 0001_idx; d + idx = insImm & 0x1; + insSz = 3; + } else { + return False; + } + + switch (insSz) { + case 0b00: + addr = binop(Iop_Add64, + getIReg64(rj), + mkU64(extend64(si8, 8))); + break; + case 0b01: + addr = binop(Iop_Add64, + getIReg64(rj), + mkU64(extend64(si8 << 1, 9))); + break; + case 0b10: + addr = binop(Iop_Add64, + getIReg64(rj), + mkU64(extend64(si8 << 2, 10))); + break; + case 0b11: + addr = binop(Iop_Add64, + getIReg64(rj), + mkU64(extend64(si8 << 3, 11))); + break; + default: + vassert(0); + break; + } + + DIP("vstelm.%s %s, %s, %d, %u\n", mkInsSize(insSz), nameVReg(vd), nameIReg(rj), + (Int)extend32(si8, 8), idx); + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + store(addr, binop(mkVecGetElem(insSz), getVReg(vd), mkU8(idx))); + + return True; +} + + +/*------------------------------------------------------------*/ +/*--- Disassemble a single LOONGARCH64 instruction ---*/ +/*------------------------------------------------------------*/ + +/* Disassemble a single LOONGARCH64 instruction into IR. The instruction + has is located at |guest_instr| and has guest IP of |guest_PC_curr_instr|, + which will have been set before the call here. Returns True iff the + instruction was decoded, in which case *dres will be set accordingly, + or False, in which case *dres should be ignored by the caller. */ + +static Bool disInstr_LOONGARCH64_WRK_special ( DisResult* dres, + const UChar* guest_instr ) +{ + const UChar* code = guest_instr; + /* Spot the 16-byte preamble: + 00450c00 srli.d $zero, $zero, 3 + 00453400 srli.d $zero, $zero, 13 + 00457400 srli.d $zero, $zero, 29 + 00454c00 srli.d $zero, $zero, 19 + */ + if (getUInt(code + 0) == 0x00450c00 && + getUInt(code + 4) == 0x00453400 && + getUInt(code + 8) == 0x00457400 && + getUInt(code + 12) == 0x00454c00) { + /* Got a "Special" instruction preamble. Which one is it? */ + if (getUInt(code + 16) == 0x001535ad) { /* or $t1, $t1, $t1 */ + DIP("$a7 = client_request ( $t0 )\n"); + putPC(mkU64(guest_PC_curr_instr + 20)); + dres->whatNext = Dis_StopHere; + dres->len = 20; + dres->jk_StopHere = Ijk_ClientReq; + return True; + } else if (getUInt(code + 16) == 0x001539ce) { /* or $t2, $t2, $t2 */ + DIP("$a7 = guest_NRADDR\n"); + putIReg(11, IRExpr_Get(offsetof(VexGuestLOONGARCH64State, guest_NRADDR), + Ity_I64)); + dres->len = 20; + return True; + } else if (getUInt(code + 16) == 0x00153def) { /* or $t3, $t3, $t3 */ + DIP("branch-and-link-to-noredir $t8\n"); + putIReg(1, mkU64(guest_PC_curr_instr + 20)); + putPC(getIReg64(20)); + dres->whatNext = Dis_StopHere; + dres->len = 20; + dres->jk_StopHere = Ijk_NoRedir; + return True; + } else if (getUInt(code + 16) == 0x00154210) { /* or $t4, $t4, $t4 */ + DIP("IR injection\n"); + vex_inject_ir(irsb, Iend_LE); + /* Invalidate the current insn. The reason is that the IRop we're + injecting here can change. In which case the translation has to + be redone. For ease of handling, we simply invalidate all the + time. + */ + stmt(IRStmt_Put(offsetof(VexGuestLOONGARCH64State, guest_CMSTART), + mkU64(guest_PC_curr_instr))); + stmt(IRStmt_Put(offsetof(VexGuestLOONGARCH64State, guest_CMLEN), + mkU64(20))); + putPC(mkU64(guest_PC_curr_instr + 20)); + dres->whatNext = Dis_StopHere; + dres->len = 20; + dres->jk_StopHere = Ijk_InvalICache; + return True; + } + /* We don't know what it is. */ + vassert(0); + /*NOTREACHED*/ + } + return False; +} + +static Bool disInstr_LOONGARCH64_WRK_00_0000_0000 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 15)) { + case 0b0000000: + switch (SLICE(insn, 14, 10)) { + case 0b00100: + ok = gen_clo_w(dres, insn, archinfo, abiinfo); + break; + case 0b00101: + ok = gen_clz_w(dres, insn, archinfo, abiinfo); + break; + case 0b00110: + ok = gen_cto_w(dres, insn, archinfo, abiinfo); + break; + case 0b00111: + ok = gen_ctz_w(dres, insn, archinfo, abiinfo); + break; + case 0b01000: + ok = gen_clo_d(dres, insn, archinfo, abiinfo); + break; + case 0b01001: + ok = gen_clz_d(dres, insn, archinfo, abiinfo); + break; + case 0b01010: + ok = gen_cto_d(dres, insn, archinfo, abiinfo); + break; + case 0b01011: + ok = gen_ctz_d(dres, insn, archinfo, abiinfo); + break; + case 0b01100: + ok = gen_revb_2h(dres, insn, archinfo, abiinfo); + break; + case 0b01101: + ok = gen_revb_4h(dres, insn, archinfo, abiinfo); + break; + case 0b01110: + ok = gen_revb_2w(dres, insn, archinfo, abiinfo); + break; + case 0b01111: + ok = gen_revb_d(dres, insn, archinfo, abiinfo); + break; + case 0b10000: + ok = gen_revh_2w(dres, insn, archinfo, abiinfo); + break; + case 0b10001: + ok = gen_revh_d(dres, insn, archinfo, abiinfo); + break; + case 0b10010: + ok = gen_bitrev_4b(dres, insn, archinfo, abiinfo); + break; + case 0b10011: + ok = gen_bitrev_8b(dres, insn, archinfo, abiinfo); + break; + case 0b10100: + ok = gen_bitrev_w(dres, insn, archinfo, abiinfo); + break; + case 0b10101: + ok = gen_bitrev_d(dres, insn, archinfo, abiinfo); + break; + case 0b10110: + ok = gen_ext_w_h(dres, insn, archinfo, abiinfo); + break; + case 0b10111: + ok = gen_ext_w_b(dres, insn, archinfo, abiinfo); + break; + case 0b11000: + ok = gen_rdtimel_w(dres, insn, archinfo, abiinfo); + break; + case 0b11001: + ok = gen_rdtimeh_w(dres, insn, archinfo, abiinfo); + break; + case 0b11010: + ok = gen_rdtime_d(dres, insn, archinfo, abiinfo); + break; + case 0b11011: + ok = gen_cpucfg(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b0000010: + ok = gen_asrtle_d(dres, insn, archinfo, abiinfo); + break; + case 0b0000011: + ok = gen_asrtgt_d(dres, insn, archinfo, abiinfo); + break; + case 0b0100000: + ok = gen_add_w(dres, insn, archinfo, abiinfo); + break; + case 0b0100001: + ok = gen_add_d(dres, insn, archinfo, abiinfo); + break; + case 0b0100010: + ok = gen_sub_w(dres, insn, archinfo, abiinfo); + break; + case 0b0100011: + ok = gen_sub_d(dres, insn, archinfo, abiinfo); + break; + case 0b0100100: + ok = gen_slt(dres, insn, archinfo, abiinfo); + break; + case 0b0100101: + ok = gen_sltu(dres, insn, archinfo, abiinfo); + break; + case 0b0100110: + ok = gen_maskeqz(dres, insn, archinfo, abiinfo); + break; + case 0b0100111: + ok = gen_masknez(dres, insn, archinfo, abiinfo); + break; + case 0b0101000: + ok = gen_nor(dres, insn, archinfo, abiinfo); + break; + case 0b0101001: + ok = gen_and(dres, insn, archinfo, abiinfo); + break; + case 0b0101010: + ok = gen_or(dres, insn, archinfo, abiinfo); + break; + case 0b0101011: + ok = gen_xor(dres, insn, archinfo, abiinfo); + break; + case 0b0101100: + ok = gen_orn(dres, insn, archinfo, abiinfo); + break; + case 0b0101101: + ok = gen_andn(dres, insn, archinfo, abiinfo); + break; + case 0b0101110: + ok = gen_sll_w(dres, insn, archinfo, abiinfo); + break; + case 0b0101111: + ok = gen_srl_w(dres, insn, archinfo, abiinfo); + break; + case 0b0110000: + ok = gen_sra_w(dres, insn, archinfo, abiinfo); + break; + case 0b0110001: + ok = gen_sll_d(dres, insn, archinfo, abiinfo); + break; + case 0b0110010: + ok = gen_srl_d(dres, insn, archinfo, abiinfo); + break; + case 0b0110011: + ok = gen_sra_d(dres, insn, archinfo, abiinfo); + break; + case 0b0110110: + ok = gen_rotr_w(dres, insn, archinfo, abiinfo); + break; + case 0b0110111: + ok = gen_rotr_d(dres, insn, archinfo, abiinfo); + break; + case 0b0111000: + ok = gen_mul_w(dres, insn, archinfo, abiinfo); + break; + case 0b0111001: + ok = gen_mulh_w(dres, insn, archinfo, abiinfo); + break; + case 0b0111010: + ok = gen_mulh_wu(dres, insn, archinfo, abiinfo); + break; + case 0b0111011: + ok = gen_mul_d(dres, insn, archinfo, abiinfo); + break; + case 0b0111100: + ok = gen_mulh_d(dres, insn, archinfo, abiinfo); + break; + case 0b0111101: + ok = gen_mulh_du(dres, insn, archinfo, abiinfo); + break; + case 0b0111110: + ok = gen_mulw_d_w(dres, insn, archinfo, abiinfo); + break; + case 0b0111111: + ok = gen_mulw_d_wu(dres, insn, archinfo, abiinfo); + break; + case 0b1000000: + ok = gen_div_w(dres, insn, archinfo, abiinfo); + break; + case 0b1000001: + ok = gen_mod_w(dres, insn, archinfo, abiinfo); + break; + case 0b1000010: + ok = gen_div_wu(dres, insn, archinfo, abiinfo); + break; + case 0b1000011: + ok = gen_mod_wu(dres, insn, archinfo, abiinfo); + break; + case 0b1000100: + ok = gen_div_d(dres, insn, archinfo, abiinfo); + break; + case 0b1000101: + ok = gen_mod_d(dres, insn, archinfo, abiinfo); + break; + case 0b1000110: + ok = gen_div_du(dres, insn, archinfo, abiinfo); + break; + case 0b1000111: + ok = gen_mod_du(dres, insn, archinfo, abiinfo); + break; + case 0b1001000: + ok = gen_crc_w_b_w(dres, insn, archinfo, abiinfo); + break; + case 0b1001001: + ok = gen_crc_w_h_w(dres, insn, archinfo, abiinfo); + break; + case 0b1001010: + ok = gen_crc_w_w_w(dres, insn, archinfo, abiinfo); + break; + case 0b1001011: + ok = gen_crc_w_d_w(dres, insn, archinfo, abiinfo); + break; + case 0b1001100: + ok = gen_crcc_w_b_w(dres, insn, archinfo, abiinfo); + break; + case 0b1001101: + ok = gen_crcc_w_h_w(dres, insn, archinfo, abiinfo); + break; + case 0b1001110: + ok = gen_crcc_w_w_w(dres, insn, archinfo, abiinfo); + break; + case 0b1001111: + ok = gen_crcc_w_d_w(dres, insn, archinfo, abiinfo); + break; + case 0b1010100: + ok = gen_break(dres, insn, archinfo, abiinfo); + break; + case 0b1010110: + ok = gen_syscall(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + if (ok) + return ok; + + switch (SLICE(insn, 21, 18)) { + case 0b0001: + if (SLICE(insn, 17, 17) == 0) { + ok = gen_alsl_w(dres, insn, archinfo, abiinfo); + } else { + ok = gen_alsl_wu(dres, insn, archinfo, abiinfo); + } + break; + case 0b0010: + if (SLICE(insn, 17, 17) == 0) { + ok = gen_bytepick_w(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b0011: + ok = gen_bytepick_d(dres, insn, archinfo, abiinfo); + break; + case 0b1011: + if (SLICE(insn, 17, 17) == 0) { + ok = gen_alsl_d(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_00_0000_0001 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + if (SLICE(insn, 21, 21) == 0) { + switch (SLICE(insn, 20, 16)) { + case 0b00000: + if (SLICE(insn, 15, 15) == 1) { + ok = gen_slli_w(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b00001: + ok = gen_slli_d(dres, insn, archinfo, abiinfo); + break; + case 0b00100: + if (SLICE(insn, 15, 15) == 1) { + ok = gen_srli_w(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b00101: + ok = gen_srli_d(dres, insn, archinfo, abiinfo); + break; + case 0b01000: + if (SLICE(insn, 15, 15) == 1) { + ok = gen_srai_w(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b01001: + ok = gen_srai_d(dres, insn, archinfo, abiinfo); + break; + case 0b01100: + if (SLICE(insn, 15, 15) == 1) { + ok = gen_rotri_w(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b01101: + ok = gen_rotri_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + } else { + if (SLICE(insn, 15, 15) == 0) { + ok = gen_bstrins_w(dres, insn, archinfo, abiinfo); + } else { + ok = gen_bstrpick_w(dres, insn, archinfo, abiinfo); + } + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_00_0000_0100 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 15)) { + case 0b0000001: + ok = gen_fadd_s(dres, insn, archinfo, abiinfo); + break; + case 0b0000010: + ok = gen_fadd_d(dres, insn, archinfo, abiinfo); + break; + case 0b0000101: + ok = gen_fsub_s(dres, insn, archinfo, abiinfo); + break; + case 0b0000110: + ok = gen_fsub_d(dres, insn, archinfo, abiinfo); + break; + case 0b0001001: + ok = gen_fmul_s(dres, insn, archinfo, abiinfo); + break; + case 0b0001010: + ok = gen_fmul_d(dres, insn, archinfo, abiinfo); + break; + case 0b0001101: + ok = gen_fdiv_s(dres, insn, archinfo, abiinfo); + break; + case 0b0001110: + ok = gen_fdiv_d(dres, insn, archinfo, abiinfo); + break; + case 0b0010001: + ok = gen_fmax_s(dres, insn, archinfo, abiinfo); + break; + case 0b0010010: + ok = gen_fmax_d(dres, insn, archinfo, abiinfo); + break; + case 0b0010101: + ok = gen_fmin_s(dres, insn, archinfo, abiinfo); + break; + case 0b0010110: + ok = gen_fmin_d(dres, insn, archinfo, abiinfo); + break; + case 0b0011001: + ok = gen_fmaxa_s(dres, insn, archinfo, abiinfo); + break; + case 0b0011010: + ok = gen_fmaxa_d(dres, insn, archinfo, abiinfo); + break; + case 0b0011101: + ok = gen_fmina_s(dres, insn, archinfo, abiinfo); + break; + case 0b0011110: + ok = gen_fmina_d(dres, insn, archinfo, abiinfo); + break; + case 0b0100001: + ok = gen_fscaleb_s(dres, insn, archinfo, abiinfo); + break; + case 0b0100010: + ok = gen_fscaleb_d(dres, insn, archinfo, abiinfo); + break; + case 0b0100101: + ok = gen_fcopysign_s(dres, insn, archinfo, abiinfo); + break; + case 0b0100110: + ok = gen_fcopysign_d(dres, insn, archinfo, abiinfo); + break; + case 0b0101000: + switch (SLICE(insn, 14, 10)) { + case 0b00001: + ok = gen_fabs_s(dres, insn, archinfo, abiinfo); + break; + case 0b00010: + ok = gen_fabs_d(dres, insn, archinfo, abiinfo); + break; + case 0b00101: + ok = gen_fneg_s(dres, insn, archinfo, abiinfo); + break; + case 0b00110: + ok = gen_fneg_d(dres, insn, archinfo, abiinfo); + break; + case 0b01001: + ok = gen_flogb_s(dres, insn, archinfo, abiinfo); + break; + case 0b01010: + ok = gen_flogb_d(dres, insn, archinfo, abiinfo); + break; + case 0b01101: + ok = gen_fclass_s(dres, insn, archinfo, abiinfo); + break; + case 0b01110: + ok = gen_fclass_d(dres, insn, archinfo, abiinfo); + break; + case 0b10001: + ok = gen_fsqrt_s(dres, insn, archinfo, abiinfo); + break; + case 0b10010: + ok = gen_fsqrt_d(dres, insn, archinfo, abiinfo); + break; + case 0b10101: + ok = gen_frecip_s(dres, insn, archinfo, abiinfo); + break; + case 0b10110: + ok = gen_frecip_d(dres, insn, archinfo, abiinfo); + break; + case 0b11001: + ok = gen_frsqrt_s(dres, insn, archinfo, abiinfo); + break; + case 0b11010: + ok = gen_frsqrt_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b0101001: + switch (SLICE(insn, 14, 10)) { + case 0b00101: + ok = gen_fmov_s(dres, insn, archinfo, abiinfo); + break; + case 0b00110: + ok = gen_fmov_d(dres, insn, archinfo, abiinfo); + break; + case 0b01001: + ok = gen_movgr2fr_w(dres, insn, archinfo, abiinfo); + break; + case 0b01010: + ok = gen_movgr2fr_d(dres, insn, archinfo, abiinfo); + break; + case 0b01011: + ok = gen_movgr2frh_w(dres, insn, archinfo, abiinfo); + break; + case 0b01101: + ok = gen_movfr2gr_s(dres, insn, archinfo, abiinfo); + break; + case 0b01110: + ok = gen_movfr2gr_d(dres, insn, archinfo, abiinfo); + break; + case 0b01111: + ok = gen_movfrh2gr_s(dres, insn, archinfo, abiinfo); + break; + case 0b10000: + ok = gen_movgr2fcsr(dres, insn, archinfo, abiinfo); + break; + case 0b10010: + ok = gen_movfcsr2gr(dres, insn, archinfo, abiinfo); + break; + case 0b10100: + if (SLICE(insn, 4, 3) == 0b00) { + ok = gen_movfr2cf(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b10101: + if (SLICE(insn, 9, 8) == 0b00) { + ok = gen_movcf2fr(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b10110: + if (SLICE(insn, 4, 3) == 0b00) { + ok = gen_movgr2cf(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b10111: + if (SLICE(insn, 9, 8) == 0b00) { + ok = gen_movcf2gr(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + default: + ok = False; + break; + } + break; + case 0b0110010: + switch (SLICE(insn, 14, 10)) { + case 0b00110: + ok = gen_fcvt_s_d(dres, insn, archinfo, abiinfo); + break; + case 0b01001: + ok = gen_fcvt_d_s(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b0110100: + switch (SLICE(insn, 14, 10)) { + case 0b00001: + ok = gen_ftintrm_w_s(dres, insn, archinfo, abiinfo); + break; + case 0b00010: + ok = gen_ftintrm_w_d(dres, insn, archinfo, abiinfo); + break; + case 0b01001: + ok = gen_ftintrm_l_s(dres, insn, archinfo, abiinfo); + break; + case 0b01010: + ok = gen_ftintrm_l_d(dres, insn, archinfo, abiinfo); + break; + case 0b10001: + ok = gen_ftintrp_w_s(dres, insn, archinfo, abiinfo); + break; + case 0b10010: + ok = gen_ftintrp_w_d(dres, insn, archinfo, abiinfo); + break; + case 0b11001: + ok = gen_ftintrp_l_s(dres, insn, archinfo, abiinfo); + break; + case 0b11010: + ok = gen_ftintrp_l_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b0110101: + switch (SLICE(insn, 14, 10)) { + case 0b00001: + ok = gen_ftintrz_w_s(dres, insn, archinfo, abiinfo); + break; + case 0b00010: + ok = gen_ftintrz_w_d(dres, insn, archinfo, abiinfo); + break; + case 0b01001: + ok = gen_ftintrz_l_s(dres, insn, archinfo, abiinfo); + break; + case 0b01010: + ok = gen_ftintrz_l_d(dres, insn, archinfo, abiinfo); + break; + case 0b10001: + ok = gen_ftintrne_w_s(dres, insn, archinfo, abiinfo); + break; + case 0b10010: + ok = gen_ftintrne_w_d(dres, insn, archinfo, abiinfo); + break; + case 0b11001: + ok = gen_ftintrne_l_s(dres, insn, archinfo, abiinfo); + break; + case 0b11010: + ok = gen_ftintrne_l_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b0110110: + switch (SLICE(insn, 14, 10)) { + case 0b00001: + ok = gen_ftint_w_s(dres, insn, archinfo, abiinfo); + break; + case 0b00010: + ok = gen_ftint_w_d(dres, insn, archinfo, abiinfo); + break; + case 0b01001: + ok = gen_ftint_l_s(dres, insn, archinfo, abiinfo); + break; + case 0b01010: + ok = gen_ftint_l_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b0111010: + switch (SLICE(insn, 14, 10)) { + case 0b00100: + ok = gen_ffint_s_w(dres, insn, archinfo, abiinfo); + break; + case 0b00110: + ok = gen_ffint_s_l(dres, insn, archinfo, abiinfo); + break; + case 0b01000: + ok = gen_ffint_d_w(dres, insn, archinfo, abiinfo); + break; + case 0b01010: + ok = gen_ffint_d_l(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b0111100: + switch (SLICE(insn, 14, 10)) { + case 0b10001: + ok = gen_frint_s(dres, insn, archinfo, abiinfo); + break; + case 0b10010: + ok = gen_frint_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_00_0000 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 25, 22)) { + case 0b0000: + ok = disInstr_LOONGARCH64_WRK_00_0000_0000(dres, insn, archinfo, abiinfo); + break; + case 0b0001: + ok = disInstr_LOONGARCH64_WRK_00_0000_0001(dres, insn, archinfo, abiinfo); + break; + case 0b0010: + ok = gen_bstrins_d(dres, insn, archinfo, abiinfo); + break; + case 0b0011: + ok = gen_bstrpick_d(dres, insn, archinfo, abiinfo); + break; + case 0b0100: + ok = disInstr_LOONGARCH64_WRK_00_0000_0100(dres, insn, archinfo, abiinfo); + break; + case 0b1000: + ok = gen_slti(dres, insn, archinfo, abiinfo); + break; + case 0b1001: + ok = gen_sltui(dres, insn, archinfo, abiinfo); + break; + case 0b1010: + ok = gen_addi_w(dres, insn, archinfo, abiinfo); + break; + case 0b1011: + ok = gen_addi_d(dres, insn, archinfo, abiinfo); + break; + case 0b1100: + ok = gen_lu52i_d(dres, insn, archinfo, abiinfo); + break; + case 0b1101: + ok = gen_andi(dres, insn, archinfo, abiinfo); + break; + case 0b1110: + ok = gen_ori(dres, insn, archinfo, abiinfo); + break; + case 0b1111: + ok = gen_xori(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_00_1010 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 25, 22)) { + case 0b0000: + ok = gen_ld_b(dres, insn, archinfo, abiinfo); + break; + case 0b0001: + ok = gen_ld_h(dres, insn, archinfo, abiinfo); + break; + case 0b0010: + ok = gen_ld_w(dres, insn, archinfo, abiinfo); + break; + case 0b0011: + ok = gen_ld_d(dres, insn, archinfo, abiinfo); + break; + case 0b0100: + ok = gen_st_b(dres, insn, archinfo, abiinfo); + break; + case 0b0101: + ok = gen_st_h(dres, insn, archinfo, abiinfo); + break; + case 0b0110: + ok = gen_st_w(dres, insn, archinfo, abiinfo); + break; + case 0b0111: + ok = gen_st_d(dres, insn, archinfo, abiinfo); + break; + case 0b1000: + ok = gen_ld_bu(dres, insn, archinfo, abiinfo); + break; + case 0b1001: + ok = gen_ld_hu(dres, insn, archinfo, abiinfo); + break; + case 0b1010: + ok = gen_ld_wu(dres, insn, archinfo, abiinfo); + break; + case 0b1011: + ok = gen_preld(dres, insn, archinfo, abiinfo); + break; + case 0b1100: + ok = gen_fld_s(dres, insn, archinfo, abiinfo); + break; + case 0b1101: + ok = gen_fst_s(dres, insn, archinfo, abiinfo); + break; + case 0b1110: + ok = gen_fld_d(dres, insn, archinfo, abiinfo); + break; + case 0b1111: + ok = gen_fst_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_00_1011 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 23, 22)) { + case 0b00: + ok = gen_vld(dres, insn, archinfo, abiinfo); + break; + case 0b01: + ok = gen_vst(dres, insn, archinfo, abiinfo); + break; + case 0b10: + ok = gen_xvld(dres, insn, archinfo, abiinfo); + break; + case 0b11: + ok = gen_xvst(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_00_1100 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + if (!(archinfo->hwcaps & VEX_HWCAPS_LOONGARCH_LSX)) { + dres->jk_StopHere = Ijk_SigILL; + dres->whatNext = Dis_StopHere; + return True; + } + + switch (SLICE(insn, 25, 24)) { + case 0b00: + ok = gen_vldrepl(dres, insn, archinfo, abiinfo); + break; + case 0b01: + ok = gen_vstelm(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_00_1110_0000 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 15)) { + case 0b0000000: + ok = gen_ldx_b(dres, insn, archinfo, abiinfo); + break; + case 0b0001000: + ok = gen_ldx_h(dres, insn, archinfo, abiinfo); + break; + case 0b0010000: + ok = gen_ldx_w(dres, insn, archinfo, abiinfo); + break; + case 0b0011000: + ok = gen_ldx_d(dres, insn, archinfo, abiinfo); + break; + case 0b0100000: + ok = gen_stx_b(dres, insn, archinfo, abiinfo); + break; + case 0b0101000: + ok = gen_stx_h(dres, insn, archinfo, abiinfo); + break; + case 0b0110000: + ok = gen_stx_w(dres, insn, archinfo, abiinfo); + break; + case 0b0111000: + ok = gen_stx_d(dres, insn, archinfo, abiinfo); + break; + case 0b1000000: + ok = gen_ldx_bu(dres, insn, archinfo, abiinfo); + break; + case 0b1001000: + ok = gen_ldx_hu(dres, insn, archinfo, abiinfo); + break; + case 0b1010000: + ok = gen_ldx_wu(dres, insn, archinfo, abiinfo); + break; + case 0b1011000: + ok = gen_preldx(dres, insn, archinfo, abiinfo); + break; + case 0b1100000: + ok = gen_fldx_s(dres, insn, archinfo, abiinfo); + break; + case 0b1101000: + ok = gen_fldx_d(dres, insn, archinfo, abiinfo); + break; + case 0b1110000: + ok = gen_fstx_s(dres, insn, archinfo, abiinfo); + break; + case 0b1111000: + ok = gen_fstx_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_00_1110_0001 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 15)) { + case 0b1000000: + ok = gen_amswap_w(dres, insn, archinfo, abiinfo); + break; + case 0b1000001: + ok = gen_amswap_d(dres, insn, archinfo, abiinfo); + break; + case 0b1000010: + ok = gen_amadd_w(dres, insn, archinfo, abiinfo); + break; + case 0b1000011: + ok = gen_amadd_d(dres, insn, archinfo, abiinfo); + break; + case 0b1000100: + ok = gen_amand_w(dres, insn, archinfo, abiinfo); + break; + case 0b1000101: + ok = gen_amand_d(dres, insn, archinfo, abiinfo); + break; + case 0b1000110: + ok = gen_amor_w(dres, insn, archinfo, abiinfo); + break; + case 0b1000111: + ok = gen_amor_d(dres, insn, archinfo, abiinfo); + break; + case 0b1001000: + ok = gen_amxor_w(dres, insn, archinfo, abiinfo); + break; + case 0b1001001: + ok = gen_amxor_d(dres, insn, archinfo, abiinfo); + break; + case 0b1001010: + ok = gen_ammax_w(dres, insn, archinfo, abiinfo); + break; + case 0b1001011: + ok = gen_ammax_d(dres, insn, archinfo, abiinfo); + break; + case 0b1001100: + ok = gen_ammin_w(dres, insn, archinfo, abiinfo); + break; + case 0b1001101: + ok = gen_ammin_d(dres, insn, archinfo, abiinfo); + break; + case 0b1001110: + ok = gen_ammax_wu(dres, insn, archinfo, abiinfo); + break; + case 0b1001111: + ok = gen_ammax_du(dres, insn, archinfo, abiinfo); + break; + case 0b1010000: + ok = gen_ammin_wu(dres, insn, archinfo, abiinfo); + break; + case 0b1010001: + ok = gen_ammin_du(dres, insn, archinfo, abiinfo); + break; + case 0b1010010: + ok = gen_amswap_db_w(dres, insn, archinfo, abiinfo); + break; + case 0b1010011: + ok = gen_amswap_db_d(dres, insn, archinfo, abiinfo); + break; + case 0b1010100: + ok = gen_amadd_db_w(dres, insn, archinfo, abiinfo); + break; + case 0b1010101: + ok = gen_amadd_db_d(dres, insn, archinfo, abiinfo); + break; + case 0b1010110: + ok = gen_amand_db_w(dres, insn, archinfo, abiinfo); + break; + case 0b1010111: + ok = gen_amand_db_d(dres, insn, archinfo, abiinfo); + break; + case 0b1011000: + ok = gen_amor_db_w(dres, insn, archinfo, abiinfo); + break; + case 0b1011001: + ok = gen_amor_db_d(dres, insn, archinfo, abiinfo); + break; + case 0b1011010: + ok = gen_amxor_db_w(dres, insn, archinfo, abiinfo); + break; + case 0b1011011: + ok = gen_amxor_db_d(dres, insn, archinfo, abiinfo); + break; + case 0b1011100: + ok = gen_ammax_db_w(dres, insn, archinfo, abiinfo); + break; + case 0b1011101: + ok = gen_ammax_db_d(dres, insn, archinfo, abiinfo); + break; + case 0b1011110: + ok = gen_ammin_db_w(dres, insn, archinfo, abiinfo); + break; + case 0b1011111: + ok = gen_ammin_db_d(dres, insn, archinfo, abiinfo); + break; + case 0b1100000: + ok = gen_ammax_db_wu(dres, insn, archinfo, abiinfo); + break; + case 0b1100001: + ok = gen_ammax_db_du(dres, insn, archinfo, abiinfo); + break; + case 0b1100010: + ok = gen_ammin_db_wu(dres, insn, archinfo, abiinfo); + break; + case 0b1100011: + ok = gen_ammin_db_du(dres, insn, archinfo, abiinfo); + break; + case 0b1100100: + ok = gen_dbar(dres, insn, archinfo, abiinfo); + break; + case 0b1100101: + ok = gen_ibar(dres, insn, archinfo, abiinfo); + break; + case 0b1101000: + ok = gen_fldgt_s(dres, insn, archinfo, abiinfo); + break; + case 0b1101001: + ok = gen_fldgt_d(dres, insn, archinfo, abiinfo); + break; + case 0b1101010: + ok = gen_fldle_s(dres, insn, archinfo, abiinfo); + break; + case 0b1101011: + ok = gen_fldle_d(dres, insn, archinfo, abiinfo); + break; + case 0b1101100: + ok = gen_fstgt_s(dres, insn, archinfo, abiinfo); + break; + case 0b1101101: + ok = gen_fstgt_d(dres, insn, archinfo, abiinfo); + break; + case 0b1101110: + ok = gen_fstle_s(dres, insn, archinfo, abiinfo); + break; + case 0b1101111: + ok = gen_fstle_d(dres, insn, archinfo, abiinfo); + break; + case 0b1110000: + ok = gen_ldgt_b(dres, insn, archinfo, abiinfo); + break; + case 0b1110001: + ok = gen_ldgt_h(dres, insn, archinfo, abiinfo); + break; + case 0b1110010: + ok = gen_ldgt_w(dres, insn, archinfo, abiinfo); + break; + case 0b1110011: + ok = gen_ldgt_d(dres, insn, archinfo, abiinfo); + break; + case 0b1110100: + ok = gen_ldle_b(dres, insn, archinfo, abiinfo); + break; + case 0b1110101: + ok = gen_ldle_h(dres, insn, archinfo, abiinfo); + break; + case 0b1110110: + ok = gen_ldle_w(dres, insn, archinfo, abiinfo); + break; + case 0b1110111: + ok = gen_ldle_d(dres, insn, archinfo, abiinfo); + break; + case 0b1111000: + ok = gen_stgt_b(dres, insn, archinfo, abiinfo); + break; + case 0b1111001: + ok = gen_stgt_h(dres, insn, archinfo, abiinfo); + break; + case 0b1111010: + ok = gen_stgt_w(dres, insn, archinfo, abiinfo); + break; + case 0b1111011: + ok = gen_stgt_d(dres, insn, archinfo, abiinfo); + break; + case 0b1111100: + ok = gen_stle_b(dres, insn, archinfo, abiinfo); + break; + case 0b1111101: + ok = gen_stle_h(dres, insn, archinfo, abiinfo); + break; + case 0b1111110: + ok = gen_stle_w(dres, insn, archinfo, abiinfo); + break; + case 0b1111111: + ok = gen_stle_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_FCMP_S ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 19, 15)) { + case 0x0: + ok = gen_fcmp_caf_s(dres, insn, archinfo, abiinfo); + break; + case 0x1: + ok = gen_fcmp_saf_s(dres, insn, archinfo, abiinfo); + break; + case 0x2: + ok = gen_fcmp_clt_s(dres, insn, archinfo, abiinfo); + break; + case 0x3: + ok = gen_fcmp_slt_s(dres, insn, archinfo, abiinfo); + break; + case 0x4: + ok = gen_fcmp_ceq_s(dres, insn, archinfo, abiinfo); + break; + case 0x5: + ok = gen_fcmp_seq_s(dres, insn, archinfo, abiinfo); + break; + case 0x6: + ok = gen_fcmp_cle_s(dres, insn, archinfo, abiinfo); + break; + case 0x7: + ok = gen_fcmp_sle_s(dres, insn, archinfo, abiinfo); + break; + case 0x8: + ok = gen_fcmp_cun_s(dres, insn, archinfo, abiinfo); + break; + case 0x9: + ok = gen_fcmp_sun_s(dres, insn, archinfo, abiinfo); + break; + case 0xa: + ok = gen_fcmp_cult_s(dres, insn, archinfo, abiinfo); + break; + case 0xb: + ok = gen_fcmp_sult_s(dres, insn, archinfo, abiinfo); + break; + case 0xc: + ok = gen_fcmp_cueq_s(dres, insn, archinfo, abiinfo); + break; + case 0xd: + ok = gen_fcmp_sueq_s(dres, insn, archinfo, abiinfo); + break; + case 0xe: + ok = gen_fcmp_cule_s(dres, insn, archinfo, abiinfo); + break; + case 0xf: + ok = gen_fcmp_sule_s(dres, insn, archinfo, abiinfo); + break; + case 0x10: + ok = gen_fcmp_cne_s(dres, insn, archinfo, abiinfo); + break; + case 0x11: + ok = gen_fcmp_sne_s(dres, insn, archinfo, abiinfo); + break; + case 0x14: + ok = gen_fcmp_cor_s(dres, insn, archinfo, abiinfo); + break; + case 0x15: + ok = gen_fcmp_sor_s(dres, insn, archinfo, abiinfo); + break; + case 0x18: + ok = gen_fcmp_cune_s(dres, insn, archinfo, abiinfo); + break; + case 0x19: + ok = gen_fcmp_sune_s(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_FCMP_D ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 19, 15)) { + case 0x0: + ok = gen_fcmp_caf_d(dres, insn, archinfo, abiinfo); + break; + case 0x1: + ok = gen_fcmp_saf_d(dres, insn, archinfo, abiinfo); + break; + case 0x2: + ok = gen_fcmp_clt_d(dres, insn, archinfo, abiinfo); + break; + case 0x3: + ok = gen_fcmp_slt_d(dres, insn, archinfo, abiinfo); + break; + case 0x4: + ok = gen_fcmp_ceq_d(dres, insn, archinfo, abiinfo); + break; + case 0x5: + ok = gen_fcmp_seq_d(dres, insn, archinfo, abiinfo); + break; + case 0x6: + ok = gen_fcmp_cle_d(dres, insn, archinfo, abiinfo); + break; + case 0x7: + ok = gen_fcmp_sle_d(dres, insn, archinfo, abiinfo); + break; + case 0x8: + ok = gen_fcmp_cun_d(dres, insn, archinfo, abiinfo); + break; + case 0x9: + ok = gen_fcmp_sun_d(dres, insn, archinfo, abiinfo); + break; + case 0xa: + ok = gen_fcmp_cult_d(dres, insn, archinfo, abiinfo); + break; + case 0xb: + ok = gen_fcmp_sult_d(dres, insn, archinfo, abiinfo); + break; + case 0xc: + ok = gen_fcmp_cueq_d(dres, insn, archinfo, abiinfo); + break; + case 0xd: + ok = gen_fcmp_sueq_d(dres, insn, archinfo, abiinfo); + break; + case 0xe: + ok = gen_fcmp_cule_d(dres, insn, archinfo, abiinfo); + break; + case 0xf: + ok = gen_fcmp_sule_d(dres, insn, archinfo, abiinfo); + break; + case 0x10: + ok = gen_fcmp_cne_d(dres, insn, archinfo, abiinfo); + break; + case 0x11: + ok = gen_fcmp_sne_d(dres, insn, archinfo, abiinfo); + break; + case 0x14: + ok = gen_fcmp_cor_d(dres, insn, archinfo, abiinfo); + break; + case 0x15: + ok = gen_fcmp_sor_d(dres, insn, archinfo, abiinfo); + break; + case 0x18: + ok = gen_fcmp_cune_d(dres, insn, archinfo, abiinfo); + break; + case 0x19: + ok = gen_fcmp_sune_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_00 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 29, 26)) { + case 0b0000: + ok = disInstr_LOONGARCH64_WRK_00_0000(dres, insn, archinfo, abiinfo); + break; + case 0b0010: + switch (SLICE(insn, 25, 20)) { + case 0b000001: + ok = gen_fmadd_s(dres, insn, archinfo, abiinfo); + break; + case 0b000010: + ok = gen_fmadd_d(dres, insn, archinfo, abiinfo); + break; + case 0b000101: + ok = gen_fmsub_s(dres, insn, archinfo, abiinfo); + break; + case 0b000110: + ok = gen_fmsub_d(dres, insn, archinfo, abiinfo); + break; + case 0b001001: + ok = gen_fnmadd_s(dres, insn, archinfo, abiinfo); + break; + case 0b001010: + ok = gen_fnmadd_d(dres, insn, archinfo, abiinfo); + break; + case 0b001101: + ok = gen_fnmsub_s(dres, insn, archinfo, abiinfo); + break; + case 0b001110: + ok = gen_fnmsub_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b0011: + switch (SLICE(insn, 25, 20)) { + case 0b000001: + if (SLICE(insn, 4, 3) == 0b00) { + ok = disInstr_LOONGARCH64_WRK_FCMP_S(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b000010: + if (SLICE(insn, 4, 3) == 0b00) { + ok = disInstr_LOONGARCH64_WRK_FCMP_D(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b010000: + if (SLICE(insn, 19, 18) == 0b00) { + ok = gen_fsel(dres, insn, archinfo, abiinfo); + } else { + ok = False; + } + break; + case 0b010101: + ok = gen_vshuf_b(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b0100: + ok = gen_addu16i_d(dres, insn, archinfo, abiinfo); + break; + case 0b0101: + if (SLICE(insn, 25, 25) == 0) { + ok = gen_lu12i_w(dres, insn, archinfo, abiinfo); + } else { + ok = gen_lu32i_d(dres, insn, archinfo, abiinfo); + } + break; + case 0b0110: + if (SLICE(insn, 25, 25) == 0) { + ok = gen_pcaddi(dres, insn, archinfo, abiinfo); + } else { + ok = gen_pcalau12i(dres, insn, archinfo, abiinfo); + } + break; + case 0b0111: + if (SLICE(insn, 25, 25) == 0) { + ok = gen_pcaddu12i(dres, insn, archinfo, abiinfo); + } else { + ok = gen_pcaddu18i(dres, insn, archinfo, abiinfo); + } + break; + case 0b1000: + switch (SLICE(insn, 25, 24)) { + case 0b00: + ok = gen_ll_w(dres, insn, archinfo, abiinfo); + break; + case 0b01: + ok = gen_sc_w(dres, insn, archinfo, abiinfo); + break; + case 0b10: + ok = gen_ll_d(dres, insn, archinfo, abiinfo); + break; + case 0b11: + ok = gen_sc_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b1001: + switch (SLICE(insn, 25, 24)) { + case 0b00: + ok = gen_ldptr_w(dres, insn, archinfo, abiinfo); + break; + case 0b01: + ok = gen_stptr_w(dres, insn, archinfo, abiinfo); + break; + case 0b10: + ok = gen_ldptr_d(dres, insn, archinfo, abiinfo); + break; + case 0b11: + ok = gen_stptr_d(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b1010: + ok = disInstr_LOONGARCH64_WRK_00_1010(dres, insn, archinfo, abiinfo); + break; + case 0b1011: + ok = disInstr_LOONGARCH64_WRK_00_1011(dres, insn, archinfo, abiinfo); + break; + case 0b1100: + ok = disInstr_LOONGARCH64_WRK_00_1100(dres, insn, archinfo, abiinfo); + break; + case 0b1110: + switch (SLICE(insn, 25, 22)) { + case 0b0000: + ok = disInstr_LOONGARCH64_WRK_00_1110_0000(dres, insn, archinfo, abiinfo); + break; + case 0b0001: + ok = disInstr_LOONGARCH64_WRK_00_1110_0001(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1100_0000 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 17)) { + case 0b00000: + case 0b00001: + case 0b00010: + case 0b00011: + case 0b00100: + ok = gen_vcmp_integer(dres, insn, archinfo, abiinfo); + break; + case 0b00101: + case 0b00110: + ok = gen_vadd_vsub(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1100_0001 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 18)) { + case 0b1100: + case 0b1101: + ok = gen_vmax_vmin(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1100_0100 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 17)) { + case 0b01011: + case 0b01100: + case 0b01101: + case 0b01110: + case 0b01111: + case 0b10000: + ok = gen_evod(dres, insn, archinfo, abiinfo); + break; + case 0b10001: + ok = gen_vreplve(dres, insn, archinfo, abiinfo); + break; + case 0b10011: + case 0b10100: + ok = gen_logical_v(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1100_1010_01110 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 16, 14)) { + case 0b001: + ok = gen_vmsk(dres, insn, archinfo, abiinfo); + break; + case 0b010: + ok = gen_vset(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + + +static Bool disInstr_LOONGARCH64_WRK_01_1100_1010_01111 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 16, 14)) { + case 0b100: + ok = gen_vreplgr2vr(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1100_1010 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 17)) { + case 0b00000: + case 0b00001: + case 0b00010: + case 0b00011: + case 0b00100: + ok = gen_vcmpi_integer(dres, insn, archinfo, abiinfo); + break; + case 0b00101: + case 0b00110: + ok = gen_vaddi_vsubi(dres, insn, archinfo, abiinfo); + break; + case 0b01101: + ok = gen_vfrstpi(dres, insn, archinfo, abiinfo); + break; + case 0b01110: + ok = disInstr_LOONGARCH64_WRK_01_1100_1010_01110(dres, insn, archinfo, abiinfo); + break; + case 0b01111: + ok = disInstr_LOONGARCH64_WRK_01_1100_1010_01111(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1100_1011 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 16)) { + case 0b101111: + case 0b110011: + ok = gen_vpickve2gr(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1100_1100 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 18)) { + case 0b0100: + case 0b0101: + case 0b0110: + ok = gen_vbiti(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1100_1111 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 18)) { + case 0b0100: + case 0b0101: + case 0b0110: + case 0b0111: + ok = gen_vlogical_u8(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1100 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 25, 22)) { + case 0b0000: + ok = disInstr_LOONGARCH64_WRK_01_1100_0000(dres, insn, archinfo, abiinfo); + break; + case 0b0001: + ok = disInstr_LOONGARCH64_WRK_01_1100_0001(dres, insn, archinfo, abiinfo); + break; + case 0b0100: + ok = disInstr_LOONGARCH64_WRK_01_1100_0100(dres, insn, archinfo, abiinfo); + break; + case 0b1010: + ok = disInstr_LOONGARCH64_WRK_01_1100_1010(dres, insn, archinfo, abiinfo); + break; + case 0b1011: + ok = disInstr_LOONGARCH64_WRK_01_1100_1011(dres, insn, archinfo, abiinfo); + break; + case 0b1100: + ok = disInstr_LOONGARCH64_WRK_01_1100_1100(dres, insn, archinfo, abiinfo); + break; + case 0b1111: + ok = disInstr_LOONGARCH64_WRK_01_1100_1111(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1101_0000 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 18)) { + case 0b0000: + ok = gen_xvcmp_integer(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1101_0001 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 18)) { + case 0b1101: + ok = gen_xvmax_xvmin(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1101_0100 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 18)) { + case 0b1001: + ok = gen_logical_xv(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1101_1010_0111 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 17, 14)) { + case 0b0001: + ok = gen_xvmsk(dres, insn, archinfo, abiinfo); + break; + case 0b0010: + ok = gen_xvset(dres, insn, archinfo, abiinfo); + break; + case 0b1100: + ok = gen_xvreplgr2vr(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1101_1010 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 18)) { + case 0b0111: + ok = disInstr_LOONGARCH64_WRK_01_1101_1010_0111(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1101_1100 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 18)) { + case 0b0000: + ok = gen_xvpickve(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1101_1111 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 21, 18)) { + case 0b1001: + case 0b1010: + case 0b1011: + ok = gen_xvpermi(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01_1101 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 25, 22)) { + case 0b0000: + ok = disInstr_LOONGARCH64_WRK_01_1101_0000(dres, insn, archinfo, abiinfo); + break; + case 0b0001: + ok = disInstr_LOONGARCH64_WRK_01_1101_0001(dres, insn, archinfo, abiinfo); + break; + case 0b0100: + ok = disInstr_LOONGARCH64_WRK_01_1101_0100(dres, insn, archinfo, abiinfo); + break; + case 0b1010: + ok = disInstr_LOONGARCH64_WRK_01_1101_1010(dres, insn, archinfo, abiinfo); + break; + case 0b1100: + ok = disInstr_LOONGARCH64_WRK_01_1101_1100(dres, insn, archinfo, abiinfo); + break; + case 0b1111: + ok = disInstr_LOONGARCH64_WRK_01_1101_1111(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK_01 ( DisResult* dres, UInt insn, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo ) +{ + Bool ok; + + switch (SLICE(insn, 29, 26)) { + case 0b0000: + ok = gen_beqz(dres, insn, archinfo, abiinfo); + break; + case 0b0001: + ok = gen_bnez(dres, insn, archinfo, abiinfo); + break; + case 0b0010: + switch (SLICE(insn, 9, 8)) { + case 0b00: + ok = gen_bceqz(dres, insn, archinfo, abiinfo); + break; + case 0b01: + ok = gen_bcnez(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + break; + case 0b0011: + ok = gen_jirl(dres, insn, archinfo, abiinfo); + break; + case 0b0100: + ok = gen_b(dres, insn, archinfo, abiinfo); + break; + case 0b0101: + ok = gen_bl(dres, insn, archinfo, abiinfo); + break; + case 0b0110: + ok = gen_beq(dres, insn, archinfo, abiinfo); + break; + case 0b0111: + ok = gen_bne(dres, insn, archinfo, abiinfo); + break; + case 0b1000: + ok = gen_blt(dres, insn, archinfo, abiinfo); + break; + case 0b1001: + ok = gen_bge(dres, insn, archinfo, abiinfo); + break; + case 0b1010: + ok = gen_bltu(dres, insn, archinfo, abiinfo); + break; + case 0b1011: + ok = gen_bgeu(dres, insn, archinfo, abiinfo); + break; + case 0b1100: + ok = disInstr_LOONGARCH64_WRK_01_1100(dres, insn, archinfo, abiinfo); + break; + case 0b1101: + ok = disInstr_LOONGARCH64_WRK_01_1101(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + return ok; +} + +static Bool disInstr_LOONGARCH64_WRK ( /*MB_OUT*/DisResult* dres, + const UChar* guest_instr, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo, + Bool sigill_diag ) +{ + /* Set result defaults. */ + dres->whatNext = Dis_Continue; + dres->len = 4; + dres->jk_StopHere = Ijk_INVALID; + dres->hint = Dis_HintNone; + + /* At least this is simple on LOONGARCH64: insns are all 4 bytes long, + and 4-aligned. So just fish the whole thing out of memory right now + and have done. */ + UInt insn = getUInt(guest_instr); + DIP("\t0x%llx:\t0x%08x\t", (Addr64)guest_PC_curr_instr, insn); + vassert((guest_PC_curr_instr & 3ULL) == 0); + + /* Spot "Special" instructions (see comment at top of file). */ + Bool ok = disInstr_LOONGARCH64_WRK_special(dres, guest_instr); + if (ok) + return ok; + + /* Main LOONGARCH64 instruction decoder starts here. */ + switch (SLICE(insn, 31, 30)) { + case 0b00: + ok = disInstr_LOONGARCH64_WRK_00(dres, insn, archinfo, abiinfo); + break; + case 0b01: + ok = disInstr_LOONGARCH64_WRK_01(dres, insn, archinfo, abiinfo); + break; + default: + ok = False; + break; + } + + /* If the next-level down decoders failed, make sure |dres| didn't + get changed. */ + if (!ok) { + vassert(dres->whatNext == Dis_Continue); + vassert(dres->len == 4); + vassert(dres->jk_StopHere == Ijk_INVALID); + } + return ok; +} + + +/*------------------------------------------------------------*/ +/*--- Top-level fn ---*/ +/*------------------------------------------------------------*/ + +/* Disassemble a single instruction into IR. The instruction + is located in host memory at &guest_code[delta]. */ + +DisResult disInstr_LOONGARCH64 ( IRSB* irsb_IN, + const UChar* guest_code_IN, + Long delta_IN, + Addr guest_IP, + VexArch guest_arch, + const VexArchInfo* archinfo, + const VexAbiInfo* abiinfo, + VexEndness host_endness_IN, + Bool sigill_diag_IN ) +{ + DisResult dres; + vex_bzero(&dres, sizeof(dres)); + + /* Set globals (see top of this file) */ + vassert(guest_arch == VexArchLOONGARCH64); + + irsb = irsb_IN; + host_endness = host_endness_IN; + guest_PC_curr_instr = (Addr64)guest_IP; + + /* Try to decode */ + Bool ok = disInstr_LOONGARCH64_WRK(&dres, + &guest_code_IN[delta_IN], + archinfo, abiinfo, sigill_diag_IN); + + if (ok) { + /* All decode successes end up here. */ + vassert(dres.len == 4 || dres.len == 20); + switch (dres.whatNext) { + case Dis_Continue: + putPC(mkU64(dres.len + guest_PC_curr_instr)); + break; + case Dis_StopHere: + break; + default: + vassert(0); + break; + } + DIP("\n"); + } else { + /* All decode failures end up here. */ + if (sigill_diag_IN) { + Int i, j; + UChar buf[64]; + UInt insn = getUInt(&guest_code_IN[delta_IN]); + vex_bzero(buf, sizeof(buf)); + for (i = j = 0; i < 32; i++) { + if (i > 0 && (i & 3) == 0) + buf[j++] = ' '; + buf[j++] = (insn & (1 << (31 - i))) ? '1' : '0'; + } + vex_printf("disInstr(loongarch64): unhandled instruction 0x%08x\n", insn); + vex_printf("disInstr(loongarch64): %s\n", buf); + } + + /* Tell the dispatcher that this insn cannot be decoded, and so + has not been executed, and (is currently) the next to be + executed. PC should be up-to-date since it is made so at the + start of each insn, but nevertheless be paranoid and update + it again right now. */ + putPC(mkU64(guest_PC_curr_instr)); + dres.len = 0; + dres.whatNext = Dis_StopHere; + dres.jk_StopHere = Ijk_NoDecode; + } + + return dres; +} + + +/*--------------------------------------------------------------------*/ +/*--- end guest_loongarch64_toIR.c ---*/ +/*--------------------------------------------------------------------*/ diff --git a/VEX/priv/host_loongarch64_defs.c b/VEX/priv/host_loongarch64_defs.c new file mode 100644 index 0000000..6b50970 --- /dev/null +++ b/VEX/priv/host_loongarch64_defs.c @@ -0,0 +1,3929 @@ + +/*---------------------------------------------------------------*/ +/*--- begin host_loongarch64_defs.c ---*/ +/*---------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#include "libvex_basictypes.h" +#include "libvex.h" +#include "libvex_trc_values.h" + +#include "main_util.h" +#include "host_generic_regs.h" +#include "host_loongarch64_defs.h" + + +/* --------- Local helpers. --------- */ + +static inline void mapReg ( HRegRemap* m, HReg* r ) +{ + *r = lookupHRegRemap(m, *r); +} + +static inline Int extend ( UInt imm, UInt size ) +{ + UInt shift = 32 - size; + return (((Int)imm << shift) >> shift); +} + + +/* --------- Registers. --------- */ + +const RRegUniverse* getRRegUniverse_LOONGARCH64 ( void ) +{ + /* The real-register universe is a big constant, so we just want to + initialise it once. */ + static RRegUniverse rRegUniverse_LOONGARCH64; + static Bool rRegUniverse_LOONGARCH64_initted = False; + + /* Handy shorthand, nothing more */ + RRegUniverse* ru = &rRegUniverse_LOONGARCH64; + + /* This isn't thread-safe. Sigh. */ + if (LIKELY(rRegUniverse_LOONGARCH64_initted == True)) + return ru; + + RRegUniverse__init(ru); + + /* Add the registers. The initial segment of this array must be + those available for allocation by reg-alloc, and those that + follow are not available for allocation. */ + ru->allocable_start[HRcInt64] = ru->size; + ru->regs[ru->size++] = hregLOONGARCH64_R23(); + ru->regs[ru->size++] = hregLOONGARCH64_R24(); + ru->regs[ru->size++] = hregLOONGARCH64_R25(); + ru->regs[ru->size++] = hregLOONGARCH64_R26(); + ru->regs[ru->size++] = hregLOONGARCH64_R27(); + ru->regs[ru->size++] = hregLOONGARCH64_R28(); + ru->regs[ru->size++] = hregLOONGARCH64_R29(); + ru->regs[ru->size++] = hregLOONGARCH64_R30(); + // $r31 is used as guest stack pointer, not available to regalloc. + + // $r12 is used as a chaining/ProfInc/Cmove/genSpill/genReload temporary + // $r13 is used as a ProfInc temporary + ru->regs[ru->size++] = hregLOONGARCH64_R14(); + ru->regs[ru->size++] = hregLOONGARCH64_R15(); + ru->regs[ru->size++] = hregLOONGARCH64_R16(); + ru->regs[ru->size++] = hregLOONGARCH64_R17(); + ru->regs[ru->size++] = hregLOONGARCH64_R18(); + ru->regs[ru->size++] = hregLOONGARCH64_R19(); + ru->regs[ru->size++] = hregLOONGARCH64_R20(); + ru->allocable_end[HRcInt64] = ru->size - 1; + + ru->allocable_start[HRcFlt64] = ru->size; + ru->regs[ru->size++] = hregLOONGARCH64_F24(); + ru->regs[ru->size++] = hregLOONGARCH64_F25(); + ru->regs[ru->size++] = hregLOONGARCH64_F26(); + ru->regs[ru->size++] = hregLOONGARCH64_F27(); + ru->regs[ru->size++] = hregLOONGARCH64_F28(); + ru->regs[ru->size++] = hregLOONGARCH64_F29(); + ru->regs[ru->size++] = hregLOONGARCH64_F30(); + ru->regs[ru->size++] = hregLOONGARCH64_F31(); + ru->allocable_end[HRcFlt64] = ru->size - 1; + + ru->allocable_start[HRcVec128] = ru->size; + ru->regs[ru->size++] = hregLOONGARCH64_V24(); + ru->regs[ru->size++] = hregLOONGARCH64_V25(); + ru->regs[ru->size++] = hregLOONGARCH64_V26(); + ru->regs[ru->size++] = hregLOONGARCH64_V27(); + ru->regs[ru->size++] = hregLOONGARCH64_V28(); + ru->regs[ru->size++] = hregLOONGARCH64_V29(); + ru->regs[ru->size++] = hregLOONGARCH64_V30(); + ru->regs[ru->size++] = hregLOONGARCH64_V31(); + ru->allocable_end[HRcVec128] = ru->size - 1; + + ru->allocable = ru->size; + + /* And other regs, not available to the allocator. */ + ru->regs[ru->size++] = hregLOONGARCH64_R0(); + ru->regs[ru->size++] = hregLOONGARCH64_R1(); + ru->regs[ru->size++] = hregLOONGARCH64_R2(); + ru->regs[ru->size++] = hregLOONGARCH64_R3(); + ru->regs[ru->size++] = hregLOONGARCH64_R4(); + ru->regs[ru->size++] = hregLOONGARCH64_R5(); + ru->regs[ru->size++] = hregLOONGARCH64_R6(); + ru->regs[ru->size++] = hregLOONGARCH64_R7(); + ru->regs[ru->size++] = hregLOONGARCH64_R8(); + ru->regs[ru->size++] = hregLOONGARCH64_R9(); + ru->regs[ru->size++] = hregLOONGARCH64_R10(); + ru->regs[ru->size++] = hregLOONGARCH64_R11(); + ru->regs[ru->size++] = hregLOONGARCH64_R12(); + ru->regs[ru->size++] = hregLOONGARCH64_R13(); + ru->regs[ru->size++] = hregLOONGARCH64_R21(); + ru->regs[ru->size++] = hregLOONGARCH64_R22(); + ru->regs[ru->size++] = hregLOONGARCH64_R31(); + ru->regs[ru->size++] = hregLOONGARCH64_FCSR3(); + + rRegUniverse_LOONGARCH64_initted = True; + + RRegUniverse__check_is_sane(ru); + return ru; +} + +UInt ppHRegLOONGARCH64 ( HReg reg ) +{ + Int r; + Int ret = 0; + static const HChar* ireg_names[32] = { + "$zero", + "$ra", + "$tp", + "$sp", + "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", + "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8", + "$r21", /* Reserved */ + "$fp", + "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", "$s8" + }; + static const HChar* freg_names[32] = { + "$fa0", "$fa1", "$fa2", "$fa3", "$fa4", "$fa5", "$fa6", "$fa7", + "$ft0", "$ft1", "$ft2", "$ft3", "$ft4", "$ft5", "$ft6", "$ft7", + "$ft8", "$ft9", "$ft10", "$ft11", "$ft12", "$ft13", "$ft14", "$ft15", + "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", "$fs6", "$fs7" + }; + static const HChar* vreg_names[32] = { + "$vr0", "$vr1", "$vr2", "$vr3", "$vr4", "$vr5", "$vr6", "$vr7", + "$vr8", "$vr9", "$vr10", "$vr11", "$vr12", "$vr13", "$vr14", "$vr15", + "$vr16", "$vr17", "$vr18", "$vr19", "$vr20", "$vr21", "$vr22", "$vr23", + "$vr24", "$vr25", "$vr26", "$vr27", "$vr28", "$vr29", "$vr30", "$vr31" + }; + + /* Be generic for all virtual regs. */ + if (hregIsVirtual(reg)) { + return ppHReg(reg); + } + + /* But specific for real regs. */ + switch (hregClass(reg)) { + case HRcInt32: + r = hregEncoding(reg); + vassert(r < 4); + ret = vex_printf("$fcsr%d", r); + break; + case HRcInt64: + r = hregEncoding(reg); + vassert(r < 32); + ret = vex_printf("%s", ireg_names[r]); + break; + case HRcFlt64: + r = hregEncoding(reg); + vassert(r < 32); + ret = vex_printf("%s", freg_names[r]); + break; + case HRcVec128: + r = hregEncoding(reg); + vassert(r < 32); + ret = vex_printf("%s", vreg_names[r]); + break; + default: + vpanic("ppHRegLOONGARCH64"); + break; + } + + return ret; +} + + +/* --------- Condition codes, LOONGARCH64 encoding. --------- */ + +static inline const HChar* showLOONGARCH64CondCode ( LOONGARCH64CondCode cond ) +{ + const HChar* ret; + switch (cond) { + case LAcc_EQ: + ret = "eq"; /* equal */ + break; + case LAcc_NE: + ret = "ne"; /* not equal */ + break; + case LAcc_LT: + ret = "lt"; /* less than (signed) */ + break; + case LAcc_GE: + ret = "ge"; /* great equal (signed) */ + break; + case LAcc_LTU: + ret = "ltu"; /* less than (unsigned) */ + break; + case LAcc_GEU: + ret = "geu"; /* great equal (unsigned) */ + break; + case LAcc_AL: + ret = "al"; /* always (unconditional) */ + break; + default: + vpanic("showLOONGARCH64CondCode"); + break; + } + return ret; +} + + +/* --------- Memory address expressions (amodes). --------- */ + +LOONGARCH64AMode* LOONGARCH64AMode_RI ( HReg reg, UShort imm ) +{ + LOONGARCH64AMode* am = LibVEX_Alloc_inline(sizeof(LOONGARCH64AMode)); + am->tag = LAam_RI; + am->LAam.RI.base = reg; + am->LAam.RI.index = imm; + return am; +} + +LOONGARCH64AMode* LOONGARCH64AMode_RR ( HReg base, HReg index ) +{ + LOONGARCH64AMode* am = LibVEX_Alloc_inline(sizeof(LOONGARCH64AMode)); + am->tag = LAam_RR; + am->LAam.RR.base = base; + am->LAam.RR.index = index; + return am; +} + +static inline void ppLOONGARCH64AMode ( LOONGARCH64AMode* am ) +{ + switch (am->tag) { + case LAam_RI: + ppHRegLOONGARCH64(am->LAam.RI.base); + vex_printf(", "); + vex_printf("%d", extend((UInt)am->LAam.RI.index, 12)); + break; + case LAam_RR: + ppHRegLOONGARCH64(am->LAam.RR.base); + vex_printf(", "); + ppHRegLOONGARCH64(am->LAam.RR.index); + break; + default: + vpanic("ppLOONGARCH64AMode"); + break; + } +} + +static inline void addRegUsage_LOONGARCH64AMode( HRegUsage* u, + LOONGARCH64AMode* am ) +{ + switch (am->tag) { + case LAam_RI: + addHRegUse(u, HRmRead, am->LAam.RI.base); + break; + case LAam_RR: + addHRegUse(u, HRmRead, am->LAam.RR.base); + addHRegUse(u, HRmRead, am->LAam.RR.index); + break; + default: + vpanic("addRegUsage_LOONGARCH64AMode"); + break; + } +} + +static inline void mapRegs_LOONGARCH64AMode( HRegRemap* m, + LOONGARCH64AMode* am ) +{ + switch (am->tag) { + case LAam_RI: + mapReg(m, &am->LAam.RI.base); + break; + case LAam_RR: + mapReg(m, &am->LAam.RR.base); + mapReg(m, &am->LAam.RR.index); + break; + default: + vpanic("mapRegs_LOONGARCH64AMode"); + break; + } +} + + +/* --------- Operand, which can be reg or imm. --------- */ + +LOONGARCH64RI* LOONGARCH64RI_R ( HReg reg ) +{ + LOONGARCH64RI* op = LibVEX_Alloc_inline(sizeof(LOONGARCH64RI)); + op->tag = LAri_Reg; + op->LAri.R.reg = reg; + return op; +} + +LOONGARCH64RI* LOONGARCH64RI_I ( UShort imm, UChar size, Bool isSigned ) +{ + LOONGARCH64RI* op = LibVEX_Alloc_inline(sizeof(LOONGARCH64RI)); + op->tag = LAri_Imm; + op->LAri.I.imm = imm; + op->LAri.I.size = size; + op->LAri.I.isSigned = isSigned; + return op; +} + +static inline void ppLOONGARCH64RI ( LOONGARCH64RI* ri ) +{ + switch (ri->tag) { + case LAri_Reg: + ppHRegLOONGARCH64(ri->LAri.R.reg); + break; + case LAri_Imm: + if (ri->LAri.I.isSigned) { + vex_printf("%d", extend((UInt)ri->LAri.I.imm, ri->LAri.I.size)); + } else { + vex_printf("%u", (UInt)ri->LAri.I.imm); + } + break; + default: + vpanic("ppLOONGARCH64RI"); + break; + } +} + +static inline void addRegUsage_LOONGARCH64RI( HRegUsage* u, LOONGARCH64RI* ri ) +{ + switch (ri->tag) { + case LAri_Reg: + addHRegUse(u, HRmRead, ri->LAri.R.reg); + break; + case LAri_Imm: + break; + default: + vpanic("addRegUsage_LOONGARCH64RI"); + break; + } +} + +static inline void mapRegs_LOONGARCH64RI( HRegRemap* m, LOONGARCH64RI* ri ) +{ + switch (ri->tag) { + case LAri_Reg: + mapReg(m, &ri->LAri.R.reg); + break; + case LAri_Imm: + break; + default: + vpanic("mapRegs_LOONGARCH64RI"); + break; + } +} + + +/* --------- Instructions. --------- */ + +static inline const HChar* showLOONGARCH64UnOp ( LOONGARCH64UnOp op ) +{ + switch (op) { + case LAun_CLZ_W: + return "clz.w"; + case LAun_CTZ_W: + return "ctz.w"; + case LAun_CLZ_D: + return "clz.d"; + case LAun_CTZ_D: + return "ctz.w"; + case LAun_EXT_W_H: + return "ext.w.h"; + case LAun_EXT_W_B: + return "ext.w.b"; + default: + vpanic("showLOONGARCH64UnOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64BinOp ( LOONGARCH64BinOp op ) +{ + switch (op) { + case LAbin_ADD_W: + return "add.w"; + case LAbin_ADD_D: + return "add.d"; + case LAbin_SUB_W: + return "sub.w"; + case LAbin_SUB_D: + return "sub.d"; + case LAbin_NOR: + return "nor"; + case LAbin_AND: + return "and"; + case LAbin_OR: + return "or"; + case LAbin_XOR: + return "xor"; + case LAbin_SLL_W: + return "sll.w"; + case LAbin_SRL_W: + return "srl.w"; + case LAbin_SRA_W: + return "sra.w"; + case LAbin_SLL_D: + return "sll.d"; + case LAbin_SRL_D: + return "srl.d"; + case LAbin_SRA_D: + return "sra.d"; + case LAbin_MUL_W: + return "mul.w"; + case LAbin_MUL_D: + return "mul.d"; + case LAbin_MULH_W: + return "mulh.w"; + case LAbin_MULH_WU: + return "mulh.wu"; + case LAbin_MULH_D: + return "mulh.d"; + case LAbin_MULH_DU: + return "mulh.du"; + case LAbin_MULW_D_W: + return "mulw.d.w"; + case LAbin_MULW_D_WU: + return "mulw.d.wu"; + case LAbin_DIV_W: + return "div.w"; + case LAbin_MOD_W: + return "mod.w"; + case LAbin_DIV_WU: + return "div.wu"; + case LAbin_MOD_WU: + return "mod.wu"; + case LAbin_DIV_D: + return "div.d"; + case LAbin_MOD_D: + return "mod.d"; + case LAbin_DIV_DU: + return "div.du"; + case LAbin_MOD_DU: + return "mod.du"; + case LAbin_SLLI_W: + return "slli.w"; + case LAbin_SLLI_D: + return "slli.d"; + case LAbin_SRLI_W: + return "srli.w"; + case LAbin_SRLI_D: + return "srli.d"; + case LAbin_SRAI_W: + return "srai.w"; + case LAbin_SRAI_D: + return "srai.d"; + case LAbin_ADDI_W: + return "addi.w"; + case LAbin_ADDI_D: + return "addi.d"; + case LAbin_ANDI: + return "andi"; + case LAbin_ORI: + return "ori"; + case LAbin_XORI: + return "xori"; + default: + vpanic("showLOONGARCH64BinOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64LoadOp ( LOONGARCH64LoadOp op ) +{ + switch (op) { + case LAload_LD_D: + return "ld.d"; + case LAload_LD_BU: + return "ld.bu"; + case LAload_LD_HU: + return "ld.hu"; + case LAload_LD_WU: + return "ld.wu"; + case LAload_LDX_D: + return "ldx.d"; + case LAload_LDX_BU: + return "ldx.bu"; + case LAload_LDX_HU: + return "ldx.hu"; + case LAload_LDX_WU: + return "ldx.wu"; + default: + vpanic("LOONGARCH64LoadOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64StoreOp ( LOONGARCH64StoreOp op ) +{ + switch (op) { + case LAstore_ST_B: + return "st.b"; + case LAstore_ST_H: + return "st.h"; + case LAstore_ST_W: + return "st.w"; + case LAstore_ST_D: + return "st.d"; + case LAstore_STX_B: + return "stx.b"; + case LAstore_STX_H: + return "stx.h"; + case LAstore_STX_W: + return "stx.w"; + case LAstore_STX_D: + return "stx.d"; + default: + vpanic("LOONGARCH64StoreOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64LLSCOp ( LOONGARCH64LLSCOp op ) +{ + switch (op) { + case LAllsc_LL_W: + return "ll.w"; + case LAllsc_SC_W: + return "sc.w"; + case LAllsc_LL_D: + return "ll.d"; + case LAllsc_SC_D: + return "sc.d"; + default: + vpanic("LOONGARCH64LLSCOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64BarOp ( LOONGARCH64BarOp op ) +{ + const HChar* ret; + switch (op) { + case LAbar_DBAR: + return "dbar"; + case LAbar_IBAR: + return "ibar"; + default: + vpanic("showLOONGARCH64BarOp"); + break; + } + return ret; +} + +static inline const HChar* showLOONGARCH64FpUnOp ( LOONGARCH64FpUnOp op ) +{ + const HChar* ret; + switch (op) { + case LAfpun_FABS_S: + return "fabs.s"; + case LAfpun_FABS_D: + return "fabs.d"; + case LAfpun_FNEG_S: + return "fneg.s"; + case LAfpun_FNEG_D: + return "fneg.d"; + case LAfpun_FLOGB_S: + return "flogb.s"; + case LAfpun_FLOGB_D: + return "flogb.d"; + case LAfpun_FSQRT_S: + return "fsqrt.s"; + case LAfpun_FSQRT_D: + return "fsqrt.d"; + case LAfpun_FRSQRT_S: + return "frsqrt.s"; + case LAfpun_FRSQRT_D: + return "frsqrt.d"; + case LAfpun_FCVT_S_D: + return "fcvt.s.d"; + case LAfpun_FCVT_D_S: + return "fcvt.d.s"; + case LAfpun_FTINT_W_S: + return "ftint.w.s"; + case LAfpun_FTINT_W_D: + return "ftint.w.d"; + case LAfpun_FTINT_L_S: + return "ftint.l.s"; + case LAfpun_FTINT_L_D: + return "ftint.l.d"; + case LAfpun_FFINT_S_W: + return "ffint.s.w"; + case LAfpun_FFINT_S_L: + return "ffint.s.l"; + case LAfpun_FFINT_D_W: + return "ffint.d.w"; + case LAfpun_FFINT_D_L: + return "ffint.d.l"; + case LAfpun_FRINT_S: + return "frint.s"; + case LAfpun_FRINT_D: + return "frint.d"; + default: + vpanic("showLOONGARCH64FpUnOp"); + break; + } + return ret; +} + +static inline const HChar* showLOONGARCH64FpBinOp ( LOONGARCH64FpBinOp op ) +{ + const HChar* ret; + switch (op) { + case LAfpbin_FADD_S: + return "fadd.s"; + case LAfpbin_FADD_D: + return "fadd.d"; + case LAfpbin_FSUB_S: + return "fsub.s"; + case LAfpbin_FSUB_D: + return "fsub.d"; + case LAfpbin_FMUL_S: + return "fmul.s"; + case LAfpbin_FMUL_D: + return "fmul.d"; + case LAfpbin_FDIV_S: + return "fdiv.s"; + case LAfpbin_FDIV_D: + return "fdiv.d"; + case LAfpbin_FMAX_S: + return "fmax.s"; + case LAfpbin_FMAX_D: + return "fmax.d"; + case LAfpbin_FMIN_S: + return "fmin.s"; + case LAfpbin_FMIN_D: + return "fmin.d"; + case LAfpbin_FMAXA_S: + return "fmaxa.s"; + case LAfpbin_FMAXA_D: + return "fmaxa.d"; + case LAfpbin_FMINA_S: + return "fmina.s"; + case LAfpbin_FMINA_D: + return "fmina.d"; + case LAfpbin_FSCALEB_S: + return "fscaleb.s"; + case LAfpbin_FSCALEB_D: + return "fscaleb.d"; + default: + vpanic("showLOONGARCH64FpBinOp"); + break; + } + return ret; +} + +static inline const HChar* showLOONGARCH64FpTriOp ( LOONGARCH64FpTriOp op ) +{ + const HChar* ret; + switch (op) { + case LAfpbin_FMADD_S: + return "fmadd.s"; + case LAfpbin_FMADD_D: + return "fmadd.d"; + case LAfpbin_FMSUB_S: + return "fmsub.s"; + case LAfpbin_FMSUB_D: + return "fmsub.d"; + default: + vpanic("showLOONGARCH64FpTriOp"); + break; + } + return ret; +} + +static inline const HChar* showLOONGARCH64FpLoadOp ( LOONGARCH64FpLoadOp op ) +{ + switch (op) { + case LAfpload_FLD_S: + return "fld.s"; + case LAfpload_FLD_D: + return "fld.d"; + case LAfpload_FLDX_S: + return "fldx.s"; + case LAfpload_FLDX_D: + return "fldx.d"; + default: + vpanic("LOONGARCH64FpLoadOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64FpStoreOp ( LOONGARCH64FpStoreOp op ) +{ + switch (op) { + case LAfpstore_FST_S: + return "fst.s"; + case LAfpstore_FST_D: + return "fst.d"; + case LAfpstore_FSTX_S: + return "fstx.s"; + case LAfpstore_FSTX_D: + return "fstx.d"; + default: + vpanic("LOONGARCH64FpStoreOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64FpMoveOp ( LOONGARCH64FpMoveOp op ) +{ + switch (op) { + case LAfpmove_FMOV_S: + return "fmov.s"; + case LAfpmove_FMOV_D: + return "fmov.d"; + case LAfpmove_MOVGR2FR_W: + return "movgr2fr.w"; + case LAfpmove_MOVGR2FR_D: + return "movgr2fr.d"; + case LAfpmove_MOVFR2GR_S: + return "movfr2gr.s"; + case LAfpmove_MOVFR2GR_D: + return "movfr2gr.d"; + case LAfpmove_MOVGR2FCSR: + return "movgr2fcsr"; + case LAfpmove_MOVFCSR2GR: + return "movfcsr2gr"; + default: + vpanic("showLOONGARCH64FpMoveOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64FpCmpOp ( LOONGARCH64FpCmpOp op ) +{ + const HChar* ret; + switch (op) { + case LAfpcmp_FCMP_CLT_S: + return "fcmp.clt.s"; + case LAfpcmp_FCMP_CLT_D: + return "fcmp.clt.d"; + case LAfpcmp_FCMP_CEQ_S: + return "fcmp.ceq.s"; + case LAfpcmp_FCMP_CEQ_D: + return "fcmp.ceq.d"; + case LAfpcmp_FCMP_CUN_S: + return "fcmp.cun.s"; + case LAfpcmp_FCMP_CUN_D: + return "fcmp.cun.d"; + default: + vpanic("showLOONGARCH64FpCmpOp"); + break; + } + return ret; +} + +static inline const HChar* showLOONGARCH64VecUnOp ( LOONGARCH64VecUnOp op ) +{ + switch (op) { + case LAvecun_VCLO_B: + return "vclo.b"; + case LAvecun_VCLO_H: + return "vclo.h"; + case LAvecun_VCLO_W: + return "vclo.w"; + case LAvecun_VCLZ_B: + return "vclz.b"; + case LAvecun_VCLZ_H: + return "vclz.h"; + case LAvecun_VCLZ_W: + return "vclz.w"; + case LAvecun_VCLZ_D: + return "vclz.d"; + case LAvecun_VPCNT_B: + return "vpcnt.b"; + case LAvecun_VEXTH_H_B: + return "vexth.h.b"; + case LAvecun_VEXTH_W_H: + return "vexth.w.h"; + case LAvecun_VEXTH_D_W: + return "vexth.d.w"; + case LAvecun_VEXTH_Q_D: + return "vexth.q.d"; + case LAvecun_VEXTH_HU_BU: + return "vexth.hu.bu"; + case LAvecun_VEXTH_WU_HU: + return "vexth.wu.hu"; + case LAvecun_VEXTH_DU_WU: + return "vexth.du.wu"; + case LAvecun_VEXTH_QU_DU: + return "vexth.qu.du"; + case LAvecun_VREPLGR2VR_B: + return "vreplgr2vr.b"; + case LAvecun_VREPLGR2VR_H: + return "vreplgr2vr.h"; + case LAvecun_VREPLGR2VR_W: + return "vreplgr2vr.w"; + case LAvecun_VREPLGR2VR_D: + return "vreplgr2vr.d"; + default: + vpanic("showLOONGARCH64VecUnOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64VecBinOp ( LOONGARCH64VecBinOp op ) +{ + switch (op) { + case LAvecbin_VSEQ_B: + return "vseq.b"; + case LAvecbin_VSEQ_H: + return "vseq.h"; + case LAvecbin_VSEQ_W: + return "vseq.w"; + case LAvecbin_VSEQ_D: + return "vseq.d"; + case LAvecbin_VSLT_B: + return "vslt.b"; + case LAvecbin_VSLT_H: + return "vslt.h"; + case LAvecbin_VSLT_W: + return "vslt.w"; + case LAvecbin_VSLT_D: + return "vslt.d"; + case LAvecbin_VSLT_BU: + return "vslt.bu"; + case LAvecbin_VSLT_HU: + return "vslt.hu"; + case LAvecbin_VSLT_WU: + return "vslt.wu"; + case LAvecbin_VSLT_DU: + return "vslt.du"; + case LAvecbin_VADD_B: + return "vadd.b"; + case LAvecbin_VADD_H: + return "vadd.h"; + case LAvecbin_VADD_W: + return "vadd.w"; + case LAvecbin_VADD_D: + return "vadd.d"; + case LAvecbin_VSUB_B: + return "vsub.b"; + case LAvecbin_VSUB_H: + return "vsub.h"; + case LAvecbin_VSUB_W: + return "vsub.w"; + case LAvecbin_VSUB_D: + return "vsub.d"; + case LAvecbin_VSADD_B: + return "vsadd.b"; + case LAvecbin_VSADD_H: + return "vsadd.h"; + case LAvecbin_VSADD_W: + return "vsadd.w"; + case LAvecbin_VSADD_D: + return "vsadd.d"; + case LAvecbin_VSSUB_B: + return "vssub.b"; + case LAvecbin_VSSUB_H: + return "vssub.h"; + case LAvecbin_VSSUB_W: + return "vssub.w"; + case LAvecbin_VSSUB_D: + return "vssub.d"; + case LAvecbin_VSADD_BU: + return "vsadd.bu"; + case LAvecbin_VSADD_HU: + return "vsadd.hu"; + case LAvecbin_VSADD_WU: + return "vsadd.wu"; + case LAvecbin_VSADD_DU: + return "vsadd.du"; + case LAvecbin_VSSUB_BU: + return "vssub.bu"; + case LAvecbin_VSSUB_HU: + return "vssub.hu"; + case LAvecbin_VSSUB_WU: + return "vssub.wu"; + case LAvecbin_VSSUB_DU: + return "vssub.du"; + case LAvecbin_VADDA_B: + return "vadda.b"; + case LAvecbin_VADDA_H: + return "vadda.h"; + case LAvecbin_VADDA_W: + return "vadda.w"; + case LAvecbin_VADDA_D: + return "vadda.d"; + case LAvecbin_VAVGR_B: + return "vavgr.b"; + case LAvecbin_VAVGR_H: + return "vavgr.h"; + case LAvecbin_VAVGR_W: + return "vavgr.w"; + case LAvecbin_VAVGR_D: + return "vavgr.d"; + case LAvecbin_VAVGR_BU: + return "vavgr.bu"; + case LAvecbin_VAVGR_HU: + return "vavgr.hu"; + case LAvecbin_VAVGR_WU: + return "vavgr.wu"; + case LAvecbin_VAVGR_DU: + return "vavgr.du"; + case LAvecbin_VMAX_B: + return "vmax.b"; + case LAvecbin_VMAX_H: + return "vmax.h"; + case LAvecbin_VMAX_W: + return "vmax.w"; + case LAvecbin_VMAX_D: + return "vmax.d"; + case LAvecbin_VMIN_B: + return "vmin.b"; + case LAvecbin_VMIN_H: + return "vmin.h"; + case LAvecbin_VMIN_W: + return "vmin.w"; + case LAvecbin_VMIN_D: + return "vmin.d"; + case LAvecbin_VMAX_BU: + return "vmax.bu"; + case LAvecbin_VMAX_HU: + return "vmax.hu"; + case LAvecbin_VMAX_WU: + return "vmax.wu"; + case LAvecbin_VMAX_DU: + return "vmax.du"; + case LAvecbin_VMIN_BU: + return "vmin.bu"; + case LAvecbin_VMIN_HU: + return "vmin.hu"; + case LAvecbin_VMIN_WU: + return "vmin.wu"; + case LAvecbin_VMIN_DU: + return "vmin.du"; + case LAvecbin_VMUL_B: + return "vmul.b"; + case LAvecbin_VMUL_H: + return "vmul.h"; + case LAvecbin_VMUL_W: + return "vmul.w"; + case LAvecbin_VMUH_B: + return "vmuh.b"; + case LAvecbin_VMUH_H: + return "vmuh.h"; + case LAvecbin_VMUH_W: + return "vmuh.w"; + case LAvecbin_VMUH_BU: + return "vmuh.bu"; + case LAvecbin_VMUH_HU: + return "vmuh.hu"; + case LAvecbin_VMUH_WU: + return "vmuh.wu"; + case LAvecbin_VSLL_B: + return "vsll.b"; + case LAvecbin_VSLL_H: + return "vsll.h"; + case LAvecbin_VSLL_W: + return "vsll.w"; + case LAvecbin_VSLL_D: + return "vsll.d"; + case LAvecbin_VSRL_B: + return "vsrl.b"; + case LAvecbin_VSRL_H: + return "vsrl.h"; + case LAvecbin_VSRL_W: + return "vsrl.w"; + case LAvecbin_VSRL_D: + return "vsrl.d"; + case LAvecbin_VSRA_B: + return "vsra.b"; + case LAvecbin_VSRA_H: + return "vsra.h"; + case LAvecbin_VSRA_W: + return "vsra.w"; + case LAvecbin_VSRA_D: + return "vsra.d"; + case LAvecbin_VILVL_B: + return "vilvl.b"; + case LAvecbin_VILVL_H: + return "vilvl.h"; + case LAvecbin_VILVL_W: + return "vilvl.w"; + case LAvecbin_VILVL_D: + return "vilvl.d"; + case LAvecbin_VILVH_B: + return "vilvh.b"; + case LAvecbin_VILVH_H: + return "vilvh.h"; + case LAvecbin_VILVH_W: + return "vilvh.w"; + case LAvecbin_VILVH_D: + return "vilvh.d"; + case LAvecbin_VPICKEV_B: + return "vpickev.b"; + case LAvecbin_VPICKEV_H: + return "vpickev.h"; + case LAvecbin_VPICKEV_W: + return "vpickev.w"; + case LAvecbin_VPICKOD_B: + return "vpickod.b"; + case LAvecbin_VPICKOD_H: + return "vpickod.h"; + case LAvecbin_VPICKOD_W: + return "vpickod.w"; + case LAvecbin_VREPLVE_B: + return "vreplve.b"; + case LAvecbin_VREPLVE_H: + return "vreplve.h"; + case LAvecbin_VREPLVE_W: + return "vreplve.w"; + case LAvecbin_VREPLVE_D: + return "vreplve.d"; + case LAvecbin_VAND_V: + return "vand.v"; + case LAvecbin_VOR_V: + return "vor.v"; + case LAvecbin_VXOR_V: + return "vxor.v"; + case LAvecbin_VNOR_V: + return "vnor.v"; + case LAvecbin_VADD_Q: + return "vadd.q"; + case LAvecbin_VSUB_Q: + return "vsub.q"; + case LAvecbin_VFADD_S: + return "vfadd.s"; + case LAvecbin_VFADD_D: + return "vfadd.d"; + case LAvecbin_VFSUB_S: + return "vfsub.s"; + case LAvecbin_VFSUB_D: + return "vfsub.d"; + case LAvecbin_VFMUL_S: + return "vfmul.s"; + case LAvecbin_VFMUL_D: + return "vfmul.d"; + case LAvecbin_VFDIV_S: + return "vfdiv.s"; + case LAvecbin_VFDIV_D: + return "vfdiv.d"; + case LAvecbin_VFMAX_S: + return "vfmax.s"; + case LAvecbin_VFMAX_D: + return "vfmax.d"; + case LAvecbin_VFMIN_S: + return "vfmin.s"; + case LAvecbin_VFMIN_D: + return "vfmin.d"; + case LAvecbin_VBSLL_V: + return "vbsll.v"; + case LAvecbin_VBSRL_V: + return "vbsrl.v"; + case LAvecbin_VINSGR2VR_B: + return "vinsgr2vr.b"; + case LAvecbin_VINSGR2VR_H: + return "vinsgr2vr.h"; + case LAvecbin_VINSGR2VR_W: + return "vinsgr2vr.w"; + case LAvecbin_VINSGR2VR_D: + return "vinsgr2vr.d"; + case LAvecbin_VPICKVE2GR_W: + return "vpickve2gr.w"; + case LAvecbin_VPICKVE2GR_D: + return "vpickve2gr.d"; + case LAvecbin_VPICKVE2GR_BU: + return "vpickve2gr.bu"; + case LAvecbin_VPICKVE2GR_HU: + return "vpickve2gr.hu"; + case LAvecbin_VPICKVE2GR_WU: + return "vpickve2gr.wu"; + case LAvecbin_VPICKVE2GR_DU: + return "vpickve2gr.du"; + case LAvecbin_VSLLI_B: + return "vslli.b"; + case LAvecbin_VSLLI_H: + return "vslli.h"; + case LAvecbin_VSLLI_W: + return "vslli.w"; + case LAvecbin_VSLLI_D: + return "vslli.d"; + case LAvecbin_VSRLI_B: + return "vsrli.b"; + case LAvecbin_VSRLI_H: + return "vsrli.h"; + case LAvecbin_VSRLI_W: + return "vsrli.w"; + case LAvecbin_VSRLI_D: + return "vsrli.d"; + case LAvecbin_VSRAI_B: + return "vsrai.b"; + case LAvecbin_VSRAI_H: + return "vsrai.h"; + case LAvecbin_VSRAI_W: + return "vsrai.w"; + case LAvecbin_VSRAI_D: + return "vsrai.d"; + case LAvecbin_VORI_B: + return "vori.b"; + default: + vpanic("showLOONGARCH64VecBinOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64VecLoadOp ( LOONGARCH64VecLoadOp op ) +{ + switch (op) { + case LAvecload_VLD: + return "vld"; + case LAvecload_VLDX: + return "vldx"; + default: + vpanic("showLOONGARCH64VecLoadOp"); + break; + } +} + +static inline const HChar* showLOONGARCH64VecStoreOp ( LOONGARCH64VecStoreOp op ) +{ + switch (op) { + case LAvecstore_VST: + return "vst"; + case LAvecstore_VSTX: + return "vstx"; + default: + vpanic("showLOONGARCH64VecStoreOp"); + break; + } +} + +LOONGARCH64Instr* LOONGARCH64Instr_LI ( ULong imm, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_LI; + i->LAin.LI.imm = imm; + i->LAin.LI.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_Unary ( LOONGARCH64UnOp op, + HReg src, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_Un; + i->LAin.Unary.op = op; + i->LAin.Unary.src = src; + i->LAin.Unary.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_Binary ( LOONGARCH64BinOp op, + LOONGARCH64RI* src2, + HReg src1, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_Bin; + i->LAin.Binary.op = op; + i->LAin.Binary.src2 = src2; + i->LAin.Binary.src1 = src1; + i->LAin.Binary.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_Load ( LOONGARCH64LoadOp op, + LOONGARCH64AMode* src, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_Load; + i->LAin.Load.op = op; + i->LAin.Load.src = src; + i->LAin.Load.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_Store ( LOONGARCH64StoreOp op, + LOONGARCH64AMode* dst, HReg src ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_Store; + i->LAin.Store.op = op; + i->LAin.Store.dst = dst; + i->LAin.Store.src = src; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_LLSC ( LOONGARCH64LLSCOp op, Bool isLoad, + LOONGARCH64AMode* addr, HReg val ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_LLSC; + i->LAin.LLSC.op = op; + i->LAin.LLSC.isLoad = isLoad; + i->LAin.LLSC.addr = addr; + i->LAin.LLSC.val = val; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_Bar ( LOONGARCH64BarOp op, UShort hint ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_Bar; + i->LAin.Bar.op = op; + i->LAin.Bar.hint = hint; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_FpUnary ( LOONGARCH64FpUnOp op, + HReg src, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_FpUn; + i->LAin.FpUnary.op = op; + i->LAin.FpUnary.src = src; + i->LAin.FpUnary.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_FpBinary ( LOONGARCH64FpBinOp op, HReg src2, + HReg src1, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_FpBin; + i->LAin.FpBinary.op = op; + i->LAin.FpBinary.src2 = src2; + i->LAin.FpBinary.src1 = src1; + i->LAin.FpBinary.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_FpTrinary ( LOONGARCH64FpTriOp op, + HReg src3, HReg src2, + HReg src1, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_FpTri; + i->LAin.FpTrinary.op = op; + i->LAin.FpTrinary.src3 = src3; + i->LAin.FpTrinary.src2 = src2; + i->LAin.FpTrinary.src1 = src1; + i->LAin.FpTrinary.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_FpLoad ( LOONGARCH64FpLoadOp op, + LOONGARCH64AMode* src, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_FpLoad; + i->LAin.FpLoad.op = op; + i->LAin.FpLoad.src = src; + i->LAin.FpLoad.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_FpStore ( LOONGARCH64FpStoreOp op, + LOONGARCH64AMode* dst, HReg src ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_FpStore; + i->LAin.FpStore.op = op; + i->LAin.FpStore.dst = dst; + i->LAin.FpStore.src = src; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_FpMove ( LOONGARCH64FpMoveOp op, + HReg src, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_FpMove; + i->LAin.FpMove.op = op; + i->LAin.FpMove.src = src; + i->LAin.FpMove.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_FpCmp ( LOONGARCH64FpCmpOp op, HReg src2, + HReg src1, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_FpCmp; + i->LAin.FpCmp.op = op; + i->LAin.FpCmp.src2 = src2; + i->LAin.FpCmp.src1 = src1; + i->LAin.FpCmp.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_VecUnary ( LOONGARCH64VecUnOp op, + HReg src, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_VecUn; + i->LAin.VecUnary.op = op; + i->LAin.VecUnary.src = src; + i->LAin.VecUnary.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_VecBinary ( LOONGARCH64VecBinOp op, + LOONGARCH64RI* src2, + HReg src1, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_VecBin; + i->LAin.VecBinary.op = op; + i->LAin.VecBinary.src2 = src2; + i->LAin.VecBinary.src1 = src1; + i->LAin.VecBinary.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_VecLoad ( LOONGARCH64VecLoadOp op, + LOONGARCH64AMode* src, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_VecLoad; + i->LAin.VecLoad.op = op; + i->LAin.VecLoad.src = src; + i->LAin.VecLoad.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_VecStore ( LOONGARCH64VecStoreOp op, + LOONGARCH64AMode* dst, HReg src) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_VecStore; + i->LAin.VecStore.op = op; + i->LAin.VecStore.dst = dst; + i->LAin.VecStore.src = src; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_Cas ( HReg old, HReg addr, HReg expd, + HReg data, Bool size64 ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_Cas; + i->LAin.Cas.old = old; + i->LAin.Cas.addr = addr; + i->LAin.Cas.expd = expd; + i->LAin.Cas.data = data; + i->LAin.Cas.size64 = size64; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_Cmp ( LOONGARCH64CondCode cond, + HReg src2, HReg src1, HReg dst ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_Cmp; + i->LAin.Cmp.cond = cond; + i->LAin.Cmp.src2 = src2; + i->LAin.Cmp.src1 = src1; + i->LAin.Cmp.dst = dst; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_CMove ( HReg cond, HReg r0, HReg r1, + HReg dst, Bool isInt ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_CMove; + i->LAin.CMove.cond = cond; + i->LAin.CMove.r0 = r0; + i->LAin.CMove.r1 = r1; + i->LAin.CMove.dst = dst; + i->LAin.CMove.isInt = isInt; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_Call ( HReg cond, Addr64 target, + UInt nArgRegs, RetLoc rloc ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_Call; + i->LAin.Call.cond = cond; + i->LAin.Call.target = target; + i->LAin.Call.nArgRegs = nArgRegs; + i->LAin.Call.rloc = rloc; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_XDirect ( Addr64 dstGA, + LOONGARCH64AMode* amPC, + HReg cond, Bool toFastEP ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_XDirect; + i->LAin.XDirect.dstGA = dstGA; + i->LAin.XDirect.amPC = amPC; + i->LAin.XDirect.cond = cond; + i->LAin.XDirect.toFastEP = toFastEP; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_XIndir ( HReg dstGA, LOONGARCH64AMode* amPC, + HReg cond ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_XIndir; + i->LAin.XIndir.dstGA = dstGA; + i->LAin.XIndir.amPC = amPC; + i->LAin.XIndir.cond = cond; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_XAssisted ( HReg dstGA, + LOONGARCH64AMode* amPC, + HReg cond, IRJumpKind jk ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_XAssisted; + i->LAin.XAssisted.dstGA = dstGA; + i->LAin.XAssisted.amPC = amPC; + i->LAin.XAssisted.cond = cond; + i->LAin.XAssisted.jk = jk; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_EvCheck ( LOONGARCH64AMode* amCounter, + LOONGARCH64AMode* amFailAddr ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_EvCheck; + i->LAin.EvCheck.amCounter = amCounter; + i->LAin.EvCheck.amFailAddr = amFailAddr; + return i; +} + +LOONGARCH64Instr* LOONGARCH64Instr_ProfInc ( void ) +{ + LOONGARCH64Instr* i = LibVEX_Alloc_inline(sizeof(LOONGARCH64Instr)); + i->tag = LAin_ProfInc; + return i; +} + + +/* -------- Pretty Print instructions ------------- */ + +static inline void ppLI ( ULong imm, HReg dst ) +{ + vex_printf("li "); + ppHRegLOONGARCH64(dst); + vex_printf(", 0x%llx", imm); +} + +static inline void ppUnary ( LOONGARCH64UnOp op, HReg src, HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64UnOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppHRegLOONGARCH64(src); +} + +static inline void ppBinary ( LOONGARCH64BinOp op, LOONGARCH64RI* src2, + HReg src1, HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64BinOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppHRegLOONGARCH64(src1); + vex_printf(", "); + ppLOONGARCH64RI(src2); +} + +static inline void ppLoad ( LOONGARCH64LoadOp op, LOONGARCH64AMode* src, + HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64LoadOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppLOONGARCH64AMode(src); +} + +static inline void ppStore ( LOONGARCH64StoreOp op, LOONGARCH64AMode* dst, + HReg src ) +{ + vex_printf("%s ", showLOONGARCH64StoreOp(op)); + ppHRegLOONGARCH64(src); + vex_printf(", "); + ppLOONGARCH64AMode(dst); +} + +static inline void ppLLSC ( LOONGARCH64LLSCOp op, LOONGARCH64AMode* addr, + HReg val ) +{ + vex_printf("%s ", showLOONGARCH64LLSCOp(op)); + ppHRegLOONGARCH64(val); + vex_printf(", "); + ppLOONGARCH64AMode(addr); +} + +static inline void ppBar ( LOONGARCH64BarOp op, UShort hint ) +{ + vex_printf("%s %u", showLOONGARCH64BarOp(op), (UInt)hint); +} + +static inline void ppFpUnary ( LOONGARCH64FpUnOp op, HReg src, HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64FpUnOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppHRegLOONGARCH64(src); +} + +static inline void ppFpBinary ( LOONGARCH64FpBinOp op, HReg src2, + HReg src1, HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64FpBinOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppHRegLOONGARCH64(src1); + vex_printf(", "); + ppHRegLOONGARCH64(src2); +} + +static inline void ppFpTrinary ( LOONGARCH64FpTriOp op, HReg src3, + HReg src2, HReg src1, HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64FpTriOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppHRegLOONGARCH64(src1); + vex_printf(", "); + ppHRegLOONGARCH64(src2); + vex_printf(", "); + ppHRegLOONGARCH64(src3); +} + +static inline void ppFpLoad ( LOONGARCH64FpLoadOp op, LOONGARCH64AMode* src, + HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64FpLoadOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppLOONGARCH64AMode(src); +} + +static inline void ppFpStore ( LOONGARCH64FpStoreOp op, LOONGARCH64AMode* dst, + HReg src ) +{ + vex_printf("%s ", showLOONGARCH64FpStoreOp(op)); + ppHRegLOONGARCH64(src); + vex_printf(", "); + ppLOONGARCH64AMode(dst); +} + +static inline void ppFpMove ( LOONGARCH64FpMoveOp op, HReg src, HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64FpMoveOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppHRegLOONGARCH64(src); +} + +static inline void ppFpCmp ( LOONGARCH64FpCmpOp op, HReg src2, + HReg src1, HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64FpCmpOp(op)); + vex_printf("$fcc0, "); + ppHRegLOONGARCH64(src1); + vex_printf(", "); + ppHRegLOONGARCH64(src2); + vex_printf("; movcf2gr "); + ppHRegLOONGARCH64(dst); + vex_printf(", $fcc0"); +} + +static inline void ppVecUnary ( LOONGARCH64VecUnOp op, HReg src, HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64VecUnOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppHRegLOONGARCH64(src); +} + +static inline void ppVecBinary ( LOONGARCH64VecBinOp op, LOONGARCH64RI* src2, + HReg src1, HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64VecBinOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppHRegLOONGARCH64(src1); + vex_printf(", "); + ppLOONGARCH64RI(src2); +} + +static inline void ppVecLoad ( LOONGARCH64VecLoadOp op, LOONGARCH64AMode* src, + HReg dst ) +{ + vex_printf("%s ", showLOONGARCH64VecLoadOp(op)); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppLOONGARCH64AMode(src); +} + +static inline void ppVecStore ( LOONGARCH64VecStoreOp op, LOONGARCH64AMode* dst, + HReg src ) +{ + vex_printf("%s ", showLOONGARCH64VecStoreOp(op)); + ppHRegLOONGARCH64(src); + vex_printf(", "); + ppLOONGARCH64AMode(dst); +} + +static inline void ppCas ( HReg old, HReg addr, HReg expd, + HReg data, Bool size64) +{ + ppHRegLOONGARCH64(old); + vex_printf(" = cas(%dbit)(", size64 ? 64 : 32); + ppHRegLOONGARCH64(expd); + vex_printf(", "); + ppHRegLOONGARCH64(data); + vex_printf(" -> "); + ppHRegLOONGARCH64(addr); + vex_printf(")"); +} + +static inline void ppCmp ( LOONGARCH64CondCode cond, HReg src2, + HReg src1, HReg dst ) +{ + ppHRegLOONGARCH64(dst); + vex_printf(" = cmp%s(", showLOONGARCH64CondCode(cond)); + ppHRegLOONGARCH64(src1); + vex_printf(", "); + ppHRegLOONGARCH64(src2); + vex_printf(")"); +} + +static inline void ppCMove ( HReg cond, HReg r0, HReg r1, + HReg dst, Bool isInt ) +{ + if (isInt) { + vex_printf("masknez $t0, "); + ppHRegLOONGARCH64(r0); + vex_printf(", "); + ppHRegLOONGARCH64(cond); + vex_printf("; maskeqz "); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppHRegLOONGARCH64(r1); + vex_printf(", "); + ppHRegLOONGARCH64(cond); + vex_printf("; or "); + ppHRegLOONGARCH64(dst); + vex_printf(", $t0, "); + ppHRegLOONGARCH64(dst); + } else { + vex_printf("movgr2cf "); + ppHRegLOONGARCH64(cond); + vex_printf(", $fcc0; fsel "); + ppHRegLOONGARCH64(dst); + vex_printf(", "); + ppHRegLOONGARCH64(r0); + vex_printf(", "); + ppHRegLOONGARCH64(r1); + vex_printf(", $fcc0"); + } +} + +static inline void ppCall ( HReg cond, Addr64 target, + UInt nArgRegs, RetLoc rloc ) +{ + if (!hregIsInvalid(cond)) { + vex_printf("if ("); + ppHRegLOONGARCH64(cond); + vex_printf(") { "); + } + vex_printf("call 0x%llx [nArgRegs=%u, ", target, nArgRegs); + ppRetLoc(rloc); + vex_printf("]"); + if (!hregIsInvalid(cond)) + vex_printf(" }"); +} + +static inline void ppXDirect ( Addr64 dstGA, LOONGARCH64AMode* amPC, + HReg cond, Bool toFastEP ) +{ + vex_printf("(xDirect) "); + if (!hregIsInvalid(cond)) { + vex_printf("if ("); + ppHRegLOONGARCH64(cond); + vex_printf(") { "); + } + vex_printf("li $t0, 0x%llx; ", (ULong)dstGA); + vex_printf("st.w $t0, "); + ppLOONGARCH64AMode(amPC); + vex_printf("; li $t0, $disp_cp_chain_me_to_%sEP; ", + toFastEP ? "fast" : "slow"); + vex_printf("jirl $ra, $t0, 0"); + if (!hregIsInvalid(cond)) + vex_printf(" }"); +} + +static inline void ppXIndir ( HReg dstGA, LOONGARCH64AMode* amPC, + HReg cond ) +{ + vex_printf("(xIndir) "); + if (!hregIsInvalid(cond)) { + vex_printf("if ("); + ppHRegLOONGARCH64(cond); + vex_printf(") { "); + } + vex_printf("st.w "); + ppHRegLOONGARCH64(dstGA); + vex_printf(", "); + ppLOONGARCH64AMode(amPC); + vex_printf("; la $t0, disp_indir; "); + vex_printf("jirl $ra, $t0, 0"); + if (!hregIsInvalid(cond)) + vex_printf(" }"); +} + +static inline void ppXAssisted ( HReg dstGA, LOONGARCH64AMode* amPC, + HReg cond, IRJumpKind jk) +{ + vex_printf("(xAssisted) "); + if (!hregIsInvalid(cond)) { + vex_printf("if ("); + ppHRegLOONGARCH64(cond); + vex_printf(") { "); + } + vex_printf("st.w "); + ppHRegLOONGARCH64(dstGA); + vex_printf(", "); + ppLOONGARCH64AMode(amPC); + vex_printf("; li.w $s8, IRJumpKind_to_TRCVAL(%d); ", (Int)jk); + vex_printf("la $t0, disp_assisted; "); + vex_printf("jirl $ra, $t0, 0"); + if (!hregIsInvalid(cond)) + vex_printf(" }"); +} + +static inline void ppEvCheck ( LOONGARCH64AMode* amCounter, + LOONGARCH64AMode* amFailAddr ) +{ + vex_printf("(evCheck) "); + vex_printf("ld.w $t0, "); + ppLOONGARCH64AMode(amCounter); + vex_printf("; addi.d $t0, $t0, -1; "); + vex_printf("st.w $t0, "); + ppLOONGARCH64AMode(amCounter); + vex_printf("; bge $t0, $zero, nofail; "); + vex_printf("ld.d $t0, "); + ppLOONGARCH64AMode(amFailAddr); + vex_printf("; jirl $ra, $t0, 0"); + vex_printf("; nofail:"); +} + +static inline void ppProfInc ( void ) +{ + vex_printf("(profInc) "); + vex_printf("li $t0, NotKnownYet; "); + vex_printf("ld.d $t1, $t0, 0; "); + vex_printf("addi.d $t1, $t1, 1; "); + vex_printf("st.d $t1, $t0, 0;"); +} + +void ppLOONGARCH64Instr ( const LOONGARCH64Instr* i, Bool mode64 ) +{ + vassert(mode64 == True); + switch (i->tag) { + case LAin_LI: + ppLI(i->LAin.LI.imm, i->LAin.LI.dst); + break; + case LAin_Un: + ppUnary(i->LAin.Unary.op, i->LAin.Unary.src, i->LAin.Unary.dst); + break; + case LAin_Bin: + ppBinary(i->LAin.Binary.op, i->LAin.Binary.src2, + i->LAin.Binary.src1, i->LAin.Binary.dst); + break; + case LAin_Load: + ppLoad(i->LAin.Load.op, i->LAin.Load.src, i->LAin.Load.dst); + break; + case LAin_Store: + ppStore(i->LAin.Store.op, i->LAin.Store.dst, i->LAin.Store.src); + break; + case LAin_LLSC: + ppLLSC(i->LAin.LLSC.op, i->LAin.LLSC.addr, i->LAin.LLSC.val); + break; + case LAin_Bar: + ppBar(i->LAin.Bar.op, i->LAin.Bar.hint); + break; + case LAin_FpUn: + ppFpUnary(i->LAin.FpUnary.op, i->LAin.FpUnary.src, + i->LAin.FpUnary.dst); + break; + case LAin_FpBin: + ppFpBinary(i->LAin.FpBinary.op, i->LAin.FpBinary.src2, + i->LAin.FpBinary.src1, i->LAin.FpBinary.dst); + break; + case LAin_FpTri: + ppFpTrinary(i->LAin.FpTrinary.op, i->LAin.FpTrinary.src3, + i->LAin.FpTrinary.src2, i->LAin.FpTrinary.src1, + i->LAin.FpTrinary.dst); + break; + case LAin_FpLoad: + ppFpLoad(i->LAin.FpLoad.op, i->LAin.FpLoad.src, i->LAin.FpLoad.dst); + break; + case LAin_FpStore: + ppFpStore(i->LAin.FpStore.op, i->LAin.FpStore.dst, + i->LAin.FpStore.src); + break; + case LAin_FpMove: + ppFpMove(i->LAin.FpMove.op, i->LAin.FpMove.src, + i->LAin.FpMove.dst); + break; + case LAin_FpCmp: + ppFpCmp(i->LAin.FpCmp.op, i->LAin.FpCmp.src2, + i->LAin.FpCmp.src1, i->LAin.FpCmp.dst); + break; + case LAin_VecUn: + ppVecUnary(i->LAin.VecUnary.op, i->LAin.VecUnary.src, + i->LAin.VecUnary.dst); + break; + case LAin_VecBin: + ppVecBinary(i->LAin.VecBinary.op, i->LAin.VecBinary.src2, + i->LAin.VecBinary.src1, i->LAin.VecBinary.dst); + break; + case LAin_VecLoad: + ppVecLoad(i->LAin.VecLoad.op, i->LAin.VecLoad.src, + i->LAin.VecLoad.dst); + break; + case LAin_VecStore: + ppVecStore(i->LAin.VecStore.op, i->LAin.VecStore.dst, + i->LAin.VecStore.src); + break; + case LAin_Cas: + ppCas(i->LAin.Cas.old, i->LAin.Cas.addr, i->LAin.Cas.expd, + i->LAin.Cas.data, i->LAin.Cas.size64); + break; + case LAin_Cmp: + ppCmp(i->LAin.Cmp.cond, i->LAin.Cmp.src2, + i->LAin.Cmp.src1, i->LAin.Cmp.dst); + break; + case LAin_CMove: + ppCMove(i->LAin.CMove.cond, i->LAin.CMove.r0, + i->LAin.CMove.r1, i->LAin.CMove.dst, + i->LAin.CMove.isInt); + break; + case LAin_Call: + ppCall(i->LAin.Call.cond, i->LAin.Call.target, + i->LAin.Call.nArgRegs, i->LAin.Call.rloc); + break; + case LAin_XDirect: + ppXDirect(i->LAin.XDirect.dstGA, i->LAin.XDirect.amPC, + i->LAin.XDirect.cond, i->LAin.XDirect.toFastEP); + break; + case LAin_XIndir: + ppXIndir(i->LAin.XIndir.dstGA, i->LAin.XIndir.amPC, + i->LAin.XIndir.cond); + break; + case LAin_XAssisted: + ppXAssisted(i->LAin.XAssisted.dstGA, i->LAin.XAssisted.amPC, + i->LAin.XAssisted.cond, i->LAin.XAssisted.jk); + break; + case LAin_EvCheck: + ppEvCheck(i->LAin.EvCheck.amCounter, i->LAin.EvCheck.amFailAddr); + break; + case LAin_ProfInc: + ppProfInc(); + break; + default: + vpanic("ppLOONGARCH64Instr"); + break; + } +} + + +/* --------- Helpers for register allocation. --------- */ + +void getRegUsage_LOONGARCH64Instr ( HRegUsage* u, const LOONGARCH64Instr* i, + Bool mode64 ) +{ + vassert(mode64 == True); + initHRegUsage(u); + switch (i->tag) { + case LAin_LI: + addHRegUse(u, HRmWrite, i->LAin.LI.dst); + break; + case LAin_Un: + addHRegUse(u, HRmRead, i->LAin.Unary.src); + addHRegUse(u, HRmWrite, i->LAin.Unary.dst); + break; + case LAin_Bin: + addRegUsage_LOONGARCH64RI(u, i->LAin.Binary.src2); + addHRegUse(u, HRmRead, i->LAin.Binary.src1); + addHRegUse(u, HRmWrite, i->LAin.Binary.dst); + break; + case LAin_Load: + addRegUsage_LOONGARCH64AMode(u, i->LAin.Load.src); + addHRegUse(u, HRmWrite, i->LAin.Load.dst); + break; + case LAin_Store: + addRegUsage_LOONGARCH64AMode(u, i->LAin.Store.dst); + addHRegUse(u, HRmRead, i->LAin.Store.src); + break; + case LAin_LLSC: + addRegUsage_LOONGARCH64AMode(u, i->LAin.LLSC.addr); + if (i->LAin.LLSC.isLoad) + addHRegUse(u, HRmWrite, i->LAin.LLSC.val); + else + addHRegUse(u, HRmRead, i->LAin.LLSC.val); + break; + case LAin_Bar: + /* No regs. */ + break; + case LAin_FpUn: + addHRegUse(u, HRmRead, i->LAin.FpUnary.src); + addHRegUse(u, HRmWrite, i->LAin.FpUnary.dst); + break; + case LAin_FpBin: + addHRegUse(u, HRmRead, i->LAin.FpBinary.src2); + addHRegUse(u, HRmRead, i->LAin.FpBinary.src1); + addHRegUse(u, HRmWrite, i->LAin.FpBinary.dst); + break; + case LAin_FpTri: + addHRegUse(u, HRmRead, i->LAin.FpTrinary.src3); + addHRegUse(u, HRmRead, i->LAin.FpTrinary.src2); + addHRegUse(u, HRmRead, i->LAin.FpTrinary.src1); + addHRegUse(u, HRmWrite, i->LAin.FpTrinary.dst); + break; + case LAin_FpLoad: + addRegUsage_LOONGARCH64AMode(u, i->LAin.FpLoad.src); + addHRegUse(u, HRmWrite, i->LAin.FpLoad.dst); + break; + case LAin_FpStore: + addRegUsage_LOONGARCH64AMode(u, i->LAin.FpStore.dst); + addHRegUse(u, HRmRead, i->LAin.FpStore.src); + break; + case LAin_FpMove: + addHRegUse(u, HRmRead, i->LAin.FpMove.src); + addHRegUse(u, HRmWrite, i->LAin.FpMove.dst); + break; + case LAin_FpCmp: + addHRegUse(u, HRmRead, i->LAin.FpCmp.src2); + addHRegUse(u, HRmRead, i->LAin.FpCmp.src1); + addHRegUse(u, HRmWrite, i->LAin.FpCmp.dst); + break; + case LAin_VecUn: + addHRegUse(u, HRmRead, i->LAin.VecUnary.src); + addHRegUse(u, HRmWrite, i->LAin.VecUnary.dst); + break; + case LAin_VecBin: + addRegUsage_LOONGARCH64RI(u, i->LAin.VecBinary.src2); + addHRegUse(u, HRmRead, i->LAin.VecBinary.src1); + addHRegUse(u, HRmWrite, i->LAin.VecBinary.dst); + break; + case LAin_VecLoad: + addRegUsage_LOONGARCH64AMode(u, i->LAin.VecLoad.src); + addHRegUse(u, HRmWrite, i->LAin.VecLoad.dst); + break; + case LAin_VecStore: + addRegUsage_LOONGARCH64AMode(u, i->LAin.VecStore.dst); + addHRegUse(u, HRmRead, i->LAin.VecStore.src); + break; + case LAin_Cas: + addHRegUse(u, HRmWrite, i->LAin.Cas.old); + addHRegUse(u, HRmRead, i->LAin.Cas.addr); + addHRegUse(u, HRmRead, i->LAin.Cas.expd); + addHRegUse(u, HRmModify, i->LAin.Cas.data); + break; + case LAin_Cmp: + addHRegUse(u, HRmRead, i->LAin.Cmp.src2); + addHRegUse(u, HRmRead, i->LAin.Cmp.src1); + addHRegUse(u, HRmWrite, i->LAin.Cmp.dst); + break; + case LAin_CMove: + addHRegUse(u, HRmRead, i->LAin.CMove.cond); + addHRegUse(u, HRmRead, i->LAin.CMove.r0); + addHRegUse(u, HRmRead, i->LAin.CMove.r1); + addHRegUse(u, HRmWrite, i->LAin.CMove.dst); + break; + case LAin_Call: + /* logic and comments copied/modified from mips and arm64 back end */ + /* This is a bit subtle. */ + /* First off, we need to consider the cond register. */ + if (!hregIsInvalid(i->LAin.Call.cond)) + addHRegUse(u, HRmRead, i->LAin.Call.cond); + /* Then, claim it trashes all the caller-saved regs + which fall within the register allocator's jurisdiction. */ + addHRegUse(u, HRmWrite, hregLOONGARCH64_R14()); + addHRegUse(u, HRmWrite, hregLOONGARCH64_R15()); + addHRegUse(u, HRmWrite, hregLOONGARCH64_R16()); + addHRegUse(u, HRmWrite, hregLOONGARCH64_R17()); + addHRegUse(u, HRmWrite, hregLOONGARCH64_R18()); + addHRegUse(u, HRmWrite, hregLOONGARCH64_R19()); + addHRegUse(u, HRmWrite, hregLOONGARCH64_R20()); + /* Now we have to state any parameter-carrying registers + which might be read. This depends on nArgRegs. */ + switch (i->LAin.Call.nArgRegs) { + case 8: addHRegUse(u, HRmRead, hregLOONGARCH64_R11()); /* fallthrough */ + case 7: addHRegUse(u, HRmRead, hregLOONGARCH64_R10()); /* fallthrough */ + case 6: addHRegUse(u, HRmRead, hregLOONGARCH64_R9()); /* fallthrough */ + case 5: addHRegUse(u, HRmRead, hregLOONGARCH64_R8()); /* fallthrough */ + case 4: addHRegUse(u, HRmRead, hregLOONGARCH64_R7()); /* fallthrough */ + case 3: addHRegUse(u, HRmRead, hregLOONGARCH64_R6()); /* fallthrough */ + case 2: addHRegUse(u, HRmRead, hregLOONGARCH64_R5()); /* fallthrough */ + case 1: addHRegUse(u, HRmRead, hregLOONGARCH64_R4()); /* fallthrough */ + case 0: break; + default: vpanic("getRegUsage_LOONGARCH64:Call:regparms"); break; + } + /* Finally, there is the issue that the insn trashes a + register because the literal target address has to be + loaded into a register. However, we reserve $t0 for that + purpose so there's no further complexity here. Stating $t0 + as trashed is pointless since it's not under the control + of the allocator, but what the hell. */ + addHRegUse(u, HRmWrite, hregT0()); + break; + /* XDirect/XIndir/XAssisted are also a bit subtle. They + conditionally exit the block. Hence we only need to list (1) + the registers that they read, and (2) the registers that they + write in the case where the block is not exited. (2) is + empty, hence only (1) is relevant here. */ + case LAin_XDirect: + addRegUsage_LOONGARCH64AMode(u, i->LAin.XDirect.amPC); + if (!hregIsInvalid(i->LAin.XDirect.cond)) + addHRegUse(u, HRmRead, i->LAin.XDirect.cond); + addHRegUse(u, HRmWrite, hregT0()); /* unavail to RA */ + break; + case LAin_XIndir: + addHRegUse(u, HRmRead, i->LAin.XIndir.dstGA); + addRegUsage_LOONGARCH64AMode(u, i->LAin.XIndir.amPC); + if (!hregIsInvalid(i->LAin.XIndir.cond)) + addHRegUse(u, HRmRead, i->LAin.XIndir.cond); + addHRegUse(u, HRmWrite, hregT0()); /* unavail to RA */ + break; + case LAin_XAssisted: + addHRegUse(u, HRmRead, i->LAin.XAssisted.dstGA); + addRegUsage_LOONGARCH64AMode(u, i->LAin.XAssisted.amPC); + if (!hregIsInvalid(i->LAin.XAssisted.cond)) + addHRegUse(u, HRmRead, i->LAin.XAssisted.cond); + addHRegUse(u, HRmWrite, hregT0()); /* unavail to RA */ + break; + case LAin_EvCheck: + /* We expect both amodes only to mention $r31, so this is in + fact pointless, since $r31 isn't allocatable, but anyway.. */ + addRegUsage_LOONGARCH64AMode(u, i->LAin.EvCheck.amCounter); + addRegUsage_LOONGARCH64AMode(u, i->LAin.EvCheck.amFailAddr); + addHRegUse(u, HRmWrite, hregT0()); /* unavail to RA */ + break; + case LAin_ProfInc: + /* Again, pointless to actually state these since neither + is available to RA. */ + addHRegUse(u, HRmWrite, hregT0()); /* unavail to RA */ + addHRegUse(u, HRmWrite, hregT1()); /* unavail to RA */ + break; + default: + ppLOONGARCH64Instr(i, mode64); + vpanic("getRegUsage_LOONGARCH64Instr"); + break; + } +} + +void mapRegs_LOONGARCH64Instr ( HRegRemap* m, LOONGARCH64Instr* i, + Bool mode64 ) +{ + vassert(mode64 == True); + switch (i->tag) { + case LAin_LI: + mapReg(m, &i->LAin.LI.dst); + break; + case LAin_Un: + mapReg(m, &i->LAin.Unary.src); + mapReg(m, &i->LAin.Unary.dst); + break; + case LAin_Bin: + mapRegs_LOONGARCH64RI(m, i->LAin.Binary.src2); + mapReg(m, &i->LAin.Binary.src1); + mapReg(m, &i->LAin.Binary.dst); + break; + case LAin_Load: + mapRegs_LOONGARCH64AMode(m, i->LAin.Load.src); + mapReg(m, &i->LAin.Load.dst); + break; + case LAin_Store: + mapRegs_LOONGARCH64AMode(m, i->LAin.Store.dst); + mapReg(m, &i->LAin.Store.src); + break; + case LAin_LLSC: + mapRegs_LOONGARCH64AMode(m, i->LAin.LLSC.addr); + mapReg(m, &i->LAin.LLSC.val); + break; + case LAin_Bar: + /* No regs. */ + break; + case LAin_FpUn: + mapReg(m, &i->LAin.FpUnary.src); + mapReg(m, &i->LAin.FpUnary.dst); + break; + case LAin_FpBin: + mapReg(m, &i->LAin.FpBinary.src2); + mapReg(m, &i->LAin.FpBinary.src1); + mapReg(m, &i->LAin.FpBinary.dst); + break; + case LAin_FpTri: + mapReg(m, &i->LAin.FpTrinary.src3); + mapReg(m, &i->LAin.FpTrinary.src2); + mapReg(m, &i->LAin.FpTrinary.src1); + mapReg(m, &i->LAin.FpTrinary.dst); + break; + case LAin_FpLoad: + mapRegs_LOONGARCH64AMode(m, i->LAin.FpLoad.src); + mapReg(m, &i->LAin.FpLoad.dst); + break; + case LAin_FpStore: + mapRegs_LOONGARCH64AMode(m, i->LAin.FpStore.dst); + mapReg(m, &i->LAin.FpStore.src); + break; + case LAin_FpMove: + mapReg(m, &i->LAin.FpMove.src); + mapReg(m, &i->LAin.FpMove.dst); + break; + case LAin_FpCmp: + mapReg(m, &i->LAin.FpCmp.src2); + mapReg(m, &i->LAin.FpCmp.src1); + mapReg(m, &i->LAin.FpCmp.dst); + break; + case LAin_VecUn: + mapReg(m, &i->LAin.VecUnary.src); + mapReg(m, &i->LAin.VecUnary.dst); + break; + case LAin_VecBin: + mapRegs_LOONGARCH64RI(m, i->LAin.VecBinary.src2); + mapReg(m, &i->LAin.VecBinary.src1); + mapReg(m, &i->LAin.VecBinary.dst); + break; + case LAin_VecLoad: + mapRegs_LOONGARCH64AMode(m, i->LAin.VecLoad.src); + mapReg(m, &i->LAin.VecLoad.dst); + break; + case LAin_VecStore: + mapRegs_LOONGARCH64AMode(m, i->LAin.VecStore.dst); + mapReg(m, &i->LAin.VecStore.src); + break; + case LAin_Cas: + mapReg(m, &i->LAin.Cas.old); + mapReg(m, &i->LAin.Cas.addr); + mapReg(m, &i->LAin.Cas.expd); + mapReg(m, &i->LAin.Cas.data); + break; + case LAin_Cmp: + mapReg(m, &i->LAin.Cmp.src2); + mapReg(m, &i->LAin.Cmp.src1); + mapReg(m, &i->LAin.Cmp.dst); + break; + case LAin_CMove: + mapReg(m, &i->LAin.CMove.cond); + mapReg(m, &i->LAin.CMove.r0); + mapReg(m, &i->LAin.CMove.r1); + mapReg(m, &i->LAin.CMove.dst); + break; + case LAin_Call: + if (!hregIsInvalid(i->LAin.Call.cond)) + mapReg(m, &i->LAin.Call.cond); + /* Hardwires $r12. */ + break; + /* XDirect/XIndir/XAssisted are also a bit subtle. They + conditionally exit the block. Hence we only need to list (1) + the registers that they read, and (2) the registers that they + write in the case where the block is not exited. (2) is + empty, hence only (1) is relevant here. */ + case LAin_XDirect: + mapRegs_LOONGARCH64AMode(m, i->LAin.XDirect.amPC); + if (!hregIsInvalid(i->LAin.XDirect.cond)) + mapReg(m, &i->LAin.XDirect.cond); + break; + case LAin_XIndir: + mapReg(m, &i->LAin.XIndir.dstGA); + mapRegs_LOONGARCH64AMode(m, i->LAin.XIndir.amPC); + if (!hregIsInvalid(i->LAin.XIndir.cond)) + mapReg(m, &i->LAin.XIndir.cond); + break; + case LAin_XAssisted: + mapReg(m, &i->LAin.XAssisted.dstGA); + mapRegs_LOONGARCH64AMode(m, i->LAin.XAssisted.amPC); + if (!hregIsInvalid(i->LAin.XAssisted.cond)) + mapReg(m, &i->LAin.XAssisted.cond); + break; + case LAin_EvCheck: + /* We expect both amodes only to mention $r31, so this is in + fact pointless, since $r31 isn't allocatable, but anyway.. */ + mapRegs_LOONGARCH64AMode(m, i->LAin.EvCheck.amCounter); + mapRegs_LOONGARCH64AMode(m, i->LAin.EvCheck.amFailAddr); + break; + case LAin_ProfInc: + /* Hardwires $r12 and $r13 -- nothing to modify. */ + break; + default: + ppLOONGARCH64Instr(i, mode64); + vpanic("mapRegs_LOONGARCH64Instr"); + break; + } +} + +/* Generate loongarch64 spill instructions under the direction of the + register allocator. */ +void genSpill_LOONGARCH64 ( /*OUT*/ HInstr** i1, /*OUT*/ HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ) +{ + vassert(mode64 == True); + vassert(offsetB >= 0); + vassert(!hregIsVirtual(rreg)); + + LOONGARCH64AMode* am; + *i1 = *i2 = NULL; + + switch (hregClass(rreg)) { + case HRcInt64: + if (offsetB < 1024) { + am = LOONGARCH64AMode_RI(hregGSP(), offsetB); + *i1 = LOONGARCH64Instr_Store(LAstore_ST_D, am, rreg); + } else { + *i1 = LOONGARCH64Instr_LI(offsetB, hregT0()); + am = LOONGARCH64AMode_RR(hregGSP(), hregT0()); + *i2 = LOONGARCH64Instr_Store(LAstore_STX_D, am, rreg); + } + break; + case HRcFlt64: + if (offsetB < 1024) { + am = LOONGARCH64AMode_RI(hregGSP(), offsetB); + *i1 = LOONGARCH64Instr_FpStore(LAfpstore_FST_D, am, rreg); + } else { + *i1 = LOONGARCH64Instr_LI(offsetB, hregT0()); + am = LOONGARCH64AMode_RR(hregGSP(), hregT0()); + *i2 = LOONGARCH64Instr_FpStore(LAfpstore_FSTX_D, am, rreg); + } + break; + case HRcVec128: + if (offsetB < 1024) { + am = LOONGARCH64AMode_RI(hregGSP(), offsetB); + *i1 = LOONGARCH64Instr_VecStore(LAvecstore_VST, am, rreg); + } else { + am = LOONGARCH64AMode_RR(hregGSP(), hregT0()); + *i1 = LOONGARCH64Instr_LI(offsetB, hregT0()); + *i2 = LOONGARCH64Instr_VecStore(LAvecstore_VSTX, am, rreg); + } + break; + default: + ppHRegClass(hregClass(rreg)); + vpanic("genSpill_LOONGARCH64: unimplemented regclass"); + break; + } +} + +/* Generate loongarch64 reload instructions under the direction of the + register allocator. */ +void genReload_LOONGARCH64 ( /*OUT*/ HInstr** i1, /*OUT*/ HInstr** i2, + HReg rreg, Int offsetB, Bool mode64 ) +{ + vassert(mode64 == True); + vassert(offsetB >= 0); + vassert(!hregIsVirtual(rreg)); + + LOONGARCH64AMode* am; + *i1 = *i2 = NULL; + + switch (hregClass(rreg)) { + case HRcInt64: + if (offsetB < 1024) { + am = LOONGARCH64AMode_RI(hregGSP(), offsetB); + *i1 = LOONGARCH64Instr_Load(LAload_LD_D, am, rreg); + } else { + *i1 = LOONGARCH64Instr_LI(offsetB, hregT0()); + am = LOONGARCH64AMode_RR(hregGSP(), hregT0()); + *i2 = LOONGARCH64Instr_Load(LAload_LDX_D, am, rreg); + } + break; + case HRcFlt64: + if (offsetB < 1024) { + am = LOONGARCH64AMode_RI(hregGSP(), offsetB); + *i1 = LOONGARCH64Instr_FpLoad(LAfpload_FLD_D, am, rreg); + } else { + *i1 = LOONGARCH64Instr_LI(offsetB, hregT0()); + am = LOONGARCH64AMode_RR(hregGSP(), hregT0()); + *i2 = LOONGARCH64Instr_FpLoad(LAfpload_FLDX_D, am, rreg); + } + break; + case HRcVec128: + if (offsetB < 1024) { + am = LOONGARCH64AMode_RI(hregGSP(), offsetB); + *i1 = LOONGARCH64Instr_VecLoad(LAvecload_VLD, am, rreg); + } else { + am = LOONGARCH64AMode_RR(hregGSP(), hregT0()); + *i1 = LOONGARCH64Instr_LI(offsetB, hregT0()); + *i2 = LOONGARCH64Instr_VecLoad(LAvecload_VLDX, am, rreg); + } + break; + default: + ppHRegClass(hregClass(rreg)); + vpanic("genReload_LOONGARCH64: unimplemented regclass"); + break; + } +} + +/* Generate loongarch64 move instructions under the direction of the + register allocator. */ +LOONGARCH64Instr* genMove_LOONGARCH64 ( HReg from, HReg to, Bool mode64 ) +{ + vassert(mode64 == True); + switch (hregClass(from)) { + case HRcInt64: + return LOONGARCH64Instr_Binary(LAbin_OR, + LOONGARCH64RI_R(hregZERO()), + from, to); + case HRcFlt64: + return LOONGARCH64Instr_FpMove(LAfpmove_FMOV_D, from, to); + case HRcVec128: + return LOONGARCH64Instr_VecBinary(LAvecbin_VORI_B, + LOONGARCH64RI_I(0, 8, False), + from, to); + default: + ppHRegClass(hregClass(from)); + vpanic("genMove_LOONGARCH64: unimplemented regclass"); + } +} + + +/* --------- The loongarch64 assembler --------- */ + +static inline UInt iregEnc ( HReg r ) +{ + vassert(hregClass(r) == HRcInt64); + vassert(!hregIsVirtual(r)); + UInt n = hregEncoding(r); + vassert(n < 32); + return n; +} + +static inline UInt fregEnc ( HReg r ) +{ + vassert(hregClass(r) == HRcFlt64); + vassert(!hregIsVirtual(r)); + UInt n = hregEncoding(r); + vassert(n < 32); + return n; +} + +static inline UInt vregEnc ( HReg r ) +{ + vassert(hregClass(r) == HRcVec128); + vassert(!hregIsVirtual(r)); + UInt n = hregEncoding(r); + vassert(n < 32); + return n; +} + +static inline UInt fcsrEnc ( HReg r ) +{ + vassert(hregClass(r) == HRcInt32); + vassert(!hregIsVirtual(r)); + UInt n = hregEncoding(r); + vassert(n < 32); + return n; +} + +static inline UInt emit_op_rj_rd ( UInt op, UInt rj, UInt rd ) +{ + vassert(rj < (1 << 5)); + vassert(rd < (1 << 5)); + return op | (rj << 5) | rd; +} + +static inline UInt emit_op_rk_rj_rd ( UInt op, UInt rk, UInt rj, UInt rd ) +{ + vassert(rk < (1 << 5)); + vassert(rj < (1 << 5)); + vassert(rd < (1 << 5)); + return op | (rk << 10) | (rj << 5) | rd; +} + +static inline UInt emit_op_fj_fd ( UInt op, UInt fj, UInt fd ) +{ + vassert(fj < (1 << 5)); + vassert(fd < (1 << 5)); + return op | (fj << 5) | fd; +} + +static inline UInt emit_op_fa_fk_fj_fd ( UInt op, UInt fa, UInt fk, UInt fj, UInt fd ) +{ + vassert(fa < (1 << 5)); + vassert(fk < (1 << 5)); + vassert(fj < (1 << 5)); + vassert(fd < (1 << 5)); + return op | (fa << 15) | (fk << 10) | (fj << 5) | fd; +} + +static inline UInt emit_op_fk_fj_fd ( UInt op, UInt fk, UInt fj, UInt fd ) +{ + vassert(fk < (1 << 5)); + vassert(fj < (1 << 5)); + vassert(fd < (1 << 5)); + return op | (fk << 10) | (fj << 5) | fd; +} + +static inline UInt emit_op_ca_fk_fj_fd ( UInt op, UInt ca, UInt fk, UInt fj, UInt fd ) +{ + vassert(ca < (1 << 3)); + vassert(fk < (1 << 5)); + vassert(fj < (1 << 5)); + vassert(fd < (1 << 5)); + return op | (ca << 15) | (fk << 10) | (fj << 5) | fd; +} + +static inline UInt emit_op_fk_fj_cd ( UInt op, UInt fk, UInt fj, UInt cd ) +{ + vassert(fk < (1 << 5)); + vassert(fj < (1 << 5)); + vassert(cd < (1 << 3)); + return op | (fk << 10) | (fj << 5) | cd; +} + +static inline UInt emit_op_cj_rd ( UInt op, UInt cj, UInt rd ) +{ + vassert(cj < (1 << 3)); + vassert(rd < (1 << 5)); + return op | (cj << 5) | rd; +} + +static inline UInt emit_op_rj_cd ( UInt op, UInt rj, UInt cd ) +{ + vassert(rj < (1 << 5)); + vassert(cd < (1 << 3)); + return op | (rj << 5) | cd; +} + +static inline UInt emit_op_rj_fd ( UInt op, UInt rj, UInt fd ) +{ + vassert(rj < (1 << 5)); + vassert(fd < (1 << 5)); + return op | (rj << 5) | fd; +} + +static inline UInt emit_op_fj_rd ( UInt op, UInt fj, UInt rd ) +{ + vassert(fj < (1 << 5)); + vassert(rd < (1 << 5)); + return op | (fj << 5) | rd; +} + +static inline UInt emit_op_rj_fcsr ( UInt op, UInt rj, UInt fcsr ) +{ + vassert(rj < (1 << 5)); + vassert(fcsr < (1 << 5)); + return op | (rj << 5) | fcsr; +} + +static inline UInt emit_op_fcsr_rd ( UInt op, UInt fcsr, UInt rd ) +{ + vassert(fcsr < (1 << 5)); + vassert(rd < (1 << 5)); + return op | (fcsr << 5) | rd; +} + +static inline UInt emit_op_ui5_rj_rd ( UInt op, UInt ui5, UInt rj, UInt rd ) +{ + vassert(ui5 < (1 << 5)); + vassert(rj < (1 << 5)); + vassert(rd < (1 << 5)); + return op | (ui5 << 10) | (rj << 5) | rd; +} + +static inline UInt emit_op_ui6_rj_rd ( UInt op, UInt ui6, UInt rj, UInt rd ) +{ + vassert(ui6 < (1 << 6)); + vassert(rj < (1 << 5)); + vassert(rd < (1 << 5)); + return op | (ui6 << 10) | (rj << 5) | rd; +} + +static inline UInt emit_op_ui12_rj_rd ( UInt op, UInt ui12, UInt rj, UInt rd ) +{ + vassert(ui12 < (1 << 12)); + vassert(rj < (1 << 5)); + vassert(rd < (1 << 5)); + return op | (ui12 << 10) | (rj << 5) | rd; +} + +static inline UInt emit_op_si12_rj_rd ( UInt op, UInt si12, UInt rj, UInt rd ) +{ + vassert(si12 < (1 << 12)); + vassert(rj < (1 << 5)); + vassert(rd < (1 << 5)); + return op | (si12 << 10) | (rj << 5) | rd; +} + +static inline UInt emit_op_si14_rj_rd ( UInt op, UInt si14, UInt rj, UInt rd ) +{ + vassert(si14 < (1 << 14)); + vassert(rj < (1 << 5)); + vassert(rd < (1 << 5)); + return op | (si14 << 10) | (rj << 5) | rd; +} + +static inline UInt emit_op_si20_rd ( UInt op, UInt si20, UInt rd ) +{ + vassert(si20 < (1 << 20)); + vassert(rd < (1 << 5)); + return op | (si20 << 5) | rd; +} + +static inline UInt emit_op_offs16_rj_rd ( UInt op, UInt offs16, UInt rj, UInt rd ) +{ + vassert(offs16 < (1 << 16)); + vassert(rj < (1 << 5)); + vassert(rd < (1 << 5)); + return op | (offs16 << 10) | (rj << 5) | rd; +} + +static inline UInt emit_op_offs26 ( UInt op, UInt offs26 ) +{ + vassert(offs26 < (1 << 26)); + return op | ((offs26 & 0xffff) << 10) | (offs26 >> 16); +} + +static inline UInt emit_op_hint15 ( UInt op, UInt hint ) +{ + vassert(hint < (1 << 15)); + return op | hint; +} + +static inline UInt emit_op_si12_rj_vd ( UInt op, UInt si12, UInt rj, UInt vd ) +{ + vassert(si12 < (1 << 12)); + vassert(rj < (1 << 5)); + vassert(vd < (1 << 5)); + return op | (si12 << 10) | (rj << 5) | vd; +} + +static inline UInt emit_op_rk_rj_vd ( UInt op, UInt rk, UInt rj, UInt vd ) +{ + vassert(rk < (1 << 5)); + vassert(rj < (1 << 5)); + vassert(vd < (1 << 5)); + return op | (rk << 10) | (rj << 5) | vd; +} + +static inline UInt emit_unop_r ( UInt op, Int src, UInt dst, UInt dst_size) +{ + vassert(src < (1 << 5)); + vassert(dst < (1 << dst_size)); + return op | (src << 5) | dst; +} + +static inline UInt emit_binop_rr ( UInt op, UInt src2, UInt src1, UInt dst ) +{ + vassert(src2 < (1 << 5)); + vassert(src1 < (1 << 5)); + vassert(dst < (1 << 5)); + return op | (src2 << 10) | (src1 << 5) | dst; +} + +static inline UInt emit_binop_ri ( UInt op, UInt imm, UInt size, UInt src, UInt dst ) +{ + vassert(imm < (1 << size)); + vassert(src < (1 << 5)); + vassert(dst < (1 << 5)); + return op | (imm << 10) | (src << 5) | dst; +} + + +static UInt* mkLoadImm_EXACTLY4 ( UInt* p, HReg dst, ULong imm ) +{ + /* + lu12i.w dst, imm[31:12] + ori dst, dst, imm[11:0] + lu32i.d dst, imm[51:32] + lu52i.d dst, dst, imm[63:52] + */ + UInt d = iregEnc(dst); + *p++ = emit_op_si20_rd(LAextra_LU12I_W, (imm >> 12) & 0xfffff, d); + *p++ = emit_op_si12_rj_rd(LAbin_ORI, imm & 0xfff, d, d); + *p++ = emit_op_si20_rd(LAextra_LU32I_D, (imm >> 32) & 0xfffff, d); + *p++ = emit_op_si12_rj_rd(LAextra_LU52I_D, (imm >> 52) & 0xfff, d, d); + return p; +} + +static inline UInt* mkLoadImm_EXACTLY2 ( UInt* p, HReg dst, ULong imm ) +{ + /* + lu12i.w dst, imm[31:12] + ori dst, dst, imm[11:0] + */ + UInt d = iregEnc(dst); + *p++ = emit_op_si20_rd(LAextra_LU12I_W, (imm >> 12) & 0xfffff, d); + *p++ = emit_op_si12_rj_rd(LAbin_ORI, imm & 0xfff, d, d); + return p; +} + +static inline UInt* mkLoadImm_EXACTLY1 ( UInt* p, HReg dst, ULong imm ) +{ + /* ori dst, $zero, imm[11:0] */ + *p++ = emit_op_si12_rj_rd(LAbin_ORI, imm, 0, iregEnc(dst)); + return p; +} + +static UInt* mkLoadImm ( UInt* p, HReg dst, ULong imm ) +{ + if ((imm >> 12) == 0) + p = mkLoadImm_EXACTLY1(p, dst, imm); + else if (imm < 0x80000000 || (imm >> 31) == 0x1ffffffffUL) + p = mkLoadImm_EXACTLY2(p, dst, imm); + else + p = mkLoadImm_EXACTLY4(p, dst, imm); + return p; +} + +static Bool is_LoadImm_EXACTLY4 ( UInt* p, HReg dst, ULong imm ) +{ + UInt expect[4]; + mkLoadImm_EXACTLY4(expect, dst, imm); + return toBool(p[0] == expect[0] && p[1] == expect[1] && + p[2] == expect[2] && p[3] == expect[3]); +} + +static inline UInt* mkUnary ( UInt* p, LOONGARCH64UnOp op, HReg src, HReg dst ) +{ + switch (op) { + case LAun_CLZ_W: + case LAun_CTZ_W: + case LAun_CLZ_D: + case LAun_CTZ_D: + case LAun_EXT_W_H: + case LAun_EXT_W_B: + *p++ = emit_op_rj_rd(op, iregEnc(src), iregEnc(dst)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkBinary ( UInt* p, LOONGARCH64BinOp op, + LOONGARCH64RI* src2, HReg src1, HReg dst ) +{ + switch (op) { + case LAbin_ADD_W: + case LAbin_ADD_D: + case LAbin_SUB_W: + case LAbin_SUB_D: + case LAbin_NOR: + case LAbin_AND: + case LAbin_OR: + case LAbin_XOR: + case LAbin_SLL_W: + case LAbin_SRL_W: + case LAbin_SRA_W: + case LAbin_SLL_D: + case LAbin_SRL_D: + case LAbin_SRA_D: + case LAbin_MUL_W: + case LAbin_MUL_D: + case LAbin_MULH_W: + case LAbin_MULH_WU: + case LAbin_MULH_D: + case LAbin_MULH_DU: + case LAbin_MULW_D_W: + case LAbin_MULW_D_WU: + case LAbin_DIV_W: + case LAbin_MOD_W: + case LAbin_DIV_WU: + case LAbin_MOD_WU: + case LAbin_DIV_D: + case LAbin_MOD_D: + case LAbin_DIV_DU: + case LAbin_MOD_DU: + vassert(src2->tag == LAri_Reg); + *p++ = emit_op_rk_rj_rd(op, iregEnc(src2->LAri.R.reg), + iregEnc(src1), iregEnc(dst)); + return p; + case LAbin_SLLI_W: + case LAbin_SRLI_W: + case LAbin_SRAI_W: + vassert(src2->tag == LAri_Imm); + *p++ = emit_op_ui5_rj_rd(op, src2->LAri.I.imm, + iregEnc(src1), iregEnc(dst)); + return p; + case LAbin_SLLI_D: + case LAbin_SRLI_D: + case LAbin_SRAI_D: + vassert(src2->tag == LAri_Imm); + *p++ = emit_op_ui6_rj_rd(op, src2->LAri.I.imm, + iregEnc(src1), iregEnc(dst)); + return p; + case LAbin_ADDI_W: + case LAbin_ADDI_D: + vassert(src2->tag == LAri_Imm); + *p++ = emit_op_si12_rj_rd(op, src2->LAri.I.imm, + iregEnc(src1), iregEnc(dst)); + return p; + case LAbin_ANDI: + case LAbin_ORI: + case LAbin_XORI: + vassert(src2->tag == LAri_Imm); + *p++ = emit_op_ui12_rj_rd(op, src2->LAri.I.imm, + iregEnc(src1), iregEnc(dst)); + return p; + default: + return NULL; + } +} + +static UInt* mkLoad ( UInt* p, LOONGARCH64LoadOp op, + LOONGARCH64AMode* src, HReg dst ) +{ + switch (op) { + case LAload_LD_W: + case LAload_LD_D: + case LAload_LD_BU: + case LAload_LD_HU: + case LAload_LD_WU: + vassert(src->tag == LAam_RI); + *p++ = emit_op_si12_rj_rd(op, src->LAam.RI.index, + iregEnc(src->LAam.RI.base), iregEnc(dst)); + return p; + case LAload_LDX_D: + case LAload_LDX_BU: + case LAload_LDX_HU: + case LAload_LDX_WU: + vassert(src->tag == LAam_RR); + *p++ = emit_op_rk_rj_rd(op, iregEnc(src->LAam.RR.index), + iregEnc(src->LAam.RR.base), iregEnc(dst)); + return p; + default: + return NULL; + } +} + +static UInt* mkStore ( UInt* p, LOONGARCH64StoreOp op, + LOONGARCH64AMode* dst, HReg src ) +{ + switch (op) { + case LAstore_ST_B: + case LAstore_ST_H: + case LAstore_ST_W: + case LAstore_ST_D: + vassert(dst->tag == LAam_RI); + *p++ = emit_op_si12_rj_rd(op, dst->LAam.RI.index, + iregEnc(dst->LAam.RI.base), iregEnc(src)); + return p; + case LAstore_STX_B: + case LAstore_STX_H: + case LAstore_STX_W: + case LAstore_STX_D: + vassert(dst->tag == LAam_RR); + *p++ = emit_op_rk_rj_rd(op, iregEnc(dst->LAam.RR.index), + iregEnc(dst->LAam.RR.base), iregEnc(src)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkLLSC ( UInt* p, LOONGARCH64LLSCOp op, + LOONGARCH64AMode* addr, HReg val ) +{ + switch (op) { + case LAllsc_LL_W: + case LAllsc_SC_W: + case LAllsc_LL_D: + case LAllsc_SC_D: + vassert(addr->tag == LAam_RI); + *p++ = emit_op_si14_rj_rd(op, addr->LAam.RI.index, + iregEnc(addr->LAam.RI.base), iregEnc(val)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkBar ( UInt* p, LOONGARCH64BarOp op, UShort hint ) +{ + switch (op) { + case LAbar_DBAR: + case LAbar_IBAR: + *p++ = emit_op_hint15(op, hint); + return p; + default: + return NULL; + } +} + +static inline UInt* mkFpUnary ( UInt* p, LOONGARCH64FpUnOp op, HReg src, HReg dst ) +{ + switch (op) { + case LAfpun_FABS_S: + case LAfpun_FABS_D: + case LAfpun_FNEG_S: + case LAfpun_FNEG_D: + case LAfpun_FLOGB_S: + case LAfpun_FLOGB_D: + case LAfpun_FSQRT_S: + case LAfpun_FSQRT_D: + case LAfpun_FRSQRT_S: + case LAfpun_FRSQRT_D: + case LAfpun_FCVT_S_D: + case LAfpun_FCVT_D_S: + case LAfpun_FTINT_W_S: + case LAfpun_FTINT_W_D: + case LAfpun_FTINT_L_S: + case LAfpun_FTINT_L_D: + case LAfpun_FFINT_S_W: + case LAfpun_FFINT_S_L: + case LAfpun_FFINT_D_W: + case LAfpun_FFINT_D_L: + case LAfpun_FRINT_S: + case LAfpun_FRINT_D: + *p++ = emit_op_fj_fd(op, fregEnc(src), fregEnc(dst)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkFpBinary ( UInt* p, LOONGARCH64FpBinOp op, HReg src2, + HReg src1, HReg dst ) +{ + switch (op) { + case LAfpbin_FADD_S: + case LAfpbin_FADD_D: + case LAfpbin_FSUB_S: + case LAfpbin_FSUB_D: + case LAfpbin_FMUL_S: + case LAfpbin_FMUL_D: + case LAfpbin_FDIV_S: + case LAfpbin_FDIV_D: + case LAfpbin_FMAX_S: + case LAfpbin_FMAX_D: + case LAfpbin_FMIN_S: + case LAfpbin_FMIN_D: + case LAfpbin_FMAXA_S: + case LAfpbin_FMAXA_D: + case LAfpbin_FMINA_S: + case LAfpbin_FMINA_D: + case LAfpbin_FSCALEB_S: + case LAfpbin_FSCALEB_D: + *p++ = emit_op_fk_fj_fd(op, fregEnc(src2), fregEnc(src1), fregEnc(dst)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkFpTrinary ( UInt* p, LOONGARCH64FpTriOp op, HReg src3, + HReg src2, HReg src1, HReg dst ) +{ + switch (op) { + case LAfpbin_FMADD_S: + case LAfpbin_FMADD_D: + case LAfpbin_FMSUB_S: + case LAfpbin_FMSUB_D: + *p++ = emit_op_fa_fk_fj_fd(op, fregEnc(src3), fregEnc(src2), + fregEnc(src1), fregEnc(dst)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkFpLoad ( UInt* p, LOONGARCH64FpLoadOp op, + LOONGARCH64AMode* src, HReg dst ) +{ + switch (op) { + case LAfpload_FLD_S: + case LAfpload_FLD_D: + vassert(src->tag == LAam_RI); + *p++ = emit_op_si12_rj_rd(op, src->LAam.RI.index, + iregEnc(src->LAam.RI.base), fregEnc(dst)); + return p; + case LAfpload_FLDX_S: + case LAfpload_FLDX_D: + vassert(src->tag == LAam_RR); + *p++ = emit_op_rk_rj_rd(op, iregEnc(src->LAam.RR.index), + iregEnc(src->LAam.RR.base), fregEnc(dst)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkFpStore ( UInt* p, LOONGARCH64FpStoreOp op, + LOONGARCH64AMode* dst, HReg src ) +{ + switch (op) { + case LAfpstore_FST_S: + case LAfpstore_FST_D: + vassert(dst->tag == LAam_RI); + *p++ = emit_op_si12_rj_rd(op, dst->LAam.RI.index, + iregEnc(dst->LAam.RI.base), fregEnc(src)); + return p; + case LAfpstore_FSTX_S: + case LAfpstore_FSTX_D: + vassert(dst->tag == LAam_RR); + *p++ = emit_op_rk_rj_rd(op, iregEnc(dst->LAam.RR.index), + iregEnc(dst->LAam.RR.base), fregEnc(src)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkFpMove ( UInt* p, LOONGARCH64FpMoveOp op, HReg src, HReg dst ) +{ + switch (op) { + case LAfpmove_FMOV_S: + case LAfpmove_FMOV_D: + *p++ = emit_op_fj_fd(op, fregEnc(src), fregEnc(dst)); + return p; + case LAfpmove_MOVGR2FR_W: + case LAfpmove_MOVGR2FR_D: + *p++ = emit_op_rj_fd(op, iregEnc(src), fregEnc(dst)); + return p; + case LAfpmove_MOVFR2GR_S: + case LAfpmove_MOVFR2GR_D: + *p++ = emit_op_fj_rd(op, fregEnc(src), iregEnc(dst)); + return p; + case LAfpmove_MOVGR2FCSR: + *p++ = emit_op_rj_fcsr(op, iregEnc(src), fcsrEnc(dst)); + return p; + case LAfpmove_MOVFCSR2GR: + *p++ = emit_op_fcsr_rd(op, fcsrEnc(src), iregEnc(dst)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkFpCmp ( UInt* p, LOONGARCH64FpCmpOp op, HReg src2, + HReg src1, HReg dst ) +{ + /* + fcmp.cond.[sd] $fcc0, src1, src2 + movcf2gr dst, $fcc0 + */ + switch (op) { + case LAfpcmp_FCMP_CLT_S: + case LAfpcmp_FCMP_CLT_D: + case LAfpcmp_FCMP_CEQ_S: + case LAfpcmp_FCMP_CEQ_D: + case LAfpcmp_FCMP_CUN_S: + case LAfpcmp_FCMP_CUN_D: + *p++ = emit_op_fk_fj_cd(op, fregEnc(src2), fregEnc(src1), 0); + *p++ = emit_op_cj_rd(LAextra_MOVCF2GR, 0, iregEnc(dst)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkVecUnary ( UInt* p, LOONGARCH64VecUnOp op, HReg src, HReg dst ) +{ + switch (op) { + case LAvecun_VCLO_B: + case LAvecun_VCLO_H: + case LAvecun_VCLO_W: + case LAvecun_VCLZ_B: + case LAvecun_VCLZ_H: + case LAvecun_VCLZ_W: + case LAvecun_VCLZ_D: + case LAvecun_VPCNT_B: + case LAvecun_VEXTH_H_B: + case LAvecun_VEXTH_W_H: + case LAvecun_VEXTH_D_W: + case LAvecun_VEXTH_Q_D: + case LAvecun_VEXTH_HU_BU: + case LAvecun_VEXTH_WU_HU: + case LAvecun_VEXTH_DU_WU: + case LAvecun_VEXTH_QU_DU: + *p++ = emit_unop_r(op, vregEnc(src), vregEnc(dst), 5); + return p; + case LAvecun_VREPLGR2VR_B: + case LAvecun_VREPLGR2VR_H: + case LAvecun_VREPLGR2VR_W: + case LAvecun_VREPLGR2VR_D: + *p++ = emit_unop_r(op, iregEnc(src), vregEnc(dst), 5); + return p; + default: + return NULL; + } +} + +static inline UInt* mkVecBinary ( UInt* p, LOONGARCH64VecBinOp op, + LOONGARCH64RI* src2, HReg src1, HReg dst ) +{ + switch (op) { + case LAvecbin_VSEQ_B: + case LAvecbin_VSEQ_H: + case LAvecbin_VSEQ_W: + case LAvecbin_VSEQ_D: + case LAvecbin_VSLT_B: + case LAvecbin_VSLT_H: + case LAvecbin_VSLT_W: + case LAvecbin_VSLT_D: + case LAvecbin_VSLT_BU: + case LAvecbin_VSLT_HU: + case LAvecbin_VSLT_WU: + case LAvecbin_VSLT_DU: + case LAvecbin_VADD_B: + case LAvecbin_VADD_H: + case LAvecbin_VADD_D: + case LAvecbin_VADD_W: + case LAvecbin_VSUB_B: + case LAvecbin_VSUB_H: + case LAvecbin_VSUB_W: + case LAvecbin_VSUB_D: + case LAvecbin_VSADD_B: + case LAvecbin_VSADD_H: + case LAvecbin_VSADD_W: + case LAvecbin_VSADD_D: + case LAvecbin_VSSUB_B: + case LAvecbin_VSSUB_H: + case LAvecbin_VSSUB_W: + case LAvecbin_VSSUB_D: + case LAvecbin_VSADD_BU: + case LAvecbin_VSADD_HU: + case LAvecbin_VSADD_WU: + case LAvecbin_VSADD_DU: + case LAvecbin_VSSUB_BU: + case LAvecbin_VSSUB_HU: + case LAvecbin_VSSUB_WU: + case LAvecbin_VSSUB_DU: + case LAvecbin_VADDA_B: + case LAvecbin_VADDA_H: + case LAvecbin_VADDA_W: + case LAvecbin_VADDA_D: + case LAvecbin_VAVGR_B: + case LAvecbin_VAVGR_H: + case LAvecbin_VAVGR_W: + case LAvecbin_VAVGR_D: + case LAvecbin_VAVGR_BU: + case LAvecbin_VAVGR_HU: + case LAvecbin_VAVGR_WU: + case LAvecbin_VAVGR_DU: + case LAvecbin_VMAX_B: + case LAvecbin_VMAX_H: + case LAvecbin_VMAX_W: + case LAvecbin_VMAX_D: + case LAvecbin_VMIN_B: + case LAvecbin_VMIN_H: + case LAvecbin_VMIN_W: + case LAvecbin_VMIN_D: + case LAvecbin_VMAX_BU: + case LAvecbin_VMAX_HU: + case LAvecbin_VMAX_WU: + case LAvecbin_VMAX_DU: + case LAvecbin_VMIN_BU: + case LAvecbin_VMIN_HU: + case LAvecbin_VMIN_WU: + case LAvecbin_VMIN_DU: + case LAvecbin_VMUL_B: + case LAvecbin_VMUL_H: + case LAvecbin_VMUL_W: + case LAvecbin_VMUH_B: + case LAvecbin_VMUH_H: + case LAvecbin_VMUH_W: + case LAvecbin_VMUH_BU: + case LAvecbin_VMUH_HU: + case LAvecbin_VMUH_WU: + case LAvecbin_VSLL_B: + case LAvecbin_VSLL_H: + case LAvecbin_VSLL_W: + case LAvecbin_VSLL_D: + case LAvecbin_VSRL_B: + case LAvecbin_VSRL_H: + case LAvecbin_VSRL_W: + case LAvecbin_VSRL_D: + case LAvecbin_VSRA_B: + case LAvecbin_VSRA_H: + case LAvecbin_VSRA_W: + case LAvecbin_VSRA_D: + case LAvecbin_VILVL_B: + case LAvecbin_VILVL_H: + case LAvecbin_VILVL_W: + case LAvecbin_VILVL_D: + case LAvecbin_VILVH_B: + case LAvecbin_VILVH_H: + case LAvecbin_VILVH_W: + case LAvecbin_VILVH_D: + case LAvecbin_VPICKEV_B: + case LAvecbin_VPICKEV_H: + case LAvecbin_VPICKEV_W: + case LAvecbin_VPICKOD_B: + case LAvecbin_VPICKOD_H: + case LAvecbin_VPICKOD_W: + case LAvecbin_VAND_V: + case LAvecbin_VOR_V: + case LAvecbin_VXOR_V: + case LAvecbin_VNOR_V: + case LAvecbin_VADD_Q: + case LAvecbin_VSUB_Q: + case LAvecbin_VFADD_S: + case LAvecbin_VFADD_D: + case LAvecbin_VFSUB_S: + case LAvecbin_VFSUB_D: + case LAvecbin_VFMUL_S: + case LAvecbin_VFMUL_D: + case LAvecbin_VFDIV_S: + case LAvecbin_VFDIV_D: + case LAvecbin_VFMAX_S: + case LAvecbin_VFMAX_D: + case LAvecbin_VFMIN_S: + case LAvecbin_VFMIN_D: + vassert(src2->tag == LAri_Reg); + *p++ = emit_binop_rr(op, vregEnc(src2->LAri.R.reg), vregEnc(src1), vregEnc(dst)); + return p; + case LAvecbin_VREPLVE_B: + case LAvecbin_VREPLVE_H: + case LAvecbin_VREPLVE_W: + case LAvecbin_VREPLVE_D: + vassert(src2->tag == LAri_Reg); + *p++ = emit_binop_rr(op, iregEnc(src2->LAri.R.reg), vregEnc(src1), vregEnc(dst)); + return p; + case LAvecbin_VINSGR2VR_D: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 1, iregEnc(src1), vregEnc(dst)); + return p; + case LAvecbin_VPICKVE2GR_D: + case LAvecbin_VPICKVE2GR_DU: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 1, vregEnc(src1), iregEnc(dst)); + return p; + case LAvecbin_VINSGR2VR_W: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 2, iregEnc(src1), vregEnc(dst)); + return p; + case LAvecbin_VPICKVE2GR_W: + case LAvecbin_VPICKVE2GR_WU: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 2, vregEnc(src1), iregEnc(dst)); + return p; + case LAvecbin_VSLLI_B: + case LAvecbin_VSRLI_B: + case LAvecbin_VSRAI_B: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 3, vregEnc(src1), vregEnc(dst)); + return p; + case LAvecbin_VINSGR2VR_H: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 3, iregEnc(src1), vregEnc(dst)); + return p; + case LAvecbin_VPICKVE2GR_HU: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 3, vregEnc(src1), iregEnc(dst)); + return p; + case LAvecbin_VSLLI_H: + case LAvecbin_VSRLI_H: + case LAvecbin_VSRAI_H: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 4, vregEnc(src1), vregEnc(dst)); + return p; + case LAvecbin_VINSGR2VR_B: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 4, iregEnc(src1), vregEnc(dst)); + return p; + case LAvecbin_VPICKVE2GR_BU: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 4, vregEnc(src1), iregEnc(dst)); + return p; + case LAvecbin_VBSLL_V: + case LAvecbin_VBSRL_V: + case LAvecbin_VSLLI_W: + case LAvecbin_VSRLI_W: + case LAvecbin_VSRAI_W: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 5, vregEnc(src1), vregEnc(dst)); + return p; + case LAvecbin_VSLLI_D: + case LAvecbin_VSRLI_D: + case LAvecbin_VSRAI_D: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 6, vregEnc(src1), vregEnc(dst)); + return p; + case LAvecbin_VORI_B: + vassert(src2->tag == LAri_Imm); + *p++ = emit_binop_ri(op, src2->LAri.I.imm, 8, vregEnc(src1), vregEnc(dst)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkVecLoad ( UInt* p, LOONGARCH64VecLoadOp op, + LOONGARCH64AMode* src, HReg dst ) +{ + switch (op) { + case LAvecload_VLD: + vassert(src->tag == LAam_RI); + *p++ = emit_op_si12_rj_vd(op, src->LAam.RI.index, + iregEnc(src->LAam.RI.base), vregEnc(dst)); + return p; + case LAvecload_VLDX: + vassert(src->tag == LAam_RR); + *p++ = emit_op_rk_rj_rd(op, iregEnc(src->LAam.RR.index), + iregEnc(src->LAam.RR.base), vregEnc(dst)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkVecStore ( UInt* p, LOONGARCH64VecStoreOp op, + LOONGARCH64AMode* dst, HReg src ) +{ + switch (op) { + case LAvecstore_VST: + vassert(dst->tag == LAam_RI); + *p++ = emit_op_si12_rj_vd(op, dst->LAam.RI.index, + iregEnc(dst->LAam.RI.base), vregEnc(src)); + return p; + case LAvecstore_VSTX: + vassert(dst->tag == LAam_RR); + *p++ = emit_op_rk_rj_vd(op, iregEnc(dst->LAam.RR.index), + iregEnc(dst->LAam.RR.base), vregEnc(src)); + return p; + default: + return NULL; + } +} + +static inline UInt* mkCas ( UInt* p, HReg old, HReg addr, HReg expd, + HReg data, Bool size64 ) +{ + /* + ll.[wd] old, addr, 0 + bne old, expd, barrier + or $t0, data, $zero + sc.[wd] $t0, addr, 0 + beq $t0, zero, fail + or old, expd, $zero + b end + barrier: + dbar 0 + fail: + or old, data, $zero + end: + */ + UInt o = iregEnc(old); + UInt a = iregEnc(addr); + UInt e = iregEnc(expd); + UInt d = iregEnc(data); + UInt t = 12; + UInt z = 0; + + if (size64) { + *p++ = emit_op_si14_rj_rd(LAllsc_LL_D, 0, a, o); + } else { + *p++ = emit_op_ui6_rj_rd(LAbin_SLLI_W, 0, e, e); // Sign-extend expd + *p++ = emit_op_si14_rj_rd(LAllsc_LL_W, 0, a, o); + } + *p++ = emit_op_offs16_rj_rd(LAextra_BNE, 6, o, e); + *p++ = emit_op_rk_rj_rd(LAbin_OR, z, d, t); + if (size64) { + *p++ = emit_op_si14_rj_rd(LAllsc_SC_D, 0, a, t); + } else { + *p++ = emit_op_si14_rj_rd(LAllsc_SC_W, 0, a, t); + } + *p++ = emit_op_offs16_rj_rd(LAextra_BEQ, 4, t, z); + *p++ = emit_op_rk_rj_rd(LAbin_OR, z, e, o); + *p++ = emit_op_offs26(LAextra_B, 3); + *p++ = emit_op_hint15(LAbar_DBAR, 0); + *p++ = emit_op_rk_rj_rd(LAbin_OR, z, d, o); + return p; +} + +static inline UInt* mkCmp ( UInt* p, LOONGARCH64CondCode cond, + HReg src2, HReg src1, HReg dst ) +{ + UInt d = iregEnc(dst); + UInt s1 = iregEnc(src1); + UInt s2 = iregEnc(src2); + + switch (cond) { + case LAcc_EQ: + /* + xor dst, src1, src2 + sltui dst, dst, 1 + */ + *p++ = emit_op_rk_rj_rd(LAbin_XOR, s2, s1, d); + *p++ = emit_op_si12_rj_rd(LAextra_SLTUI, 1, d, d); + return p; + case LAcc_NE: + /* + xor dst, src1, src2 + sltu dst, $zero, dst + */ + *p++ = emit_op_rk_rj_rd(LAbin_XOR, s2, s1, d); + *p++ = emit_op_rk_rj_rd(LAextra_SLTU, d, 0, d); + return p; + case LAcc_LT: + /* slt dst, src1, src2 */ + *p++ = emit_op_rk_rj_rd(LAextra_SLT, s2, s1, d); + return p; + case LAcc_GE: + /* + slt dst, src1, src2 + sltui dst, dst, 1 + */ + *p++ = emit_op_rk_rj_rd(LAextra_SLT, s2, s1, d); + *p++ = emit_op_si12_rj_rd(LAextra_SLTUI, 1, d, d); + return p; + case LAcc_LTU: + /* sltu dst, src1, src2 */ + *p++ = emit_op_rk_rj_rd(LAextra_SLTU, s2, s1, d); + return p; + case LAcc_GEU: + /* + sltu dst, src1, src2 + sltui dst, dst, 1 + */ + *p++ = emit_op_rk_rj_rd(LAextra_SLTU, s2, s1, d); + *p++ = emit_op_si12_rj_rd(LAextra_SLTUI, 1, d, d); + return p; + /* No LAcc_AL here. + case LAcc_AL: + break; + */ + default: + return NULL; + } +} + +static inline UInt* mkCMove ( UInt* p, HReg cond, HReg r0, + HReg r1, HReg dst, Bool isInt ) +{ + if (isInt) { + /* + masknez $t0, r0, cond + maskeqz dst, r1, cond + or dst, $t0, dst + */ + UInt c = iregEnc(cond); + UInt d = iregEnc(dst); + *p++ = emit_op_rk_rj_rd(LAextra_MASKNEZ, c, iregEnc(r0), 12); + *p++ = emit_op_rk_rj_rd(LAextra_MASKEQZ, c, iregEnc(r1), d); + *p++ = emit_op_rk_rj_rd(LAbin_OR, d, 12, d); + } else { + /* + movgr2cf $fcc0, cond + fsel dst, r0, r1, $fcc0 + */ + *p++ = emit_op_rj_cd(LAextra_MOVGR2CF, iregEnc(cond), 0); + *p++ = emit_op_ca_fk_fj_fd(LAextra_FSEL, 0, fregEnc(r1), + fregEnc(r0), fregEnc(dst)); + } + return p; +} + +static inline UInt* mkCall ( UInt* p, HReg cond, Addr64 target, RetLoc rloc ) +{ + if (!hregIsInvalid(cond) && rloc.pri != RLPri_None) { + /* The call might not happen (it isn't unconditional) and + it returns a result. In this case we will need to + generate a control flow diamond to put 0x555..555 in + the return register(s) in the case where the call + doesn't happen. If this ever becomes necessary, maybe + copy code from the 32-bit ARM equivalent. Until that + day, just give up. */ + return NULL; + } + + UInt* ptmp = NULL; + if (!hregIsInvalid(cond)) { + /* Create a hole to put a conditional branch in. We'll + patch it once we know the branch length. */ + ptmp = p; + p++; + } + + /* + $t0 = target + jirl $ra, $t0, 0 + */ + p = mkLoadImm(p, hregT0(), target); + *p++ = emit_op_offs16_rj_rd(LAextra_JIRL, 0, 12, 1); + + /* Patch the hole if necessary */ + if (!hregIsInvalid(cond)) { + vassert(ptmp != NULL); + UInt offs = (UInt)(p - ptmp); + vassert(offs >= 3 && offs <= 6); + /* beq cond, $zero, offs */ + *ptmp++ = emit_op_offs16_rj_rd(LAextra_BEQ, offs, iregEnc(cond), 0); + } + + return p; +} + +static inline UInt* mkXDirect ( UInt* p, Addr64 dstGA, + LOONGARCH64AMode* amPC, + HReg cond, Bool toFastEP, + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP ) +{ + /* NB: what goes on here has to be very closely coordinated + with chainXDirect_LOONGARCH64 and unchainXDirect_LOONGARCH64 below. */ + /* We're generating chain-me requests here, so we need to be + sure this is actually allowed -- no-redir translations + can't use chain-me's. Hence: */ + vassert(disp_cp_chain_me_to_slowEP != NULL); + vassert(disp_cp_chain_me_to_fastEP != NULL); + + /* Use ptmp for backpatching conditional jumps. */ + UInt* ptmp = NULL; + + /* First off, if this is conditional, create a conditional + jump over the rest of it. Or at least, leave a space for + it that we will shortly fill in. */ + if (!hregIsInvalid(cond)) { + ptmp = p; + p++; + } + + /* Update the guest PC. + $t0 = dstGA + st.d $t0, amPC + */ + p = mkLoadImm(p, hregT0(), (ULong)dstGA); + p = mkStore(p, LAstore_ST_D, amPC, hregT0()); + + /* --- FIRST PATCHABLE BYTE follows --- */ + /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're + calling to) backs up the return address, so as to find the + address of the first patchable byte. So: don't change the + number of instructions (5) below. */ + /* + la $t0, VG_(disp_cp_chain_me_to_{slowEP,fastEP}) + jirl $ra, $t0, 0 + */ + const void* disp_cp_chain_me = toFastEP ? disp_cp_chain_me_to_fastEP + : disp_cp_chain_me_to_slowEP; + p = mkLoadImm_EXACTLY4(p, hregT0(), (ULong)(Addr)disp_cp_chain_me); + *p++ = emit_op_offs16_rj_rd(LAextra_JIRL, 0, 12, 1); + /* --- END of PATCHABLE BYTES --- */ + + /* Fix up the conditional jump, if there was one. */ + if (!hregIsInvalid(cond)) { + vassert(ptmp != NULL); + UInt offs = (UInt)(p - ptmp); + vassert(offs >= 8 && offs <= 11); + /* beq cond, $zero, offs */ + *ptmp++ = emit_op_offs16_rj_rd(LAextra_BEQ, offs, iregEnc(cond), 0); + } + + return p; +} + +static inline UInt* mkXIndir ( UInt* p, HReg dstGA, LOONGARCH64AMode* amPC, + HReg cond, const void* disp_cp_xindir ) +{ + /* We're generating transfers that could lead indirectly to a + chain-me, so we need to be sure this is actually allowed -- + no-redir translations are not allowed to reach normal + translations without going through the scheduler. That means + no XDirects or XIndirs out from no-redir translations. + Hence: */ + vassert(disp_cp_xindir != NULL); + + /* Use ptmp for backpatching conditional jumps. */ + UInt* ptmp = NULL; + + /* First off, if this is conditional, create a conditional + jump over the rest of it. */ + if (!hregIsInvalid(cond)) { + ptmp = p; + p++; + } + + /* Update the guest PC. + or $t0, dstGA, $zero + st.d $t0, amPC + */ + *p++ = emit_op_rk_rj_rd(LAbin_OR, 0, iregEnc(dstGA), 12); + p = mkStore(p, LAstore_ST_D, amPC, hregT0()); + + /* + la $t0, VG_(disp_cp_xindir) + jirl $ra, $t0, 0 + */ + p = mkLoadImm(p, hregT0(), (ULong)(Addr)disp_cp_xindir); + *p++ = emit_op_offs16_rj_rd(LAextra_JIRL, 0, 12, 1); + + /* Fix up the conditional jump, if there was one. */ + if (!hregIsInvalid(cond)) { + vassert(ptmp != NULL); + UInt offs = (UInt)(p - ptmp); + vassert(offs >= 5 && offs <= 8); + /* beq cond, $zero, offs */ + *ptmp++ = emit_op_offs16_rj_rd(LAextra_BEQ, offs, iregEnc(cond), 0); + } + + return p; +} + +static inline UInt* mkXAssisted ( UInt* p, HReg dstGA, LOONGARCH64AMode* amPC, + HReg cond, IRJumpKind jk, + const void* disp_cp_xassisted ) +{ + /* First off, if this is conditional, create a conditional jump + over the rest of it. Or at least, leave a space for it that + we will shortly fill in. */ + UInt* ptmp = NULL; + if (!hregIsInvalid(cond)) { + ptmp = p; + p++; + } + + /* Update the guest PC. + or $t0, dstGA, $zero + st.d $t0, amPC + */ + *p++ = emit_op_rk_rj_rd(LAbin_OR, 0, iregEnc(dstGA), 12); + p = mkStore(p, LAstore_ST_D, amPC, hregT0()); + + /* li.w $s8, magic_number */ + UInt trcval = 0; + switch (jk) { + case Ijk_Boring: + trcval = VEX_TRC_JMP_BORING; + break; + case Ijk_ClientReq: + trcval = VEX_TRC_JMP_CLIENTREQ; + break; + case Ijk_NoDecode: + trcval = VEX_TRC_JMP_NODECODE; + break; + case Ijk_InvalICache: + trcval = VEX_TRC_JMP_INVALICACHE; + break; + case Ijk_NoRedir: + trcval = VEX_TRC_JMP_NOREDIR; + break; + case Ijk_SigTRAP: + trcval = VEX_TRC_JMP_SIGTRAP; + break; + case Ijk_SigSEGV: + trcval = VEX_TRC_JMP_SIGSEGV; + break; + case Ijk_SigBUS: + trcval = VEX_TRC_JMP_SIGBUS; + break; + case Ijk_SigFPE_IntDiv: + trcval = VEX_TRC_JMP_SIGFPE_INTDIV; + break; + case Ijk_SigFPE_IntOvf: + trcval = VEX_TRC_JMP_SIGFPE_INTOVF; + break; + case Ijk_SigSYS: + trcval = VEX_TRC_JMP_SIGSYS; + break; + case Ijk_Sys_syscall: + trcval = VEX_TRC_JMP_SYS_SYSCALL; + break; + /* We don't expect to see the following being assisted. + case Ijk_Call: + case Ijk_Ret: + case Ijk_Yield: + case Ijk_EmWarn: + case Ijk_EmFail: + case Ijk_MapFail: + case Ijk_FlushDCache: + case Ijk_SigILL: + case Ijk_SigFPE: + case Ijk_Sys_int32: + case Ijk_Sys_int128: + case Ijk_Sys_int129: + case Ijk_Sys_int130: + case Ijk_Sys_int145: + case Ijk_Sys_int210: + case Ijk_Sys_sysenter: + */ + default: + ppIRJumpKind(jk); + vpanic("emit_LOONGARCH64Instr.LAin_XAssisted: unexpected jump kind"); + } + vassert(trcval != 0); + p = mkLoadImm(p, hregGSP(), trcval); + + /* + la $t0, VG_(disp_cp_xassisted) + jirl $ra, $t0, 0 + */ + p = mkLoadImm(p, hregT0(), (ULong)(Addr)disp_cp_xassisted); + *p++ = emit_op_offs16_rj_rd(LAextra_JIRL, 0, 12, 1); + + /* Fix up the conditional jump, if there was one. */ + if (!hregIsInvalid(cond)) { + vassert(ptmp != NULL); + UInt offs = (UInt)(p - ptmp); + vassert(offs >= 6 && offs <= 12); + /* beq cond, $zero, offs */ + *ptmp++ = emit_op_offs16_rj_rd(LAextra_BEQ, offs, iregEnc(cond), 0); + } + + return p; +} + +static inline UInt* mkEvCheck ( UInt* p, LOONGARCH64AMode* amCounter, + LOONGARCH64AMode* amFailAddr ) +{ + UInt* p0 = p; + + /* + ld.w $t0, amCounter + addi.d $t0, $t0, -1 + st.w $t0, amCounter + bge $t0, $zero, nofail + ld.d $t0, amFailAddr + jirl $ra, $t0, 0 + nofail: + */ + p = mkLoad(p, LAload_LD_W, amCounter, hregT0()); + *p++ = emit_op_si12_rj_rd(LAbin_ADDI_D, -1 & 0xfff, 12, 12); + p = mkStore(p, LAstore_ST_W, amCounter, hregT0()); + *p++ = emit_op_offs16_rj_rd(LAextra_BGE, 3, 12, 0); + p = mkLoad(p, LAload_LD_W, amFailAddr, hregT0()); + *p++ = emit_op_offs16_rj_rd(LAextra_JIRL, 0, 12, 1); + + /* Crosscheck */ + vassert(evCheckSzB_LOONGARCH64() == (UChar*)p - (UChar*)p0); + return p; +} + +static inline UInt* mkProfInc ( UInt* p ) +{ + /* + li $t0, 0x6555755585559555UL + ld.d $t1, $t0, 0 + addi.d $t1, $t1, 1 + st.d $t1, $t0, 0 + */ + p = mkLoadImm_EXACTLY4(p, hregT0(), 0x6555755585559555UL); + *p++ = emit_op_si12_rj_rd(LAload_LD_D, 0, 12, 13); + *p++ = emit_op_si12_rj_rd(LAbin_ADDI_D, 1, 13, 13); + *p++ = emit_op_si12_rj_rd(LAstore_ST_D, 0, 12, 13); + return p; +} + +/* Emit an instruction into buf and return the number of bytes used. + Note that buf is not the insn's final place, and therefore it is + imperative to emit position-independent code. If the emitted + instruction was a profiler inc, set *is_profInc to True, else + leave it unchanged. */ +Int emit_LOONGARCH64Instr ( /*MB_MOD*/Bool* is_profInc, + UChar* buf, + Int nbuf, + const LOONGARCH64Instr* i, + Bool mode64, + VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ) +{ + vassert(mode64 == True); + + UInt* p = (UInt*)buf; + vassert(nbuf >= 32); + vassert((((HWord)buf) & 3) == 0); + + switch (i->tag) { + case LAin_LI: + p = mkLoadImm(p, i->LAin.LI.dst, i->LAin.LI.imm); + break; + case LAin_Un: + p = mkUnary(p, i->LAin.Unary.op, i->LAin.Unary.src, + i->LAin.Unary.dst); + break; + case LAin_Bin: + p = mkBinary(p, i->LAin.Binary.op, i->LAin.Binary.src2, + i->LAin.Binary.src1, i->LAin.Binary.dst); + break; + case LAin_Load: + p = mkLoad(p, i->LAin.Load.op, i->LAin.Load.src, + i->LAin.Load.dst); + break; + case LAin_Store: + p = mkStore(p, i->LAin.Store.op, i->LAin.Store.dst, + i->LAin.Store.src); + break; + case LAin_LLSC: + p = mkLLSC(p, i->LAin.LLSC.op, i->LAin.LLSC.addr, i->LAin.LLSC.val); + break; + case LAin_Bar: + p = mkBar(p, i->LAin.Bar.op, i->LAin.Bar.hint); + break; + case LAin_FpUn: + p = mkFpUnary(p, i->LAin.FpUnary.op, i->LAin.FpUnary.src, + i->LAin.FpUnary.dst); + break; + case LAin_FpBin: + p = mkFpBinary(p, i->LAin.FpBinary.op, i->LAin.FpBinary.src2, + i->LAin.FpBinary.src1, i->LAin.FpBinary.dst); + break; + case LAin_FpTri: + p = mkFpTrinary(p, i->LAin.FpTrinary.op, i->LAin.FpTrinary.src3, + i->LAin.FpTrinary.src2, i->LAin.FpTrinary.src1, + i->LAin.FpTrinary.dst); + break; + case LAin_FpLoad: + p = mkFpLoad(p, i->LAin.FpLoad.op, i->LAin.FpLoad.src, + i->LAin.FpLoad.dst); + break; + case LAin_FpStore: + p = mkFpStore(p, i->LAin.FpStore.op, i->LAin.FpStore.dst, + i->LAin.FpStore.src); + break; + case LAin_FpMove: + p = mkFpMove(p, i->LAin.FpMove.op, i->LAin.FpMove.src, + i->LAin.FpMove.dst); + break; + case LAin_FpCmp: + p = mkFpCmp(p, i->LAin.FpCmp.op, i->LAin.FpCmp.src2, + i->LAin.FpCmp.src1, i->LAin.FpCmp.dst); + break; + case LAin_VecUn: + p = mkVecUnary(p, i->LAin.VecUnary.op, i->LAin.VecUnary.src, + i->LAin.VecUnary.dst); + break; + case LAin_VecBin: + p = mkVecBinary(p, i->LAin.VecBinary.op, i->LAin.VecBinary.src2, + i->LAin.VecBinary.src1, i->LAin.VecBinary.dst); + break; + case LAin_VecLoad: + p = mkVecLoad(p, i->LAin.VecLoad.op, i->LAin.VecLoad.src, + i->LAin.VecLoad.dst); + break; + case LAin_VecStore: + p = mkVecStore(p, i->LAin.VecStore.op, i->LAin.VecStore.dst, + i->LAin.VecStore.src); + break; + case LAin_Cas: + p = mkCas(p, i->LAin.Cas.old, i->LAin.Cas.addr, i->LAin.Cas.expd, + i->LAin.Cas.data, i->LAin.Cas.size64); + break; + case LAin_Cmp: + p = mkCmp(p, i->LAin.Cmp.cond, i->LAin.Cmp.src2, + i->LAin.Cmp.src1, i->LAin.Cmp.dst); + break; + case LAin_CMove: + p = mkCMove(p, i->LAin.CMove.cond, i->LAin.CMove.r0, + i->LAin.CMove.r1, i->LAin.CMove.dst, + i->LAin.CMove.isInt); + break; + case LAin_Call: + p = mkCall(p, i->LAin.Call.cond, i->LAin.Call.target, + i->LAin.Call.rloc); + break; + case LAin_XDirect: + p = mkXDirect(p, i->LAin.XDirect.dstGA, i->LAin.XDirect.amPC, + i->LAin.XDirect.cond, i->LAin.XDirect.toFastEP, + disp_cp_chain_me_to_slowEP, + disp_cp_chain_me_to_fastEP); + break; + case LAin_XIndir: + p = mkXIndir(p, i->LAin.XIndir.dstGA, i->LAin.XIndir.amPC, + i->LAin.XIndir.cond, disp_cp_xindir); + break; + case LAin_XAssisted: + p = mkXAssisted(p, i->LAin.XAssisted.dstGA, i->LAin.XAssisted.amPC, + i->LAin.XAssisted.cond, i->LAin.XAssisted.jk, + disp_cp_xassisted); + break; + case LAin_EvCheck: + p = mkEvCheck(p, i->LAin.EvCheck.amCounter, + i->LAin.EvCheck.amFailAddr); + break; + case LAin_ProfInc: + p = mkProfInc(p); + break; + default: + p = NULL; + break; + } + + if (p == NULL) { + ppLOONGARCH64Instr(i, True); + vpanic("emit_LOONGARCH64Instr"); + /*NOTREACHED*/ + } + + vassert(((UChar*)p) - &buf[0] <= 48); + return ((UChar*)p) - &buf[0]; +} + +/* How big is an event check? See case for mkEvCheck just above. That + crosschecks what this returns, so we can tell if we're inconsistent. */ +Int evCheckSzB_LOONGARCH64 ( void ) +{ + return 6 * 4; // 6 insns +} + +/* NB: what goes on here has to be very closely coordinated with the + emitInstr case for XDirect, above. */ +VexInvalRange chainXDirect_LOONGARCH64 ( VexEndness endness_host, + void* place_to_chain, + const void* disp_cp_chain_me_EXPECTED, + const void* place_to_jump_to ) +{ + vassert(endness_host == VexEndnessLE); + + /* What we're expecting to see is: + * la $t0, disp_cp_chain_me_to_EXPECTED + * jirl $ra, $t0, 0 + * viz + * <16 bytes generated by mkLoadImm_EXACTLY4> + * jirl $ra, $t0, 0 + */ + UInt* p = (UInt*)place_to_chain; + vassert(((HWord)p & 3) == 0); + vassert(is_LoadImm_EXACTLY4(p, hregT0(), (ULong)(Addr)disp_cp_chain_me_EXPECTED)); + vassert(p[4] == emit_op_offs16_rj_rd(LAextra_JIRL, 0, 12, 1)); + + /* And what we want to change it to is: + * la $t0, place_to_jump_to + * jirl $ra, $t0, 0 + * viz + * <16 bytes generated by mkLoadImm_EXACTLY4> + * jirl $ra, $t0, 0 + * + * The replacement has the same length as the original. + */ + p = mkLoadImm_EXACTLY4(p, hregT0(), (ULong)(Addr)place_to_jump_to); + *p++ = emit_op_offs16_rj_rd(LAextra_JIRL, 0, 12, 1); + + VexInvalRange vir = { (HWord)place_to_chain, 4 * 4 + 4 }; + return vir; +} + +/* NB: what goes on here has to be very closely coordinated with the + emitInstr case for XDirect, above. */ +VexInvalRange unchainXDirect_LOONGARCH64 ( VexEndness endness_host, + void* place_to_unchain, + const void* place_to_jump_to_EXPECTED, + const void* disp_cp_chain_me ) +{ + vassert(endness_host == VexEndnessLE); + + /* What we're expecting to see is: + * la $t0, place_to_jump_to_EXPECTED + * jirl $ra, $t0, 0 + * viz + * <16 bytes generated by mkLoadImm_EXACTLY4> + * jirl $ra, $t0, 0 + */ + UInt* p = (UInt*)place_to_unchain; + vassert(((HWord)p & 3) == 0); + vassert(is_LoadImm_EXACTLY4(p, hregT0(), (ULong)(Addr)place_to_jump_to_EXPECTED)); + vassert(p[4] == emit_op_offs16_rj_rd(LAextra_JIRL, 0, 12, 1)); + + /* And what we want to change it to is: + * la $t0, disp_cp_chain_me + * jirl $ra, $t0, 0 + * viz + * <16 bytes generated by mkLoadImm_EXACTLY4> + * jirl $ra, $t0, 0 + * + * The replacement has the same length as the original. + */ + p = mkLoadImm_EXACTLY4(p, hregT0(), (ULong)(Addr)disp_cp_chain_me); + *p++ = emit_op_offs16_rj_rd(LAextra_JIRL, 0, 12, 1); + + VexInvalRange vir = { (HWord)place_to_unchain, 4 * 4 + 4 }; + return vir; +} + +/* Patch the counter address into a profile inc point, as previously + created by the mkProfInc. */ +VexInvalRange patchProfInc_LOONGARCH64 ( VexEndness endness_host, + void* place_to_patch, + const ULong* location_of_counter ) +{ + vassert(endness_host == VexEndnessLE); + vassert(sizeof(ULong*) == 8); + + /* + $t0 = NotKnownYet + ld.d $t1, $t0, 0 + addi.d $t1, $t1, 1 + st.d $t1, $t0, 0 + */ + UInt* p = (UInt*)place_to_patch; + vassert(((HWord)p & 3) == 0); + vassert(is_LoadImm_EXACTLY4(p, hregT0(), 0x6555755585559555UL)); + vassert(p[4] == emit_op_si12_rj_rd(LAload_LD_D, 0, 12, 13)); + vassert(p[5] == emit_op_si12_rj_rd(LAbin_ADDI_D, 1, 13, 13)); + vassert(p[6] == emit_op_si12_rj_rd(LAstore_ST_D, 0, 12, 13)); + + p = mkLoadImm_EXACTLY4(p, hregT0(), (ULong)(Addr)location_of_counter); + + VexInvalRange vir = { (HWord)place_to_patch, 4 * 4 }; + return vir; +} + + +/*---------------------------------------------------------------*/ +/*--- end host_loongarch64_defs.c ---*/ +/*---------------------------------------------------------------*/ diff --git a/VEX/priv/host_loongarch64_defs.h b/VEX/priv/host_loongarch64_defs.h new file mode 100644 index 0000000..acf38b1 --- /dev/null +++ b/VEX/priv/host_loongarch64_defs.h @@ -0,0 +1,919 @@ + +/*---------------------------------------------------------------*/ +/*--- begin host_loongarch64_defs.h ---*/ +/*---------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#ifndef __VEX_HOST_LOONGARCH64_DEFS_H +#define __VEX_HOST_LOONGARCH64_DEFS_H + +#include "libvex_basictypes.h" +#include "libvex.h" /* VexArch */ +#include "host_generic_regs.h" /* HReg */ + + +/* --------- Registers. --------- */ + +#define ST_IN static inline + +/* Integer static registers */ +ST_IN HReg hregLOONGARCH64_R23 ( void ) { return mkHReg(False, HRcInt64, 23, 0); } +ST_IN HReg hregLOONGARCH64_R24 ( void ) { return mkHReg(False, HRcInt64, 24, 1); } +ST_IN HReg hregLOONGARCH64_R25 ( void ) { return mkHReg(False, HRcInt64, 25, 2); } +ST_IN HReg hregLOONGARCH64_R26 ( void ) { return mkHReg(False, HRcInt64, 26, 3); } +ST_IN HReg hregLOONGARCH64_R27 ( void ) { return mkHReg(False, HRcInt64, 27, 4); } +ST_IN HReg hregLOONGARCH64_R28 ( void ) { return mkHReg(False, HRcInt64, 28, 5); } +ST_IN HReg hregLOONGARCH64_R29 ( void ) { return mkHReg(False, HRcInt64, 29, 6); } +ST_IN HReg hregLOONGARCH64_R30 ( void ) { return mkHReg(False, HRcInt64, 30, 7); } +/* $r31 is used as guest stack pointer */ + +/* Integer temporary registers */ +/* $r12 is used as a chaining/ProfInc/Cmove/genSpill/genReload temporary */ +/* $r13 is used as a ProfInc temporary */ +ST_IN HReg hregLOONGARCH64_R14 ( void ) { return mkHReg(False, HRcInt64, 14, 8); } +ST_IN HReg hregLOONGARCH64_R15 ( void ) { return mkHReg(False, HRcInt64, 15, 9); } +ST_IN HReg hregLOONGARCH64_R16 ( void ) { return mkHReg(False, HRcInt64, 16, 10); } +ST_IN HReg hregLOONGARCH64_R17 ( void ) { return mkHReg(False, HRcInt64, 17, 11); } +ST_IN HReg hregLOONGARCH64_R18 ( void ) { return mkHReg(False, HRcInt64, 18, 12); } +ST_IN HReg hregLOONGARCH64_R19 ( void ) { return mkHReg(False, HRcInt64, 19, 13); } +ST_IN HReg hregLOONGARCH64_R20 ( void ) { return mkHReg(False, HRcInt64, 20, 14); } + +/* Floating point static registers */ +ST_IN HReg hregLOONGARCH64_F24 ( void ) { return mkHReg(False, HRcFlt64, 24, 15); } +ST_IN HReg hregLOONGARCH64_F25 ( void ) { return mkHReg(False, HRcFlt64, 25, 16); } +ST_IN HReg hregLOONGARCH64_F26 ( void ) { return mkHReg(False, HRcFlt64, 26, 17); } +ST_IN HReg hregLOONGARCH64_F27 ( void ) { return mkHReg(False, HRcFlt64, 27, 18); } +ST_IN HReg hregLOONGARCH64_F28 ( void ) { return mkHReg(False, HRcFlt64, 28, 19); } +ST_IN HReg hregLOONGARCH64_F29 ( void ) { return mkHReg(False, HRcFlt64, 29, 20); } +ST_IN HReg hregLOONGARCH64_F30 ( void ) { return mkHReg(False, HRcFlt64, 30, 21); } +ST_IN HReg hregLOONGARCH64_F31 ( void ) { return mkHReg(False, HRcFlt64, 31, 22); } + +/* Vector static registers */ +ST_IN HReg hregLOONGARCH64_V24 ( void ) { return mkHReg(False, HRcVec128, 24, 23); } +ST_IN HReg hregLOONGARCH64_V25 ( void ) { return mkHReg(False, HRcVec128, 25, 24); } +ST_IN HReg hregLOONGARCH64_V26 ( void ) { return mkHReg(False, HRcVec128, 26, 25); } +ST_IN HReg hregLOONGARCH64_V27 ( void ) { return mkHReg(False, HRcVec128, 27, 26); } +ST_IN HReg hregLOONGARCH64_V28 ( void ) { return mkHReg(False, HRcVec128, 28, 27); } +ST_IN HReg hregLOONGARCH64_V29 ( void ) { return mkHReg(False, HRcVec128, 29, 28); } +ST_IN HReg hregLOONGARCH64_V30 ( void ) { return mkHReg(False, HRcVec128, 30, 29); } +ST_IN HReg hregLOONGARCH64_V31 ( void ) { return mkHReg(False, HRcVec128, 31, 30); } + +/* Other Integer registers */ +ST_IN HReg hregLOONGARCH64_R0 ( void ) { return mkHReg(False, HRcInt64, 0, 31); } +ST_IN HReg hregLOONGARCH64_R1 ( void ) { return mkHReg(False, HRcInt64, 1, 32); } +ST_IN HReg hregLOONGARCH64_R2 ( void ) { return mkHReg(False, HRcInt64, 2, 33); } +ST_IN HReg hregLOONGARCH64_R3 ( void ) { return mkHReg(False, HRcInt64, 3, 34); } +ST_IN HReg hregLOONGARCH64_R4 ( void ) { return mkHReg(False, HRcInt64, 4, 35); } +ST_IN HReg hregLOONGARCH64_R5 ( void ) { return mkHReg(False, HRcInt64, 5, 36); } +ST_IN HReg hregLOONGARCH64_R6 ( void ) { return mkHReg(False, HRcInt64, 6, 37); } +ST_IN HReg hregLOONGARCH64_R7 ( void ) { return mkHReg(False, HRcInt64, 7, 38); } +ST_IN HReg hregLOONGARCH64_R8 ( void ) { return mkHReg(False, HRcInt64, 8, 39); } +ST_IN HReg hregLOONGARCH64_R9 ( void ) { return mkHReg(False, HRcInt64, 9, 40); } +ST_IN HReg hregLOONGARCH64_R10 ( void ) { return mkHReg(False, HRcInt64, 10, 41); } +ST_IN HReg hregLOONGARCH64_R11 ( void ) { return mkHReg(False, HRcInt64, 11, 42); } +ST_IN HReg hregLOONGARCH64_R12 ( void ) { return mkHReg(False, HRcInt64, 12, 43); } +ST_IN HReg hregLOONGARCH64_R13 ( void ) { return mkHReg(False, HRcInt64, 13, 44); } +ST_IN HReg hregLOONGARCH64_R21 ( void ) { return mkHReg(False, HRcInt64, 21, 45); } +ST_IN HReg hregLOONGARCH64_R22 ( void ) { return mkHReg(False, HRcInt64, 22, 46); } +ST_IN HReg hregLOONGARCH64_R31 ( void ) { return mkHReg(False, HRcInt64, 31, 47); } + +/* Special registers */ +ST_IN HReg hregLOONGARCH64_FCSR3 ( void ) { return mkHReg(False, HRcInt32, 3, 48); } + +#undef ST_IN + +#define hregZERO() hregLOONGARCH64_R0() +#define hregSP() hregLOONGARCH64_R3() +#define hregT0() hregLOONGARCH64_R12() +#define hregT1() hregLOONGARCH64_R13() +#define hregGSP() hregLOONGARCH64_R31() + +extern UInt ppHRegLOONGARCH64 ( HReg reg ); + +/* Number of registers used arg passing in function calls */ +#define LOONGARCH64_N_ARGREGS 8 /* a0 ... a7 */ + + +/* --------- Condition codes, LOONGARCH64 encoding. --------- */ +typedef enum { + LAcc_EQ = 0, /* equal */ + LAcc_NE = 1, /* not equal */ + + LAcc_LT = 2, /* less than (signed) */ + LAcc_GE = 3, /* great equal (signed) */ + + LAcc_LTU = 4, /* less than (unsigned) */ + LAcc_GEU = 5, /* great equal (unsigned) */ + + LAcc_AL = 6 /* always (unconditional) */ +} LOONGARCH64CondCode; + + +/* --------- Memory address expressions (amodes). --------- */ + +typedef enum { + LAam_RI, /* Reg + Imm (signed 12-bit) */ + LAam_RR /* Reg1 + Reg2 */ +} LOONGARCH64AModeTag; + +typedef struct { + LOONGARCH64AModeTag tag; + union { + struct { + HReg base; + UShort index; + } RI; + struct { + HReg base; + HReg index; + } RR; + } LAam; +} LOONGARCH64AMode; + +extern LOONGARCH64AMode* LOONGARCH64AMode_RI ( HReg reg, UShort imm ); +extern LOONGARCH64AMode* LOONGARCH64AMode_RR ( HReg base, HReg index ); + + +/* --------- Operand, which can be reg or imm. --------- */ + +typedef enum { + LAri_Reg, + LAri_Imm +} LOONGARCH64RITag; + +typedef struct { + LOONGARCH64RITag tag; + union { + struct { + HReg reg; + } R; + struct { + UShort imm; + UChar size; // size == 5 || size == 6 || size == 12 + Bool isSigned; + } I; + } LAri; +} LOONGARCH64RI; + +extern LOONGARCH64RI* LOONGARCH64RI_R ( HReg reg ); +extern LOONGARCH64RI* LOONGARCH64RI_I ( UShort imm, UChar size, Bool isSigned ); + + +/* --------- Instructions. --------- */ + +/* Tags for unary operations */ +typedef enum { + LAun_CLZ_W = 0x00001400, + LAun_CTZ_W = 0x00001c00, + LAun_CLZ_D = 0x00002400, + LAun_CTZ_D = 0x00002c00, + LAun_EXT_W_H = 0x00005800, + LAun_EXT_W_B = 0x00005c00 +} LOONGARCH64UnOp; + +/* Tags for binary operations */ +typedef enum { + LAbin_ADD_W = 0x00100000, + LAbin_ADD_D = 0x00108000, + LAbin_SUB_W = 0x00110000, + LAbin_SUB_D = 0x00118000, + LAbin_NOR = 0x00140000, + LAbin_AND = 0x00148000, + LAbin_OR = 0x00150000, + LAbin_XOR = 0x00158000, + LAbin_SLL_W = 0x00170000, + LAbin_SRL_W = 0x00178000, + LAbin_SRA_W = 0x00180000, + LAbin_SLL_D = 0x00188000, + LAbin_SRL_D = 0x00190000, + LAbin_SRA_D = 0x00198000, + LAbin_MUL_W = 0x001c0000, + LAbin_MUL_D = 0x001d8000, + LAbin_MULH_W = 0x001c8000, + LAbin_MULH_WU = 0x001d0000, + LAbin_MULH_D = 0x001e0000, + LAbin_MULH_DU = 0x001e8000, + LAbin_MULW_D_W = 0x001f0000, + LAbin_MULW_D_WU = 0x001f8000, + LAbin_DIV_W = 0x00200000, + LAbin_MOD_W = 0x00208000, + LAbin_DIV_WU = 0x00210000, + LAbin_MOD_WU = 0x00218000, + LAbin_DIV_D = 0x00220000, + LAbin_MOD_D = 0x00228000, + LAbin_DIV_DU = 0x00230000, + LAbin_MOD_DU = 0x00238000, + LAbin_SLLI_W = 0x00408000, + LAbin_SLLI_D = 0x00410000, + LAbin_SRLI_W = 0x00448000, + LAbin_SRLI_D = 0x00450000, + LAbin_SRAI_W = 0x00488000, + LAbin_SRAI_D = 0x00490000, + LAbin_ADDI_W = 0x02800000, + LAbin_ADDI_D = 0x02c00000, + LAbin_ANDI = 0x03400000, + LAbin_ORI = 0x03800000, + LAbin_XORI = 0x03c00000 +} LOONGARCH64BinOp; + +/* Tags for load operations */ +typedef enum { + LAload_LD_W = 0x28800000, + LAload_LD_D = 0x28c00000, + LAload_LD_BU = 0x2a000000, + LAload_LD_HU = 0x2a400000, + LAload_LD_WU = 0x2a800000, + LAload_LDX_D = 0x380c0000, + LAload_LDX_BU = 0x38200000, + LAload_LDX_HU = 0x38240000, + LAload_LDX_WU = 0x38280000 +} LOONGARCH64LoadOp; + +/* Tags for store operations */ +typedef enum { + LAstore_ST_B = 0x29000000, + LAstore_ST_H = 0x29400000, + LAstore_ST_W = 0x29800000, + LAstore_ST_D = 0x29c00000, + LAstore_STX_B = 0x38100000, + LAstore_STX_H = 0x38140000, + LAstore_STX_W = 0x38180000, + LAstore_STX_D = 0x381c0000 +} LOONGARCH64StoreOp; + +/* Tags for ll/sc operations */ +typedef enum { + LAllsc_LL_W = 0x20000000, + LAllsc_SC_W = 0x21000000, + LAllsc_LL_D = 0x22000000, + LAllsc_SC_D = 0x23000000 +} LOONGARCH64LLSCOp; + +/* Tags for barrier operations */ +typedef enum { + LAbar_DBAR = 0x38720000, + LAbar_IBAR = 0x38728000 +} LOONGARCH64BarOp; + +/* Tags for floating point unary operations */ +typedef enum { + LAfpun_FABS_S = 0x01140400, + LAfpun_FABS_D = 0x01140800, + LAfpun_FNEG_S = 0x01141400, + LAfpun_FNEG_D = 0x01141800, + LAfpun_FLOGB_S = 0x01142400, + LAfpun_FLOGB_D = 0x01142800, + LAfpun_FSQRT_S = 0x01144400, + LAfpun_FSQRT_D = 0x01144800, + LAfpun_FRSQRT_S = 0x01146400, + LAfpun_FRSQRT_D = 0x01146800, + LAfpun_FCVT_S_D = 0x01191800, + LAfpun_FCVT_D_S = 0x01192400, + LAfpun_FTINT_W_S = 0x011b0400, + LAfpun_FTINT_W_D = 0x011b0800, + LAfpun_FTINT_L_S = 0x011b2400, + LAfpun_FTINT_L_D = 0x011b2800, + LAfpun_FFINT_S_W = 0x011d1000, + LAfpun_FFINT_S_L = 0x011d1800, + LAfpun_FFINT_D_W = 0x011d2000, + LAfpun_FFINT_D_L = 0x011d2800, + LAfpun_FRINT_S = 0x011e4400, + LAfpun_FRINT_D = 0x011e4800 +} LOONGARCH64FpUnOp; + +/* Tags for floating point binary operations */ +typedef enum { + LAfpbin_FADD_S = 0x01008000, + LAfpbin_FADD_D = 0x01010000, + LAfpbin_FSUB_S = 0x01028000, + LAfpbin_FSUB_D = 0x01030000, + LAfpbin_FMUL_S = 0x01048000, + LAfpbin_FMUL_D = 0x01050000, + LAfpbin_FDIV_S = 0x01068000, + LAfpbin_FDIV_D = 0x01070000, + LAfpbin_FMAX_S = 0x01088000, + LAfpbin_FMAX_D = 0x01090000, + LAfpbin_FMIN_S = 0x010a8000, + LAfpbin_FMIN_D = 0x010b0000, + LAfpbin_FMAXA_S = 0x010c8000, + LAfpbin_FMAXA_D = 0x010d0000, + LAfpbin_FMINA_S = 0x010e8000, + LAfpbin_FMINA_D = 0x010f0000, + LAfpbin_FSCALEB_S = 0x01108000, + LAfpbin_FSCALEB_D = 0x01110000 +} LOONGARCH64FpBinOp; + +/* Tags for floating point trinary operations */ +typedef enum { + LAfpbin_FMADD_S = 0x08100000, + LAfpbin_FMADD_D = 0x08200000, + LAfpbin_FMSUB_S = 0x08500000, + LAfpbin_FMSUB_D = 0x08600000 +} LOONGARCH64FpTriOp; + +/* Tags for floating point load operations */ +typedef enum { + LAfpload_FLD_S = 0x2b000000, + LAfpload_FLD_D = 0x2b800000, + LAfpload_FLDX_S = 0x38300000, + LAfpload_FLDX_D = 0x38340000 +} LOONGARCH64FpLoadOp; + +/* Tags for floating point store operations */ +typedef enum { + LAfpstore_FST_S = 0x2b400000, + LAfpstore_FST_D = 0x2bc00000, + LAfpstore_FSTX_S = 0x38380000, + LAfpstore_FSTX_D = 0x383c0000 +} LOONGARCH64FpStoreOp; + +/* Tags for floating point move operations */ +typedef enum { + LAfpmove_FMOV_S = 0x01149400, + LAfpmove_FMOV_D = 0x01149800, + LAfpmove_MOVGR2FR_W = 0x0114a400, + LAfpmove_MOVGR2FR_D = 0x0114a800, + LAfpmove_MOVFR2GR_S = 0x0114b400, + LAfpmove_MOVFR2GR_D = 0x0114b800, + LAfpmove_MOVGR2FCSR = 0x0114c000, + LAfpmove_MOVFCSR2GR = 0x0114c800 +} LOONGARCH64FpMoveOp; + +/* Tags for floating point compare operations */ +typedef enum { + LAfpcmp_FCMP_CLT_S = 0x0c110000, + LAfpcmp_FCMP_CLT_D = 0x0c210000, + LAfpcmp_FCMP_CEQ_S = 0x0c120000, + LAfpcmp_FCMP_CEQ_D = 0x0c220000, + LAfpcmp_FCMP_CUN_S = 0x0c140000, + LAfpcmp_FCMP_CUN_D = 0x0c240000 +} LOONGARCH64FpCmpOp; + +/* Tags for vector unary operations */ +typedef enum { + LAvecun_VCLO_B = 0x729c0000, + LAvecun_VCLO_H = 0x729c0400, + LAvecun_VCLO_W = 0x729c0800, + LAvecun_VCLZ_B = 0x729c1000, + LAvecun_VCLZ_H = 0x729c1400, + LAvecun_VCLZ_W = 0x729c1800, + LAvecun_VCLZ_D = 0x729c1c00, + LAvecun_VPCNT_B = 0x729c2000, + LAvecun_VEXTH_H_B = 0x729ee000, + LAvecun_VEXTH_W_H = 0x729ee400, + LAvecun_VEXTH_D_W = 0x729ee800, + LAvecun_VEXTH_Q_D = 0x729eec00, + LAvecun_VEXTH_HU_BU = 0x729ef000, + LAvecun_VEXTH_WU_HU = 0x729ef400, + LAvecun_VEXTH_DU_WU = 0x729ef800, + LAvecun_VEXTH_QU_DU = 0x729efc00, + LAvecun_VREPLGR2VR_B = 0x729f0000, + LAvecun_VREPLGR2VR_H = 0x729f0400, + LAvecun_VREPLGR2VR_W = 0x729f0800, + LAvecun_VREPLGR2VR_D = 0x729f0c00 +} LOONGARCH64VecUnOp; + +/* Tags for vector binary operations */ +typedef enum { + LAvecbin_VSEQ_B = 0x70000000, + LAvecbin_VSEQ_H = 0x70008000, + LAvecbin_VSEQ_W = 0x70010000, + LAvecbin_VSEQ_D = 0x70018000, + LAvecbin_VSLT_B = 0x70060000, + LAvecbin_VSLT_H = 0x70068000, + LAvecbin_VSLT_W = 0x70070000, + LAvecbin_VSLT_D = 0x70078000, + LAvecbin_VSLT_BU = 0x70080000, + LAvecbin_VSLT_HU = 0x70088000, + LAvecbin_VSLT_WU = 0x70090000, + LAvecbin_VSLT_DU = 0x70098000, + LAvecbin_VADD_B = 0x700a0000, + LAvecbin_VADD_H = 0x700a8000, + LAvecbin_VADD_W = 0x700b0000, + LAvecbin_VADD_D = 0x700b8000, + LAvecbin_VSUB_B = 0x700c0000, + LAvecbin_VSUB_H = 0x700c8000, + LAvecbin_VSUB_W = 0x700d0000, + LAvecbin_VSUB_D = 0x700d8000, + LAvecbin_VSADD_B = 0x70460000, + LAvecbin_VSADD_H = 0x70468000, + LAvecbin_VSADD_W = 0x70470000, + LAvecbin_VSADD_D = 0x70478000, + LAvecbin_VSSUB_B = 0x70480000, + LAvecbin_VSSUB_H = 0x70488000, + LAvecbin_VSSUB_W = 0x70490000, + LAvecbin_VSSUB_D = 0x70498000, + LAvecbin_VSADD_BU = 0x704a0000, + LAvecbin_VSADD_HU = 0x704a8000, + LAvecbin_VSADD_WU = 0x704b0000, + LAvecbin_VSADD_DU = 0x704b8000, + LAvecbin_VSSUB_BU = 0x704c0000, + LAvecbin_VSSUB_HU = 0x704c8000, + LAvecbin_VSSUB_WU = 0x704d0000, + LAvecbin_VSSUB_DU = 0x704d8000, + LAvecbin_VADDA_B = 0x705c0000, + LAvecbin_VADDA_H = 0x705c8000, + LAvecbin_VADDA_W = 0x705d0000, + LAvecbin_VADDA_D = 0x705d8000, + LAvecbin_VAVGR_B = 0x70680000, + LAvecbin_VAVGR_H = 0x70688000, + LAvecbin_VAVGR_W = 0x70690000, + LAvecbin_VAVGR_D = 0x70698000, + LAvecbin_VAVGR_BU = 0x706a0000, + LAvecbin_VAVGR_HU = 0x706a8000, + LAvecbin_VAVGR_WU = 0x706b0000, + LAvecbin_VAVGR_DU = 0x706b8000, + LAvecbin_VMAX_B = 0x70700000, + LAvecbin_VMAX_H = 0x70708000, + LAvecbin_VMAX_W = 0x70710000, + LAvecbin_VMAX_D = 0x70718000, + LAvecbin_VMIN_B = 0x70720000, + LAvecbin_VMIN_H = 0x70728000, + LAvecbin_VMIN_W = 0x70730000, + LAvecbin_VMIN_D = 0x70738000, + LAvecbin_VMAX_BU = 0x70740000, + LAvecbin_VMAX_HU = 0x70748000, + LAvecbin_VMAX_WU = 0x70750000, + LAvecbin_VMAX_DU = 0x70758000, + LAvecbin_VMIN_BU = 0x70760000, + LAvecbin_VMIN_HU = 0x70768000, + LAvecbin_VMIN_WU = 0x70770000, + LAvecbin_VMIN_DU = 0x70778000, + LAvecbin_VMUL_B = 0x70840000, + LAvecbin_VMUL_H = 0x70848000, + LAvecbin_VMUL_W = 0x70850000, + LAvecbin_VMUH_B = 0x70860000, + LAvecbin_VMUH_H = 0x70868000, + LAvecbin_VMUH_W = 0x70870000, + LAvecbin_VMUH_BU = 0x70880000, + LAvecbin_VMUH_HU = 0x70888000, + LAvecbin_VMUH_WU = 0x70890000, + LAvecbin_VSLL_B = 0x70e80000, + LAvecbin_VSLL_H = 0x70e88000, + LAvecbin_VSLL_W = 0x70e90000, + LAvecbin_VSLL_D = 0x70e98000, + LAvecbin_VSRL_B = 0x70ea0000, + LAvecbin_VSRL_H = 0x70ea8000, + LAvecbin_VSRL_W = 0x70eb0000, + LAvecbin_VSRL_D = 0x70eb8000, + LAvecbin_VSRA_B = 0x70ec0000, + LAvecbin_VSRA_H = 0x70ec8000, + LAvecbin_VSRA_W = 0x70ed0000, + LAvecbin_VSRA_D = 0x70ed8000, + LAvecbin_VILVL_B = 0x711a0000, + LAvecbin_VILVL_H = 0x711a8000, + LAvecbin_VILVL_W = 0x711b0000, + LAvecbin_VILVL_D = 0x711b8000, + LAvecbin_VILVH_B = 0x711c0000, + LAvecbin_VILVH_H = 0x711c8000, + LAvecbin_VILVH_W = 0x711d0000, + LAvecbin_VILVH_D = 0x711d8000, + LAvecbin_VPICKEV_B = 0x711e0000, + LAvecbin_VPICKEV_H = 0x711e8000, + LAvecbin_VPICKEV_W = 0x711f0000, + LAvecbin_VPICKOD_B = 0x71200000, + LAvecbin_VPICKOD_H = 0x71208000, + LAvecbin_VPICKOD_W = 0x71210000, + LAvecbin_VREPLVE_B = 0x71220000, + LAvecbin_VREPLVE_H = 0x71228000, + LAvecbin_VREPLVE_W = 0x71230000, + LAvecbin_VREPLVE_D = 0x71238000, + LAvecbin_VAND_V = 0x71260000, + LAvecbin_VOR_V = 0x71268000, + LAvecbin_VXOR_V = 0x71270000, + LAvecbin_VNOR_V = 0x71278000, + LAvecbin_VADD_Q = 0x712d0000, + LAvecbin_VSUB_Q = 0x712d8000, + LAvecbin_VFADD_S = 0x71308000, + LAvecbin_VFADD_D = 0x71310000, + LAvecbin_VFSUB_S = 0x71328000, + LAvecbin_VFSUB_D = 0x71330000, + LAvecbin_VFMUL_S = 0x71388000, + LAvecbin_VFMUL_D = 0x71390000, + LAvecbin_VFDIV_S = 0x713a8000, + LAvecbin_VFDIV_D = 0x713b0000, + LAvecbin_VFMAX_S = 0x713c8000, + LAvecbin_VFMAX_D = 0x713d0000, + LAvecbin_VFMIN_S = 0x713e8000, + LAvecbin_VFMIN_D = 0x713f0000, + LAvecbin_VBSLL_V = 0x728e0000, + LAvecbin_VBSRL_V = 0x728e8000, + LAvecbin_VINSGR2VR_B = 0x72eb8000, + LAvecbin_VINSGR2VR_H = 0x72ebc000, + LAvecbin_VINSGR2VR_W = 0x72ebe000, + LAvecbin_VINSGR2VR_D = 0x72ebf000, + LAvecbin_VPICKVE2GR_W = 0x72efe000, + LAvecbin_VPICKVE2GR_D = 0x72eff000, + LAvecbin_VPICKVE2GR_BU = 0x72f38000, + LAvecbin_VPICKVE2GR_HU = 0x72f3c000, + LAvecbin_VPICKVE2GR_WU = 0x72f3e000, + LAvecbin_VPICKVE2GR_DU = 0x72f3f000, + LAvecbin_VSLLI_B = 0x732c2000, + LAvecbin_VSLLI_H = 0x732c4000, + LAvecbin_VSLLI_W = 0x732c8000, + LAvecbin_VSLLI_D = 0x732d0000, + LAvecbin_VSRLI_B = 0x73302000, + LAvecbin_VSRLI_H = 0x73304000, + LAvecbin_VSRLI_W = 0x73308000, + LAvecbin_VSRLI_D = 0x73310000, + LAvecbin_VSRAI_B = 0x73342000, + LAvecbin_VSRAI_H = 0x73344000, + LAvecbin_VSRAI_W = 0x73348000, + LAvecbin_VSRAI_D = 0x73350000, + LAvecbin_VORI_B = 0x73d40000 +} LOONGARCH64VecBinOp; + +/* Tags for vector load operations */ +typedef enum { + LAvecload_VLD = 0x2c000000, + LAvecload_VLDX = 0x38400000 +} LOONGARCH64VecLoadOp; + +/* Tags for vector store operations */ +typedef enum { + LAvecstore_VST = 0x2c400000, + LAvecstore_VSTX = 0x38440000 +} LOONGARCH64VecStoreOp; + +/* Tags for extra operations, we only use them when emiting code directly */ +typedef enum { + LAextra_MOVGR2CF = 0x0114d800, + LAextra_MOVCF2GR = 0x0114dc00, + LAextra_SLT = 0x00120000, + LAextra_SLTU = 0x00128000, + LAextra_MASKEQZ = 0x00130000, + LAextra_MASKNEZ = 0x00138000, + LAextra_SLTI = 0x02000000, + LAextra_SLTUI = 0x02400000, + LAextra_LU52I_D = 0x03000000, + LAextra_FSEL = 0x0d000000, + LAextra_LU12I_W = 0x14000000, + LAextra_LU32I_D = 0x16000000, + LAextra_JIRL = 0x4c000000, + LAextra_B = 0x50000000, + LAextra_BEQ = 0x58000000, + LAextra_BNE = 0x5c000000, + LAextra_BGE = 0x64000000 +} LOONGARCH64ExtraOp; + +/* Tags for instructions */ +typedef enum { + /* Pseudo-insn, used for generating a 64-bit + literal to register */ + LAin_LI, /* load imm */ + + /* Integer insns */ + LAin_Un, /* unary */ + LAin_Bin, /* binary */ + LAin_Load, /* load */ + LAin_Store, /* store */ + LAin_LLSC, /* ll/sc */ + LAin_Bar, /* barrier */ + + /* Floating point insns */ + LAin_FpUn, /* floating point unary */ + LAin_FpBin, /* floating point binary */ + LAin_FpTri, /* floating point trinary */ + LAin_FpLoad, /* floating point load */ + LAin_FpStore, /* floating point store */ + LAin_FpMove, /* floating point move */ + LAin_FpCmp, /* floating point compare */ + + /* Vector insns */ + LAin_VecUn, /* vector unary */ + LAin_VecBin, /* vector binary */ + LAin_VecLoad, /* vector load */ + LAin_VecStore, /* vector store */ + + /* Pseudo-insn */ + LAin_Cas, /* compare and swap */ + LAin_Cmp, /* word compare */ + LAin_CMove, /* condition move */ + + /* Call target (an absolute address), on given + condition (which could be LAcc_AL). */ + LAin_Call, /* call */ + + /* The following 5 insns are mandated by translation chaining */ + LAin_XDirect, /* direct transfer to GA */ + LAin_XIndir, /* indirect transfer to GA */ + LAin_XAssisted, /* assisted transfer to GA */ + LAin_EvCheck, /* Event check */ + LAin_ProfInc /* 64-bit profile counter increment */ +} LOONGARCH64InstrTag; + +typedef struct { + LOONGARCH64InstrTag tag; + union { + struct { + ULong imm; + HReg dst; + } LI; + struct { + LOONGARCH64UnOp op; + HReg src; + HReg dst; + } Unary; + struct { + LOONGARCH64BinOp op; + LOONGARCH64RI* src2; + HReg src1; + HReg dst; + } Binary; + struct { + LOONGARCH64LoadOp op; + LOONGARCH64AMode* src; + HReg dst; + } Load; + struct { + LOONGARCH64StoreOp op; + LOONGARCH64AMode* dst; + HReg src; + } Store; + struct { + LOONGARCH64LLSCOp op; + Bool isLoad; + LOONGARCH64AMode* addr; + HReg val; + } LLSC; + struct { + LOONGARCH64BarOp op; + UShort hint; + } Bar; + struct { + LOONGARCH64FpUnOp op; + HReg src; + HReg dst; + } FpUnary; + struct { + LOONGARCH64FpBinOp op; + HReg src2; + HReg src1; + HReg dst; + } FpBinary; + struct { + LOONGARCH64FpTriOp op; + HReg src3; + HReg src2; + HReg src1; + HReg dst; + } FpTrinary; + struct { + LOONGARCH64FpLoadOp op; + LOONGARCH64AMode* src; + HReg dst; + } FpLoad; + struct { + LOONGARCH64FpStoreOp op; + LOONGARCH64AMode* dst; + HReg src; + } FpStore; + struct { + LOONGARCH64FpMoveOp op; + HReg src; + HReg dst; + } FpMove; + struct { + LOONGARCH64FpCmpOp op; + HReg src2; + HReg src1; + HReg dst; + } FpCmp; + struct { + LOONGARCH64VecUnOp op; + HReg src; + HReg dst; + } VecUnary; + struct { + LOONGARCH64VecBinOp op; + LOONGARCH64RI* src2; + HReg src1; + HReg dst; + } VecBinary; + struct { + LOONGARCH64VecLoadOp op; + LOONGARCH64AMode* src; + HReg dst; + } VecLoad; + struct { + LOONGARCH64VecStoreOp op; + LOONGARCH64AMode* dst; + HReg src; + } VecStore; + struct { + HReg old; + HReg addr; + HReg expd; + HReg data; + Bool size64; + } Cas; + struct { + LOONGARCH64CondCode cond; + HReg dst; + HReg src1; + HReg src2; + } Cmp; + struct { + HReg cond; + HReg r0; + HReg r1; + HReg dst; + Bool isInt; + } CMove; + struct { + HReg cond; + Addr64 target; + UInt nArgRegs; + RetLoc rloc; + } Call; + struct { + Addr64 dstGA; + LOONGARCH64AMode* amPC; + HReg cond; + Bool toFastEP; + } XDirect; + struct { + HReg dstGA; + LOONGARCH64AMode* amPC; + HReg cond; + } XIndir; + struct { + HReg dstGA; + LOONGARCH64AMode* amPC; + HReg cond; + IRJumpKind jk; + } XAssisted; + struct { + LOONGARCH64AMode* amCounter; + LOONGARCH64AMode* amFailAddr; + } EvCheck; + struct { + /* No fields. The address of the counter to inc is + installed later, post-translation, by patching it in, + as it is not known at translation time. */ + } ProfInc; + } LAin; +} LOONGARCH64Instr; + +extern LOONGARCH64Instr* LOONGARCH64Instr_LI ( ULong imm, HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_Unary ( LOONGARCH64UnOp op, + HReg src, HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_Binary ( LOONGARCH64BinOp op, + LOONGARCH64RI* src2, + HReg src1, HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_Load ( LOONGARCH64LoadOp op, + LOONGARCH64AMode* src, + HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_Store ( LOONGARCH64StoreOp op, + LOONGARCH64AMode* dst, + HReg src ); +extern LOONGARCH64Instr* LOONGARCH64Instr_LLSC ( LOONGARCH64LLSCOp op, + Bool isLoad, + LOONGARCH64AMode* addr, + HReg val ); +extern LOONGARCH64Instr* LOONGARCH64Instr_Bar ( LOONGARCH64BarOp op, + UShort hint ); +extern LOONGARCH64Instr* LOONGARCH64Instr_FpUnary ( LOONGARCH64FpUnOp op, + HReg src, HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_FpBinary ( LOONGARCH64FpBinOp op, + HReg src2, HReg src1, + HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_FpTrinary ( LOONGARCH64FpTriOp op, + HReg src3, HReg src2, + HReg src1, HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_FpLoad ( LOONGARCH64FpLoadOp op, + LOONGARCH64AMode* src, + HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_FpStore ( LOONGARCH64FpStoreOp op, + LOONGARCH64AMode* dst, + HReg src ); +extern LOONGARCH64Instr* LOONGARCH64Instr_FpMove ( LOONGARCH64FpMoveOp op, + HReg src, HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_FpCmp ( LOONGARCH64FpCmpOp op, + HReg src2, HReg src1, + HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_VecUnary ( LOONGARCH64VecUnOp op, + HReg src, HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_VecBinary ( LOONGARCH64VecBinOp op, + LOONGARCH64RI* src2, + HReg src1, HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_VecLoad ( LOONGARCH64VecLoadOp op, + LOONGARCH64AMode* src, + HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_VecStore ( LOONGARCH64VecStoreOp op, + LOONGARCH64AMode* dst, + HReg src ); +extern LOONGARCH64Instr* LOONGARCH64Instr_Cas ( HReg old, HReg addr, + HReg expd, HReg data, + Bool size64 ); +extern LOONGARCH64Instr* LOONGARCH64Instr_Cmp ( LOONGARCH64CondCode cond, + HReg src2, HReg src1, + HReg dst ); +extern LOONGARCH64Instr* LOONGARCH64Instr_CMove ( HReg cond, HReg r0, HReg r1, + HReg dst, Bool isInt ); +extern LOONGARCH64Instr* LOONGARCH64Instr_Call ( HReg cond, Addr64 target, + UInt nArgRegs, RetLoc rloc ); +extern LOONGARCH64Instr* LOONGARCH64Instr_XDirect ( Addr64 dstGA, + LOONGARCH64AMode* amPC, + HReg cond, Bool toFastEP ); +extern LOONGARCH64Instr* LOONGARCH64Instr_XIndir ( HReg dstGA, + LOONGARCH64AMode* amPC, + HReg cond ); +extern LOONGARCH64Instr* LOONGARCH64Instr_XAssisted ( HReg dstGA, + LOONGARCH64AMode* amPC, + HReg cond, IRJumpKind jk ); +extern LOONGARCH64Instr* LOONGARCH64Instr_EvCheck ( LOONGARCH64AMode* amCounter, + LOONGARCH64AMode* amFailAddr ); +extern LOONGARCH64Instr* LOONGARCH64Instr_ProfInc ( void ); + +extern void ppLOONGARCH64Instr ( const LOONGARCH64Instr* i, Bool mode64 ); + +/* Some functions that insulate the register allocator from details + of the underlying instruction set. */ +extern void getRegUsage_LOONGARCH64Instr ( HRegUsage* u, + const LOONGARCH64Instr* i, + Bool mode64 ); +extern void mapRegs_LOONGARCH64Instr ( HRegRemap* m, LOONGARCH64Instr* i, + Bool mode64 ); +extern Int emit_LOONGARCH64Instr (/*MB_MOD*/Bool* is_profInc, + UChar* buf, + Int nbuf, + const LOONGARCH64Instr* i, + Bool mode64, + VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ); + +extern void genSpill_LOONGARCH64 ( /*OUT*/ HInstr** i1, /*OUT*/ HInstr** i2, + HReg rreg, Int offsetB, Bool mode64); +extern void genReload_LOONGARCH64 ( /*OUT*/ HInstr** i1, /*OUT*/ HInstr** i2, + HReg rreg, Int offsetB, Bool mode64); +extern LOONGARCH64Instr* genMove_LOONGARCH64 ( HReg from, HReg to, + Bool mode64 ); + +extern const RRegUniverse* getRRegUniverse_LOONGARCH64 ( void ); + +extern HInstrArray* iselSB_LOONGARCH64 ( const IRSB*, + VexArch, + const VexArchInfo*, + const VexAbiInfo*, + Int offs_Host_EvC_Counter, + Int offs_Host_EvC_FailAddr, + Bool chainingAllowed, + Bool addProfInc, + Addr max_ga ); + +/* How big is an event check? See case for Min_EvCheck in + emit_LOONGARCH64Instr just above. That crosschecks what this returns, + so we can tell if we're inconsistent. */ +extern Int evCheckSzB_LOONGARCH64 ( void ); + +/* NB: what goes on here has to be very closely coordinated with the + emitInstr case for XDirect, above. */ +extern VexInvalRange chainXDirect_LOONGARCH64 ( VexEndness endness_host, + void* place_to_chain, + const void* disp_cp_chain_me_EXPECTED, + const void* place_to_jump_to ); + +/* NB: what goes on here has to be very closely coordinated with the + emitInstr case for XDirect, above. */ +extern VexInvalRange unchainXDirect_LOONGARCH64 ( VexEndness endness_host, + void* place_to_unchain, + const void* place_to_jump_to_EXPECTED, + const void* disp_cp_chain_me ); + +/* Patch the counter address into a profile inc point, as previously + created by the Min_ProfInc case for emit_LOONGARCH64Instr. */ +extern VexInvalRange patchProfInc_LOONGARCH64 ( VexEndness endness_host, + void* place_to_patch, + const ULong* location_of_counter ); + +#endif /* ndef __VEX_HOST_LOONGARCH64_DEFS_H */ + + +/*---------------------------------------------------------------*/ +/*--- end host-loongarch64_defs.h ---*/ +/*---------------------------------------------------------------*/ diff --git a/VEX/priv/host_loongarch64_isel.c b/VEX/priv/host_loongarch64_isel.c new file mode 100644 index 0000000..d60a2b3 --- /dev/null +++ b/VEX/priv/host_loongarch64_isel.c @@ -0,0 +1,3748 @@ + +/*---------------------------------------------------------------*/ +/*--- begin host_loongarch64_isel.c ---*/ +/*---------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details-> + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#include "libvex_basictypes.h" +#include "libvex_ir.h" +#include "libvex.h" + +#include "main_util.h" +#include "main_globals.h" +#include "host_generic_regs.h" +#include "host_loongarch64_defs.h" + + +/*---------------------------------------------------------*/ +/*--- ISelEnv ---*/ +/*---------------------------------------------------------*/ + +/* This carries around: + + - A mapping from IRTemp to IRType, giving the type of any IRTemp we + might encounter. This is computed before insn selection starts, + and does not change. + + - A mapping from IRTemp to HReg. This tells the insn selector + which virtual register is associated with each IRTemp temporary. + This is computed before insn selection starts, and does not + change. We expect this mapping to map precisely the same set of + IRTemps as the type mapping does. + + |vregmap| holds the primary register for the IRTemp. + |vregmapHI| is only used for 128-bit integer-typed + IRTemps. It holds the identity of a second + 64-bit virtual HReg, which holds the high half + of the value. + + - The code array, that is, the insns selected so far. + + - A counter, for generating new virtual registers. + + - The host hardware capabilities word. This is set at the start + and does not change. + + - A Bool for indicating whether we may generate chain-me + instructions for control flow transfers, or whether we must use + XAssisted. + + - The maximum guest address of any guest insn in this block. + Actually, the address of the highest-addressed byte from any insn + in this block. Is set at the start and does not change. This is + used for detecting jumps which are definitely forward-edges from + this block, and therefore can be made (chained) to the fast entry + point of the destination, thereby avoiding the destination's + event check. + + - An IRExpr*, which may be NULL, holding the IR expression (an + IRRoundingMode-encoded value) to which the FPU's rounding mode + was most recently set. Setting to NULL is always safe. Used to + avoid redundant settings of the FPU's rounding mode, as + described in set_FPCR_rounding_mode below. + + Note, this is all (well, mostly) host-independent. +*/ + +typedef + struct { + /* Constant -- are set at the start and do not change. */ + IRTypeEnv* type_env; + + HReg* vregmap; + HReg* vregmapHI; + Int n_vregmap; + + UInt hwcaps; + + Bool chainingAllowed; + Addr64 max_ga; + + /* These are modified as we go along. */ + HInstrArray* code; + Int vreg_ctr; + } + ISelEnv; + + +static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp ) +{ + vassert(tmp < env->n_vregmap); + return env->vregmap[tmp]; +} + +static void lookupIRTempPair ( HReg* vrHI, HReg* vrLO, + ISelEnv* env, IRTemp tmp ) +{ + vassert(tmp < env->n_vregmap); + vassert(!hregIsInvalid(env->vregmapHI[tmp])); + *vrLO = env->vregmap[tmp]; + *vrHI = env->vregmapHI[tmp]; +} + +static void addInstr ( ISelEnv* env, LOONGARCH64Instr* instr ) +{ + addHInstr(env->code, instr); + if (vex_traceflags & VEX_TRACE_VCODE) { + ppLOONGARCH64Instr(instr, True); + vex_printf("\n"); + } +} + +static HReg newVRegI ( ISelEnv* env ) +{ + HReg reg = mkHReg(True/*virtual reg*/, HRcInt64, 0, env->vreg_ctr); + env->vreg_ctr++; + return reg; +} + +static HReg newVRegF ( ISelEnv* env ) +{ + HReg reg = mkHReg(True/*virtual reg*/, HRcFlt64, 0, env->vreg_ctr); + env->vreg_ctr++; + return reg; +} + +static HReg newVRegV ( ISelEnv* env ) +{ + HReg reg = mkHReg(True/*virtual reg*/, HRcVec128, 0, env->vreg_ctr); + env->vreg_ctr++; + return reg; +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Forward declarations ---*/ +/*---------------------------------------------------------*/ + +/* These are organised as iselXXX and iselXXX_wrk pairs. The + iselXXX_wrk do the real work, but are not to be called directly. + For each XXX, iselXXX calls its iselXXX_wrk counterpart, then + checks that all returned registers are virtual. You should not + call the _wrk version directly. +*/ + +static LOONGARCH64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, + IRExpr* e, IRType dty ); +static LOONGARCH64AMode* iselIntExpr_AMode ( ISelEnv* env, + IRExpr* e, IRType dty ); + +static LOONGARCH64RI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e, + UChar size, Bool isSigned ); +static LOONGARCH64RI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e, + UChar size, Bool isSigned ); + +static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ); +static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e ); + +static HReg iselCondCode_R_wrk ( ISelEnv* env, IRExpr* e ); +static HReg iselCondCode_R ( ISelEnv* env, IRExpr* e ); + +static void iselInt128Expr_wrk ( HReg* hi, HReg* lo, + ISelEnv* env, IRExpr* e ); +static void iselInt128Expr ( HReg* hi, HReg* lo, + ISelEnv* env, IRExpr* e ); + +static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ); +static HReg iselFltExpr ( ISelEnv* env, IRExpr* e ); + +static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e ); +static HReg iselV128Expr ( ISelEnv* env, IRExpr* e ); + +static void iselV256Expr_wrk ( HReg* hi, HReg* lo, + ISelEnv* env, IRExpr* e ); +static void iselV256Expr ( HReg* hi, HReg* lo, + ISelEnv* env, IRExpr* e ); + + +/*---------------------------------------------------------*/ +/*--- ISEL: Misc helpers ---*/ +/*---------------------------------------------------------*/ + +/* Generate move insn */ +static LOONGARCH64Instr* LOONGARCH64Instr_Move ( HReg to, HReg from ) +{ + LOONGARCH64RI *ri = LOONGARCH64RI_R(hregZERO()); + return LOONGARCH64Instr_Binary(LAbin_OR, ri, from, to); +} + +/* Generate vector move insn */ +static LOONGARCH64Instr* LOONGARCH64Instr_VecMove ( HReg to, HReg from ) +{ + LOONGARCH64RI *ri = LOONGARCH64RI_I(0, 8, False); + return LOONGARCH64Instr_VecBinary(LAvecbin_VORI_B, ri, from, to); +} + +/* Generate LOONGARCH64AMode from HReg and UInt */ +static LOONGARCH64AMode* mkLOONGARCH64AMode_RI ( HReg reg, UInt imm ) +{ + vassert(imm < (1 << 12)); + return LOONGARCH64AMode_RI(reg, (UShort)imm); +} + +/* Set floating point rounding mode */ +static void set_rounding_mode ( ISelEnv* env, IRExpr* mode ) +{ + /* + rounding mode | LOONGARCH | IR + ------------------------------ + to nearest | 00 | 00 + to zero | 01 | 11 + to +infinity | 10 | 10 + to -infinity | 11 | 01 + */ + + /* rm = XOR(rm, (rm << 1)) & 3 */ + HReg rm = iselIntExpr_R(env, mode); + HReg tmp = newVRegI(env); + LOONGARCH64RI* ri = LOONGARCH64RI_I(1, 5, False); + LOONGARCH64RI* ri2 = LOONGARCH64RI_R(rm); + LOONGARCH64RI* ri3 = LOONGARCH64RI_I(3, 12, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri, rm, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_XOR, ri2, tmp, rm)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ANDI, ri3, rm, rm)); + + /* Save old value of FCSR3 */ + HReg fcsr = newVRegI(env); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVFCSR2GR, + hregLOONGARCH64_FCSR3(), fcsr)); + + /* Store old FCSR3 to stack */ + LOONGARCH64RI* ri4 = LOONGARCH64RI_I(-4 & 0xfff, 12, True); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ADDI_D, ri4, hregSP(), hregSP())); + LOONGARCH64AMode* am = LOONGARCH64AMode_RI(hregSP(), 0); + addInstr(env, LOONGARCH64Instr_Store(LAstore_ST_W, am, fcsr)); + + /* Set new value of FCSR3 */ + LOONGARCH64RI* ri5 = LOONGARCH64RI_I(8, 5, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri5, rm, rm)); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVGR2FCSR, + rm, hregLOONGARCH64_FCSR3())); +} + +static void set_rounding_mode_default ( ISelEnv* env ) +{ + /* Load old FCSR3 from stack */ + HReg fcsr = newVRegI(env); + LOONGARCH64AMode* am = LOONGARCH64AMode_RI(hregSP(), 0); + addInstr(env, LOONGARCH64Instr_Load(LAload_LD_WU, am, fcsr)); + + /* Restore SP */ + LOONGARCH64RI* ri = LOONGARCH64RI_I(4, 12, True); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ADDI_D, ri, hregSP(), hregSP())); + + /* Set new value of FCSR3 */ + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVGR2FCSR, + fcsr, hregLOONGARCH64_FCSR3())); +} + +/* Convert LOONGARCH FCMP cond to IR result */ +static HReg convert_cond_to_IR ( ISelEnv* env, HReg src2, HReg src1, Bool size64 ) +{ + HReg tmp = newVRegI(env); + HReg dst = newVRegI(env); + + LOONGARCH64RI* ri1 = LOONGARCH64RI_I(63, 6, False); + LOONGARCH64RI* ri2 = LOONGARCH64RI_I(0x45, 12, False); + if (size64) + addInstr(env, LOONGARCH64Instr_FpCmp(LAfpcmp_FCMP_CUN_D, src2, src1, tmp)); + else + addInstr(env, LOONGARCH64Instr_FpCmp(LAfpcmp_FCMP_CUN_S, src2, src1, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri1, tmp, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRAI_D, ri1, tmp, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ANDI, ri2, tmp, dst)); + + LOONGARCH64RI* ri3 = LOONGARCH64RI_I(0x1, 12, False); + LOONGARCH64RI* ri4 = LOONGARCH64RI_R(tmp); + if (size64) + addInstr(env, LOONGARCH64Instr_FpCmp(LAfpcmp_FCMP_CLT_D, src2, src1, tmp)); + else + addInstr(env, LOONGARCH64Instr_FpCmp(LAfpcmp_FCMP_CLT_S, src2, src1, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri1, tmp, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRAI_D, ri1, tmp, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ANDI, ri3, tmp, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, ri4, dst, dst)); + + LOONGARCH64RI* ri5 = LOONGARCH64RI_I(0x40, 12, False); + if (size64) + addInstr(env, LOONGARCH64Instr_FpCmp(LAfpcmp_FCMP_CEQ_D, src2, src1, tmp)); + else + addInstr(env, LOONGARCH64Instr_FpCmp(LAfpcmp_FCMP_CEQ_S, src2, src1, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri1, tmp, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRAI_D, ri1, tmp, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ANDI, ri5, tmp, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, ri4, dst, dst)); + + return dst; +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Function call helpers ---*/ +/*---------------------------------------------------------*/ + +/* Used only in doHelperCall. See big comment in doHelperCall re + handling of register-parameter args. This function figures out + whether evaluation of an expression might require use of a fixed + register. If in doubt return True (safe but suboptimal). +*/ +static Bool mightRequireFixedRegs ( IRExpr* e ) +{ + if (UNLIKELY(is_IRExpr_VECRET_or_GSPTR(e))) { + // These are always "safe" -- either a copy of SP in some + // arbitrary vreg, or a copy of $r31, respectively. + return False; + } + /* Else it's a "normal" expression. */ + switch (e->tag) { + case Iex_RdTmp: case Iex_Const: case Iex_Get: + return False; + default: + return True; + } +} + +/* Do a complete function call. |guard| is a Ity_Bit expression + indicating whether or not the call happens. If guard==NULL, the + call is unconditional. |retloc| is set to indicate where the + return value is after the call. The caller (of this fn) must + generate code to add |stackAdjustAfterCall| to the stack pointer + after the call is done. Returns True iff it managed to handle this + combination of arg/return types, else returns False. */ +static Bool doHelperCall( /*OUT*/UInt* stackAdjustAfterCall, + /*OUT*/RetLoc* retloc, + ISelEnv* env, + IRExpr* guard, + IRCallee* cee, IRType retTy, IRExpr** args ) +{ + HReg cond; + HReg argregs[LOONGARCH64_N_ARGREGS]; + HReg tmpregs[LOONGARCH64_N_ARGREGS]; + Bool go_fast; + Int n_args, i, nextArgReg; + Addr64 target; + + vassert(LOONGARCH64_N_ARGREGS == 8); + + /* Set default returns. We'll update them later if needed. */ + *stackAdjustAfterCall = 0; + *retloc = mk_RetLoc_INVALID(); + + /* These are used for cross-checking that IR-level constraints on + the use of IRExpr_VECRET() and IRExpr_GSPTR() are observed. */ + UInt nVECRETs = 0; + UInt nGSPTRs = 0; + + /* Marshal args for a call and do the call. + + This function only deals with a tiny set of possibilities, which + cover all helpers in practice. The restrictions are that only + arguments in registers are supported, hence only + LOONGARCH64_N_ARGREGS x 64 integer bits in total can be passed. + In fact the only supported arg type is I64. + + The return type can be I{64,32} or V{128,256}. In the latter two + cases, it is expected that |args| will contain the special node + IRExpr_VECRET(), in which case this routine generates code to + allocate space on the stack for the vector return value. Since + we are not passing any scalars on the stack, it is enough to + preallocate the return space before marshalling any arguments, + in this case. + + |args| may also contain IRExpr_GSPTR(), in which case the + value in $r31 is passed as the corresponding argument. + + Generating code which is both efficient and correct when + parameters are to be passed in registers is difficult, for the + reasons elaborated in detail in comments attached to + doHelperCall() in priv/host_x86_isel.c. Here, we use a variant + of the method described in those comments. + + The problem is split into two cases: the fast scheme and the + slow scheme. In the fast scheme, arguments are computed + directly into the target (real) registers. This is only safe + when we can be sure that computation of each argument will not + trash any real registers set by computation of any other + argument. + + In the slow scheme, all args are first computed into vregs, and + once they are all done, they are moved to the relevant real + regs. This always gives correct code, but it also gives a bunch + of vreg-to-rreg moves which are usually redundant but are hard + for the register allocator to get rid of. + + To decide which scheme to use, all argument expressions are + first examined. If they are all so simple that it is clear they + will be evaluated without use of any fixed registers, use the + fast scheme, else use the slow scheme. Note also that only + unconditional calls may use the fast scheme, since having to + compute a condition expression could itself trash real + registers. + + Note this requires being able to examine an expression and + determine whether or not evaluation of it might use a fixed + register. That requires knowledge of how the rest of this insn + selector works. Currently just the following 3 are regarded as + safe -- hopefully they cover the majority of arguments in + practice: IRExpr_Tmp IRExpr_Const IRExpr_Get. + */ + + /* LOONGARCH64 calling convention: up to eight registers ($a0 ... $a7) + are allowed to be used for passing integer arguments. They correspond + to regs $r4 ... $r11. Note that the cee->regparms field is meaningless + on LOONGARCH64 host (since we only implement one calling convention) + and so we always ignore it. */ + + n_args = 0; + for (i = 0; args[i]; i++) { + IRExpr* arg = args[i]; + if (UNLIKELY(arg->tag == Iex_VECRET)) { + nVECRETs++; + } else if (UNLIKELY(arg->tag == Iex_GSPTR)) { + nGSPTRs++; + } + n_args++; + } + + /* If this fails, the IR is ill-formed */ + vassert(nGSPTRs == 0 || nGSPTRs == 1); + + /* If we have a VECRET, allocate space on the stack for the return + value, and record the stack pointer after that. */ + HReg r_vecRetAddr = INVALID_HREG; + LOONGARCH64RI* ri; + if (nVECRETs == 1) { + vassert(retTy == Ity_V128 || retTy == Ity_V256); + r_vecRetAddr = newVRegI(env); + if (retTy == Ity_V128) + ri = LOONGARCH64RI_I(-16 & 0xfff, 12, True); + else // retTy == Ity_V256 + ri = LOONGARCH64RI_I(-32 & 0xfff, 12, True); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ADDI_D, ri, hregSP(), hregSP())); + addInstr(env, LOONGARCH64Instr_Move(r_vecRetAddr, hregSP())); + } else { + // If either of these fail, the IR is ill-formed + vassert(retTy != Ity_V128 && retTy != Ity_V256); + vassert(nVECRETs == 0); + } + + if (n_args > LOONGARCH64_N_ARGREGS) { + vpanic("doHelperCall(loongarch64): cannot currently handle > 8 args"); + } + + argregs[0] = hregLOONGARCH64_R4(); + argregs[1] = hregLOONGARCH64_R5(); + argregs[2] = hregLOONGARCH64_R6(); + argregs[3] = hregLOONGARCH64_R7(); + argregs[4] = hregLOONGARCH64_R8(); + argregs[5] = hregLOONGARCH64_R9(); + argregs[6] = hregLOONGARCH64_R10(); + argregs[7] = hregLOONGARCH64_R11(); + + tmpregs[0] = tmpregs[1] = tmpregs[2] = tmpregs[3] = INVALID_HREG; + tmpregs[4] = tmpregs[5] = tmpregs[6] = tmpregs[7] = INVALID_HREG; + + /* First decide which scheme (slow or fast) is to be used. First assume the + fast scheme, and select slow if any contraindications (wow) appear. */ + + go_fast = True; + + if (guard) { + if (guard->tag == Iex_Const + && guard->Iex.Const.con->tag == Ico_U1 + && guard->Iex.Const.con->Ico.U1 == True) { + /* unconditional */ + } else { + /* Not manifestly unconditional -- be conservative. */ + go_fast = False; + } + } + + if (go_fast) { + for (i = 0; i < n_args; i++) { + if (mightRequireFixedRegs(args[i])) { + go_fast = False; + break; + } + } + } + + if (go_fast) { + if (retTy == Ity_V128 || retTy == Ity_V256) + go_fast = False; + } + + /* At this point the scheme to use has been established. Generate + code to get the arg values into the argument rregs. If we run + out of arg regs, give up. */ + + if (go_fast) { + /* FAST SCHEME */ + nextArgReg = 0; + + for (i = 0; i < n_args; i++) { + IRExpr* arg = args[i]; + + IRType aTy = Ity_INVALID; + if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg))) + aTy = typeOfIRExpr(env->type_env, args[i]); + + if (nextArgReg >= LOONGARCH64_N_ARGREGS) + return False; /* out of argregs */ + + if (aTy == Ity_I64) { + addInstr(env, LOONGARCH64Instr_Move(argregs[nextArgReg], + iselIntExpr_R(env, args[i]))); + nextArgReg++; + } else if (arg->tag == Iex_GSPTR) { + addInstr(env, LOONGARCH64Instr_Move(argregs[nextArgReg], hregGSP())); + nextArgReg++; + } else if (arg->tag == Iex_VECRET) { + // because of the go_fast logic above, we can't get here, + // since vector return values makes us use the slow path + // instead. + vassert(0); + } else + return False; /* unhandled arg type */ + } + + /* Fast scheme only applies for unconditional calls. Hence: */ + cond = INVALID_HREG; + } else { + /* SLOW SCHEME; move via temporaries */ + nextArgReg = 0; + + for (i = 0; i < n_args; i++) { + IRExpr* arg = args[i]; + + IRType aTy = Ity_INVALID; + if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg))) + aTy = typeOfIRExpr(env->type_env, args[i]); + + if (nextArgReg >= LOONGARCH64_N_ARGREGS) + return False; /* out of argregs */ + + if (aTy == Ity_I64) { + tmpregs[nextArgReg] = iselIntExpr_R(env, args[i]); + nextArgReg++; + } else if (arg->tag == Iex_GSPTR) { + tmpregs[nextArgReg] = hregGSP(); + nextArgReg++; + } else if (arg->tag == Iex_VECRET) { + vassert(!hregIsInvalid(r_vecRetAddr)); + tmpregs[nextArgReg] = r_vecRetAddr; + nextArgReg++; + } else + return False; /* unhandled arg type */ + } + + /* Now we can compute the condition. We can't do it earlier + because the argument computations could trash the condition + codes. Be a bit clever to handle the common case where the + guard is 1:Bit. */ + cond = INVALID_HREG; + if (guard) { + if (guard->tag == Iex_Const + && guard->Iex.Const.con->tag == Ico_U1 + && guard->Iex.Const.con->Ico.U1 == True) { + /* unconditional -- do nothing */ + } else { + cond = iselCondCode_R(env, guard); + } + } + + /* Move the args to their final destinations. */ + for (i = 0; i < nextArgReg; i++) { + vassert(!(hregIsInvalid(tmpregs[i]))); + /* None of these insns, including any spill code that might + be generated, may alter the condition codes. */ + addInstr(env, LOONGARCH64Instr_Move(argregs[i], tmpregs[i])); + } + } + + /* Should be assured by checks above */ + vassert(nextArgReg <= LOONGARCH64_N_ARGREGS); + + /* Do final checks, set the return values, and generate the call + instruction proper. */ + vassert(nGSPTRs == 0 || nGSPTRs == 1); + vassert(nVECRETs == ((retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0)); + vassert(*stackAdjustAfterCall == 0); + vassert(is_RetLoc_INVALID(*retloc)); + switch (retTy) { + case Ity_INVALID: + /* Function doesn't return a value. */ + *retloc = mk_RetLoc_simple(RLPri_None); + break; + case Ity_I8: case Ity_I16: case Ity_I32: case Ity_I64: + *retloc = mk_RetLoc_simple(RLPri_Int); + break; + case Ity_V128: + *retloc = mk_RetLoc_spRel(RLPri_V128SpRel, 0); + *stackAdjustAfterCall = 16; + break; + case Ity_V256: + *retloc = mk_RetLoc_spRel(RLPri_V256SpRel, 0); + *stackAdjustAfterCall = 32; + break; + default: + /* IR can denote other possible return types, but we don't + handle those here. */ + vassert(0); + break; + } + + /* Finally, generate the call itself. This needs the *retloc value + set in the switch above, which is why it's at the end. */ + + /* nextArgReg doles out argument registers. Since these are + assigned in the order $a0 .. $a7, its numeric value at this point, + which must be between 0 and 8 inclusive, is going to be equal to + the number of arg regs in use for the call. Hence bake that + number into the call (we'll need to know it when doing register + allocation, to know what regs the call reads.) */ + + target = (Addr)cee->addr; + addInstr(env, LOONGARCH64Instr_Call(cond, target, nextArgReg, *retloc)); + + return True; /* success */ +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Integer expressions (64/32/16/8 bit) ---*/ +/*---------------------------------------------------------*/ + +/* Select insns for an integer-typed expression, and add them to the + code list. Return a reg holding the result. This reg will be a + virtual register. THE RETURNED REG MUST NOT BE MODIFIED. If you + want to modify it, ask for a new vreg, copy it in there, and modify + the copy. The register allocator will do its best to map both + vregs to the same real register, so the copies will often disappear + later in the game. + + This should handle expressions of 64, 32, 16 and 8-bit type. + All results are returned in a (mode64 ? 64bit : 32bit) register. + For 16- and 8-bit expressions, the upper (32/48/56 : 16/24) bits + are arbitrary, so you should mask or sign extend partial values + if necessary. +*/ + +/* --------------------- AMode --------------------- */ + +static LOONGARCH64AMode* iselIntExpr_AMode ( ISelEnv* env, + IRExpr* e, IRType dty ) +{ + LOONGARCH64AMode* am = iselIntExpr_AMode_wrk(env, e, dty); + + /* sanity checks ... */ + switch (am->tag) { + case LAam_RI: + vassert(am->LAam.RI.index < (1 << 12)); + vassert(hregClass(am->LAam.RI.base) == HRcInt64); + vassert(hregIsVirtual(am->LAam.RI.base)); + break; + case LAam_RR: + vassert(hregClass(am->LAam.RR.base) == HRcInt64); + vassert(hregIsVirtual(am->LAam.RR.base)); + vassert(hregClass(am->LAam.RR.index) == HRcInt64); + vassert(hregIsVirtual(am->LAam.RR.index)); + break; + default: + vpanic("iselIntExpr_AMode: unknown LOONGARCH64 AMode tag"); + break; + } + + return am; +} + +/* DO NOT CALL THIS DIRECTLY ! */ +static LOONGARCH64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, + IRExpr* e, IRType dty ) +{ + IRType ty = typeOfIRExpr(env->type_env, e); + vassert(e); + vassert(ty == Ity_I64); + + /* Add64(expr, i), where i <= 0x7ff */ + if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_Add64 + && e->Iex.Binop.arg2->tag == Iex_Const + && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64 + && e->Iex.Binop.arg2->Iex.Const.con->Ico.U64 <= 0x7ff) { + return LOONGARCH64AMode_RI(iselIntExpr_R(env, e->Iex.Binop.arg1), + (UShort)e->Iex.Binop.arg2->Iex.Const.con->Ico.U64); + } + + /* Add64(expr, expr) */ + if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_Add64) { + HReg base = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg index = iselIntExpr_R(env, e->Iex.Binop.arg2); + return LOONGARCH64AMode_RR(base, index); + } + + /* Doesn't match anything in particular. Generate it into + a register and use that. */ + return LOONGARCH64AMode_RI(iselIntExpr_R(env, e), 0); +} + +/* --------------------- RI --------------------- */ + +static LOONGARCH64RI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e, + UChar size, Bool isSigned ) +{ + LOONGARCH64RI* ri = iselIntExpr_RI_wrk(env, e, size, isSigned); + + /* sanity checks ... */ + switch (ri->tag) { + case LAri_Imm: + switch (ri->LAri.I.size) { + case 0 ... 4: + case 6 ... 7: + vassert(ri->LAri.I.isSigned == False); + break; + case 9 ... 11: + vassert(ri->LAri.I.isSigned == True); + break; + case 5: case 8: case 12: + break; + default: + break; + vassert(0); + } + vassert(ri->LAri.I.imm < (1 << ri->LAri.I.size)); + break; + case LAri_Reg: + vassert(hregClass(ri->LAri.R.reg) == HRcInt64); + vassert(hregIsVirtual(ri->LAri.R.reg)); + break; + default: + vpanic("iselIntExpr_RI: unknown LOONGARCH64 RI tag"); + break; + } + + return ri; +} + +/* DO NOT CALL THIS DIRECTLY ! */ +static LOONGARCH64RI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e, + UChar size, Bool isSigned ) +{ + IRType ty = typeOfIRExpr(env->type_env, e); + vassert(e); + vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ty == Ity_I64); + + LOONGARCH64RI *ri = NULL; + + /* special case: immediate */ + if (e->tag == Iex_Const) { + switch (e->Iex.Const.con->tag) { + case Ico_U8: + if (!isSigned && e->Iex.Const.con->Ico.U8 < (1 << size)) { + UShort imm = e->Iex.Const.con->Ico.U8; + ri = LOONGARCH64RI_I(imm, size, isSigned); + } + break; + case Ico_U32: + if (!isSigned && e->Iex.Const.con->Ico.U32 < (1 << size)) { + UShort imm = e->Iex.Const.con->Ico.U32; + ri = LOONGARCH64RI_I(imm, size, isSigned); + } + break; + case Ico_U64: + if (!isSigned && e->Iex.Const.con->Ico.U64 < (1 << size)) { + UShort imm = e->Iex.Const.con->Ico.U64; + ri = LOONGARCH64RI_I(imm, size, isSigned); + } + break; + default: + break; + } + /* else fail, fall through to default case */ + } + + if (ri == NULL) { + /* default case: calculate into a register and return that */ + HReg reg = iselIntExpr_R(env, e); + ri = LOONGARCH64RI_R(reg); + } + + return ri; +} + +/* --------------------- Reg --------------------- */ + +static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e ) +{ + HReg r = iselIntExpr_R_wrk(env, e); + + /* sanity checks ... */ + vassert(hregClass(r) == HRcInt64); + vassert(hregIsVirtual(r)); + + return r; +} + +/* DO NOT CALL THIS DIRECTLY ! */ +static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env, e); + vassert(e); + vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ty == Ity_I64); + + switch (e->tag) { + /* --------- TEMP --------- */ + case Iex_RdTmp: + return lookupIRTemp(env, e->Iex.RdTmp.tmp); + + /* --------- LOAD --------- */ + case Iex_Load: { + if (e->Iex.Load.end != Iend_LE) + goto irreducible; + + LOONGARCH64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr, ty); + HReg dst = newVRegI(env); + LOONGARCH64LoadOp op; + switch (ty) { + case Ity_I8: + op = (am->tag == LAam_RI) ? LAload_LD_BU : LAload_LDX_BU; + break; + case Ity_I16: + op = (am->tag == LAam_RI) ? LAload_LD_HU : LAload_LDX_HU; + break; + case Ity_I32: + op = (am->tag == LAam_RI) ? LAload_LD_WU : LAload_LDX_WU; + break; + case Ity_I64: + op = (am->tag == LAam_RI) ? LAload_LD_D : LAload_LDX_D; + break; + default: + goto irreducible; + } + addInstr(env, LOONGARCH64Instr_Load(op, am, dst)); + return dst; + } + + /* --------- BINARY OP --------- */ + case Iex_Binop: { + switch (e->Iex.Binop.op) { + case Iop_8HLto16: { + HReg dst = newVRegI(env); + HReg tHi = newVRegI(env); + HReg tLow = newVRegI(env); + HReg sHi = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg sLow = iselIntExpr_R(env, e->Iex.Binop.arg2); + LOONGARCH64RI* ui5 = LOONGARCH64RI_I(8, 5, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ui5, sHi, tHi)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ui5, sLow, tLow)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRLI_W, ui5, tLow, tLow)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, LOONGARCH64RI_R(tHi), tLow, dst)); + return dst; + } + case Iop_16HLto32: { + HReg dst = newVRegI(env); + HReg tHi = newVRegI(env); + HReg tLow = newVRegI(env); + HReg sHi = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg sLow = iselIntExpr_R(env, e->Iex.Binop.arg2); + LOONGARCH64RI* ui5 = LOONGARCH64RI_I(16, 5, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ui5, sHi, tHi)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ui5, sLow, tLow)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRLI_W, ui5, tLow, tLow)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, LOONGARCH64RI_R(tHi), tLow, dst)); + return dst; + } + case Iop_32HLto64: { + HReg dst = newVRegI(env); + HReg hi = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* lo = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + LOONGARCH64RI* ri = LOONGARCH64RI_I(32, 6, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri, hi, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, lo, dst, dst)); + return dst; + } + case Iop_Add32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 12, True); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_ADD_W : LAbin_ADDI_W; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_Add64: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 12, True); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_ADD_D : LAbin_ADDI_D; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_And8: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 12, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_AND : LAbin_ANDI; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_And32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 12, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_AND : LAbin_ANDI; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_And64: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 12, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_AND : LAbin_ANDI; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_DivModS32to32: { + HReg dst = newVRegI(env); + HReg tmp = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg src2 = iselIntExpr_R(env, e->Iex.Binop.arg2); + LOONGARCH64RI* ri1 = LOONGARCH64RI_I(0, 5, False); + LOONGARCH64RI* ri2 = LOONGARCH64RI_R(src2); + LOONGARCH64RI* ri3 = LOONGARCH64RI_I(32, 6, False); + LOONGARCH64RI* ri4 = LOONGARCH64RI_R(tmp); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri1, src1, src1)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri1, src2, src2)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_DIV_W, ri2, src1, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_MOD_W, ri2, src1, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri3, tmp, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri3, dst, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRLI_D, ri3, dst, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, ri4, dst, dst)); + return dst; + } + case Iop_DivModU32to32: { + HReg dst = newVRegI(env); + HReg tmp = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg src2 = iselIntExpr_R(env, e->Iex.Binop.arg2); + LOONGARCH64RI* ri1 = LOONGARCH64RI_I(0, 5, False); + LOONGARCH64RI* ri2 = LOONGARCH64RI_R(src2); + LOONGARCH64RI* ri3 = LOONGARCH64RI_I(32, 6, False); + LOONGARCH64RI* ri4 = LOONGARCH64RI_R(tmp); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri1, src1, src1)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri1, src2, src2)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_DIV_WU, ri2, src1, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_MOD_WU, ri2, src1, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri3, tmp, tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri3, dst, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRLI_D, ri3, dst, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, ri4, dst, dst)); + return dst; + } + case Iop_DivS32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg src2 = iselIntExpr_R(env, e->Iex.Binop.arg2); + LOONGARCH64RI* ri1 = LOONGARCH64RI_I(0, 5, False); + LOONGARCH64RI* ri2 = LOONGARCH64RI_R(src2); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri1, src1, src1)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri1, src2, src2)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_DIV_W, ri2, src1, dst)); + return dst; + } + case Iop_DivS64: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_DIV_D, src2, src1, dst)); + return dst; + } + case Iop_DivU32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg src2 = iselIntExpr_R(env, e->Iex.Binop.arg2); + LOONGARCH64RI* ri1 = LOONGARCH64RI_I(0, 5, False); + LOONGARCH64RI* ri2 = LOONGARCH64RI_R(src2); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri1, src1, src1)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri1, src2, src2)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_DIV_WU, ri2, src1, dst)); + return dst; + } + case Iop_DivU64: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_DIV_DU, src2, src1, dst)); + return dst; + } + case Iop_CmpF32: { + HReg src1 = iselFltExpr(env, e->Iex.Binop.arg1); + HReg src2 = iselFltExpr(env, e->Iex.Binop.arg2); + return convert_cond_to_IR(env, src2, src1, False); + } + case Iop_CmpF64: { + HReg src1 = iselFltExpr(env, e->Iex.Binop.arg1); + HReg src2 = iselFltExpr(env, e->Iex.Binop.arg2); + return convert_cond_to_IR(env, src2, src1, True); + } + case Iop_F32toI32S: { + HReg tmp = newVRegF(env); + HReg dst = newVRegI(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FTINT_W_S, src, tmp)); + set_rounding_mode_default(env); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVFR2GR_S, tmp, dst)); + return dst; + } + case Iop_F32toI64S: { + HReg tmp = newVRegF(env); + HReg dst = newVRegI(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FTINT_L_S, src, tmp)); + set_rounding_mode_default(env); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVFR2GR_D, tmp, dst)); + return dst; + } + case Iop_F64toI32S: { + HReg tmp = newVRegF(env); + HReg dst = newVRegI(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FTINT_W_D, src, tmp)); + set_rounding_mode_default(env); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVFR2GR_S, tmp, dst)); + return dst; + } + case Iop_F64toI64S: { + HReg tmp = newVRegF(env); + HReg dst = newVRegI(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FTINT_L_D, src, tmp)); + set_rounding_mode_default(env); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVFR2GR_D, tmp, dst)); + return dst; + } + case Iop_GetElem16x8: + case Iop_GetElem32x4: + case Iop_GetElem64x2: + case Iop_GetElem8x16: { + UChar size; + LOONGARCH64VecBinOp pickOp, veplOp; + switch (e->Iex.Binop.op) { + case Iop_GetElem8x16: + size = 4; + pickOp = LAvecbin_VPICKVE2GR_BU; + veplOp = LAvecbin_VREPLVE_B; + break; + case Iop_GetElem16x8: + size = 3; + pickOp = LAvecbin_VPICKVE2GR_HU; + veplOp = LAvecbin_VREPLVE_H; + break; + case Iop_GetElem32x4: + size = 2; + pickOp = LAvecbin_VPICKVE2GR_WU; + veplOp = LAvecbin_VREPLVE_W; + break; + case Iop_GetElem64x2: + size = 1; + pickOp = LAvecbin_VPICKVE2GR_DU; + veplOp = LAvecbin_VREPLVE_D; + break; + default: + vassert(0); + break; + } + HReg dst = newVRegI(env); + HReg src1 = iselV128Expr(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, size, False); + if (src2->tag == LAri_Imm) { + addInstr(env, LOONGARCH64Instr_VecBinary(pickOp, src2, src1, dst)); + } else { + HReg v_tmp = newVRegV(env); + addInstr(env, LOONGARCH64Instr_VecBinary(veplOp, src2, src1, v_tmp)); + addInstr(env, LOONGARCH64Instr_VecBinary(pickOp, LOONGARCH64RI_I(0, size, False), v_tmp, dst)); + } + + return dst; + } + case Iop_Max32U: { + HReg cond = newVRegI(env); + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg src2 = iselIntExpr_R(env, e->Iex.Binop.arg2); + addInstr(env, LOONGARCH64Instr_Cmp(LAcc_LTU, src2, src1, cond)); + addInstr(env, LOONGARCH64Instr_CMove(cond, src1, src2, dst, True)); + return dst; + } + case Iop_MullS32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_MULW_D_W, src2, src1, dst)); + return dst; + } + case Iop_MullU32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_MULW_D_WU, src2, src1, dst)); + return dst; + } + case Iop_Or32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 12, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_OR : LAbin_ORI; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_Or64: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 12, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_OR : LAbin_ORI; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_Sar32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 5, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_SRA_W : LAbin_SRAI_W; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_Sar64: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 6, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_SRA_D : LAbin_SRAI_D; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_Shl32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 5, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_SLL_W : LAbin_SLLI_W; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_Shl64: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 6, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_SLL_D : LAbin_SLLI_D; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_Shr32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 5, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_SRL_W : LAbin_SRLI_W; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_Shr64: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 6, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_SRL_D : LAbin_SRLI_D; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_Sub32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SUB_W, src2, src1, dst)); + return dst; + } + case Iop_Sub64: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SUB_D, src2, src1, dst)); + return dst; + } + case Iop_Xor32: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 12, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_XOR : LAbin_XORI; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_Xor64: { + HReg dst = newVRegI(env); + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 12, False); + LOONGARCH64BinOp op = (src2->tag == LAri_Reg) ? LAbin_XOR : LAbin_XORI; + addInstr(env, LOONGARCH64Instr_Binary(op, src2, src1, dst)); + return dst; + } + case Iop_64HLtoV128: { + HReg dst = newVRegV(env); + HReg sHi = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg sLow = iselIntExpr_R(env, e->Iex.Binop.arg2); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_D, + LOONGARCH64RI_I(0, 1, False), sLow, dst)); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_D, + LOONGARCH64RI_I(1, 1, False), sHi, dst)); + return dst; + } + default: + goto irreducible; + } + } + + /* --------- UNARY OP --------- */ + case Iex_Unop: { + switch (e->Iex.Unop.op) { + case Iop_128HIto64: { + HReg hi, lo; + iselInt128Expr(&hi, &lo, env, e->Iex.Unop.arg); + return hi; + } + case Iop_128to64: { + HReg hi, lo; + iselInt128Expr(&hi, &lo, env, e->Iex.Unop.arg); + return lo; + } + case Iop_16Sto64: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_Unary(LAun_EXT_W_H, src, dst)); + return dst; + } + case Iop_16Uto32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(48, 6, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri, src, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRLI_D, ri, dst, dst)); + return dst; + } + case Iop_16Uto64: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(48, 6, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri, src, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRLI_D, ri, dst, dst)); + return dst; + } + case Iop_1Sto32: { + HReg dst = newVRegI(env); + HReg src = iselCondCode_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(63, 6, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri, src, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRAI_D, ri, dst, dst)); + return dst; + } + case Iop_1Sto64: { + HReg dst = newVRegI(env); + HReg src = iselCondCode_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(63, 6, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri, src, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRAI_D, ri, dst, dst)); + return dst; + } + case Iop_1Uto64: { + HReg dst = newVRegI(env); + HReg src = iselCondCode_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(0x1, 12, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ANDI, ri, src, dst)); + return dst; + } + case Iop_1Uto8: { + HReg dst = newVRegI(env); + HReg src = iselCondCode_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(0x1, 12, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ANDI, ri, src, dst)); + return dst; + } + case Iop_32Sto64: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(0, 5, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri, src, dst)); + return dst; + } + case Iop_32Uto64: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(32, 6, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri, src, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRLI_D, ri, dst, dst)); + return dst; + } + case Iop_32to8: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(0xff, 12, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ANDI, ri, src, dst)); + return dst; + } + case Iop_64HIto32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(32, 6, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRLI_D, ri, src, dst)); + return dst; + } + case Iop_64to32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(32, 6, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri, src, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRLI_D, ri, dst, dst)); + return dst; + } + case Iop_64to8: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(0xff, 12, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ANDI, ri, src, dst)); + return dst; + } + case Iop_8Sto64: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_Unary(LAun_EXT_W_B, src, dst)); + return dst; + } + case Iop_8Uto32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(0xff, 12, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ANDI, ri, src, dst)); + return dst; + } + case Iop_8Uto64: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(0xff, 12, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ANDI, ri, src, dst)); + return dst; + } + case Iop_CmpwNEZ32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(63, 6, False); + addInstr(env, LOONGARCH64Instr_Cmp(LAcc_NE, hregZERO(), src, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri, dst, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRAI_D, ri, dst, dst)); + return dst; + } + case Iop_CmpwNEZ64: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_I(63, 6, False); + addInstr(env, LOONGARCH64Instr_Cmp(LAcc_NE, hregZERO(), src, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_D, ri, dst, dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SRAI_D, ri, dst, dst)); + return dst; + } + case Iop_Clz32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_Unary(LAun_CLZ_W, src, dst)); + return dst; + } + case Iop_Clz64: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_Unary(LAun_CLZ_D, src, dst)); + return dst; + } + case Iop_Ctz32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_Unary(LAun_CTZ_W, src, dst)); + return dst; + } + case Iop_Ctz64: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_Unary(LAun_CTZ_D, src, dst)); + return dst; + } + case Iop_Left16: { + HReg tmp = newVRegI(env); + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_R(src); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SUB_D, ri, hregZERO(), tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, ri, tmp, dst)); + return dst; + } + case Iop_Left32: { + HReg tmp = newVRegI(env); + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_R(src); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SUB_D, ri, hregZERO(), tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, ri, tmp, dst)); + return dst; + } + case Iop_Left64: { + HReg tmp = newVRegI(env); + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_R(src); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SUB_D, ri, hregZERO(), tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, ri, tmp, dst)); + return dst; + } + case Iop_Left8: { + HReg tmp = newVRegI(env); + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_R(src); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SUB_D, ri, hregZERO(), tmp)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, ri, tmp, dst)); + return dst; + } + case Iop_ReinterpF32asI32: { + HReg dst = newVRegI(env); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVFR2GR_S, src, dst)); + return dst; + } + case Iop_ReinterpF64asI64: { + HReg dst = newVRegI(env); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVFR2GR_D, src, dst)); + return dst; + } + case Iop_Not32: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_R(hregZERO()); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_NOR, ri, src, dst)); + return dst; + } + case Iop_Not64: { + HReg dst = newVRegI(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_R(hregZERO()); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_NOR, ri, src, dst)); + return dst; + } + case Iop_V128to32: { + HReg dst = newVRegI(env); + HReg src = iselV128Expr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VPICKVE2GR_W, + LOONGARCH64RI_I(0, 2, False), src, dst)); + return dst; + } + case Iop_V128to64: { + HReg dst = newVRegI(env); + HReg src = iselV128Expr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VPICKVE2GR_D, + LOONGARCH64RI_I(0, 1, False), src, dst)); + return dst; + } + case Iop_V128HIto64: { + HReg dst = newVRegI(env); + HReg src = iselV128Expr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VPICKVE2GR_D, + LOONGARCH64RI_I(1, 1, False), src, dst)); + return dst; + } + case Iop_V256to64_0: case Iop_V256to64_1: + case Iop_V256to64_2: case Iop_V256to64_3: { + UShort id; + HReg vHi, vLo, vec; + iselV256Expr(&vHi, &vLo, env, e->Iex.Unop.arg); + switch (e->Iex.Unop.op) { + case Iop_V256to64_0: vec = vLo; id = 0; break; + case Iop_V256to64_1: vec = vLo; id = 1; break; + case Iop_V256to64_2: vec = vHi; id = 0; break; + case Iop_V256to64_3: vec = vHi; id = 1; break; + default: vassert(0); break; + } + HReg dst = newVRegI(env); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VPICKVE2GR_D, + LOONGARCH64RI_I(id, 1, False), vec, dst)); + return dst; + } + default: + goto irreducible; + } + } + + /* --------- GET --------- */ + case Iex_Get: { + Bool ri = e->Iex.Get.offset < 1024; + HReg dst = newVRegI(env); + HReg tmp; + LOONGARCH64AMode* am; + LOONGARCH64LoadOp op; + switch (ty) { + case Ity_I8: + op = ri ? LAload_LD_BU : LAload_LDX_BU; + break; + case Ity_I16: + op = ri ? LAload_LD_HU : LAload_LDX_HU; + break; + case Ity_I32: + op = ri ? LAload_LD_WU : LAload_LDX_WU; + break; + case Ity_I64: + op = ri ? LAload_LD_D : LAload_LDX_D; + break; + default: + goto irreducible; + } + if (ri) { + am = LOONGARCH64AMode_RI(hregGSP(), e->Iex.Get.offset); + } else { + tmp = newVRegI(env); + addInstr(env, LOONGARCH64Instr_LI(e->Iex.Get.offset, tmp)); + am = LOONGARCH64AMode_RR(hregGSP(), tmp); + } + addInstr(env, LOONGARCH64Instr_Load(op, am, dst)); + return dst; + } + + /* --------- CCALL --------- */ + case Iex_CCall: { + HReg dst = newVRegI(env); + vassert(ty == e->Iex.CCall.retty); + + /* be very restrictive for now. Only 64-bit ints allowed for + args, and 64 bits for return type. Don't forget to change + the RetLoc if more types are allowed in future. */ + if (e->Iex.CCall.retty != Ity_I64) + goto irreducible; + + /* Marshal args, do the call, clear stack. */ + UInt addToSp = 0; + RetLoc rloc = mk_RetLoc_INVALID(); + Bool ok = doHelperCall(&addToSp, &rloc, env, NULL, + e->Iex.CCall.cee, e->Iex.CCall.retty, + e->Iex.CCall.args); + + if (ok) { + vassert(is_sane_RetLoc(rloc)); + vassert(rloc.pri == RLPri_Int); + vassert(addToSp == 0); + addInstr(env, LOONGARCH64Instr_Move(dst, hregLOONGARCH64_R4())); + return dst; + } + goto irreducible; + } + + /* --------- LITERAL --------- */ + /* 64-bit literals */ + case Iex_Const: { + ULong imm = 0; + HReg dst = newVRegI(env); + switch (e->Iex.Const.con->tag) { + case Ico_U64: + imm = e->Iex.Const.con->Ico.U64; + break; + case Ico_U32: + imm = e->Iex.Const.con->Ico.U32; + break; + case Ico_U16: + imm = e->Iex.Const.con->Ico.U16; + break; + case Ico_U8: + imm = e->Iex.Const.con->Ico.U8; + break; + default: + ppIRExpr(e); + vpanic("iselIntExpr_R.Iex_Const(loongarch64)"); + } + addInstr(env, LOONGARCH64Instr_LI(imm, dst)); + return dst; + } + + case Iex_ITE: { + HReg r0 = iselIntExpr_R(env, e->Iex.ITE.iffalse); + HReg r1 = iselIntExpr_R(env, e->Iex.ITE.iftrue); + HReg cond = iselCondCode_R(env, e->Iex.ITE.cond); + HReg dst = newVRegI(env); + addInstr(env, LOONGARCH64Instr_CMove(cond, r0, r1, dst, True)); + return dst; + } + + default: + break; + } + + /* We get here if no pattern matched. */ +irreducible: + ppIRExpr(e); + vpanic("iselIntExpr_R(loongarch64): cannot reduce tree"); +} + +/* ------------------- CondCode ------------------- */ + +/* Generate code to evaluated a bit-typed expression, returning the + condition code which would correspond when the expression would + notionally have returned 1. */ + +static HReg iselCondCode_R ( ISelEnv* env, IRExpr* e ) +{ + HReg r = iselCondCode_R_wrk(env, e); + + /* sanity checks ... */ + vassert(hregClass(r) == HRcInt64); + vassert(hregIsVirtual(r)); + + return r; +} + +/* DO NOT CALL THIS DIRECTLY ! */ +static HReg iselCondCode_R_wrk ( ISelEnv* env, IRExpr* e ) +{ + vassert(e); + vassert(typeOfIRExpr(env->type_env, e) == Ity_I1); + + HReg dst = newVRegI(env); + + /* var */ + if (e->tag == Iex_RdTmp) { + HReg tmp = newVRegI(env); + dst = lookupIRTemp(env, e->Iex.RdTmp.tmp); + addInstr(env, LOONGARCH64Instr_LI(1, tmp)); + addInstr(env, LOONGARCH64Instr_Cmp(LAcc_EQ, dst, tmp, dst)); + return dst; + } + + /* const */ + if (e->tag == Iex_Const && e->Iex.Const.con->tag == Ico_U1) { + UInt imm = e->Iex.Const.con->Ico.U1; + addInstr(env, LOONGARCH64Instr_LI(imm, dst)); + return dst; + } + + if (e->tag == Iex_Unop) { + if (e->Iex.Unop.op == Iop_Not1) { + HReg src = iselCondCode_R(env, e->Iex.Unop.arg); + LOONGARCH64RI* ri = LOONGARCH64RI_R(hregZERO()); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_NOR, ri, src, dst)); + return dst; + } + + LOONGARCH64CondCode cc; + switch (e->Iex.Unop.op) { + case Iop_CmpNEZ16: + cc = LAcc_NE; + break; + case Iop_CmpNEZ32: + cc = LAcc_NE; + break; + case Iop_CmpNEZ64: + cc = LAcc_NE; + break; + case Iop_CmpNEZ8: + cc = LAcc_NE; + break; + default: + goto irreducible; + } + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_Cmp(cc, hregZERO(), src, dst)); + return dst; + } + + if (e->tag == Iex_Binop) { + if (e->Iex.Binop.op == Iop_And1) { + HReg src1 = iselCondCode_R(env, e->Iex.Binop.arg1); + HReg src2 = iselCondCode_R(env, e->Iex.Binop.arg2); + LOONGARCH64RI* ri = LOONGARCH64RI_R(src2); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_AND, ri, src1, dst)); + return dst; + } else if (e->Iex.Binop.op == Iop_Or1) { + HReg src1 = iselCondCode_R(env, e->Iex.Binop.arg1); + HReg src2 = iselCondCode_R(env, e->Iex.Binop.arg2); + LOONGARCH64RI* ri = LOONGARCH64RI_R(src2); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_OR, ri, src1, dst)); + return dst; + } + + Bool extend = False; + Bool reverse = False; + LOONGARCH64CondCode cc; + switch (e->Iex.Binop.op) { + case Iop_CasCmpEQ32: + cc = LAcc_EQ; + break; + case Iop_CasCmpEQ64: + cc = LAcc_EQ; + break; + case Iop_CasCmpNE32: + cc = LAcc_NE; + break; + case Iop_CasCmpNE64: + cc = LAcc_NE; + break; + case Iop_CmpEQ32: + cc = LAcc_EQ; + break; + case Iop_CmpEQ64: + cc = LAcc_EQ; + break; + case Iop_CmpLE32S: + cc = LAcc_GE; + reverse = True; + break; + case Iop_CmpLE32U: + cc = LAcc_GEU; + reverse = True; + break; + case Iop_CmpLE64S: + cc = LAcc_GE; + reverse = True; + break; + case Iop_CmpLE64U: + cc = LAcc_GEU; + reverse = True; + break; + case Iop_CmpLT32S: + cc = LAcc_LT; + extend = True; + break; + case Iop_CmpLT32U: + cc = LAcc_LTU; + extend = True; + break; + case Iop_CmpLT64S: + cc = LAcc_LT; + break; + case Iop_CmpLT64U: + cc = LAcc_LTU; + break; + case Iop_CmpNE32: + cc = LAcc_NE; + break; + case Iop_CmpNE64: + cc = LAcc_NE; + break; + default: + goto irreducible; + } + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg src2 = iselIntExpr_R(env, e->Iex.Binop.arg2); + if (extend) { + /* Sign-extend */ + LOONGARCH64RI* ri = LOONGARCH64RI_I(0, 5, False); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri, src1, src1)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_SLLI_W, ri, src2, src2)); + } + if (reverse) { + addInstr(env, LOONGARCH64Instr_Cmp(cc, src1, src2, dst)); + } else { + addInstr(env, LOONGARCH64Instr_Cmp(cc, src2, src1, dst)); + } + return dst; + } + + /* We get here if no pattern matched. */ +irreducible: + ppIRExpr(e); + vpanic("iselCondCode(loongarch64): cannot reduce tree"); +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Integer expressions (128 bit) ---*/ +/*---------------------------------------------------------*/ + +/* Compute a 128-bit value into a register pair, which is returned as + the first two parameters. As with iselIntExpr_R, these may be + either real or virtual regs; in any case they must not be changed + by subsequent code emitted by the caller. */ + +static void iselInt128Expr (HReg* hi, HReg* lo, ISelEnv* env, IRExpr* e) +{ + iselInt128Expr_wrk(hi, lo, env, e); + + /* sanity checks ... */ + vassert(hregClass(*hi) == HRcInt64); + vassert(hregIsVirtual(*hi)); + vassert(hregClass(*lo) == HRcInt64); + vassert(hregIsVirtual(*lo)); +} + +/* DO NOT CALL THIS DIRECTLY ! */ +static void iselInt128Expr_wrk (HReg* hi, HReg* lo, ISelEnv* env, IRExpr* e) +{ + vassert(e); + vassert(typeOfIRExpr(env->type_env, e) == Ity_I128); + + /* --------- TEMP --------- */ + if (e->tag == Iex_RdTmp) { + lookupIRTempPair(hi, lo, env, e->Iex.RdTmp.tmp); + return; + } + + /* --------- BINARY OP --------- */ + if (e->tag == Iex_Binop) { + switch (e->Iex.Binop.op) { + case Iop_64HLto128: { + *hi = iselIntExpr_R(env, e->Iex.Binop.arg1); + *lo = iselIntExpr_R(env, e->Iex.Binop.arg2); + return; + } + case Iop_DivModS64to64: { + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + HReg dstLo = newVRegI(env); + HReg dstHi = newVRegI(env); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_DIV_D, src2, src1, dstLo)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_MOD_D, src2, src1, dstHi)); + *hi = dstHi; + *lo = dstLo; + return; + } + case Iop_DivModU64to64: { + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + HReg dstLo = newVRegI(env); + HReg dstHi = newVRegI(env); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_DIV_DU, src2, src1, dstLo)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_MOD_DU, src2, src1, dstHi)); + *hi = dstHi; + *lo = dstLo; + return; + } + case Iop_MullS64: { + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + HReg dstLo = newVRegI(env); + HReg dstHi = newVRegI(env); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_MUL_D, src2, src1, dstLo)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_MULH_D, src2, src1, dstHi)); + *hi = dstHi; + *lo = dstLo; + return; + } + case Iop_MullU64: { + HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, 0, False); + HReg dstLo = newVRegI(env); + HReg dstHi = newVRegI(env); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_MUL_D, src2, src1, dstLo)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_MULH_DU, src2, src1, dstHi)); + *hi = dstHi; + *lo = dstLo; + return; + } + default: + goto irreducible; + } + } + + /* We get here if no pattern matched. */ +irreducible: + ppIRExpr(e); + vpanic("iselInt128Expr(loongarch64): cannot reduce tree"); +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Floating point expressions (64/32 bit) ---*/ +/*---------------------------------------------------------*/ + +/* Compute a floating point value into a register, the identity of + which is returned. As with iselIntExpr_R, the reg may be either + real or virtual; in any case it must not be changed by subsequent + code emitted by the caller. */ + +static HReg iselFltExpr ( ISelEnv* env, IRExpr* e ) +{ + HReg r = iselFltExpr_wrk(env, e); + + /* sanity checks ... */ + vassert(hregClass(r) == HRcFlt64); + vassert(hregIsVirtual(r)); + + return r; +} + +/* DO NOT CALL THIS DIRECTLY */ +static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env, e); + vassert(e); + vassert(ty == Ity_F32 || ty == Ity_F64); + + switch (e->tag) { + /* --------- TEMP --------- */ + case Iex_RdTmp: + return lookupIRTemp(env, e->Iex.RdTmp.tmp); + + /* --------- LOAD --------- */ + case Iex_Load: { + if (e->Iex.Load.end != Iend_LE) + goto irreducible; + + LOONGARCH64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr, ty); + HReg dst = newVRegF(env); + LOONGARCH64FpLoadOp op; + switch (ty) { + case Ity_F32: + op = (am->tag == LAam_RI) ? LAfpload_FLD_S : LAfpload_FLDX_S; + break; + case Ity_F64: + op = (am->tag == LAam_RI) ? LAfpload_FLD_D : LAfpload_FLDX_D; + break; + default: + goto irreducible; + } + addInstr(env, LOONGARCH64Instr_FpLoad(op, am, dst)); + return dst; + } + + /* --------- GET --------- */ + case Iex_Get: { + Bool ri = e->Iex.Get.offset < 1024; + HReg dst = newVRegF(env); + HReg tmp; + LOONGARCH64AMode* am; + LOONGARCH64FpLoadOp op; + switch (ty) { + case Ity_F32: + op = ri ? LAfpload_FLD_S : LAfpload_FLDX_S; + break; + case Ity_F64: + op = ri ? LAfpload_FLD_D : LAfpload_FLDX_D; + break; + default: + goto irreducible; + } + if (ri) { + am = LOONGARCH64AMode_RI(hregGSP(), e->Iex.Get.offset); + } else { + tmp = newVRegI(env); + addInstr(env, LOONGARCH64Instr_LI(e->Iex.Get.offset, tmp)); + am = LOONGARCH64AMode_RR(hregGSP(), tmp); + } + addInstr(env, LOONGARCH64Instr_FpLoad(op, am, dst)); + return dst; + } + + /* --------- QUATERNARY OP --------- */ + case Iex_Qop: { + switch (e->Iex.Qop.details->op) { + case Iop_MAddF32: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Qop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Qop.details->arg3); + HReg src3 = iselFltExpr(env, e->Iex.Qop.details->arg4); + set_rounding_mode(env, e->Iex.Qop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpTrinary(LAfpbin_FMADD_S, src3, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_MAddF64: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Qop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Qop.details->arg3); + HReg src3 = iselFltExpr(env, e->Iex.Qop.details->arg4); + set_rounding_mode(env, e->Iex.Qop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpTrinary(LAfpbin_FMADD_D, src3, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_MSubF32: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Qop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Qop.details->arg3); + HReg src3 = iselFltExpr(env, e->Iex.Qop.details->arg4); + set_rounding_mode(env, e->Iex.Qop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpTrinary(LAfpbin_FMSUB_S, src3, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_MSubF64: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Qop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Qop.details->arg3); + HReg src3 = iselFltExpr(env, e->Iex.Qop.details->arg4); + set_rounding_mode(env, e->Iex.Qop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpTrinary(LAfpbin_FMSUB_D, src3, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + default: + goto irreducible; + } + } + + /* --------- TERNARY OP --------- */ + case Iex_Triop: { + switch (e->Iex.Triop.details->op) { + case Iop_AddF32: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Triop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Triop.details->arg3); + set_rounding_mode(env, e->Iex.Triop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FADD_S, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_AddF64: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Triop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Triop.details->arg3); + set_rounding_mode(env, e->Iex.Triop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FADD_D, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_DivF32: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Triop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Triop.details->arg3); + set_rounding_mode(env, e->Iex.Triop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FDIV_S, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_DivF64: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Triop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Triop.details->arg3); + set_rounding_mode(env, e->Iex.Triop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FDIV_D, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_MulF32: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Triop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Triop.details->arg3); + set_rounding_mode(env, e->Iex.Triop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FMUL_S, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_MulF64: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Triop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Triop.details->arg3); + set_rounding_mode(env, e->Iex.Triop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FMUL_D, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_ScaleBF32: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Triop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Triop.details->arg3); + set_rounding_mode(env, e->Iex.Triop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FSCALEB_S, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_ScaleBF64: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Triop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Triop.details->arg3); + set_rounding_mode(env, e->Iex.Triop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FSCALEB_D, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_SubF32: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Triop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Triop.details->arg3); + set_rounding_mode(env, e->Iex.Triop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FSUB_S, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_SubF64: { + HReg dst = newVRegF(env); + HReg src1 = iselFltExpr(env, e->Iex.Triop.details->arg2); + HReg src2 = iselFltExpr(env, e->Iex.Triop.details->arg3); + set_rounding_mode(env, e->Iex.Triop.details->arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FSUB_D, src2, src1, dst)); + set_rounding_mode_default(env); + return dst; + } + default: + goto irreducible; + } + } + + /* --------- BINARY OP --------- */ + case Iex_Binop: { + switch (e->Iex.Binop.op) { + case Iop_F64toF32: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FCVT_S_D, src, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_I32StoF32: { + HReg tmp = newVRegF(env); + HReg dst = newVRegF(env); + HReg src = iselIntExpr_R(env, e->Iex.Binop.arg2); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVGR2FR_D, src, tmp)); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FFINT_S_W, tmp, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_I64StoF32: { + HReg tmp = newVRegF(env); + HReg dst = newVRegF(env); + HReg src = iselIntExpr_R(env, e->Iex.Binop.arg2); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVGR2FR_D, src, tmp)); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FFINT_S_L, tmp, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_I64StoF64: { + HReg tmp = newVRegF(env); + HReg dst = newVRegF(env); + HReg src = iselIntExpr_R(env, e->Iex.Binop.arg2); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVGR2FR_D, src, tmp)); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FFINT_D_L, tmp, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_LogBF32: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FLOGB_S, src, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_LogBF64: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FLOGB_D, src, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_MaxNumAbsF32: { + HReg dst = newVRegF(env); + HReg src2 = iselFltExpr(env, e->Iex.Binop.arg2); + HReg src1 = iselFltExpr(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FMAXA_S, src2, src1, dst)); + return dst; + } + case Iop_MaxNumF32: { + HReg dst = newVRegF(env); + HReg src2 = iselFltExpr(env, e->Iex.Binop.arg2); + HReg src1 = iselFltExpr(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FMAX_S, src2, src1, dst)); + return dst; + } + case Iop_MaxNumAbsF64: { + HReg dst = newVRegF(env); + HReg src2 = iselFltExpr(env, e->Iex.Binop.arg2); + HReg src1 = iselFltExpr(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FMAXA_D, src2, src1, dst)); + return dst; + } + case Iop_MaxNumF64: { + HReg dst = newVRegF(env); + HReg src2 = iselFltExpr(env, e->Iex.Binop.arg2); + HReg src1 = iselFltExpr(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FMAX_D, src2, src1, dst)); + return dst; + } + case Iop_MinNumAbsF32: { + HReg dst = newVRegF(env); + HReg src2 = iselFltExpr(env, e->Iex.Binop.arg2); + HReg src1 = iselFltExpr(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FMINA_S, src2, src1, dst)); + return dst; + } + case Iop_MinNumF32: { + HReg dst = newVRegF(env); + HReg src2 = iselFltExpr(env, e->Iex.Binop.arg2); + HReg src1 = iselFltExpr(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FMIN_S, src2, src1, dst)); + return dst; + } + case Iop_MinNumAbsF64: { + HReg dst = newVRegF(env); + HReg src2 = iselFltExpr(env, e->Iex.Binop.arg2); + HReg src1 = iselFltExpr(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FMINA_D, src2, src1, dst)); + return dst; + } + case Iop_MinNumF64: { + HReg dst = newVRegF(env); + HReg src2 = iselFltExpr(env, e->Iex.Binop.arg2); + HReg src1 = iselFltExpr(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpBinary(LAfpbin_FMIN_D, src2, src1, dst)); + return dst; + } + case Iop_RoundF32toInt: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FRINT_S, src, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_RoundF64toInt: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FRINT_D, src, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_RSqrtF32: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FRSQRT_S, src, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_RSqrtF64: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FRSQRT_D, src, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_SqrtF32: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FSQRT_S, src, dst)); + set_rounding_mode_default(env); + return dst; + } + case Iop_SqrtF64: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Binop.arg2); + set_rounding_mode(env, e->Iex.Binop.arg1); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FSQRT_D, src, dst)); + set_rounding_mode_default(env); + return dst; + } + default: + goto irreducible; + } + } + + /* --------- UNARY OP --------- */ + case Iex_Unop: { + switch (e->Iex.Unop.op) { + case Iop_AbsF32: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FABS_S, src, dst)); + return dst; + } + case Iop_AbsF64: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FABS_D, src, dst)); + return dst; + } + case Iop_F32toF64: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FCVT_D_S, src, dst)); + return dst; + } + case Iop_I32StoF64: { + HReg tmp = newVRegF(env); + HReg dst = newVRegF(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVGR2FR_D, src, tmp)); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FFINT_D_W, tmp, dst)); + return dst; + } + case Iop_NegF32: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FNEG_S, src, dst)); + return dst; + } + case Iop_NegF64: { + HReg dst = newVRegF(env); + HReg src = iselFltExpr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FNEG_D, src, dst)); + return dst; + } + case Iop_ReinterpI32asF32: { + HReg dst = newVRegF(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVGR2FR_W, src, dst)); + return dst; + } + case Iop_ReinterpI64asF64: { + HReg dst = newVRegF(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVGR2FR_D, src, dst)); + return dst; + } + default: + goto irreducible; + } + } + + /* --------- LITERAL --------- */ + case Iex_Const: { + /* Just handle the one case. */ + IRConst* con = e->Iex.Const.con; + if (con->tag == Ico_F32i && con->Ico.F32i == 1) { + HReg tmp = newVRegI(env); + HReg dst = newVRegF(env); + LOONGARCH64RI* ri = LOONGARCH64RI_I(1, 12, True); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ADDI_W, ri, hregZERO(), tmp)); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVGR2FR_W, tmp, dst)); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FFINT_S_W, dst, dst)); + return dst; + } else if (con->tag == Ico_F64i && con->Ico.F64i == 1) { + HReg tmp = newVRegI(env); + HReg dst = newVRegF(env); + LOONGARCH64RI* ri = LOONGARCH64RI_I(1, 12, True); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ADDI_D, ri, hregZERO(), tmp)); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_MOVGR2FR_D, tmp, dst)); + addInstr(env, LOONGARCH64Instr_FpUnary(LAfpun_FFINT_D_L, dst, dst)); + return dst; + } else { + goto irreducible; + } + } + + case Iex_ITE: { + HReg r0 = iselFltExpr(env, e->Iex.ITE.iffalse); + HReg r1 = iselFltExpr(env, e->Iex.ITE.iftrue); + HReg cond = iselCondCode_R(env, e->Iex.ITE.cond); + HReg dst = newVRegF(env); + addInstr(env, LOONGARCH64Instr_CMove(cond, r0, r1, dst, False)); + return dst; + } + + default: + break; + } + + /* We get here if no pattern matched. */ +irreducible: + ppIRExpr(e); + vpanic("iselFltExpr(loongarch64): cannot reduce tree"); +} + +/*---------------------------------------------------------*/ +/*--- ISEL: Vector expressions (128 bit) ---*/ +/*---------------------------------------------------------*/ + +/* Compute a vector value into a register, the identity of + which is returned. As with iselIntExpr_R, the reg may be either + real or virtual; in any case it must not be changed by subsequent + code emitted by the caller. */ + +static HReg iselV128Expr ( ISelEnv* env, IRExpr* e ) +{ + HReg r = iselV128Expr_wrk(env, e); + + /* sanity checks ... */ + vassert(hregClass(r) == HRcVec128); + vassert(hregIsVirtual(r)); + + return r; +} + +/* DO NOT CALL THIS DIRECTLY */ +static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env, e); + vassert(e); + vassert(ty == Ity_V128); + + switch (e->tag) { + /* --------- TEMP --------- */ + case Iex_RdTmp: + return lookupIRTemp(env, e->Iex.RdTmp.tmp); + + /* --------- LOAD --------- */ + case Iex_Load: { + if (e->Iex.Load.end != Iend_LE) + goto irreducible; + + HReg dst = newVRegV(env); + LOONGARCH64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr, ty); + LOONGARCH64VecLoadOp op = (am->tag == LAam_RI) ? LAvecload_VLD : LAvecload_VLDX; + addInstr(env, LOONGARCH64Instr_VecLoad(op, am, dst)); + return dst; + } + + /* --------- GET --------- */ + case Iex_Get: { + Bool ri = e->Iex.Get.offset < 1024; + HReg dst = newVRegV(env); + HReg tmp; + LOONGARCH64AMode* am; + LOONGARCH64VecLoadOp op; + if (ri) { + op = LAvecload_VLD; + am = LOONGARCH64AMode_RI(hregGSP(), e->Iex.Get.offset); + } else { + op = LAvecload_VLDX; + tmp = newVRegI(env); + addInstr(env, LOONGARCH64Instr_LI(e->Iex.Get.offset, tmp)); + am = LOONGARCH64AMode_RR(hregGSP(), tmp); + } + addInstr(env, LOONGARCH64Instr_VecLoad(op, am, dst)); + return dst; + } + + /* --------- TERNARY OP --------- */ + case Iex_Triop: { + IRTriop *triop = e->Iex.Triop.details; + switch (triop->op) { + case Iop_SetElem8x16: case Iop_SetElem16x8: case Iop_SetElem32x4: { + LOONGARCH64VecBinOp op; + UChar size; + switch (triop->op) { + case Iop_SetElem8x16: op = LAvecbin_VINSGR2VR_B; size = 4; break; + case Iop_SetElem16x8: op = LAvecbin_VINSGR2VR_H; size = 3; break; + case Iop_SetElem32x4: op = LAvecbin_VINSGR2VR_W; size = 2; break; + default: vassert(0); break; + } + HReg dst = newVRegV(env); + HReg src1 = iselV128Expr(env, triop->arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, triop->arg2, size, False); + HReg src3 = iselIntExpr_R(env, triop->arg3); + addInstr(env, LOONGARCH64Instr_VecMove(dst, src1)); + addInstr(env, LOONGARCH64Instr_VecBinary(op, src2, src3, dst)); + return dst; + } + case Iop_Add32Fx4: case Iop_Add64Fx2: + case Iop_Sub32Fx4: case Iop_Sub64Fx2: + case Iop_Mul32Fx4: case Iop_Mul64Fx2: + case Iop_Div32Fx4: case Iop_Div64Fx2: { + LOONGARCH64VecBinOp op; + switch (triop->op) { + case Iop_Add32Fx4: op = LAvecbin_VFADD_S; break; + case Iop_Add64Fx2: op = LAvecbin_VFADD_D; break; + case Iop_Sub32Fx4: op = LAvecbin_VFSUB_S; break; + case Iop_Sub64Fx2: op = LAvecbin_VFSUB_D; break; + case Iop_Mul32Fx4: op = LAvecbin_VFMUL_S; break; + case Iop_Mul64Fx2: op = LAvecbin_VFMUL_D; break; + case Iop_Div32Fx4: op = LAvecbin_VFDIV_S; break; + case Iop_Div64Fx2: op = LAvecbin_VFDIV_D; break; + default: vassert(0); break; + } + HReg dst = newVRegV(env); + HReg src1 = iselV128Expr(env, triop->arg2); + HReg src2 = iselV128Expr(env, triop->arg3); + set_rounding_mode(env, triop->arg1); + addInstr(env, LOONGARCH64Instr_VecBinary(op, LOONGARCH64RI_R(src2), src1, dst)); + set_rounding_mode_default(env); + return dst; + } + default: goto irreducible; + } + } + + /* --------- BINARY OP --------- */ + case Iex_Binop: { + switch (e->Iex.Binop.op) { + case Iop_AndV128: case Iop_OrV128: case Iop_XorV128: + case Iop_Add8x16: case Iop_Add16x8: case Iop_Add32x4: case Iop_Add64x2: case Iop_Add128x1: + case Iop_Sub8x16: case Iop_Sub16x8: case Iop_Sub32x4: case Iop_Sub64x2: case Iop_Sub128x1: + case Iop_QAdd8Sx16: case Iop_QAdd16Sx8: case Iop_QAdd32Sx4: case Iop_QAdd64Sx2: + case Iop_QAdd8Ux16: case Iop_QAdd16Ux8: case Iop_QAdd32Ux4: case Iop_QAdd64Ux2: + case Iop_QSub8Sx16: case Iop_QSub16Sx8: case Iop_QSub32Sx4: case Iop_QSub64Sx2: + case Iop_QSub8Ux16: case Iop_QSub16Ux8: case Iop_QSub32Ux4: case Iop_QSub64Ux2: + case Iop_InterleaveHI8x16: case Iop_InterleaveHI16x8: case Iop_InterleaveHI32x4: case Iop_InterleaveHI64x2: + case Iop_InterleaveLO8x16: case Iop_InterleaveLO16x8: case Iop_InterleaveLO32x4: case Iop_InterleaveLO64x2: + case Iop_Max8Sx16: case Iop_Max16Sx8: case Iop_Max32Sx4: case Iop_Max64Sx2: + case Iop_Max8Ux16: case Iop_Max16Ux8: case Iop_Max32Ux4: case Iop_Max64Ux2: + case Iop_Min8Sx16: case Iop_Min16Sx8: case Iop_Min32Sx4: case Iop_Min64Sx2: + case Iop_Min8Ux16: case Iop_Min16Ux8: case Iop_Min32Ux4: case Iop_Min64Ux2: + case Iop_CmpEQ8x16: case Iop_CmpEQ16x8: case Iop_CmpEQ32x4: case Iop_CmpEQ64x2: + case Iop_PackOddLanes8x16: case Iop_PackOddLanes16x8: case Iop_PackOddLanes32x4: + case Iop_PackEvenLanes8x16: case Iop_PackEvenLanes16x8: case Iop_PackEvenLanes32x4: + case Iop_Avg8Ux16: case Iop_Avg16Ux8: case Iop_Avg32Ux4: case Iop_Avg64Ux2: + case Iop_Avg8Sx16: case Iop_Avg16Sx8: case Iop_Avg32Sx4: case Iop_Avg64Sx2: + case Iop_Mul8x16: case Iop_Mul16x8: case Iop_Mul32x4: + case Iop_MulHi8Ux16: case Iop_MulHi16Ux8: case Iop_MulHi32Ux4: + case Iop_MulHi8Sx16: case Iop_MulHi16Sx8: case Iop_MulHi32Sx4: + case Iop_Shl8x16: case Iop_Shl16x8: case Iop_Shl32x4: case Iop_Shl64x2: + case Iop_Shr8x16: case Iop_Shr16x8: case Iop_Shr32x4: case Iop_Shr64x2: + case Iop_Sar8x16: case Iop_Sar16x8: case Iop_Sar32x4: case Iop_Sar64x2: + case Iop_CmpGT8Sx16: case Iop_CmpGT16Sx8: case Iop_CmpGT32Sx4: case Iop_CmpGT64Sx2: + case Iop_CmpGT8Ux16: case Iop_CmpGT16Ux8: case Iop_CmpGT32Ux4: case Iop_CmpGT64Ux2: + case Iop_Max32Fx4: case Iop_Max64Fx2: + case Iop_Min32Fx4: case Iop_Min64Fx2: { + LOONGARCH64VecBinOp op; + Bool reverse = False; + switch (e->Iex.Binop.op) { + case Iop_AndV128: op = LAvecbin_VAND_V; break; + case Iop_OrV128: op = LAvecbin_VOR_V; break; + case Iop_XorV128: op = LAvecbin_VXOR_V; break; + case Iop_Add8x16: op = LAvecbin_VADD_B; break; + case Iop_Add16x8: op = LAvecbin_VADD_H; break; + case Iop_Add32x4: op = LAvecbin_VADD_W; break; + case Iop_Add64x2: op = LAvecbin_VADD_D; break; + case Iop_Add128x1: op = LAvecbin_VADD_Q; break; + case Iop_Sub8x16: op = LAvecbin_VSUB_B; break; + case Iop_Sub16x8: op = LAvecbin_VSUB_H; break; + case Iop_Sub32x4: op = LAvecbin_VSUB_W; break; + case Iop_Sub64x2: op = LAvecbin_VSUB_D; break; + case Iop_Sub128x1: op = LAvecbin_VSUB_Q; break; + case Iop_QAdd8Sx16: op = LAvecbin_VSADD_B; break; + case Iop_QAdd16Sx8: op = LAvecbin_VSADD_H; break; + case Iop_QAdd32Sx4: op = LAvecbin_VSADD_W; break; + case Iop_QAdd64Sx2: op = LAvecbin_VSADD_D; break; + case Iop_QAdd8Ux16: op = LAvecbin_VSADD_BU; break; + case Iop_QAdd16Ux8: op = LAvecbin_VSADD_HU; break; + case Iop_QAdd32Ux4: op = LAvecbin_VSADD_WU; break; + case Iop_QAdd64Ux2: op = LAvecbin_VSADD_DU; break; + case Iop_QSub8Sx16: op = LAvecbin_VSSUB_B; break; + case Iop_QSub16Sx8: op = LAvecbin_VSSUB_H; break; + case Iop_QSub32Sx4: op = LAvecbin_VSSUB_W; break; + case Iop_QSub64Sx2: op = LAvecbin_VSSUB_D; break; + case Iop_QSub8Ux16: op = LAvecbin_VSSUB_BU; break; + case Iop_QSub16Ux8: op = LAvecbin_VSSUB_HU; break; + case Iop_QSub32Ux4: op = LAvecbin_VSSUB_WU; break; + case Iop_QSub64Ux2: op = LAvecbin_VSSUB_DU; break; + case Iop_InterleaveHI8x16: op = LAvecbin_VILVH_B; break; + case Iop_InterleaveHI16x8: op = LAvecbin_VILVH_H; break; + case Iop_InterleaveHI32x4: op = LAvecbin_VILVH_W; break; + case Iop_InterleaveHI64x2: op = LAvecbin_VILVH_D; break; + case Iop_InterleaveLO8x16: op = LAvecbin_VILVL_B; break; + case Iop_InterleaveLO16x8: op = LAvecbin_VILVL_H; break; + case Iop_InterleaveLO32x4: op = LAvecbin_VILVL_W; break; + case Iop_InterleaveLO64x2: op = LAvecbin_VILVL_D; break; + case Iop_Max8Sx16: op = LAvecbin_VMAX_B; break; + case Iop_Max16Sx8: op = LAvecbin_VMAX_H; break; + case Iop_Max32Sx4: op = LAvecbin_VMAX_W; break; + case Iop_Max64Sx2: op = LAvecbin_VMAX_D; break; + case Iop_Max8Ux16: op = LAvecbin_VMAX_BU; break; + case Iop_Max16Ux8: op = LAvecbin_VMAX_HU; break; + case Iop_Max32Ux4: op = LAvecbin_VMAX_WU; break; + case Iop_Max64Ux2: op = LAvecbin_VMAX_DU; break; + case Iop_Min8Sx16: op = LAvecbin_VMIN_B; break; + case Iop_Min16Sx8: op = LAvecbin_VMIN_H; break; + case Iop_Min32Sx4: op = LAvecbin_VMIN_W; break; + case Iop_Min64Sx2: op = LAvecbin_VMIN_D; break; + case Iop_Min8Ux16: op = LAvecbin_VMIN_BU; break; + case Iop_Min16Ux8: op = LAvecbin_VMIN_HU; break; + case Iop_Min32Ux4: op = LAvecbin_VMIN_WU; break; + case Iop_Min64Ux2: op = LAvecbin_VMIN_DU; break; + case Iop_CmpEQ8x16: op = LAvecbin_VSEQ_B; break; + case Iop_CmpEQ16x8: op = LAvecbin_VSEQ_H; break; + case Iop_CmpEQ32x4: op = LAvecbin_VSEQ_W; break; + case Iop_CmpEQ64x2: op = LAvecbin_VSEQ_D; break; + case Iop_PackOddLanes8x16: op = LAvecbin_VPICKOD_B; break; + case Iop_PackOddLanes16x8: op = LAvecbin_VPICKOD_H; break; + case Iop_PackOddLanes32x4: op = LAvecbin_VPICKOD_W; break; + case Iop_PackEvenLanes8x16: op = LAvecbin_VPICKEV_B; break; + case Iop_PackEvenLanes16x8: op = LAvecbin_VPICKEV_H; break; + case Iop_PackEvenLanes32x4: op = LAvecbin_VPICKEV_W; break; + case Iop_Avg8Ux16: op = LAvecbin_VAVGR_BU; break; + case Iop_Avg16Ux8: op = LAvecbin_VAVGR_HU; break; + case Iop_Avg32Ux4: op = LAvecbin_VAVGR_WU; break; + case Iop_Avg64Ux2: op = LAvecbin_VAVGR_DU; break; + case Iop_Avg8Sx16: op = LAvecbin_VAVGR_B; break; + case Iop_Avg16Sx8: op = LAvecbin_VAVGR_H; break; + case Iop_Avg32Sx4: op = LAvecbin_VAVGR_W; break; + case Iop_Avg64Sx2: op = LAvecbin_VAVGR_D; break; + case Iop_Mul8x16: op = LAvecbin_VMUL_B; break; + case Iop_Mul16x8: op = LAvecbin_VMUL_H; break; + case Iop_Mul32x4: op = LAvecbin_VMUL_W; break; + case Iop_MulHi8Ux16: op = LAvecbin_VMUH_BU; break; + case Iop_MulHi16Ux8: op = LAvecbin_VMUH_HU; break; + case Iop_MulHi32Ux4: op = LAvecbin_VMUH_WU; break; + case Iop_MulHi8Sx16: op = LAvecbin_VMUH_B; break; + case Iop_MulHi16Sx8: op = LAvecbin_VMUH_H; break; + case Iop_MulHi32Sx4: op = LAvecbin_VMUH_W; break; + case Iop_Shl8x16: op = LAvecbin_VSLL_B; break; + case Iop_Shl16x8: op = LAvecbin_VSLL_H; break; + case Iop_Shl32x4: op = LAvecbin_VSLL_W; break; + case Iop_Shl64x2: op = LAvecbin_VSLL_D; break; + case Iop_Shr8x16: op = LAvecbin_VSRL_B; break; + case Iop_Shr16x8: op = LAvecbin_VSRL_H; break; + case Iop_Shr32x4: op = LAvecbin_VSRL_W; break; + case Iop_Shr64x2: op = LAvecbin_VSRL_D; break; + case Iop_Sar8x16: op = LAvecbin_VSRA_B; break; + case Iop_Sar16x8: op = LAvecbin_VSRA_H; break; + case Iop_Sar32x4: op = LAvecbin_VSRA_W; break; + case Iop_Sar64x2: op = LAvecbin_VSRA_D; break; + case Iop_CmpGT8Sx16: op = LAvecbin_VSLT_B; reverse = True; break; + case Iop_CmpGT16Sx8: op = LAvecbin_VSLT_H; reverse = True; break; + case Iop_CmpGT32Sx4: op = LAvecbin_VSLT_W; reverse = True; break; + case Iop_CmpGT64Sx2: op = LAvecbin_VSLT_D; reverse = True; break; + case Iop_CmpGT8Ux16: op = LAvecbin_VSLT_BU; reverse = True; break; + case Iop_CmpGT16Ux8: op = LAvecbin_VSLT_HU; reverse = True; break; + case Iop_CmpGT32Ux4: op = LAvecbin_VSLT_WU; reverse = True; break; + case Iop_CmpGT64Ux2: op = LAvecbin_VSLT_DU; reverse = True; break; + case Iop_Max32Fx4: op = LAvecbin_VFMAX_S; break; + case Iop_Max64Fx2: op = LAvecbin_VFMAX_D; break; + case Iop_Min32Fx4: op = LAvecbin_VFMIN_S; break; + case Iop_Min64Fx2: op = LAvecbin_VFMIN_D; break; + default: vassert(0); break; + } + HReg dst = newVRegV(env); + HReg src1 = iselV128Expr(env, e->Iex.Binop.arg1); + HReg src2 = iselV128Expr(env, e->Iex.Binop.arg2); + if (reverse) + addInstr(env, LOONGARCH64Instr_VecBinary(op, LOONGARCH64RI_R(src1), src2, dst)); + else + addInstr(env, LOONGARCH64Instr_VecBinary(op, LOONGARCH64RI_R(src2), src1, dst)); + return dst; + } + case Iop_ShlN8x16: case Iop_ShlN16x8: case Iop_ShlN32x4: case Iop_ShlN64x2: + case Iop_ShrN8x16: case Iop_ShrN16x8: case Iop_ShrN32x4: case Iop_ShrN64x2: + case Iop_SarN8x16: case Iop_SarN16x8: case Iop_SarN32x4: case Iop_SarN64x2: + case Iop_ShlV128: case Iop_ShrV128: { + UChar size; + LOONGARCH64VecBinOp op; + switch (e->Iex.Binop.op) { + case Iop_ShlN8x16: op = LAvecbin_VSLLI_B; size = 3; break; + case Iop_ShlN16x8: op = LAvecbin_VSLLI_H; size = 4; break; + case Iop_ShlN32x4: op = LAvecbin_VSLLI_W; size = 5; break; + case Iop_ShlN64x2: op = LAvecbin_VSLLI_D; size = 6; break; + case Iop_ShrN8x16: op = LAvecbin_VSRLI_B; size = 3; break; + case Iop_ShrN16x8: op = LAvecbin_VSRLI_H; size = 4; break; + case Iop_ShrN32x4: op = LAvecbin_VSRLI_W; size = 5; break; + case Iop_ShrN64x2: op = LAvecbin_VSRLI_D; size = 6; break; + case Iop_SarN8x16: op = LAvecbin_VSRAI_B; size = 3; break; + case Iop_SarN16x8: op = LAvecbin_VSRAI_H; size = 4; break; + case Iop_SarN32x4: op = LAvecbin_VSRAI_W; size = 5; break; + case Iop_SarN64x2: op = LAvecbin_VSRAI_D; size = 6; break; + case Iop_ShlV128: op = LAvecbin_VBSLL_V; size = 5; break; + case Iop_ShrV128: op = LAvecbin_VBSRL_V; size = 5; break; + default: vassert(0); break; + } + HReg dst = newVRegV(env); + HReg src1 = iselV128Expr(env, e->Iex.Binop.arg1); + LOONGARCH64RI* src2 = iselIntExpr_RI(env, e->Iex.Binop.arg2, size, False); + vassert(e->Iex.Binop.arg2->tag == Iex_Const); + vassert(e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8); + vassert(e->Iex.Binop.arg2->Iex.Const.con->Ico.U8 <= 63); + addInstr(env, LOONGARCH64Instr_VecBinary(op, src2, src1, dst)); + return dst; + } + case Iop_64HLtoV128: { + HReg dst = newVRegV(env); + HReg sHi = iselIntExpr_R(env, e->Iex.Binop.arg1); + HReg sLow = iselIntExpr_R(env, e->Iex.Binop.arg2); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_D, + LOONGARCH64RI_I(0, 1, False), sLow, dst)); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_D, + LOONGARCH64RI_I(1, 1, False), sHi, dst)); + return dst; + } + default: goto irreducible; + } + } + + /* --------- UNARY OP --------- */ + case Iex_Unop: { + switch (e->Iex.Unop.op) { + case Iop_32UtoV128: { + HReg dst = newVRegV(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_W, + LOONGARCH64RI_I(0, 2, False), src, dst)); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_W, + LOONGARCH64RI_I(1, 2, False), hregZERO(), dst)); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_W, + LOONGARCH64RI_I(2, 2, False), hregZERO(), dst)); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_W, + LOONGARCH64RI_I(3, 2, False), hregZERO(), dst)); + return dst; + } + case Iop_64UtoV128: { + HReg dst = newVRegV(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_D, + LOONGARCH64RI_I(0, 1, False), src, dst)); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_D, + LOONGARCH64RI_I(1, 1, False), hregZERO(), dst)); + return dst; + } + case Iop_NotV128: { + HReg dst = newVRegV(env); + HReg src = iselV128Expr(env, e->Iex.Unop.arg); + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VNOR_V, + LOONGARCH64RI_R(src), src, dst)); + return dst; + } + case Iop_Abs8x16: case Iop_Abs16x8: + case Iop_Abs32x4: case Iop_Abs64x2: { + LOONGARCH64VecBinOp subOp, addOp; + switch (e->Iex.Unop.op) { + case Iop_Abs8x16: + subOp = LAvecbin_VSUB_B; + addOp = LAvecbin_VADDA_B; + break; + case Iop_Abs16x8: + subOp = LAvecbin_VSUB_H; + addOp = LAvecbin_VADDA_H; + break; + case Iop_Abs32x4: + subOp = LAvecbin_VSUB_W; + addOp = LAvecbin_VADDA_W; + break; + case Iop_Abs64x2: + subOp = LAvecbin_VSUB_D; + addOp = LAvecbin_VADDA_D; + break; + default: + vassert(0); + break; + }; + HReg dst = newVRegV(env); + HReg src = iselV128Expr(env, e->Iex.Unop.arg); + HReg sub = newVRegV(env); + addInstr(env, LOONGARCH64Instr_VecBinary(subOp, LOONGARCH64RI_R(src), src, sub)); + addInstr(env, LOONGARCH64Instr_VecBinary(addOp, LOONGARCH64RI_R(src), sub, dst)); + return dst; + } + case Iop_Dup8x16: case Iop_Dup16x8: case Iop_Dup32x4: { + HReg dst = newVRegV(env); + HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); + LOONGARCH64VecUnOp op; + switch (e->Iex.Unop.op) { + case Iop_Dup8x16: op = LAvecun_VREPLGR2VR_B; break; + case Iop_Dup16x8: op = LAvecun_VREPLGR2VR_H; break; + case Iop_Dup32x4: op = LAvecun_VREPLGR2VR_W; break; + default: vassert(0); break; + } + addInstr(env, LOONGARCH64Instr_VecUnary(op, src, dst)); + return dst; + } + case Iop_V256toV128_0: + case Iop_V256toV128_1: { + HReg vHi, vLo; + iselV256Expr(&vHi, &vLo, env, e->Iex.Unop.arg); + return (e->Iex.Unop.op == Iop_V256toV128_1) ? vHi : vLo; + } + default: + goto irreducible; + } + } + + case Iex_Const: { + IRConst *con = e->Iex.Const.con; + + if (con->tag != Ico_V128) { + vpanic("iselV128Expr.const(LoongArch)"); + goto irreducible; + } + + HReg dst = newVRegV(env); + UShort val = con->Ico.V128; + + if (val == 0) { + addInstr(env, LOONGARCH64Instr_VecUnary(LAvecun_VREPLGR2VR_D, hregZERO(), dst)); + } else { + HReg r_tmp = newVRegI(env); + UInt i; + addInstr(env, LOONGARCH64Instr_LI(0xfful, r_tmp)); + if (val & 1) { + addInstr(env, LOONGARCH64Instr_VecUnary(LAvecun_VREPLGR2VR_B, r_tmp, dst)); + } else { + addInstr(env, LOONGARCH64Instr_VecUnary(LAvecun_VREPLGR2VR_B, hregZERO(), dst)); + } + for (i = 1; i < 16; i++) { + val >>= 1; + if (val & 1) { + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_B, + LOONGARCH64RI_I(i, 4, False), + r_tmp, dst)); + } else { + addInstr(env, LOONGARCH64Instr_VecBinary(LAvecbin_VINSGR2VR_B, + LOONGARCH64RI_I(i, 4, False), + hregZERO(), dst)); + } + } + } + + return dst; + } + + default: + break; + } + + /* We get here if no pattern matched. */ +irreducible: + ppIRExpr(e); + vpanic("iselV128Expr(loongarch64): cannot reduce tree"); +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Vector expressions (256 bit) ---*/ +/*---------------------------------------------------------*/ + +/* Compute a vector value into a register, the identity of + which is returned. As with iselIntExpr_R, the reg may be either + real or virtual; in any case it must not be changed by subsequent + code emitted by the caller. */ + +static void iselV256Expr ( HReg* hi, HReg* lo, + ISelEnv* env, IRExpr* e ) +{ + iselV256Expr_wrk( hi, lo, env, e ); + + /* sanity checks ... */ + vassert(hregClass(*hi) == HRcVec128); + vassert(hregIsVirtual(*hi)); + vassert(hregClass(*lo) == HRcVec128); + vassert(hregIsVirtual(*lo)); +} + +/* DO NOT CALL THIS DIRECTLY */ +static void iselV256Expr_wrk ( HReg* hi, HReg* lo, + ISelEnv* env, IRExpr* e ) +{ + IRType ty = typeOfIRExpr(env->type_env, e); + vassert(e); + vassert(ty == Ity_V256); + + switch (e->tag) { + /* --------- TEMP --------- */ + case Iex_RdTmp: { + lookupIRTempPair(hi, lo, env, e->Iex.RdTmp.tmp); + return; + } + + /* --------- LOAD --------- */ + case Iex_Load: { + if (e->Iex.Load.end != Iend_LE) + goto irreducible; + + HReg dstHi = newVRegV(env); + HReg dstLo = newVRegV(env); + LOONGARCH64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr, ty); + LOONGARCH64VecLoadOp op = (am->tag == LAam_RI) ? LAvecload_VLD : LAvecload_VLDX; + HReg addr = iselIntExpr_R(env, e->Iex.Load.addr); + LOONGARCH64AMode* am16 = LOONGARCH64AMode_RI(addr, 16); + addInstr(env, LOONGARCH64Instr_VecLoad(op, am, dstLo)); + addInstr(env, LOONGARCH64Instr_VecLoad(LAvecload_VLD, am16, dstHi)); + *hi = dstHi; + *lo = dstLo; + return; + } + + /* --------- GET --------- */ + case Iex_Get: { + Bool ri = e->Iex.Get.offset < 1024; + HReg dstHi = newVRegV(env); + HReg dstLo = newVRegV(env); + LOONGARCH64VecLoadOp op, op2; + HReg tmp, tmp2; + LOONGARCH64AMode* am; + LOONGARCH64AMode* am2; + if (ri) { + op = LAvecload_VLD; + am = LOONGARCH64AMode_RI(hregGSP(), e->Iex.Get.offset); + } else { + op = LAvecload_VLDX; + tmp = newVRegI(env); + addInstr(env, LOONGARCH64Instr_LI(e->Iex.Get.offset, tmp)); + am = LOONGARCH64AMode_RR(hregGSP(), tmp); + } + if (e->Iex.Get.offset + 16 < 1024) { + op2 = LAvecload_VLD; + am2 = LOONGARCH64AMode_RI(hregGSP(), e->Iex.Get.offset + 16); + } else { + op2 = LAvecload_VLDX; + tmp2 = newVRegI(env); + addInstr(env, LOONGARCH64Instr_LI(e->Iex.Get.offset + 16, tmp2)); + am2 = LOONGARCH64AMode_RR(hregGSP(), tmp2); + } + addInstr(env, LOONGARCH64Instr_VecLoad(op, am, dstLo)); + addInstr(env, LOONGARCH64Instr_VecLoad(op2, am2, dstHi)); + *hi = dstHi; + *lo = dstLo; + return; + } + + /* --------- BINARY OP --------- */ + case Iex_Binop: { + switch (e->Iex.Binop.op) { + case Iop_V128HLtoV256: { + *hi = iselV128Expr(env, e->Iex.Binop.arg1); + *lo = iselV128Expr(env, e->Iex.Binop.arg2); + return; + } + case Iop_XorV256: + case Iop_CmpEQ8x32: case Iop_CmpEQ16x16: case Iop_CmpEQ32x8: case Iop_CmpEQ64x4: + case Iop_Max8Sx32: case Iop_Max16Sx16: case Iop_Max32Sx8: case Iop_Max64Sx4: + case Iop_Max8Ux32: case Iop_Max16Ux16: case Iop_Max32Ux8: case Iop_Max64Ux4: + case Iop_Min8Sx32: case Iop_Min16Sx16: case Iop_Min32Sx8: case Iop_Min64Sx4: + case Iop_Min8Ux32: case Iop_Min16Ux16: case Iop_Min32Ux8: case Iop_Min64Ux4: { + LOONGARCH64VecBinOp op; + switch (e->Iex.Binop.op) { + case Iop_XorV256: op = LAvecbin_VXOR_V; break; + case Iop_CmpEQ8x32: op = LAvecbin_VSEQ_B; break; + case Iop_CmpEQ16x16: op = LAvecbin_VSEQ_H; break; + case Iop_CmpEQ32x8: op = LAvecbin_VSEQ_W; break; + case Iop_CmpEQ64x4: op = LAvecbin_VSEQ_D; break; + case Iop_Max8Sx32: op = LAvecbin_VMAX_B; break; + case Iop_Max16Sx16: op = LAvecbin_VMAX_H; break; + case Iop_Max32Sx8: op = LAvecbin_VMAX_W; break; + case Iop_Max64Sx4: op = LAvecbin_VMAX_D; break; + case Iop_Max8Ux32: op = LAvecbin_VMAX_BU; break; + case Iop_Max16Ux16: op = LAvecbin_VMAX_HU; break; + case Iop_Max32Ux8: op = LAvecbin_VMAX_WU; break; + case Iop_Max64Ux4: op = LAvecbin_VMAX_DU; break; + case Iop_Min8Sx32: op = LAvecbin_VMIN_B; break; + case Iop_Min16Sx16: op = LAvecbin_VMIN_H; break; + case Iop_Min32Sx8: op = LAvecbin_VMIN_W; break; + case Iop_Min64Sx4: op = LAvecbin_VMIN_D; break; + case Iop_Min8Ux32: op = LAvecbin_VMIN_BU; break; + case Iop_Min16Ux16: op = LAvecbin_VMIN_HU; break; + case Iop_Min32Ux8: op = LAvecbin_VMIN_WU; break; + case Iop_Min64Ux4: op = LAvecbin_VMIN_DU; break; + default: vassert(0); break; + } + HReg src1Hi, src1Lo, src2Hi, src2Lo; + iselV256Expr(&src1Hi, &src1Lo, env, e->Iex.Binop.arg1); + iselV256Expr(&src2Hi, &src2Lo, env, e->Iex.Binop.arg2); + HReg dstHi = newVRegV(env); + HReg dstLo = newVRegV(env); + addInstr(env, LOONGARCH64Instr_VecBinary(op, LOONGARCH64RI_R(src2Hi), src1Hi, dstHi)); + addInstr(env, LOONGARCH64Instr_VecBinary(op, LOONGARCH64RI_R(src2Lo), src1Lo, dstLo)); + *hi = dstHi; + *lo = dstLo; + return; + } + default: goto irreducible; + } + } + + default: + break; + } + + /* We get here if no pattern matched. */ +irreducible: + ppIRExpr(e); + vpanic("iselV256Expr(loongarch64): cannot reduce tree"); +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Statements ---*/ +/*---------------------------------------------------------*/ + +static void iselStmtStore ( ISelEnv* env, IRStmt* stmt ) +{ + IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr); + IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data); + + if (tya != Ity_I64 || stmt->Ist.Store.end != Iend_LE) + vpanic("iselStmt(loongarch64): Ist_Store"); + + LOONGARCH64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd); + LOONGARCH64StoreOp op; + Bool ok = True; + switch (tyd) { + case Ity_I8: + op = (am->tag == LAam_RI) ? LAstore_ST_B : LAstore_STX_B; + break; + case Ity_I16: + op = (am->tag == LAam_RI) ? LAstore_ST_H : LAstore_STX_H; + break; + case Ity_I32: + op = (am->tag == LAam_RI) ? LAstore_ST_W : LAstore_STX_W; + break; + case Ity_I64: + op = (am->tag == LAam_RI) ? LAstore_ST_D : LAstore_STX_D; + break; + default: + ok = False; + break; + } + if (ok) { + HReg src = iselIntExpr_R(env, stmt->Ist.Store.data); + addInstr(env, LOONGARCH64Instr_Store(op, am, src)); + return; + } + + LOONGARCH64FpStoreOp fop; + ok = True; + switch (tyd) { + case Ity_F32: + fop = (am->tag == LAam_RI) ? LAfpstore_FST_S : LAfpstore_FSTX_S; + break; + case Ity_F64: + fop = (am->tag == LAam_RI) ? LAfpstore_FST_D : LAfpstore_FSTX_D; + break; + default: + ok = False; + break; + } + if (ok) { + HReg src = iselFltExpr(env, stmt->Ist.Store.data); + addInstr(env, LOONGARCH64Instr_FpStore(fop, am, src)); + return; + } + + if (tyd == Ity_V128) { + LOONGARCH64VecStoreOp vop = (am->tag == LAam_RI) ? LAvecstore_VST : LAvecstore_VSTX; + HReg src = iselV128Expr(env, stmt->Ist.Store.data); + addInstr(env, LOONGARCH64Instr_VecStore(vop, am, src)); + } else if (tyd == Ity_V256) { + LOONGARCH64VecStoreOp vop = (am->tag == LAam_RI) ? LAvecstore_VST : LAvecstore_VSTX; + HReg addr = iselIntExpr_R(env, stmt->Ist.Store.addr); + LOONGARCH64AMode* am16 = LOONGARCH64AMode_RI(addr, 16); + HReg hi, lo; + iselV256Expr(&hi, &lo, env, stmt->Ist.Store.data); + addInstr(env, LOONGARCH64Instr_VecStore(vop, am, lo)); + addInstr(env, LOONGARCH64Instr_VecStore(LAvecstore_VST, am16, hi)); + } else { + vpanic("iselStmt(loongarch64): Ist_Store"); + } +} + +static void iselStmtPut ( ISelEnv* env, IRStmt* stmt ) +{ + IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.Put.data); + + Bool ri = stmt->Ist.Put.offset < 1024; + HReg tmp; + LOONGARCH64AMode* am; + + if (ri) { + am = LOONGARCH64AMode_RI(hregGSP(), stmt->Ist.Put.offset); + } else { + tmp = newVRegI(env); + addInstr(env, LOONGARCH64Instr_LI(stmt->Ist.Put.offset, tmp)); + am = LOONGARCH64AMode_RR(hregGSP(), tmp); + } + + LOONGARCH64StoreOp op; + Bool ok = True; + switch (ty) { + case Ity_I8: + op = ri ? LAstore_ST_B : LAstore_STX_B; + break; + case Ity_I16: + op = ri ? LAstore_ST_H : LAstore_STX_H; + break; + case Ity_I32: + op = ri ? LAstore_ST_W : LAstore_STX_W; + break; + case Ity_I64: + op = ri ? LAstore_ST_D : LAstore_STX_D; + break; + default: + ok = False; + break; + } + if (ok) { + HReg src = iselIntExpr_R(env, stmt->Ist.Put.data); + addInstr(env, LOONGARCH64Instr_Store(op, am, src)); + return; + } + + LOONGARCH64FpStoreOp fop; + ok = True; + switch (ty) { + case Ity_F32: + fop = ri ? LAfpstore_FST_S : LAfpstore_FSTX_S; + break; + case Ity_F64: + fop = ri ? LAfpstore_FST_D : LAfpstore_FSTX_D; + break; + default: + ok = False; + break; + } + if (ok) { + HReg src = iselFltExpr(env, stmt->Ist.Put.data); + addInstr(env, LOONGARCH64Instr_FpStore(fop, am, src)); + return; + } + + if (ty == Ity_V128) { + LOONGARCH64VecStoreOp vop = ri ? LAvecstore_VST : LAvecstore_VSTX; + HReg src = iselV128Expr(env, stmt->Ist.Put.data); + addInstr(env, LOONGARCH64Instr_VecStore(vop, am, src)); + } else if (ty == Ity_V256) { + LOONGARCH64VecStoreOp vop = ri ? LAvecstore_VST : LAvecstore_VSTX; + LOONGARCH64VecStoreOp vop2; + HReg hi, lo; + HReg tmp2; + LOONGARCH64AMode* am2; + if (stmt->Ist.Put.offset + 16 < 1024) { + vop2 = LAvecstore_VST; + am2 = LOONGARCH64AMode_RI(hregGSP(), stmt->Ist.Put.offset + 16); + } else { + vop2 = LAvecstore_VSTX; + tmp2 = newVRegI(env); + addInstr(env, LOONGARCH64Instr_LI(stmt->Ist.Put.offset + 16, tmp2)); + am2 = LOONGARCH64AMode_RR(hregGSP(), tmp2); + } + iselV256Expr(&hi, &lo, env, stmt->Ist.Put.data); + addInstr(env, LOONGARCH64Instr_VecStore(vop, am, lo)); + addInstr(env, LOONGARCH64Instr_VecStore(vop2, am2, hi)); + } else { + vpanic("iselStmt(loongarch64): Ist_Put"); + } +} + +static void iselStmtTmp ( ISelEnv* env, IRStmt* stmt ) +{ + IRTemp tmp = stmt->Ist.WrTmp.tmp; + IRType ty = typeOfIRTemp(env->type_env, tmp); + + switch (ty) { + case Ity_I8: + case Ity_I16: + case Ity_I32: + case Ity_I64: { + HReg dst = lookupIRTemp(env, tmp); + HReg src = iselIntExpr_R(env, stmt->Ist.WrTmp.data); + addInstr(env, LOONGARCH64Instr_Move(dst, src)); + break; + } + case Ity_I1: { + HReg dst = lookupIRTemp(env, tmp); + HReg src = iselCondCode_R(env, stmt->Ist.WrTmp.data); + addInstr(env, LOONGARCH64Instr_Move(dst, src)); + break; + } + case Ity_F32: { + HReg dst = lookupIRTemp(env, tmp); + HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_FMOV_S, src, dst)); + break; + } + case Ity_F64: { + HReg dst = lookupIRTemp(env, tmp); + HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data); + addInstr(env, LOONGARCH64Instr_FpMove(LAfpmove_FMOV_D, src, dst)); + break; + } + case Ity_V128: { + HReg dst = lookupIRTemp(env, tmp); + HReg src = iselV128Expr(env, stmt->Ist.WrTmp.data); + addInstr(env, LOONGARCH64Instr_VecMove(dst, src)); + break; + } + case Ity_V256: { + HReg hi, lo, dstHi, dstLo; + lookupIRTempPair(&dstHi, &dstLo, env, tmp); + iselV256Expr(&hi, &lo, env, stmt->Ist.WrTmp.data); + addInstr(env, LOONGARCH64Instr_VecMove(dstHi, hi)); + addInstr(env, LOONGARCH64Instr_VecMove(dstLo, lo)); + break; + } + default: + vpanic("iselStmt(loongarch64): Ist_WrTmp"); + break; + } +} + +static void iselStmtDirty ( ISelEnv* env, IRStmt* stmt ) +{ + IRDirty* d = stmt->Ist.Dirty.details; + + /* Figure out the return type, if any. */ + IRType retty = Ity_INVALID; + if (d->tmp != IRTemp_INVALID) + retty = typeOfIRTemp(env->type_env, d->tmp); + + Bool retty_ok = False; + switch (retty) { + case Ity_INVALID: /* function doesn't return anything */ + case Ity_I8: case Ity_I16: case Ity_I32: case Ity_I64: + case Ity_V128: case Ity_V256: + retty_ok = True; + break; + default: + break; + } + if (!retty_ok) + vpanic("iselStmt(loongarch64): Ist_Dirty"); + + /* Marshal args, do the call, and set the return value to 0x555..555 + if this is a conditional call that returns a value and the + call is skipped. */ + UInt addToSp = 0; + RetLoc rloc = mk_RetLoc_INVALID(); + doHelperCall(&addToSp, &rloc, env, d->guard, d->cee, retty, d->args); + vassert(is_sane_RetLoc(rloc)); + + /* Now figure out what to do with the returned value, if any. */ + switch (retty) { + case Ity_INVALID: { + /* No return value. Nothing to do. */ + vassert(d->tmp == IRTemp_INVALID); + vassert(rloc.pri == RLPri_None); + vassert(addToSp == 0); + break; + } + case Ity_I8: case Ity_I16: case Ity_I32: case Ity_I64: { + vassert(rloc.pri == RLPri_Int); + vassert(addToSp == 0); + /* The returned value is in $a0. Park it in the register + associated with tmp. */ + HReg dst = lookupIRTemp(env, d->tmp); + addInstr(env, LOONGARCH64Instr_Move(dst, hregLOONGARCH64_R4())); + break; + } + case Ity_V128: { + /* The returned value is on the stack, and *retloc tells + us where. Fish it off the stack and then move the + stack pointer upwards to clear it, as directed by + doHelperCall. */ + vassert(rloc.pri == RLPri_V128SpRel); + vassert((rloc.spOff < 512) && (rloc.spOff > -512)); + vassert(addToSp >= 16); + HReg dst = lookupIRTemp(env, d->tmp); + HReg tmp = newVRegI(env); + addInstr(env, LOONGARCH64Instr_Move(tmp, hregSP())); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ADDI_D, + LOONGARCH64RI_I(rloc.spOff, 12, True), + tmp, tmp)); + addInstr(env, LOONGARCH64Instr_VecLoad(LAvecload_VLD, + LOONGARCH64AMode_RI(tmp, 0), + dst)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ADDI_D, + LOONGARCH64RI_I(addToSp, 12, True), + hregSP(), hregSP())); + break; + } + case Ity_V256: { + /* See comments for Ity_V128. */ + vassert(rloc.pri == RLPri_V256SpRel); + vassert((rloc.spOff + 16 < 512) && (rloc.spOff > -512)); + vassert(addToSp >= 32); + HReg dstLo, dstHi; + lookupIRTempPair(&dstHi, &dstLo, env, d->tmp); + HReg tmp = newVRegI(env); + addInstr(env, LOONGARCH64Instr_Move(tmp, hregSP())); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ADDI_D, + LOONGARCH64RI_I(rloc.spOff, 12, True), + tmp, tmp)); + addInstr(env, LOONGARCH64Instr_VecLoad(LAvecload_VLD, + LOONGARCH64AMode_RI(tmp, 0), + dstLo)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ADDI_D, + LOONGARCH64RI_I(16, 12, True), + tmp, tmp)); + addInstr(env, LOONGARCH64Instr_VecLoad(LAvecload_VLD, + LOONGARCH64AMode_RI(tmp, 0), + dstHi)); + addInstr(env, LOONGARCH64Instr_Binary(LAbin_ADDI_D, + LOONGARCH64RI_I(addToSp, 12, True), + hregSP(), hregSP())); + break; + } + default: + /*NOTREACHED*/ + vassert(0); + break; + } +} + +static void iselStmtLLSC ( ISelEnv* env, IRStmt* stmt ) +{ + IRTemp res = stmt->Ist.LLSC.result; + IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.addr); + + /* Temporary solution; this need to be rewritten again for LOONGARCH64. + On LOONGARCH64 you can not read from address that is locked with LL + before SC. If you read from address that is locked than SC will fall. + */ + if (stmt->Ist.LLSC.storedata == NULL) { + /* LL */ + IRType ty = typeOfIRTemp(env->type_env, res); + LOONGARCH64LLSCOp op; + switch (ty) { + case Ity_I32: + op = LAllsc_LL_W; + break; + case Ity_I64: + op = LAllsc_LL_D; + break; + default: + vpanic("iselStmt(loongarch64): Ist_LLSC"); + break; + } + LOONGARCH64AMode* addr = iselIntExpr_AMode(env, stmt->Ist.LLSC.addr, tya); + HReg val = lookupIRTemp(env, res); + addInstr(env, LOONGARCH64Instr_LLSC(op, True, addr, val)); + } else { + /* SC */ + IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.storedata); + LOONGARCH64LLSCOp op; + switch (tyd) { + case Ity_I32: + op = LAllsc_SC_W; + break; + case Ity_I64: + op = LAllsc_SC_D; + break; + default: + vpanic("iselStmt(loongarch64): Ist_LLSC"); + break; + } + LOONGARCH64AMode* addr = iselIntExpr_AMode(env, stmt->Ist.LLSC.addr, tya); + HReg val = iselIntExpr_R(env, stmt->Ist.LLSC.storedata); + HReg dst = lookupIRTemp(env, res); + HReg tmp = newVRegI(env); + addInstr(env, LOONGARCH64Instr_Move(tmp, val)); + addInstr(env, LOONGARCH64Instr_LLSC(op, False, addr, tmp)); + addInstr(env, LOONGARCH64Instr_Move(dst, tmp)); + } +} + +static void iselStmtCas ( ISelEnv* env, IRStmt* stmt ) +{ + IRCAS* cas = stmt->Ist.CAS.details; + if (cas->oldHi == IRTemp_INVALID && cas->end == Iend_LE) { + /* "normal" singleton CAS */ + HReg old = lookupIRTemp(env, cas->oldLo); + HReg addr = iselIntExpr_R(env, cas->addr); + HReg expd = iselIntExpr_R(env, cas->expdLo); + HReg data = iselIntExpr_R(env, cas->dataLo); + IRType ty = typeOfIRTemp(env->type_env, cas->oldLo); + Bool size64; + switch (ty) { + case Ity_I32: + size64 = False; + break; + case Ity_I64: + size64 = True; + break; + default: + vpanic("iselStmt(loongarch64): Ist_CAS"); + break; + } + addInstr(env, LOONGARCH64Instr_Cas(old, addr, expd, data, size64)); + } else { + vpanic("iselStmt(loongarch64): Ist_CAS"); + } +} + +static void iselStmtMBE ( ISelEnv* env, IRStmt* stmt ) +{ + switch (stmt->Ist.MBE.event) { + case Imbe_Fence: + case Imbe_CancelReservation: + addInstr(env, LOONGARCH64Instr_Bar(LAbar_DBAR, 0)); + break; + case Imbe_InsnFence: + addInstr(env, LOONGARCH64Instr_Bar(LAbar_IBAR, 0)); + break; + default: + vpanic("iselStmt(loongarch64): Ist_MBE"); + break; + } +} + +static void iselStmtExit ( ISelEnv* env, IRStmt* stmt ) +{ + if (stmt->Ist.Exit.dst->tag != Ico_U64) + vpanic("iselStmt(loongarch64): Ist_Exit: dst is not a 64-bit value"); + + HReg cond = iselCondCode_R(env, stmt->Ist.Exit.guard); + LOONGARCH64AMode* am = mkLOONGARCH64AMode_RI(hregGSP(), stmt->Ist.Exit.offsIP); + + /* Case: boring transfer to known address */ + if (stmt->Ist.Exit.jk == Ijk_Boring || stmt->Ist.Exit.jk == Ijk_Call) { + if (env->chainingAllowed) { + /* .. almost always true .. */ + /* Skip the event check at the dst if this is a forwards edge. */ + Bool toFastEP = ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > env->max_ga; + addInstr(env, LOONGARCH64Instr_XDirect(stmt->Ist.Exit.dst->Ico.U64, + am, cond, toFastEP)); + } else { + /* .. very occasionally .. */ + /* We can't use chaining, so ask for an assisted transfer, + as that's the only alternative that is allowable. */ + HReg dst = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); + addInstr(env, LOONGARCH64Instr_XAssisted(dst, am, cond, Ijk_Boring)); + } + return; + } + + /* Case: assisted transfer to arbitrary address */ + switch (stmt->Ist.Exit.jk) { + /* Keep this list in sync with that for iselNext below */ + case Ijk_ClientReq: + case Ijk_Yield: + case Ijk_NoDecode: + case Ijk_InvalICache: + case Ijk_NoRedir: + case Ijk_SigILL: + case Ijk_SigTRAP: + case Ijk_SigSEGV: + case Ijk_SigBUS: + case Ijk_SigFPE_IntDiv: + case Ijk_SigFPE_IntOvf: + case Ijk_SigSYS: + case Ijk_Sys_syscall: { + HReg dst = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); + addInstr(env, LOONGARCH64Instr_XAssisted(dst, am, cond, stmt->Ist.Exit.jk)); + break; + } + default: + /* Do we ever expect to see any other kind? */ + ppIRJumpKind(stmt->Ist.Exit.jk); + vpanic("iselStmt(loongarch64): Ist_Exit: unexpected jump kind"); + break; + } +} + +static void iselStmt(ISelEnv* env, IRStmt* stmt) +{ + if (vex_traceflags & VEX_TRACE_VCODE) { + vex_printf("\n-- "); + ppIRStmt(stmt); + vex_printf("\n"); + } + + switch (stmt->tag) { + /* --------- STORE --------- */ + /* little-endian write to memory */ + case Ist_Store: + iselStmtStore(env, stmt); + break; + + /* --------- PUT --------- */ + /* write guest state, fixed offset */ + case Ist_Put: + iselStmtPut(env, stmt); + break; + + /* --------- TMP --------- */ + /* assign value to temporary */ + case Ist_WrTmp: + iselStmtTmp(env, stmt); + break; + + /* --------- Call to DIRTY helper --------- */ + /* call complex ("dirty") helper function */ + case Ist_Dirty: + iselStmtDirty(env, stmt); + break; + + /* --------- Load Linked and Store Conditional --------- */ + case Ist_LLSC: + iselStmtLLSC(env, stmt); + break; + + /* --------- CAS --------- */ + case Ist_CAS: + iselStmtCas(env, stmt); + break; + + /* --------- MEM FENCE --------- */ + case Ist_MBE: + iselStmtMBE(env, stmt); + break; + + /* --------- INSTR MARK --------- */ + /* Doesn't generate any executable code ... */ + case Ist_IMark: + break; + + /* --------- ABI HINT --------- */ + /* These have no meaning (denotation in the IR) and so we ignore + them ... if any actually made it this far. */ + case Ist_AbiHint: + break; + + /* --------- NO-OP --------- */ + case Ist_NoOp: + break; + + /* --------- EXIT --------- */ + case Ist_Exit: + iselStmtExit(env, stmt); + break; + + default: + ppIRStmt(stmt); + vpanic("iselStmt(loongarch64)"); + break; + } +} + + +/*---------------------------------------------------------*/ +/*--- ISEL: Basic block terminators (Nexts) ---*/ +/*---------------------------------------------------------*/ + +static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk, Int offsIP ) +{ + if (vex_traceflags & VEX_TRACE_VCODE) { + vex_printf("\n-- PUT(%d) = ", offsIP); + ppIRExpr(next); + vex_printf("; exit-"); + ppIRJumpKind(jk); + vex_printf("\n"); + } + + /* Case: boring transfer to known address */ + if (next->tag == Iex_Const) { + IRConst* cdst = next->Iex.Const.con; + vassert(cdst->tag == Ico_U64); + if (jk == Ijk_Boring || jk == Ijk_Call) { + /* Boring transfer to known address */ + LOONGARCH64AMode* am = mkLOONGARCH64AMode_RI(hregGSP(), offsIP); + if (env->chainingAllowed) { + /* .. almost always true .. */ + /* Skip the event check at the dst if this is a forwards edge. */ + Bool toFastEP = ((Addr64)cdst->Ico.U64) > env->max_ga; + addInstr(env, LOONGARCH64Instr_XDirect(cdst->Ico.U64, am, + INVALID_HREG, toFastEP)); + } else { + /* .. very occasionally .. */ + /* We can't use chaining, so ask for an assisted transfer, + as that's the only alternative that is allowable. */ + HReg dst = iselIntExpr_R(env, next); + addInstr(env, LOONGARCH64Instr_XAssisted(dst, am, INVALID_HREG, Ijk_Boring)); + } + return; + } + } + + /* Case: call/return (==boring) transfer to any address */ + switch (jk) { + case Ijk_Boring: + case Ijk_Ret: + case Ijk_Call: { + HReg dst = iselIntExpr_R(env, next); + LOONGARCH64AMode* am = mkLOONGARCH64AMode_RI(hregGSP(), offsIP); + if (env->chainingAllowed) { + addInstr(env, LOONGARCH64Instr_XIndir(dst, am, INVALID_HREG)); + } else { + addInstr(env, LOONGARCH64Instr_XAssisted(dst, am, + INVALID_HREG, Ijk_Boring)); + } + return; + } + default: + break; + } + + /* Case: assisted transfer to arbitrary address */ + switch (jk) { + /* Keep this list in sync with that for Ist_Exit above */ + case Ijk_ClientReq: + case Ijk_Yield: + case Ijk_NoDecode: + case Ijk_InvalICache: + case Ijk_NoRedir: + case Ijk_SigILL: + case Ijk_SigTRAP: + case Ijk_SigSEGV: + case Ijk_SigBUS: + case Ijk_SigFPE_IntDiv: + case Ijk_SigFPE_IntOvf: + case Ijk_SigSYS: + case Ijk_Sys_syscall: { + HReg dst = iselIntExpr_R(env, next); + LOONGARCH64AMode* am = mkLOONGARCH64AMode_RI(hregGSP(), offsIP); + addInstr(env, LOONGARCH64Instr_XAssisted(dst, am, INVALID_HREG, jk)); + return; + } + default: + break; + } + + vex_printf("\n-- PUT(%d) = ", offsIP); + ppIRExpr(next); + vex_printf("; exit-"); + ppIRJumpKind(jk); + vex_printf("\n"); + vassert(0); // are we expecting any other kind? +} + + +/*---------------------------------------------------------*/ +/*--- Insn selector top-level ---*/ +/*---------------------------------------------------------*/ + +/* Translate an entire BB to LOONGARCH64 code. */ +HInstrArray* iselSB_LOONGARCH64 ( const IRSB* bb, + VexArch arch_host, + const VexArchInfo* archinfo_host, + const VexAbiInfo* vbi, + Int offs_Host_EvC_Counter, + Int offs_Host_EvC_FailAddr, + Bool chainingAllowed, + Bool addProfInc, + Addr max_ga ) +{ + Int i, j; + HReg hreg, hregHI; + ISelEnv* env; + UInt hwcaps_host = archinfo_host->hwcaps; + LOONGARCH64AMode *amCounter, *amFailAddr; + + /* sanity ... */ + vassert(arch_host == VexArchLOONGARCH64); + vassert((hwcaps_host & ~(VEX_HWCAPS_LOONGARCH_CPUCFG + | VEX_HWCAPS_LOONGARCH_LAM + | VEX_HWCAPS_LOONGARCH_UAL + | VEX_HWCAPS_LOONGARCH_FP + | VEX_HWCAPS_LOONGARCH_LSX + | VEX_HWCAPS_LOONGARCH_LASX + | VEX_HWCAPS_LOONGARCH_COMPLEX + | VEX_HWCAPS_LOONGARCH_CRYPTO + | VEX_HWCAPS_LOONGARCH_LVZP + | VEX_HWCAPS_LOONGARCH_X86BT + | VEX_HWCAPS_LOONGARCH_ARMBT + | VEX_HWCAPS_LOONGARCH_MIPSBT + | VEX_HWCAPS_LOONGARCH_ISA_32BIT + | VEX_HWCAPS_LOONGARCH_ISA_64BIT)) == 0); + + /* Check that the host's endianness is as expected. */ + vassert(archinfo_host->endness == VexEndnessLE); + + /* Make up an initial environment to use. */ + env = LibVEX_Alloc_inline(sizeof(ISelEnv)); + env->vreg_ctr = 0; + + /* Set up output code array. */ + env->code = newHInstrArray(); + + /* Copy BB's type env. */ + env->type_env = bb->tyenv; + + /* Make up an IRTemp -> virtual HReg mapping. This doesn't + change as we go along. */ + env->n_vregmap = bb->tyenv->types_used; + env->vregmap = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg)); + env->vregmapHI = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg)); + + /* and finally ... */ + env->chainingAllowed = chainingAllowed; + env->hwcaps = hwcaps_host; + env->max_ga = max_ga; + + /* For each IR temporary, allocate a suitably-kinded virtual register. */ + j = 0; + for (i = 0; i < env->n_vregmap; i++) { + hregHI = hreg = INVALID_HREG; + switch (bb->tyenv->types[i]) { + case Ity_I1: + case Ity_I8: + case Ity_I16: + case Ity_I32: + case Ity_I64: + hreg = mkHReg(True, HRcInt64, 0, j++); + break; + case Ity_I128: + hreg = mkHReg(True, HRcInt64, 0, j++); + hregHI = mkHReg(True, HRcInt64, 0, j++); + break; + case Ity_F16: // we'll use HRcFlt64 regs for F16 too + case Ity_F32: // we'll use HRcFlt64 regs for F32 too + case Ity_F64: + hreg = mkHReg(True, HRcFlt64, 0, j++); + break; + case Ity_V128: + hreg = mkHReg(True, HRcVec128, 0, j++); + break; + case Ity_V256: + hreg = mkHReg(True, HRcVec128, 0, j++); + hregHI = mkHReg(True, HRcVec128, 0, j++); + break; + default: + ppIRType(bb->tyenv->types[i]); + vpanic("iselBB(loongarch64): IRTemp type"); + break; + } + env->vregmap[i] = hreg; + env->vregmapHI[i] = hregHI; + } + env->vreg_ctr = j; + + /* The very first instruction must be an event check. */ + amCounter = mkLOONGARCH64AMode_RI(hregGSP(), offs_Host_EvC_Counter); + amFailAddr = mkLOONGARCH64AMode_RI(hregGSP(), offs_Host_EvC_FailAddr); + addInstr(env, LOONGARCH64Instr_EvCheck(amCounter, amFailAddr)); + + /* Possibly a block counter increment (for profiling). At this + point we don't know the address of the counter, so just pretend + it is zero. It will have to be patched later, but before this + translation is used, by a call to LibVEX_patchProfCtr. */ + if (addProfInc) { + addInstr(env, LOONGARCH64Instr_ProfInc()); + } + + /* Ok, finally we can iterate over the statements. */ + for (i = 0; i < bb->stmts_used; i++) + iselStmt(env, bb->stmts[i]); + + iselNext(env, bb->next, bb->jumpkind, bb->offsIP); + + /* record the number of vregs we used. */ + env->code->n_vregs = env->vreg_ctr; + return env->code; +} + + +/*---------------------------------------------------------------*/ +/*--- end host_loongarch64_isel.c ---*/ +/*---------------------------------------------------------------*/ diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c index 31710eb..d6b245f 100644 --- a/VEX/priv/ir_defs.c +++ b/VEX/priv/ir_defs.c @@ -280,6 +280,8 @@ void ppIROp ( IROp op ) case Iop_SubF64: vex_printf("SubF64"); return; case Iop_MulF64: vex_printf("MulF64"); return; case Iop_DivF64: vex_printf("DivF64"); return; + case Iop_ScaleBF64: vex_printf("ScaleBF64"); return; + case Iop_ScaleBF32: vex_printf("ScaleBF32"); return; case Iop_AddF64r32: vex_printf("AddF64r32"); return; case Iop_SubF64r32: vex_printf("SubF64r32"); return; case Iop_MulF64r32: vex_printf("MulF64r32"); return; @@ -356,6 +358,10 @@ void ppIROp ( IROp op ) case Iop_SqrtF64: vex_printf("SqrtF64"); return; case Iop_SqrtF32: vex_printf("SqrtF32"); return; case Iop_SqrtF16: vex_printf("SqrtF16"); return; + case Iop_RSqrtF32: vex_printf("RSqrtF32"); return; + case Iop_RSqrtF64: vex_printf("RSqrtF64"); return; + case Iop_LogBF32: vex_printf("LogBF32"); return; + case Iop_LogBF64: vex_printf("LogBF64"); return; case Iop_SinF64: vex_printf("SinF64"); return; case Iop_CosF64: vex_printf("CosF64"); return; case Iop_TanF64: vex_printf("TanF64"); return; @@ -379,8 +385,12 @@ void ppIROp ( IROp op ) case Iop_MaxNumF64: vex_printf("MaxNumF64"); return; case Iop_MinNumF64: vex_printf("MinNumF64"); return; + case Iop_MaxNumAbsF64: vex_printf("MaxNumAbsF64"); return; + case Iop_MinNumAbsF64: vex_printf("MinNumAbsF64"); return; case Iop_MaxNumF32: vex_printf("MaxNumF32"); return; case Iop_MinNumF32: vex_printf("MinNumF32"); return; + case Iop_MaxNumAbsF32: vex_printf("MaxNumAbsF32"); return; + case Iop_MinNumAbsF32: vex_printf("MinNumAbsF32"); return; case Iop_F16toF64: vex_printf("F16toF64"); return; case Iop_F64toF16: vex_printf("F64toF16"); return; @@ -1307,16 +1317,20 @@ void ppIROp ( IROp op ) case Iop_Max8Sx32: vex_printf("Max8Sx32"); return; case Iop_Max16Sx16: vex_printf("Max16Sx16"); return; case Iop_Max32Sx8: vex_printf("Max32Sx8"); return; + case Iop_Max64Sx4: vex_printf("Max64Sx4"); return; case Iop_Max8Ux32: vex_printf("Max8Ux32"); return; case Iop_Max16Ux16: vex_printf("Max16Ux16"); return; case Iop_Max32Ux8: vex_printf("Max32Ux8"); return; + case Iop_Max64Ux4: vex_printf("Max64Ux4"); return; case Iop_Min8Sx32: vex_printf("Min8Sx32"); return; case Iop_Min16Sx16: vex_printf("Min16Sx16"); return; case Iop_Min32Sx8: vex_printf("Min32Sx8"); return; + case Iop_Min64Sx4: vex_printf("Min64Sx4"); return; case Iop_Min8Ux32: vex_printf("Min8Ux32"); return; case Iop_Min16Ux16: vex_printf("Min16Ux16"); return; case Iop_Min32Ux8: vex_printf("Min32Ux8"); return; + case Iop_Min64Ux4: vex_printf("Min64Ux4"); return; case Iop_CmpEQ8x32: vex_printf("CmpEQ8x32"); return; case Iop_CmpEQ16x16: vex_printf("CmpEQ16x16"); return; @@ -1434,10 +1448,13 @@ Bool primopMightTrap ( IROp op ) case Iop_1Uto8: case Iop_1Uto32: case Iop_1Uto64: case Iop_1Sto8: case Iop_1Sto16: case Iop_1Sto32: case Iop_1Sto64: case Iop_AddF64: case Iop_SubF64: case Iop_MulF64: case Iop_DivF64: + case Iop_ScaleBF64: case Iop_ScaleBF32: case Iop_AddF32: case Iop_SubF32: case Iop_MulF32: case Iop_DivF32: case Iop_AddF64r32: case Iop_SubF64r32: case Iop_MulF64r32: case Iop_DivF64r32: case Iop_NegF64: case Iop_AbsF64: case Iop_NegF32: case Iop_AbsF32: case Iop_SqrtF64: case Iop_SqrtF32: + case Iop_RSqrtF64: case Iop_RSqrtF32: + case Iop_LogBF64: case Iop_LogBF32: case Iop_NegF16: case Iop_AbsF16: case Iop_SqrtF16: case Iop_SubF16: case Iop_AddF16: case Iop_CmpF64: case Iop_CmpF32: case Iop_CmpF16: case Iop_CmpF128: @@ -1477,8 +1494,11 @@ Bool primopMightTrap ( IROp op ) case Iop_RSqrtEst5GoodF64: case Iop_RoundF64toF64_NEAREST: case Iop_RoundF64toF64_NegINF: case Iop_RoundF64toF64_PosINF: case Iop_RoundF64toF64_ZERO: case Iop_TruncF64asF32: case Iop_RoundF64toF32: - case Iop_RecpExpF64: case Iop_RecpExpF32: case Iop_MaxNumF64: - case Iop_MinNumF64: case Iop_MaxNumF32: case Iop_MinNumF32: + case Iop_RecpExpF64: case Iop_RecpExpF32: + case Iop_MaxNumF64: case Iop_MinNumF64: + case Iop_MaxNumAbsF64: case Iop_MinNumAbsF64: + case Iop_MaxNumF32: case Iop_MinNumF32: + case Iop_MaxNumAbsF32: case Iop_MinNumAbsF32: case Iop_F16toF64: case Iop_F64toF16: case Iop_F16toF32: case Iop_F32toF16: case Iop_QAdd32S: case Iop_QSub32S: case Iop_Add16x2: case Iop_Sub16x2: @@ -1786,10 +1806,10 @@ Bool primopMightTrap ( IROp op ) case Iop_ShlN16x16: case Iop_ShlN32x8: case Iop_ShlN64x4: case Iop_ShrN16x16: case Iop_ShrN32x8: case Iop_ShrN64x4: case Iop_SarN16x16: case Iop_SarN32x8: - case Iop_Max8Sx32: case Iop_Max16Sx16: case Iop_Max32Sx8: - case Iop_Max8Ux32: case Iop_Max16Ux16: case Iop_Max32Ux8: - case Iop_Min8Sx32: case Iop_Min16Sx16: case Iop_Min32Sx8: - case Iop_Min8Ux32: case Iop_Min16Ux16: case Iop_Min32Ux8: + case Iop_Max8Sx32: case Iop_Max16Sx16: case Iop_Max32Sx8: case Iop_Max64Sx4: + case Iop_Max8Ux32: case Iop_Max16Ux16: case Iop_Max32Ux8: case Iop_Max64Ux4: + case Iop_Min8Sx32: case Iop_Min16Sx16: case Iop_Min32Sx8: case Iop_Min64Sx4: + case Iop_Min8Ux32: case Iop_Min16Ux16: case Iop_Min32Ux8: case Iop_Min64Ux4: case Iop_Mul16x16: case Iop_Mul32x8: case Iop_MulHi16Ux16: case Iop_MulHi16Sx16: case Iop_QAdd8Ux32: case Iop_QAdd16Ux16: @@ -2075,6 +2095,7 @@ void ppIRJumpKind ( IRJumpKind kind ) case Ijk_SigFPE: vex_printf("SigFPE"); break; case Ijk_SigFPE_IntDiv: vex_printf("SigFPE_IntDiv"); break; case Ijk_SigFPE_IntOvf: vex_printf("SigFPE_IntOvf"); break; + case Ijk_SigSYS: vex_printf("SigSYS"); break; case Ijk_Sys_syscall: vex_printf("Sys_syscall"); break; case Ijk_Sys_int32: vex_printf("Sys_int32"); break; case Ijk_Sys_int128: vex_printf("Sys_int128"); break; @@ -2094,6 +2115,8 @@ void ppIRMBusEvent ( IRMBusEvent event ) vex_printf("Fence"); break; case Imbe_CancelReservation: vex_printf("CancelReservation"); break; + case Imbe_InsnFence: + vex_printf("InsnFence"); break; default: vpanic("ppIRMBusEvent"); } @@ -3372,12 +3395,14 @@ void typeOfPrimop ( IROp op, case Iop_AddF64: case Iop_SubF64: case Iop_MulF64: case Iop_DivF64: + case Iop_ScaleBF64: case Iop_AddF64r32: case Iop_SubF64r32: case Iop_MulF64r32: case Iop_DivF64r32: TERNARY(ity_RMode,Ity_F64,Ity_F64, Ity_F64); case Iop_AddF32: case Iop_SubF32: case Iop_MulF32: case Iop_DivF32: + case Iop_ScaleBF32: TERNARY(ity_RMode,Ity_F32,Ity_F32, Ity_F32); case Iop_AddF16: @@ -3394,10 +3419,14 @@ void typeOfPrimop ( IROp op, UNARY(Ity_F16, Ity_F16); case Iop_SqrtF64: + case Iop_RSqrtF64: + case Iop_LogBF64: case Iop_RecpExpF64: BINARY(ity_RMode,Ity_F64, Ity_F64); case Iop_SqrtF32: + case Iop_RSqrtF32: + case Iop_LogBF32: case Iop_RoundF32toInt: case Iop_RecpExpF32: BINARY(ity_RMode,Ity_F32, Ity_F32); @@ -3406,9 +3435,11 @@ void typeOfPrimop ( IROp op, BINARY(ity_RMode, Ity_F16, Ity_F16); case Iop_MaxNumF64: case Iop_MinNumF64: + case Iop_MaxNumAbsF64: case Iop_MinNumAbsF64: BINARY(Ity_F64,Ity_F64, Ity_F64); case Iop_MaxNumF32: case Iop_MinNumF32: + case Iop_MaxNumAbsF32: case Iop_MinNumAbsF32: BINARY(Ity_F32,Ity_F32, Ity_F32); case Iop_CmpF16: @@ -4098,10 +4129,10 @@ void typeOfPrimop ( IROp op, case Iop_Mul16x16: case Iop_Mul32x8: case Iop_MulHi16Ux16: case Iop_MulHi16Sx16: case Iop_Avg8Ux32: case Iop_Avg16Ux16: - case Iop_Max8Sx32: case Iop_Max16Sx16: case Iop_Max32Sx8: - case Iop_Max8Ux32: case Iop_Max16Ux16: case Iop_Max32Ux8: - case Iop_Min8Sx32: case Iop_Min16Sx16: case Iop_Min32Sx8: - case Iop_Min8Ux32: case Iop_Min16Ux16: case Iop_Min32Ux8: + case Iop_Max8Sx32: case Iop_Max16Sx16: case Iop_Max32Sx8: case Iop_Max64Sx4: + case Iop_Max8Ux32: case Iop_Max16Ux16: case Iop_Max32Ux8: case Iop_Max64Ux4: + case Iop_Min8Sx32: case Iop_Min16Sx16: case Iop_Min32Sx8: case Iop_Min64Sx4: + case Iop_Min8Ux32: case Iop_Min16Ux16: case Iop_Min32Ux8: case Iop_Min64Ux4: case Iop_CmpEQ8x32: case Iop_CmpEQ16x16: case Iop_CmpEQ32x8: case Iop_CmpEQ64x4: case Iop_CmpGT8Sx32: case Iop_CmpGT16Sx16: @@ -5245,7 +5276,9 @@ void tcStmt ( const IRSB* bb, const IRStmt* stmt, IRType gWordTy ) break; case Ist_MBE: switch (stmt->Ist.MBE.event) { - case Imbe_Fence: case Imbe_CancelReservation: + case Imbe_Fence: + case Imbe_CancelReservation: + case Imbe_InsnFence: break; default: sanityCheckFail(bb,stmt,"IRStmt.MBE.event: unknown"); break; diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index 482047c..98d4a81 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -43,6 +43,7 @@ #include "libvex_guest_s390x.h" #include "libvex_guest_mips32.h" #include "libvex_guest_mips64.h" +#include "libvex_guest_loongarch64.h" #include "main_globals.h" #include "main_util.h" @@ -57,6 +58,7 @@ #include "host_s390_defs.h" #include "host_mips_defs.h" #include "host_nanomips_defs.h" +#include "host_loongarch64_defs.h" #include "guest_generic_bb_to_IR.h" #include "guest_x86_defs.h" @@ -67,6 +69,7 @@ #include "guest_s390_defs.h" #include "guest_mips_defs.h" #include "guest_nanomips_defs.h" +#include "guest_loongarch64_defs.h" #include "host_generic_simd128.h" @@ -163,6 +166,14 @@ #define NANOMIPSST(f) vassert(0) #endif +#if defined(VGA_loongarch64) || defined(VEXMULTIARCH) +#define LOONGARCH64FN(f) f +#define LOONGARCH64ST(f) f +#else +#define LOONGARCH64FN(f) NULL +#define LOONGARCH64ST(f) vassert(0) +#endif + /* This file contains the top level interface to the library. */ /* --------- fwds ... --------- */ @@ -541,6 +552,23 @@ IRSB* LibVEX_FrontEnd ( /*MOD*/ VexTranslateArgs* vta, vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4); break; + case VexArchLOONGARCH64: + preciseMemExnsFn + = LOONGARCH64FN(guest_loongarch64_state_requires_precise_mem_exns); + disInstrFn = LOONGARCH64FN(disInstr_LOONGARCH64); + specHelper = LOONGARCH64FN(guest_loongarch64_spechelper); + guest_layout = LOONGARCH64FN(&loongarch64Guest_layout); + offB_CMSTART = offsetof(VexGuestLOONGARCH64State, guest_CMSTART); + offB_CMLEN = offsetof(VexGuestLOONGARCH64State, guest_CMLEN); + offB_GUEST_IP = offsetof(VexGuestLOONGARCH64State, guest_PC); + szB_GUEST_IP = sizeof( ((VexGuestLOONGARCH64State*)0)->guest_PC ); + vassert(vta->archinfo_guest.endness == VexEndnessLE); + vassert(sizeof(VexGuestLOONGARCH64State) % LibVEX_GUEST_STATE_ALIGN == 0); + vassert(sizeof( ((VexGuestLOONGARCH64State*)0)->guest_CMSTART) == 8); + vassert(sizeof( ((VexGuestLOONGARCH64State*)0)->guest_CMLEN ) == 8); + vassert(sizeof( ((VexGuestLOONGARCH64State*)0)->guest_NRADDR ) == 8); + break; + default: vpanic("LibVEX_Translate: unsupported guest insn set"); } @@ -878,6 +906,14 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR); break; + case VexArchLOONGARCH64: + preciseMemExnsFn + = LOONGARCH64FN(guest_loongarch64_state_requires_precise_mem_exns); + guest_sizeB = sizeof(VexGuestLOONGARCH64State); + offB_HOST_EvC_COUNTER = offsetof(VexGuestLOONGARCH64State, host_EvC_COUNTER); + offB_HOST_EvC_FAILADDR = offsetof(VexGuestLOONGARCH64State, host_EvC_FAILADDR); + break; + default: vpanic("LibVEX_Codegen: unsupported guest insn set"); } @@ -1052,6 +1088,23 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, || vta->archinfo_host.endness == VexEndnessBE); break; + case VexArchLOONGARCH64: + mode64 = True; + rRegUniv = LOONGARCH64FN(getRRegUniverse_LOONGARCH64()); + getRegUsage + = CAST_TO_TYPEOF(getRegUsage) LOONGARCH64FN(getRegUsage_LOONGARCH64Instr); + mapRegs = CAST_TO_TYPEOF(mapRegs) LOONGARCH64FN(mapRegs_LOONGARCH64Instr); + genSpill = CAST_TO_TYPEOF(genSpill) LOONGARCH64FN(genSpill_LOONGARCH64); + genReload = CAST_TO_TYPEOF(genReload) LOONGARCH64FN(genReload_LOONGARCH64); + genMove = CAST_TO_TYPEOF(genMove) LOONGARCH64FN(genMove_LOONGARCH64); + ppInstr = CAST_TO_TYPEOF(ppInstr) LOONGARCH64FN(ppLOONGARCH64Instr); + ppReg = CAST_TO_TYPEOF(ppReg) LOONGARCH64FN(ppHRegLOONGARCH64); + iselSB = LOONGARCH64FN(iselSB_LOONGARCH64); + emit = CAST_TO_TYPEOF(emit) LOONGARCH64FN(emit_LOONGARCH64Instr); + vassert(vta->archinfo_host.endness == VexEndnessLE + || vta->archinfo_host.endness == VexEndnessBE); + break; + default: vpanic("LibVEX_Translate: unsupported host insn set"); } @@ -1297,6 +1350,11 @@ VexInvalRange LibVEX_Chain ( VexArch arch_host, place_to_chain, disp_cp_chain_me_EXPECTED, place_to_jump_to)); + case VexArchLOONGARCH64: + LOONGARCH64ST(return chainXDirect_LOONGARCH64(endness_host, + place_to_chain, + disp_cp_chain_me_EXPECTED, + place_to_jump_to)); default: vassert(0); } @@ -1359,6 +1417,11 @@ VexInvalRange LibVEX_UnChain ( VexArch arch_host, place_to_unchain, place_to_jump_to_EXPECTED, disp_cp_chain_me)); + case VexArchLOONGARCH64: + LOONGARCH64ST(return unchainXDirect_LOONGARCH64(endness_host, + place_to_unchain, + place_to_jump_to_EXPECTED, + disp_cp_chain_me)); default: vassert(0); } @@ -1389,6 +1452,8 @@ Int LibVEX_evCheckSzB ( VexArch arch_host ) MIPS64ST(cached = evCheckSzB_MIPS()); break; case VexArchNANOMIPS: NANOMIPSST(cached = evCheckSzB_NANOMIPS()); break; + case VexArchLOONGARCH64: + LOONGARCH64ST(cached = evCheckSzB_LOONGARCH64()); break; default: vassert(0); } @@ -1432,6 +1497,10 @@ VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, case VexArchNANOMIPS: NANOMIPSST(return patchProfInc_NANOMIPS(endness_host, place_to_patch, location_of_counter)); + case VexArchLOONGARCH64: + LOONGARCH64ST(return patchProfInc_LOONGARCH64(endness_host, + place_to_patch, + location_of_counter)); default: vassert(0); } @@ -1515,6 +1584,7 @@ const HChar* LibVEX_ppVexArch ( VexArch arch ) case VexArchMIPS32: return "MIPS32"; case VexArchMIPS64: return "MIPS64"; case VexArchNANOMIPS: return "NANOMIPS"; + case VexArchLOONGARCH64: return "LOONGARCH64"; default: return "VexArch???"; } } @@ -1585,6 +1655,7 @@ static IRType arch_word_size (VexArch arch) { case VexArchMIPS64: case VexArchPPC64: case VexArchS390X: + case VexArchLOONGARCH64: return Ity_I64; default: @@ -1925,6 +1996,38 @@ static const HChar* show_hwcaps_mips64 ( UInt hwcaps ) return "Unsupported baseline"; } +static const HChar* show_hwcaps_loongarch64 ( UInt hwcaps ) +{ + static const HChar prefix[] = "loongarch64"; + static const struct { + UInt hwcaps_bit; + HChar name[16]; + } hwcaps_list[] = { + { VEX_HWCAPS_LOONGARCH_CPUCFG, "cpucfg" }, + { VEX_HWCAPS_LOONGARCH_LAM, "lam" }, + { VEX_HWCAPS_LOONGARCH_UAL, "ual" }, + { VEX_HWCAPS_LOONGARCH_FP, "fpu" }, + { VEX_HWCAPS_LOONGARCH_LSX, "lsx" }, + { VEX_HWCAPS_LOONGARCH_LASX, "lasx" }, + { VEX_HWCAPS_LOONGARCH_COMPLEX, "complex" }, + { VEX_HWCAPS_LOONGARCH_CRYPTO, "crypto" }, + { VEX_HWCAPS_LOONGARCH_LVZP, "lvz" }, + { VEX_HWCAPS_LOONGARCH_X86BT, "lbt_x86" }, + { VEX_HWCAPS_LOONGARCH_ARMBT, "lbt_arm" }, + { VEX_HWCAPS_LOONGARCH_MIPSBT, "lbt_mips" } + }; + static HChar buf[sizeof(prefix) + + NUM_HWCAPS * (sizeof hwcaps_list[0].name + 1) + 1]; // '\0' + + HChar *p = buf + vex_sprintf(buf, "%s", prefix); + UInt i; + for (i = 0 ; i < NUM_HWCAPS; ++i) { + if (hwcaps & hwcaps_list[i].hwcaps_bit) + p = p + vex_sprintf(p, "-%s", hwcaps_list[i].name); + } + return buf; +} + #undef NUM_HWCAPS /* Thie function must not return NULL. */ @@ -1941,6 +2044,7 @@ static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps ) case VexArchS390X: return show_hwcaps_s390x(hwcaps); case VexArchMIPS32: return show_hwcaps_mips32(hwcaps); case VexArchMIPS64: return show_hwcaps_mips64(hwcaps); + case VexArchLOONGARCH64: return show_hwcaps_loongarch64(hwcaps); default: return NULL; } } @@ -2203,6 +2307,11 @@ static void check_hwcaps ( VexArch arch, UInt hwcaps ) return; invalid_hwcaps(arch, hwcaps, "Unsupported baseline\n"); + case VexArchLOONGARCH64: + if (!(hwcaps & VEX_HWCAPS_LOONGARCH_ISA_64BIT)) + invalid_hwcaps(arch, hwcaps, "Unsupported baseline\n"); + return; + default: vpanic("unknown architecture"); } diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index 27bb6e0..5ed24bd 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -60,6 +60,7 @@ typedef VexArchMIPS32, VexArchMIPS64, VexArchNANOMIPS, + VexArchLOONGARCH64, } VexArch; @@ -300,6 +301,22 @@ typedef (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_P5600) && \ (VEX_MIPS_HOST_FP_MODE(x))) +/* LoongArch baseline capability */ +#define VEX_HWCAPS_LOONGARCH_CPUCFG (1 << 0) /* CPU has CPUCFG */ +#define VEX_HWCAPS_LOONGARCH_LAM (1 << 1) /* CPU has Atomic instructions */ +#define VEX_HWCAPS_LOONGARCH_UAL (1 << 2) /* CPU has Unaligned Access support */ +#define VEX_HWCAPS_LOONGARCH_FP (1 << 3) /* CPU has FPU */ +#define VEX_HWCAPS_LOONGARCH_LSX (1 << 4) /* CPU has 128-bit SIMD instructions */ +#define VEX_HWCAPS_LOONGARCH_LASX (1 << 5) /* CPU has 256-bit SIMD instructions */ +#define VEX_HWCAPS_LOONGARCH_COMPLEX (1 << 6) /* CPU has Complex instructions */ +#define VEX_HWCAPS_LOONGARCH_CRYPTO (1 << 7) /* CPU has Crypto instructions */ +#define VEX_HWCAPS_LOONGARCH_LVZP (1 << 8) /* CPU has Virtualization extension */ +#define VEX_HWCAPS_LOONGARCH_X86BT (1 << 9) /* CPU has X86 Binary Translation */ +#define VEX_HWCAPS_LOONGARCH_ARMBT (1 << 10) /* CPU has ARM Binary Translation */ +#define VEX_HWCAPS_LOONGARCH_MIPSBT (1 << 11) /* CPU has MIPS Binary Translation */ +#define VEX_HWCAPS_LOONGARCH_ISA_32BIT (1 << 30) /* 32-bit ISA */ +#define VEX_HWCAPS_LOONGARCH_ISA_64BIT (1 << 31) /* 64-bit ISA */ + /* These return statically allocated strings. */ extern const HChar* LibVEX_ppVexArch ( VexArch ); @@ -420,6 +437,7 @@ void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ); guest is mips32 ==> applicable, default True guest is mips64 ==> applicable, default True guest is arm64 ==> applicable, default False + guest is loongarch64 ==> const True host_ppc_calls_use_fndescrs: host is ppc32-linux ==> False @@ -1026,6 +1044,10 @@ extern void LibVEX_InitIRI ( const IRICB * ); ~~~~~ r21 is GSP. + loongarch64 + ~~~~~ + r31 is GSP. + ALL GUEST ARCHITECTURES ~~~~~~~~~~~~~~~~~~~~~~~ The guest state must contain two pseudo-registers, guest_CMSTART diff --git a/VEX/pub/libvex_basictypes.h b/VEX/pub/libvex_basictypes.h index e3f1485..b4c81bf 100644 --- a/VEX/pub/libvex_basictypes.h +++ b/VEX/pub/libvex_basictypes.h @@ -198,6 +198,10 @@ typedef unsigned long HWord; # define VEX_HOST_WORDSIZE 4 # define VEX_REGPARM(_n) /* */ +#elif defined(__loongarch__) && (__loongarch_grlen == 64) +# define VEX_HOST_WORDSIZE 8 +# define VEX_REGPARM(_n) /* */ + #else # error "Vex: Fatal: Can't establish the host architecture" #endif diff --git a/VEX/pub/libvex_guest_loongarch64.h b/VEX/pub/libvex_guest_loongarch64.h new file mode 100644 index 0000000..fde111f --- /dev/null +++ b/VEX/pub/libvex_guest_loongarch64.h @@ -0,0 +1,172 @@ + +/*---------------------------------------------------------------*/ +/*--- begin libvex_guest_loongarch64.h ---*/ +/*---------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. + + Neither the names of the U.S. Department of Energy nor the + University of California nor the names of its contributors may be + used to endorse or promote products derived from this software + without prior written permission. +*/ + +#ifndef __LIBVEX_PUB_GUEST_LOONGARCH64_H +#define __LIBVEX_PUB_GUEST_LOONGARCH64_H + +#include "libvex_basictypes.h" + + +/*---------------------------------------------------------------*/ +/*--- Vex's representation of the LOONGARCH64 CPU state. ---*/ +/*---------------------------------------------------------------*/ + +typedef + struct { + /* Event check fail addr and counter. */ + /* 0 */ ULong host_EvC_FAILADDR; + /* 8 */ UInt host_EvC_COUNTER; + /* 12 */ UInt _padding0; + + /* CPU Registers */ + /* 16 */ ULong guest_R0; /* Constant zero */ + /* 24 */ ULong guest_R1; /* Return address */ + /* 32 */ ULong guest_R2; /* Thread pointer */ + /* 40 */ ULong guest_R3; /* Stack pointer */ + /* 48 */ ULong guest_R4; /* Argument registers / Return value */ + /* 56 */ ULong guest_R5; + /* 64 */ ULong guest_R6; /* Argument registers */ + /* 72 */ ULong guest_R7; + /* 80 */ ULong guest_R8; + /* 88 */ ULong guest_R9; + /* 96 */ ULong guest_R10; + /* 104 */ ULong guest_R11; + /* 112 */ ULong guest_R12; /* Temporary registers */ + /* 120 */ ULong guest_R13; + /* 128 */ ULong guest_R14; + /* 136 */ ULong guest_R15; + /* 144 */ ULong guest_R16; + /* 152 */ ULong guest_R17; + /* 160 */ ULong guest_R18; + /* 168 */ ULong guest_R19; + /* 176 */ ULong guest_R20; + /* 184 */ ULong guest_R21; /* Reserved */ + /* 192 */ ULong guest_R22; /* Frame pointer / Static register */ + /* 200 */ ULong guest_R23; /* Static registers */ + /* 208 */ ULong guest_R24; + /* 216 */ ULong guest_R25; + /* 224 */ ULong guest_R26; + /* 232 */ ULong guest_R27; + /* 240 */ ULong guest_R28; + /* 248 */ ULong guest_R29; + /* 256 */ ULong guest_R30; + /* 264 */ ULong guest_R31; + + /* 272 */ ULong guest_PC; /* Program counter */ + + /* 280 */ UChar guest_FCC0; /* Condition Flag Registers */ + /* 281 */ UChar guest_FCC1; + /* 282 */ UChar guest_FCC2; + /* 283 */ UChar guest_FCC3; + /* 284 */ UChar guest_FCC4; + /* 285 */ UChar guest_FCC5; + /* 286 */ UChar guest_FCC6; + /* 287 */ UChar guest_FCC7; + /* 288 */ UInt guest_FCSR; /* FP/SIMD Control and Status Register */ + + /* Various pseudo-regs mandated by Vex or Valgrind. */ + /* Emulation notes */ + /* 292 */ UInt guest_EMNOTE; + + /* For clflush: record start and length of area to invalidate */ + /* 296 */ ULong guest_CMSTART; + /* 304 */ ULong guest_CMLEN; + + /* Used to record the unredirected guest address at the start of + a translation whose start has been redirected. By reading + this pseudo-register shortly afterwards, the translation can + find out what the corresponding no-redirection address was. + Note, this is only set for wrap-style redirects, not for + replace-style ones. */ + /* 312 */ ULong guest_NRADDR; + + /* Fallback LL/SC support. */ + /* 320 */ ULong guest_LLSC_SIZE; /* 0==no transaction, else 4 or 8. */ + /* 328 */ ULong guest_LLSC_ADDR; /* Address of the transaction. */ + /* 336 */ ULong guest_LLSC_DATA; /* Original value at ADDR. */ + + /* 344 */ ULong _padding1; + + /* FPU/SIMD Registers */ + /* 352 */ U256 guest_X0; + /* 384 */ U256 guest_X1; + /* 416 */ U256 guest_X2; + /* 448 */ U256 guest_X3; + /* 480 */ U256 guest_X4; + /* 512 */ U256 guest_X5; + /* 544 */ U256 guest_X6; + /* 576 */ U256 guest_X7; + /* 608 */ U256 guest_X8; + /* 640 */ U256 guest_X9; + /* 672 */ U256 guest_X10; + /* 704 */ U256 guest_X11; + /* 736 */ U256 guest_X12; + /* 768 */ U256 guest_X13; + /* 800 */ U256 guest_X14; + /* 832 */ U256 guest_X15; + /* 864 */ U256 guest_X16; + /* 896 */ U256 guest_X17; + /* 928 */ U256 guest_X18; + /* 960 */ U256 guest_X19; + /* 992 */ U256 guest_X20; + /* 1024 */ U256 guest_X21; + /* 1056 */ U256 guest_X22; + /* 1088 */ U256 guest_X23; + /* 1120 */ U256 guest_X24; + /* 1152 */ U256 guest_X25; + /* 1184 */ U256 guest_X26; + /* 1216 */ U256 guest_X27; + /* 1248 */ U256 guest_X28; + /* 1280 */ U256 guest_X29; + /* 1312 */ U256 guest_X30; + /* 1244 */ U256 guest_X31; + + /* 1376 */ /* VexGuestLOONGARCH64State should have a 16-aligned size */ +} VexGuestLOONGARCH64State; + +/*---------------------------------------------------------------*/ +/*--- Utility functions for LOONGARCH64 guest stuff. ---*/ +/*---------------------------------------------------------------*/ + +/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT. */ + +/* Initialise all guest LOONGARCH64 state. */ + +extern +void LibVEX_GuestLOONGARCH64_initialise ( /*OUT*/ + VexGuestLOONGARCH64State* vex_state ); + +#endif /* ndef __LIBVEX_PUB_GUEST_LOONGARCH64_H */ + +/*---------------------------------------------------------------*/ +/*--- libvex_guest_loongarch64.h ---*/ +/*---------------------------------------------------------------*/ diff --git a/VEX/pub/libvex_guest_offsets.h b/VEX/pub/libvex_guest_offsets.h index a456b6d..9faa0ce 100644 --- a/VEX/pub/libvex_guest_offsets.h +++ b/VEX/pub/libvex_guest_offsets.h @@ -162,3 +162,36 @@ #define OFFSET_mips64_PC 272 #define OFFSET_mips64_HI 280 #define OFFSET_mips64_LO 288 +#define OFFSET_loongarch64_R0 16 +#define OFFSET_loongarch64_R1 24 +#define OFFSET_loongarch64_R2 32 +#define OFFSET_loongarch64_R3 40 +#define OFFSET_loongarch64_R4 48 +#define OFFSET_loongarch64_R5 56 +#define OFFSET_loongarch64_R6 64 +#define OFFSET_loongarch64_R7 72 +#define OFFSET_loongarch64_R8 80 +#define OFFSET_loongarch64_R9 88 +#define OFFSET_loongarch64_R10 96 +#define OFFSET_loongarch64_R11 104 +#define OFFSET_loongarch64_R12 112 +#define OFFSET_loongarch64_R13 120 +#define OFFSET_loongarch64_R14 128 +#define OFFSET_loongarch64_R15 136 +#define OFFSET_loongarch64_R16 144 +#define OFFSET_loongarch64_R17 152 +#define OFFSET_loongarch64_R18 160 +#define OFFSET_loongarch64_R19 168 +#define OFFSET_loongarch64_R20 176 +#define OFFSET_loongarch64_R21 184 +#define OFFSET_loongarch64_R22 192 +#define OFFSET_loongarch64_R23 200 +#define OFFSET_loongarch64_R24 208 +#define OFFSET_loongarch64_R25 216 +#define OFFSET_loongarch64_R26 224 +#define OFFSET_loongarch64_R27 232 +#define OFFSET_loongarch64_R28 240 +#define OFFSET_loongarch64_R29 248 +#define OFFSET_loongarch64_R30 256 +#define OFFSET_loongarch64_R31 264 +#define OFFSET_loongarch64_PC 272 diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h index 85805bb..c8b2e8f 100644 --- a/VEX/pub/libvex_ir.h +++ b/VEX/pub/libvex_ir.h @@ -588,10 +588,10 @@ typedef /* Binary operations, with rounding. */ /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */ - Iop_AddF64, Iop_SubF64, Iop_MulF64, Iop_DivF64, + Iop_AddF64, Iop_SubF64, Iop_MulF64, Iop_DivF64, Iop_ScaleBF64, /* :: IRRoundingMode(I32) x F32 x F32 -> F32 */ - Iop_AddF32, Iop_SubF32, Iop_MulF32, Iop_DivF32, + Iop_AddF32, Iop_SubF32, Iop_MulF32, Iop_DivF32, Iop_ScaleBF32, /* Variants of the above which produce a 64-bit result but which round their result to a IEEE float range first. */ @@ -610,10 +610,10 @@ typedef /* Unary operations, with rounding. */ /* :: IRRoundingMode(I32) x F64 -> F64 */ - Iop_SqrtF64, + Iop_SqrtF64, Iop_RSqrtF64, Iop_LogBF64, /* :: IRRoundingMode(I32) x F32 -> F32 */ - Iop_SqrtF32, + Iop_SqrtF32, Iop_RSqrtF32, Iop_LogBF32, /* :: IRRoundingMode(I32) x F16 -> F16 */ Iop_SqrtF16, @@ -829,10 +829,14 @@ typedef /* --------- Possibly required by IEEE 754-2008. --------- */ - Iop_MaxNumF64, /* max, F64, numerical operand if other is a qNaN */ - Iop_MinNumF64, /* min, F64, ditto */ - Iop_MaxNumF32, /* max, F32, ditto */ - Iop_MinNumF32, /* min, F32, ditto */ + Iop_MaxNumF64, /* max, F64, numerical operand if other is a qNaN */ + Iop_MinNumF64, /* min, F64, ditto */ + Iop_MaxNumAbsF64, /* max abs, F64, ditto */ + Iop_MinNumAbsF64, /* min abs, F64, ditto */ + Iop_MaxNumF32, /* max, F32, ditto */ + Iop_MinNumF32, /* min, F32, ditto */ + Iop_MaxNumAbsF32, /* max abs, F32, ditto */ + Iop_MinNumAbsF32, /* min abs, F32, ditto */ /* ------------------ 16-bit scalar FP ------------------ */ @@ -2006,10 +2010,10 @@ typedef Iop_ShrN16x16, Iop_ShrN32x8, Iop_ShrN64x4, Iop_SarN16x16, Iop_SarN32x8, - Iop_Max8Sx32, Iop_Max16Sx16, Iop_Max32Sx8, - Iop_Max8Ux32, Iop_Max16Ux16, Iop_Max32Ux8, - Iop_Min8Sx32, Iop_Min16Sx16, Iop_Min32Sx8, - Iop_Min8Ux32, Iop_Min16Ux16, Iop_Min32Ux8, + Iop_Max8Sx32, Iop_Max16Sx16, Iop_Max32Sx8, Iop_Max64Sx4, + Iop_Max8Ux32, Iop_Max16Ux16, Iop_Max32Ux8, Iop_Max64Ux4, + Iop_Min8Sx32, Iop_Min16Sx16, Iop_Min32Sx8, Iop_Min64Sx4, + Iop_Min8Ux32, Iop_Min16Ux16, Iop_Min32Ux8, Iop_Min64Ux4, Iop_Mul16x16, Iop_Mul32x8, Iop_MulHi16Ux16, Iop_MulHi16Sx16, @@ -2503,6 +2507,7 @@ typedef Ijk_SigFPE, /* current instruction synths generic SIGFPE */ Ijk_SigFPE_IntDiv, /* current instruction synths SIGFPE - IntDiv */ Ijk_SigFPE_IntOvf, /* current instruction synths SIGFPE - IntOvf */ + Ijk_SigSYS, /* current instruction synths SIGSYS */ /* Unfortunately, various guest-dependent syscall kinds. They all mean: do a syscall before continuing. */ Ijk_Sys_syscall, /* amd64/x86 'syscall', ppc 'sc', arm 'svc #0' */ @@ -2662,7 +2667,12 @@ typedef /* Needed only on ARM. It cancels a reservation made by a preceding Linked-Load, and needs to be handed through to the back end, just as LL and SC themselves are. */ - Imbe_CancelReservation + Imbe_CancelReservation, + /* Needed only on LOONGARCH64. It completes the synchronization + between the store operation and the instruction fetch operation + within a single processor core, and needs to be handed through + to the back end. */ + Imbe_InsnFence } IRMBusEvent; diff --git a/VEX/pub/libvex_trc_values.h b/VEX/pub/libvex_trc_values.h index cfd54de..90e2b60 100644 --- a/VEX/pub/libvex_trc_values.h +++ b/VEX/pub/libvex_trc_values.h @@ -57,6 +57,7 @@ continuing */ #define VEX_TRC_JMP_SIGBUS 93 /* deliver SIGBUS before continuing */ #define VEX_TRC_JMP_SIGFPE 105 /* deliver SIGFPE before continuing */ +#define VEX_TRC_JMP_SIGSYS 115 /* deliver SIGSYS before continuing */ #define VEX_TRC_JMP_SIGFPE_INTDIV 97 /* deliver SIGFPE (integer divide by zero) before continuing */ diff --git a/auxprogs/Makefile.in b/auxprogs/Makefile.in index cabc2bf..d9481c3 100644 --- a/auxprogs/Makefile.in +++ b/auxprogs/Makefile.in @@ -613,6 +613,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -660,6 +666,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ dist_noinst_SCRIPTS = \ diff --git a/cachegrind/Makefile.in b/cachegrind/Makefile.in index 1363cc6..3fc4a88 100644 --- a/cachegrind/Makefile.in +++ b/cachegrind/Makefile.in @@ -661,6 +661,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -708,6 +714,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -798,6 +805,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -858,6 +869,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -930,6 +944,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/cachegrind/cg_arch.c b/cachegrind/cg_arch.c index 68314c9..55f7585 100644 --- a/cachegrind/cg_arch.c +++ b/cachegrind/cg_arch.c @@ -484,6 +484,13 @@ configure_caches(cache_t *I1c, cache_t *D1c, cache_t *LLc, *D1c = (cache_t) { 65536, 2, 64 }; *LLc = (cache_t) { 262144, 8, 64 }; +#elif defined(VGA_loongarch64) + + // Set caches to default (for LOONGARCH64 - 3A5000) + *I1c = (cache_t) { 65536, 4, 64 }; + *D1c = (cache_t) { 65536, 4, 64 }; + *LLc = (cache_t) { 262144, 16, 64 }; + #else #error "Unknown arch" diff --git a/cachegrind/cg_branchpred.c b/cachegrind/cg_branchpred.c index 927b7bf..6a97209 100644 --- a/cachegrind/cg_branchpred.c +++ b/cachegrind/cg_branchpred.c @@ -44,7 +44,7 @@ guaranteed to be zero? */ #if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) \ - || defined(VGA_arm64) + || defined(VGA_arm64) || defined(VGA_loongarch64) # define N_IADDR_LO_ZERO_BITS 2 #elif defined(VGA_x86) || defined(VGA_amd64) # define N_IADDR_LO_ZERO_BITS 0 diff --git a/cachegrind/tests/Makefile.in b/cachegrind/tests/Makefile.in index 722b1e7..7bb020e 100644 --- a/cachegrind/tests/Makefile.in +++ b/cachegrind/tests/Makefile.in @@ -629,6 +629,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -676,6 +682,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/cachegrind/tests/x86/Makefile.in b/cachegrind/tests/x86/Makefile.in index 1f7c820..6fcfd84 100644 --- a/cachegrind/tests/x86/Makefile.in +++ b/cachegrind/tests/x86/Makefile.in @@ -572,6 +572,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -619,6 +625,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/callgrind/Makefile.in b/callgrind/Makefile.in index 0c33846..a74dfa5 100644 --- a/callgrind/Makefile.in +++ b/callgrind/Makefile.in @@ -708,6 +708,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -755,6 +761,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -845,6 +852,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -905,6 +916,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -977,6 +991,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/callgrind/tests/Makefile.in b/callgrind/tests/Makefile.in index 5268175..9a98624 100644 --- a/callgrind/tests/Makefile.in +++ b/callgrind/tests/Makefile.in @@ -614,6 +614,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -661,6 +667,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/config.h b/config.h index 34b8917..9bdf4ff 100644 --- a/config.h +++ b/config.h @@ -96,7 +96,7 @@ #define HAVE_ASM_UNISTD_H 1 /* Define to 1 if as supports fxsave64/fxrstor64. */ -#define HAVE_AS_AMD64_FXSAVE64 1 +/* #undef HAVE_AS_AMD64_FXSAVE64 */ /* Define to 1 if as supports floating point phased out category. */ /* #undef HAVE_AS_PPC_FPPO */ diff --git a/configure b/configure index 26f7d89..9d6deb1 100755 --- a/configure +++ b/configure @@ -1003,6 +1003,8 @@ VGCONF_PLATFORMS_INCLUDE_AMD64_FREEBSD_FALSE VGCONF_PLATFORMS_INCLUDE_AMD64_FREEBSD_TRUE VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD_FALSE VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD_TRUE +VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX_FALSE +VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX_TRUE VGCONF_PLATFORMS_INCLUDE_NANOMIPS_LINUX_FALSE VGCONF_PLATFORMS_INCLUDE_NANOMIPS_LINUX_TRUE VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX_FALSE @@ -1025,6 +1027,8 @@ VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_FALSE VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE VGCONF_PLATFORMS_INCLUDE_X86_LINUX_FALSE VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE +VGCONF_ARCHS_INCLUDE_LOONGARCH64_FALSE +VGCONF_ARCHS_INCLUDE_LOONGARCH64_TRUE VGCONF_ARCHS_INCLUDE_NANOMIPS_FALSE VGCONF_ARCHS_INCLUDE_NANOMIPS_TRUE VGCONF_ARCHS_INCLUDE_MIPS64_FALSE @@ -6938,6 +6942,12 @@ printf "%s\n" "ok (${host_cpu})" >&6; } ARCH_MAX="nanomips" ;; + loongarch64*) + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: ok (${host_cpu})" >&5 +printf "%s\n" "ok (${host_cpu})" >&6; } + ARCH_MAX="loongarch64" + ;; + *) { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no (${host_cpu})" >&5 printf "%s\n" "no (${host_cpu})" >&6; } @@ -7764,6 +7774,18 @@ printf "%s\n" "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; } valt_load_address_sec_norml="0xUNSET" valt_load_address_sec_inner="0xUNSET" { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5 +printf "%s\n" "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; } + ;; + loongarch64-linux) + VGCONF_ARCH_PRI="loongarch64" + VGCONF_ARCH_SEC="" + VGCONF_PLATFORM_PRI_CAPS="LOONGARCH64_LINUX" + VGCONF_PLATFORM_SEC_CAPS="" + valt_load_address_pri_norml="0x58000000" + valt_load_address_pri_inner="0x38000000" + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5 printf "%s\n" "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; } ;; x86-solaris) @@ -7921,6 +7943,14 @@ else VGCONF_ARCHS_INCLUDE_NANOMIPS_FALSE= fi + if test x$VGCONF_PLATFORM_PRI_CAPS = xLOONGARCH64_LINUX ; then + VGCONF_ARCHS_INCLUDE_LOONGARCH64_TRUE= + VGCONF_ARCHS_INCLUDE_LOONGARCH64_FALSE='#' +else + VGCONF_ARCHS_INCLUDE_LOONGARCH64_TRUE='#' + VGCONF_ARCHS_INCLUDE_LOONGARCH64_FALSE= +fi + # Set up VGCONF_PLATFORMS_INCLUDE_. Either one or two of these # become defined. @@ -8017,6 +8047,14 @@ else VGCONF_PLATFORMS_INCLUDE_NANOMIPS_LINUX_FALSE= fi + if test x$VGCONF_PLATFORM_PRI_CAPS = xLOONGARCH64_LINUX; then + VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX_TRUE= + VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX_FALSE='#' +else + VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX_TRUE='#' + VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX_FALSE= +fi + if test x$VGCONF_PLATFORM_PRI_CAPS = xX86_FREEBSD \ -o x$VGCONF_PLATFORM_SEC_CAPS = xX86_FREEBSD; then VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD_TRUE= @@ -8083,7 +8121,8 @@ fi -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xNANOMIPS_LINUX; then + -o x$VGCONF_PLATFORM_PRI_CAPS = xNANOMIPS_LINUX \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xLOONGARCH64_LINUX; then VGCONF_OS_IS_LINUX_TRUE= VGCONF_OS_IS_LINUX_FALSE='#' else @@ -18254,7 +18293,8 @@ elif test x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX ; then + -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xLOONGARCH64_LINUX; then mflag_primary=$FLAG_M64 elif test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN ; then mflag_primary="$FLAG_M32 -arch i386" @@ -19213,7 +19253,7 @@ fi #---------------------------------------------------------------------------- # Nb: VEX/Makefile is generated from Makefile.vex.in. -ac_config_files="$ac_config_files Makefile VEX/Makefile:Makefile.vex.in valgrind.spec valgrind.pc glibc-2.X.supp glibc-2.X-helgrind.supp glibc-2.X-drd.supp include/valgrind.h docs/Makefile docs/xml/vg-entities.xml tests/Makefile tests/vg_regtest perf/Makefile perf/vg_perf gdbserver_tests/Makefile gdbserver_tests/solaris/Makefile include/Makefile auxprogs/Makefile mpi/Makefile coregrind/Makefile memcheck/Makefile memcheck/tests/Makefile memcheck/tests/common/Makefile memcheck/tests/amd64/Makefile memcheck/tests/x86/Makefile memcheck/tests/linux/Makefile memcheck/tests/linux/debuginfod-check.vgtest memcheck/tests/darwin/Makefile memcheck/tests/solaris/Makefile memcheck/tests/freebsd/Makefile memcheck/tests/amd64-linux/Makefile memcheck/tests/arm64-linux/Makefile memcheck/tests/x86-linux/Makefile memcheck/tests/amd64-solaris/Makefile memcheck/tests/x86-solaris/Makefile memcheck/tests/amd64-freebsd/Makefile memcheck/tests/x86-freebsd/Makefile memcheck/tests/ppc32/Makefile memcheck/tests/ppc64/Makefile memcheck/tests/s390x/Makefile memcheck/tests/mips32/Makefile memcheck/tests/mips64/Makefile memcheck/tests/vbit-test/Makefile cachegrind/Makefile cachegrind/tests/Makefile cachegrind/tests/x86/Makefile cachegrind/cg_annotate cachegrind/cg_diff cachegrind/cg_merge callgrind/Makefile callgrind/callgrind_annotate callgrind/callgrind_control callgrind/tests/Makefile helgrind/Makefile helgrind/tests/Makefile drd/Makefile drd/scripts/download-and-build-splash2 drd/tests/Makefile massif/Makefile massif/tests/Makefile massif/ms_print dhat/Makefile dhat/tests/Makefile lackey/Makefile lackey/tests/Makefile none/Makefile none/tests/Makefile none/tests/scripts/Makefile none/tests/amd64/Makefile none/tests/ppc32/Makefile none/tests/ppc64/Makefile none/tests/x86/Makefile none/tests/arm/Makefile none/tests/arm64/Makefile none/tests/s390x/Makefile none/tests/mips32/Makefile none/tests/mips64/Makefile none/tests/nanomips/Makefile none/tests/linux/Makefile none/tests/darwin/Makefile none/tests/solaris/Makefile none/tests/freebsd/Makefile none/tests/amd64-linux/Makefile none/tests/x86-linux/Makefile none/tests/amd64-darwin/Makefile none/tests/x86-darwin/Makefile none/tests/amd64-solaris/Makefile none/tests/x86-solaris/Makefile none/tests/x86-freebsd/Makefile exp-bbv/Makefile exp-bbv/tests/Makefile exp-bbv/tests/x86/Makefile exp-bbv/tests/x86-linux/Makefile exp-bbv/tests/amd64-linux/Makefile exp-bbv/tests/ppc32-linux/Makefile exp-bbv/tests/arm-linux/Makefile shared/Makefile solaris/Makefile" +ac_config_files="$ac_config_files Makefile VEX/Makefile:Makefile.vex.in valgrind.spec valgrind.pc glibc-2.X.supp glibc-2.X-helgrind.supp glibc-2.X-drd.supp include/valgrind.h docs/Makefile docs/xml/vg-entities.xml tests/Makefile tests/vg_regtest perf/Makefile perf/vg_perf gdbserver_tests/Makefile gdbserver_tests/solaris/Makefile include/Makefile auxprogs/Makefile mpi/Makefile coregrind/Makefile memcheck/Makefile memcheck/tests/Makefile memcheck/tests/common/Makefile memcheck/tests/amd64/Makefile memcheck/tests/x86/Makefile memcheck/tests/linux/Makefile memcheck/tests/linux/debuginfod-check.vgtest memcheck/tests/darwin/Makefile memcheck/tests/solaris/Makefile memcheck/tests/freebsd/Makefile memcheck/tests/amd64-linux/Makefile memcheck/tests/arm64-linux/Makefile memcheck/tests/x86-linux/Makefile memcheck/tests/loongarch64-linux/Makefile memcheck/tests/amd64-solaris/Makefile memcheck/tests/x86-solaris/Makefile memcheck/tests/amd64-freebsd/Makefile memcheck/tests/x86-freebsd/Makefile memcheck/tests/ppc32/Makefile memcheck/tests/ppc64/Makefile memcheck/tests/s390x/Makefile memcheck/tests/mips32/Makefile memcheck/tests/mips64/Makefile memcheck/tests/vbit-test/Makefile cachegrind/Makefile cachegrind/tests/Makefile cachegrind/tests/x86/Makefile cachegrind/cg_annotate cachegrind/cg_diff cachegrind/cg_merge callgrind/Makefile callgrind/callgrind_annotate callgrind/callgrind_control callgrind/tests/Makefile helgrind/Makefile helgrind/tests/Makefile drd/Makefile drd/scripts/download-and-build-splash2 drd/tests/Makefile massif/Makefile massif/tests/Makefile massif/ms_print dhat/Makefile dhat/tests/Makefile lackey/Makefile lackey/tests/Makefile none/Makefile none/tests/Makefile none/tests/scripts/Makefile none/tests/amd64/Makefile none/tests/ppc32/Makefile none/tests/ppc64/Makefile none/tests/x86/Makefile none/tests/arm/Makefile none/tests/arm64/Makefile none/tests/s390x/Makefile none/tests/mips32/Makefile none/tests/mips64/Makefile none/tests/nanomips/Makefile none/tests/loongarch64/Makefile none/tests/linux/Makefile none/tests/darwin/Makefile none/tests/solaris/Makefile none/tests/freebsd/Makefile none/tests/amd64-linux/Makefile none/tests/x86-linux/Makefile none/tests/amd64-darwin/Makefile none/tests/x86-darwin/Makefile none/tests/amd64-solaris/Makefile none/tests/x86-solaris/Makefile none/tests/x86-freebsd/Makefile exp-bbv/Makefile exp-bbv/tests/Makefile exp-bbv/tests/x86/Makefile exp-bbv/tests/x86-linux/Makefile exp-bbv/tests/amd64-linux/Makefile exp-bbv/tests/ppc32-linux/Makefile exp-bbv/tests/arm-linux/Makefile shared/Makefile solaris/Makefile" ac_config_files="$ac_config_files coregrind/link_tool_exe_linux" @@ -19450,6 +19490,10 @@ if test -z "${VGCONF_ARCHS_INCLUDE_NANOMIPS_TRUE}" && test -z "${VGCONF_ARCHS_IN as_fn_error $? "conditional \"VGCONF_ARCHS_INCLUDE_NANOMIPS\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi +if test -z "${VGCONF_ARCHS_INCLUDE_LOONGARCH64_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_LOONGARCH64_FALSE}"; then + as_fn_error $? "conditional \"VGCONF_ARCHS_INCLUDE_LOONGARCH64\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi if test -z "${VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_X86_LINUX_FALSE}"; then as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_X86_LINUX\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 @@ -19494,6 +19538,10 @@ if test -z "${VGCONF_PLATFORMS_INCLUDE_NANOMIPS_LINUX_TRUE}" && test -z "${VGCON as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_NANOMIPS_LINUX\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi +if test -z "${VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX_FALSE}"; then + as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi if test -z "${VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD_FALSE}"; then as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 @@ -20752,6 +20800,7 @@ do "memcheck/tests/amd64-linux/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/amd64-linux/Makefile" ;; "memcheck/tests/arm64-linux/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/arm64-linux/Makefile" ;; "memcheck/tests/x86-linux/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/x86-linux/Makefile" ;; + "memcheck/tests/loongarch64-linux/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/loongarch64-linux/Makefile" ;; "memcheck/tests/amd64-solaris/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/amd64-solaris/Makefile" ;; "memcheck/tests/x86-solaris/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/x86-solaris/Makefile" ;; "memcheck/tests/amd64-freebsd/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/amd64-freebsd/Makefile" ;; @@ -20797,6 +20846,7 @@ do "none/tests/mips32/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/mips32/Makefile" ;; "none/tests/mips64/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/mips64/Makefile" ;; "none/tests/nanomips/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/nanomips/Makefile" ;; + "none/tests/loongarch64/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/loongarch64/Makefile" ;; "none/tests/linux/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/linux/Makefile" ;; "none/tests/darwin/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/darwin/Makefile" ;; "none/tests/solaris/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/solaris/Makefile" ;; diff --git a/configure.ac b/configure.ac index bf024ac..47485d1 100755 --- a/configure.ac +++ b/configure.ac @@ -310,6 +310,11 @@ case "${host_cpu}" in ARCH_MAX="nanomips" ;; + loongarch64*) + AC_MSG_RESULT([ok (${host_cpu})]) + ARCH_MAX="loongarch64" + ;; + *) AC_MSG_RESULT([no (${host_cpu})]) AC_MSG_ERROR([Unsupported host architecture. Sorry]) @@ -952,6 +957,17 @@ case "$ARCH_MAX-$VGCONF_OS" in valt_load_address_sec_inner="0xUNSET" AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) ;; + loongarch64-linux) + VGCONF_ARCH_PRI="loongarch64" + VGCONF_ARCH_SEC="" + VGCONF_PLATFORM_PRI_CAPS="LOONGARCH64_LINUX" + VGCONF_PLATFORM_SEC_CAPS="" + valt_load_address_pri_norml="0x58000000" + valt_load_address_pri_inner="0x38000000" + valt_load_address_sec_norml="0xUNSET" + valt_load_address_sec_inner="0xUNSET" + AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) + ;; x86-solaris) VGCONF_ARCH_PRI="x86" VGCONF_ARCH_SEC="" @@ -1044,6 +1060,8 @@ AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_MIPS64, test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX ) AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_NANOMIPS, test x$VGCONF_PLATFORM_PRI_CAPS = xNANOMIPS_LINUX ) +AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_LOONGARCH64, + test x$VGCONF_PLATFORM_PRI_CAPS = xLOONGARCH64_LINUX ) # Set up VGCONF_PLATFORMS_INCLUDE_. Either one or two of these # become defined. @@ -1074,6 +1092,8 @@ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX, test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX) AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_NANOMIPS_LINUX, test x$VGCONF_PLATFORM_PRI_CAPS = xNANOMIPS_LINUX) +AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX, + test x$VGCONF_PLATFORM_PRI_CAPS = xLOONGARCH64_LINUX) AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD, test x$VGCONF_PLATFORM_PRI_CAPS = xX86_FREEBSD \ -o x$VGCONF_PLATFORM_SEC_CAPS = xX86_FREEBSD) @@ -1105,7 +1125,8 @@ AM_CONDITIONAL(VGCONF_OS_IS_LINUX, -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xNANOMIPS_LINUX) + -o x$VGCONF_PLATFORM_PRI_CAPS = xNANOMIPS_LINUX \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xLOONGARCH64_LINUX) AM_CONDITIONAL(VGCONF_OS_IS_FREEBSD, test x$VGCONF_PLATFORM_PRI_CAPS = xX86_FREEBSD \ -o x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_FREEBSD) @@ -4979,7 +5000,8 @@ elif test x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \ -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX ; then + -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xLOONGARCH64_LINUX; then mflag_primary=$FLAG_M64 elif test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN ; then mflag_primary="$FLAG_M32 -arch i386" @@ -5505,6 +5527,7 @@ AC_CONFIG_FILES([ memcheck/tests/amd64-linux/Makefile memcheck/tests/arm64-linux/Makefile memcheck/tests/x86-linux/Makefile + memcheck/tests/loongarch64-linux/Makefile memcheck/tests/amd64-solaris/Makefile memcheck/tests/x86-solaris/Makefile memcheck/tests/amd64-freebsd/Makefile @@ -5550,6 +5573,7 @@ AC_CONFIG_FILES([ none/tests/mips32/Makefile none/tests/mips64/Makefile none/tests/nanomips/Makefile + none/tests/loongarch64/Makefile none/tests/linux/Makefile none/tests/darwin/Makefile none/tests/solaris/Makefile diff --git a/coregrind/Makefile.am b/coregrind/Makefile.am index 8a7f753..54c4824 100644 --- a/coregrind/Makefile.am +++ b/coregrind/Makefile.am @@ -386,6 +386,7 @@ COREGRIND_SOURCES_COMMON = \ m_dispatch/dispatch-mips32-linux.S \ m_dispatch/dispatch-mips64-linux.S \ m_dispatch/dispatch-nanomips-linux.S \ + m_dispatch/dispatch-loongarch64-linux.S \ m_dispatch/dispatch-x86-freebsd.S \ m_dispatch/dispatch-amd64-freebsd.S \ m_dispatch/dispatch-x86-darwin.S \ @@ -409,6 +410,7 @@ COREGRIND_SOURCES_COMMON = \ m_gdbserver/valgrind-low-mips32.c \ m_gdbserver/valgrind-low-mips64.c \ m_gdbserver/valgrind-low-nanomips.c \ + m_gdbserver/valgrind-low-loongarch64.c \ m_gdbserver/version.c \ m_initimg/initimg-linux.c \ m_initimg/initimg-freebsd.c \ @@ -436,6 +438,7 @@ COREGRIND_SOURCES_COMMON = \ m_sigframe/sigframe-mips32-linux.c \ m_sigframe/sigframe-mips64-linux.c \ m_sigframe/sigframe-nanomips-linux.c \ + m_sigframe/sigframe-loongarch64-linux.c \ m_sigframe/sigframe-x86-darwin.c \ m_sigframe/sigframe-amd64-darwin.c \ m_sigframe/sigframe-solaris.c \ @@ -450,6 +453,7 @@ COREGRIND_SOURCES_COMMON = \ m_syswrap/syscall-mips32-linux.S \ m_syswrap/syscall-mips64-linux.S \ m_syswrap/syscall-nanomips-linux.S \ + m_syswrap/syscall-loongarch64-linux.S \ m_syswrap/syscall-x86-freebsd.S \ m_syswrap/syscall-amd64-freebsd.S \ m_syswrap/syscall-x86-darwin.S \ @@ -475,6 +479,7 @@ COREGRIND_SOURCES_COMMON = \ m_syswrap/syswrap-mips32-linux.c \ m_syswrap/syswrap-mips64-linux.c \ m_syswrap/syswrap-nanomips-linux.c \ + m_syswrap/syswrap-loongarch64-linux.c \ m_syswrap/syswrap-x86-darwin.c \ m_syswrap/syswrap-amd64-darwin.c \ m_syswrap/syswrap-xen.c \ @@ -767,7 +772,15 @@ GDBSERVER_XML_FILES = \ m_gdbserver/mips64-linux-valgrind.xml \ m_gdbserver/mips64-fpu-valgrind-s1.xml \ m_gdbserver/mips64-fpu-valgrind-s2.xml \ - m_gdbserver/mips64-fpu.xml + m_gdbserver/mips64-fpu.xml \ + m_gdbserver/loongarch-base64.xml \ + m_gdbserver/loongarch-fpu64.xml \ + m_gdbserver/loongarch64-linux.xml \ + m_gdbserver/loongarch-base64-valgrind-s1.xml \ + m_gdbserver/loongarch-base64-valgrind-s2.xml \ + m_gdbserver/loongarch-fpu64-valgrind-s1.xml \ + m_gdbserver/loongarch-fpu64-valgrind-s2.xml \ + m_gdbserver/loongarch64-linux-valgrind.xml # so as to make sure these get copied into the install tree vglibdir = $(pkglibexecdir) diff --git a/coregrind/Makefile.in b/coregrind/Makefile.in index 554ee94..a14da8d 100644 --- a/coregrind/Makefile.in +++ b/coregrind/Makefile.in @@ -280,6 +280,7 @@ am__libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES_DIST = \ m_dispatch/dispatch-mips32-linux.S \ m_dispatch/dispatch-mips64-linux.S \ m_dispatch/dispatch-nanomips-linux.S \ + m_dispatch/dispatch-loongarch64-linux.S \ m_dispatch/dispatch-x86-freebsd.S \ m_dispatch/dispatch-amd64-freebsd.S \ m_dispatch/dispatch-x86-darwin.S \ @@ -298,7 +299,8 @@ am__libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES_DIST = \ m_gdbserver/valgrind-low-s390x.c \ m_gdbserver/valgrind-low-mips32.c \ m_gdbserver/valgrind-low-mips64.c \ - m_gdbserver/valgrind-low-nanomips.c m_gdbserver/version.c \ + m_gdbserver/valgrind-low-nanomips.c \ + m_gdbserver/valgrind-low-loongarch64.c m_gdbserver/version.c \ m_initimg/initimg-linux.c m_initimg/initimg-freebsd.c \ m_initimg/initimg-darwin.c m_initimg/initimg-solaris.c \ m_mach/mach_basics.c m_mach/mach_msg.c \ @@ -319,6 +321,7 @@ am__libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES_DIST = \ m_sigframe/sigframe-mips32-linux.c \ m_sigframe/sigframe-mips64-linux.c \ m_sigframe/sigframe-nanomips-linux.c \ + m_sigframe/sigframe-loongarch64-linux.c \ m_sigframe/sigframe-x86-darwin.c \ m_sigframe/sigframe-amd64-darwin.c \ m_sigframe/sigframe-solaris.c m_syswrap/syscall-x86-linux.S \ @@ -331,6 +334,7 @@ am__libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES_DIST = \ m_syswrap/syscall-mips32-linux.S \ m_syswrap/syscall-mips64-linux.S \ m_syswrap/syscall-nanomips-linux.S \ + m_syswrap/syscall-loongarch64-linux.S \ m_syswrap/syscall-x86-freebsd.S \ m_syswrap/syscall-amd64-freebsd.S \ m_syswrap/syscall-x86-darwin.S \ @@ -350,6 +354,7 @@ am__libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES_DIST = \ m_syswrap/syswrap-mips32-linux.c \ m_syswrap/syswrap-mips64-linux.c \ m_syswrap/syswrap-nanomips-linux.c \ + m_syswrap/syswrap-loongarch64-linux.c \ m_syswrap/syswrap-x86-darwin.c \ m_syswrap/syswrap-amd64-darwin.c m_syswrap/syswrap-xen.c \ m_syswrap/syswrap-x86-solaris.c \ @@ -437,6 +442,7 @@ am__objects_1 = libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_addrinfo.$(OBJEXT m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.$(OBJEXT) \ m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips64-linux.$(OBJEXT) \ m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-nanomips-linux.$(OBJEXT) \ + m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-loongarch64-linux.$(OBJEXT) \ m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-freebsd.$(OBJEXT) \ m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-freebsd.$(OBJEXT) \ m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.$(OBJEXT) \ @@ -460,6 +466,7 @@ am__objects_1 = libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_addrinfo.$(OBJEXT m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.$(OBJEXT) \ m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips64.$(OBJEXT) \ m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-nanomips.$(OBJEXT) \ + m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-loongarch64.$(OBJEXT) \ m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.$(OBJEXT) \ m_initimg/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.$(OBJEXT) \ m_initimg/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-freebsd.$(OBJEXT) \ @@ -487,6 +494,7 @@ am__objects_1 = libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_addrinfo.$(OBJEXT m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.$(OBJEXT) \ m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips64-linux.$(OBJEXT) \ m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-nanomips-linux.$(OBJEXT) \ + m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-loongarch64-linux.$(OBJEXT) \ m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT) \ m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.$(OBJEXT) \ m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-solaris.$(OBJEXT) \ @@ -501,6 +509,7 @@ am__objects_1 = libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_addrinfo.$(OBJEXT m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips64-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-nanomips-linux.$(OBJEXT) \ + m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-loongarch64-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-freebsd.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-freebsd.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.$(OBJEXT) \ @@ -526,6 +535,7 @@ am__objects_1 = libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_addrinfo.$(OBJEXT m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips64-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-nanomips-linux.$(OBJEXT) \ + m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-loongarch64-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-xen.$(OBJEXT) \ @@ -587,6 +597,7 @@ am__libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST = \ m_dispatch/dispatch-mips32-linux.S \ m_dispatch/dispatch-mips64-linux.S \ m_dispatch/dispatch-nanomips-linux.S \ + m_dispatch/dispatch-loongarch64-linux.S \ m_dispatch/dispatch-x86-freebsd.S \ m_dispatch/dispatch-amd64-freebsd.S \ m_dispatch/dispatch-x86-darwin.S \ @@ -605,7 +616,8 @@ am__libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST = \ m_gdbserver/valgrind-low-s390x.c \ m_gdbserver/valgrind-low-mips32.c \ m_gdbserver/valgrind-low-mips64.c \ - m_gdbserver/valgrind-low-nanomips.c m_gdbserver/version.c \ + m_gdbserver/valgrind-low-nanomips.c \ + m_gdbserver/valgrind-low-loongarch64.c m_gdbserver/version.c \ m_initimg/initimg-linux.c m_initimg/initimg-freebsd.c \ m_initimg/initimg-darwin.c m_initimg/initimg-solaris.c \ m_mach/mach_basics.c m_mach/mach_msg.c \ @@ -626,6 +638,7 @@ am__libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST = \ m_sigframe/sigframe-mips32-linux.c \ m_sigframe/sigframe-mips64-linux.c \ m_sigframe/sigframe-nanomips-linux.c \ + m_sigframe/sigframe-loongarch64-linux.c \ m_sigframe/sigframe-x86-darwin.c \ m_sigframe/sigframe-amd64-darwin.c \ m_sigframe/sigframe-solaris.c m_syswrap/syscall-x86-linux.S \ @@ -638,6 +651,7 @@ am__libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST = \ m_syswrap/syscall-mips32-linux.S \ m_syswrap/syscall-mips64-linux.S \ m_syswrap/syscall-nanomips-linux.S \ + m_syswrap/syscall-loongarch64-linux.S \ m_syswrap/syscall-x86-freebsd.S \ m_syswrap/syscall-amd64-freebsd.S \ m_syswrap/syscall-x86-darwin.S \ @@ -657,6 +671,7 @@ am__libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST = \ m_syswrap/syswrap-mips32-linux.c \ m_syswrap/syswrap-mips64-linux.c \ m_syswrap/syswrap-nanomips-linux.c \ + m_syswrap/syswrap-loongarch64-linux.c \ m_syswrap/syswrap-x86-darwin.c \ m_syswrap/syswrap-amd64-darwin.c m_syswrap/syswrap-xen.c \ m_syswrap/syswrap-x86-solaris.c \ @@ -743,6 +758,7 @@ am__objects_7 = libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_addrinfo.$(OBJEXT m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.$(OBJEXT) \ m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips64-linux.$(OBJEXT) \ m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-nanomips-linux.$(OBJEXT) \ + m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-loongarch64-linux.$(OBJEXT) \ m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-freebsd.$(OBJEXT) \ m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-freebsd.$(OBJEXT) \ m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.$(OBJEXT) \ @@ -766,6 +782,7 @@ am__objects_7 = libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_addrinfo.$(OBJEXT m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.$(OBJEXT) \ m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips64.$(OBJEXT) \ m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-nanomips.$(OBJEXT) \ + m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-loongarch64.$(OBJEXT) \ m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.$(OBJEXT) \ m_initimg/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.$(OBJEXT) \ m_initimg/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-freebsd.$(OBJEXT) \ @@ -793,6 +810,7 @@ am__objects_7 = libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_addrinfo.$(OBJEXT m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.$(OBJEXT) \ m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips64-linux.$(OBJEXT) \ m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-nanomips-linux.$(OBJEXT) \ + m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-loongarch64-linux.$(OBJEXT) \ m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT) \ m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.$(OBJEXT) \ m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-solaris.$(OBJEXT) \ @@ -807,6 +825,7 @@ am__objects_7 = libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_addrinfo.$(OBJEXT m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips64-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-nanomips-linux.$(OBJEXT) \ + m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-loongarch64-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-freebsd.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-freebsd.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.$(OBJEXT) \ @@ -832,6 +851,7 @@ am__objects_7 = libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_addrinfo.$(OBJEXT m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips64-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-nanomips-linux.$(OBJEXT) \ + m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.$(OBJEXT) \ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-xen.$(OBJEXT) \ @@ -1133,6 +1153,7 @@ am__depfiles_remade = ./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-solaris.Po \ m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Po \ m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm64-linux.Po \ + m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-loongarch64-linux.Po \ m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Po \ m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips64-linux.Po \ m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-nanomips-linux.Po \ @@ -1150,6 +1171,7 @@ am__depfiles_remade = ./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-solaris.Po \ m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Po \ m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm64-linux.Po \ + m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-loongarch64-linux.Po \ m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Po \ m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips64-linux.Po \ m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-nanomips-linux.Po \ @@ -1171,6 +1193,7 @@ am__depfiles_remade = ./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Po \ m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Po \ m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm64.Po \ + m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-loongarch64.Po \ m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Po \ m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips64.Po \ m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-nanomips.Po \ @@ -1189,6 +1212,7 @@ am__depfiles_remade = ./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Po \ m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Po \ m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm64.Po \ + m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-loongarch64.Po \ m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Po \ m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips64.Po \ m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-nanomips.Po \ @@ -1243,6 +1267,7 @@ am__depfiles_remade = ./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Po \ m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm64-linux.Po \ m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-common.Po \ + m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-loongarch64-linux.Po \ m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Po \ m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips64-linux.Po \ m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-nanomips-linux.Po \ @@ -1259,6 +1284,7 @@ am__depfiles_remade = ./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Po \ m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm64-linux.Po \ m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-common.Po \ + m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-loongarch64-linux.Po \ m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Po \ m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips64-linux.Po \ m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-nanomips-linux.Po \ @@ -1275,6 +1301,7 @@ am__depfiles_remade = ./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-solaris.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm64-linux.Po \ + m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-loongarch64-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips64-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-nanomips-linux.Po \ @@ -1297,6 +1324,7 @@ am__depfiles_remade = ./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Po \ + m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips64-linux.Po \ @@ -1316,6 +1344,7 @@ am__depfiles_remade = ./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-solaris.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm64-linux.Po \ + m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-loongarch64-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips64-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-nanomips-linux.Po \ @@ -1338,6 +1367,7 @@ am__depfiles_remade = ./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Po \ + m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Po \ m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips64-linux.Po \ @@ -1818,6 +1848,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -1865,6 +1901,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -2144,6 +2181,7 @@ COREGRIND_SOURCES_COMMON = \ m_dispatch/dispatch-mips32-linux.S \ m_dispatch/dispatch-mips64-linux.S \ m_dispatch/dispatch-nanomips-linux.S \ + m_dispatch/dispatch-loongarch64-linux.S \ m_dispatch/dispatch-x86-freebsd.S \ m_dispatch/dispatch-amd64-freebsd.S \ m_dispatch/dispatch-x86-darwin.S \ @@ -2167,6 +2205,7 @@ COREGRIND_SOURCES_COMMON = \ m_gdbserver/valgrind-low-mips32.c \ m_gdbserver/valgrind-low-mips64.c \ m_gdbserver/valgrind-low-nanomips.c \ + m_gdbserver/valgrind-low-loongarch64.c \ m_gdbserver/version.c \ m_initimg/initimg-linux.c \ m_initimg/initimg-freebsd.c \ @@ -2194,6 +2233,7 @@ COREGRIND_SOURCES_COMMON = \ m_sigframe/sigframe-mips32-linux.c \ m_sigframe/sigframe-mips64-linux.c \ m_sigframe/sigframe-nanomips-linux.c \ + m_sigframe/sigframe-loongarch64-linux.c \ m_sigframe/sigframe-x86-darwin.c \ m_sigframe/sigframe-amd64-darwin.c \ m_sigframe/sigframe-solaris.c \ @@ -2208,6 +2248,7 @@ COREGRIND_SOURCES_COMMON = \ m_syswrap/syscall-mips32-linux.S \ m_syswrap/syscall-mips64-linux.S \ m_syswrap/syscall-nanomips-linux.S \ + m_syswrap/syscall-loongarch64-linux.S \ m_syswrap/syscall-x86-freebsd.S \ m_syswrap/syscall-amd64-freebsd.S \ m_syswrap/syscall-x86-darwin.S \ @@ -2233,6 +2274,7 @@ COREGRIND_SOURCES_COMMON = \ m_syswrap/syswrap-mips32-linux.c \ m_syswrap/syswrap-mips64-linux.c \ m_syswrap/syswrap-nanomips-linux.c \ + m_syswrap/syswrap-loongarch64-linux.c \ m_syswrap/syswrap-x86-darwin.c \ m_syswrap/syswrap-amd64-darwin.c \ m_syswrap/syswrap-xen.c \ @@ -2487,7 +2529,15 @@ GDBSERVER_XML_FILES = \ m_gdbserver/mips64-linux-valgrind.xml \ m_gdbserver/mips64-fpu-valgrind-s1.xml \ m_gdbserver/mips64-fpu-valgrind-s2.xml \ - m_gdbserver/mips64-fpu.xml + m_gdbserver/mips64-fpu.xml \ + m_gdbserver/loongarch-base64.xml \ + m_gdbserver/loongarch-fpu64.xml \ + m_gdbserver/loongarch64-linux.xml \ + m_gdbserver/loongarch-base64-valgrind-s1.xml \ + m_gdbserver/loongarch-base64-valgrind-s2.xml \ + m_gdbserver/loongarch-fpu64-valgrind-s1.xml \ + m_gdbserver/loongarch-fpu64-valgrind-s2.xml \ + m_gdbserver/loongarch64-linux-valgrind.xml # so as to make sure these get copied into the install tree @@ -2762,6 +2812,9 @@ m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips64-linux.$( m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-nanomips-linux.$(OBJEXT): \ m_dispatch/$(am__dirstamp) \ m_dispatch/$(DEPDIR)/$(am__dirstamp) +m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-loongarch64-linux.$(OBJEXT): \ + m_dispatch/$(am__dirstamp) \ + m_dispatch/$(DEPDIR)/$(am__dirstamp) m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-freebsd.$(OBJEXT): \ m_dispatch/$(am__dirstamp) \ m_dispatch/$(DEPDIR)/$(am__dirstamp) @@ -2837,6 +2890,9 @@ m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips64.$(O m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-nanomips.$(OBJEXT): \ m_gdbserver/$(am__dirstamp) \ m_gdbserver/$(DEPDIR)/$(am__dirstamp) +m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-loongarch64.$(OBJEXT): \ + m_gdbserver/$(am__dirstamp) \ + m_gdbserver/$(DEPDIR)/$(am__dirstamp) m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.$(OBJEXT): \ m_gdbserver/$(am__dirstamp) \ m_gdbserver/$(DEPDIR)/$(am__dirstamp) @@ -2940,6 +2996,9 @@ m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips64-linux.$( m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-nanomips-linux.$(OBJEXT): \ m_sigframe/$(am__dirstamp) \ m_sigframe/$(DEPDIR)/$(am__dirstamp) +m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-loongarch64-linux.$(OBJEXT): \ + m_sigframe/$(am__dirstamp) \ + m_sigframe/$(DEPDIR)/$(am__dirstamp) m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT): \ m_sigframe/$(am__dirstamp) \ m_sigframe/$(DEPDIR)/$(am__dirstamp) @@ -2977,6 +3036,8 @@ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips64-linux.$(OB m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-nanomips-linux.$(OBJEXT): \ m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) +m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-loongarch64-linux.$(OBJEXT): \ + m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-freebsd.$(OBJEXT): \ m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-freebsd.$(OBJEXT): \ @@ -3027,6 +3088,8 @@ m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips64-linux.$(OB m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-nanomips-linux.$(OBJEXT): \ m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) +m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-loongarch64-linux.$(OBJEXT): \ + m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.$(OBJEXT): \ m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.$(OBJEXT): \ @@ -3181,6 +3244,9 @@ m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips64-linux.$( m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-nanomips-linux.$(OBJEXT): \ m_dispatch/$(am__dirstamp) \ m_dispatch/$(DEPDIR)/$(am__dirstamp) +m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-loongarch64-linux.$(OBJEXT): \ + m_dispatch/$(am__dirstamp) \ + m_dispatch/$(DEPDIR)/$(am__dirstamp) m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-freebsd.$(OBJEXT): \ m_dispatch/$(am__dirstamp) \ m_dispatch/$(DEPDIR)/$(am__dirstamp) @@ -3250,6 +3316,9 @@ m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips64.$(O m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-nanomips.$(OBJEXT): \ m_gdbserver/$(am__dirstamp) \ m_gdbserver/$(DEPDIR)/$(am__dirstamp) +m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-loongarch64.$(OBJEXT): \ + m_gdbserver/$(am__dirstamp) \ + m_gdbserver/$(DEPDIR)/$(am__dirstamp) m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.$(OBJEXT): \ m_gdbserver/$(am__dirstamp) \ m_gdbserver/$(DEPDIR)/$(am__dirstamp) @@ -3323,6 +3392,9 @@ m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips64-linux.$( m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-nanomips-linux.$(OBJEXT): \ m_sigframe/$(am__dirstamp) \ m_sigframe/$(DEPDIR)/$(am__dirstamp) +m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-loongarch64-linux.$(OBJEXT): \ + m_sigframe/$(am__dirstamp) \ + m_sigframe/$(DEPDIR)/$(am__dirstamp) m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT): \ m_sigframe/$(am__dirstamp) \ m_sigframe/$(DEPDIR)/$(am__dirstamp) @@ -3354,6 +3426,8 @@ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips64-linux.$(OB m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-nanomips-linux.$(OBJEXT): \ m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) +m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-loongarch64-linux.$(OBJEXT): \ + m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-freebsd.$(OBJEXT): \ m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-freebsd.$(OBJEXT): \ @@ -3404,6 +3478,8 @@ m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips64-linux.$(OB m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-nanomips-linux.$(OBJEXT): \ m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) +m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.$(OBJEXT): \ + m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.$(OBJEXT): \ m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp) m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.$(OBJEXT): \ @@ -3681,6 +3757,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-solaris.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm64-linux.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-loongarch64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-nanomips-linux.Po@am__quote@ # am--include-marker @@ -3698,6 +3775,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-solaris.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm64-linux.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-loongarch64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-nanomips-linux.Po@am__quote@ # am--include-marker @@ -3719,6 +3797,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm64.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-loongarch64.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips64.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-nanomips.Po@am__quote@ # am--include-marker @@ -3737,6 +3816,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm64.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-loongarch64.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips64.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-nanomips.Po@am__quote@ # am--include-marker @@ -3791,6 +3871,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-common.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-loongarch64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-nanomips-linux.Po@am__quote@ # am--include-marker @@ -3807,6 +3888,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-common.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-loongarch64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-nanomips-linux.Po@am__quote@ # am--include-marker @@ -3823,6 +3905,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-solaris.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm64-linux.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-loongarch64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-nanomips-linux.Po@am__quote@ # am--include-marker @@ -3845,6 +3928,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips64-linux.Po@am__quote@ # am--include-marker @@ -3864,6 +3948,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-solaris.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm64-linux.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-loongarch64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-nanomips-linux.Po@am__quote@ # am--include-marker @@ -3886,6 +3971,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips64-linux.Po@am__quote@ # am--include-marker @@ -4112,6 +4198,20 @@ m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-nanomips-linux. @AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCCAS_FALSE@ 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$(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-nanomips-linux.obj `if test -f 'm_syswrap/syswrap-nanomips-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-nanomips-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-nanomips-linux.c'; fi` +m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.o: m_syswrap/syswrap-loongarch64-linux.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.o -MD -MP -MF m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Tpo -c -o m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.o `test -f 'm_syswrap/syswrap-loongarch64-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-loongarch64-linux.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Tpo m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='m_syswrap/syswrap-loongarch64-linux.c' object='m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.o `test -f 'm_syswrap/syswrap-loongarch64-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-loongarch64-linux.c + +m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.obj: m_syswrap/syswrap-loongarch64-linux.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.obj -MD -MP -MF m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Tpo -c -o m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.obj `if test -f 'm_syswrap/syswrap-loongarch64-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-loongarch64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-loongarch64-linux.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Tpo m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='m_syswrap/syswrap-loongarch64-linux.c' object='m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.obj `if test -f 'm_syswrap/syswrap-loongarch64-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-loongarch64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-loongarch64-linux.c'; fi` + m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o: m_syswrap/syswrap-x86-darwin.c @am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o -MD -MP -MF m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo -c -o m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o `test -f 'm_syswrap/syswrap-x86-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-x86-darwin.c @am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Po @@ -9786,6 +10012,7 @@ distclean: distclean-am -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-solaris.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm64-linux.Po + -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-loongarch64-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips64-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-nanomips-linux.Po @@ -9803,6 +10030,7 @@ distclean: distclean-am -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-solaris.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm64-linux.Po + -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-loongarch64-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips64-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-nanomips-linux.Po @@ -9824,6 +10052,7 @@ distclean: distclean-am -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm64.Po + -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-loongarch64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-nanomips.Po @@ -9842,6 +10071,7 @@ distclean: distclean-am -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm64.Po + -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-loongarch64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-nanomips.Po @@ -9896,6 +10126,7 @@ distclean: distclean-am -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-common.Po + -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-loongarch64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-nanomips-linux.Po @@ -9912,6 +10143,7 @@ distclean: distclean-am -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-common.Po + -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-loongarch64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-nanomips-linux.Po @@ -9928,6 +10160,7 @@ distclean: distclean-am -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-solaris.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm64-linux.Po + -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-loongarch64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-nanomips-linux.Po @@ -9950,6 +10183,7 @@ distclean: distclean-am -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Po + -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips64-linux.Po @@ -9969,6 +10203,7 @@ distclean: distclean-am -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-solaris.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm64-linux.Po + -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-loongarch64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-nanomips-linux.Po @@ -9991,6 +10226,7 @@ distclean: distclean-am -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Po + -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips64-linux.Po @@ -10223,6 +10459,7 @@ maintainer-clean: maintainer-clean-am -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-solaris.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm64-linux.Po + -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-loongarch64-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips64-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-nanomips-linux.Po @@ -10240,6 +10477,7 @@ maintainer-clean: maintainer-clean-am -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-solaris.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm64-linux.Po + -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-loongarch64-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips64-linux.Po -rm -f m_dispatch/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-nanomips-linux.Po @@ -10261,6 +10499,7 @@ maintainer-clean: maintainer-clean-am -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm64.Po + -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-loongarch64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-nanomips.Po @@ -10279,6 +10518,7 @@ maintainer-clean: maintainer-clean-am -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm64.Po + -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-loongarch64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips64.Po -rm -f m_gdbserver/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-nanomips.Po @@ -10333,6 +10573,7 @@ maintainer-clean: maintainer-clean-am -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-common.Po + -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-loongarch64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-nanomips-linux.Po @@ -10349,6 +10590,7 @@ maintainer-clean: maintainer-clean-am -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-common.Po + -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-loongarch64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips64-linux.Po -rm -f m_sigframe/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-nanomips-linux.Po @@ -10365,6 +10607,7 @@ maintainer-clean: maintainer-clean-am -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-solaris.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm64-linux.Po + -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-loongarch64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-nanomips-linux.Po @@ -10387,6 +10630,7 @@ maintainer-clean: maintainer-clean-am -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Po + -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips64-linux.Po @@ -10406,6 +10650,7 @@ maintainer-clean: maintainer-clean-am -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-solaris.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm64-linux.Po + -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-loongarch64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-nanomips-linux.Po @@ -10428,6 +10673,7 @@ maintainer-clean: maintainer-clean-am -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Po + -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-loongarch64-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Po -rm -f m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips64-linux.Po diff --git a/coregrind/launcher-linux.c b/coregrind/launcher-linux.c index bc95e3c..5307fd1 100644 --- a/coregrind/launcher-linux.c +++ b/coregrind/launcher-linux.c @@ -67,6 +67,10 @@ #define EM_NANOMIPS 249 #endif +#ifndef EM_LOONGARCH +#define EM_LOONGARCH 258 +#endif + #ifndef E_MIPS_ABI_O32 #define E_MIPS_ABI_O32 0x00001000 #endif @@ -314,6 +318,10 @@ static const char *select_platform(const char *clientname) (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV || header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) { platform = "ppc64le-linux"; + } else if (header.ehdr64.e_machine == EM_LOONGARCH && + (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV || + header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) { + platform = "loongarch64-linux"; } } else if (header.c[EI_DATA] == ELFDATA2MSB) { # if !defined(VGPV_arm_linux_android) \ @@ -415,7 +423,8 @@ int main(int argc, char** argv, char** envp) (0==strcmp(VG_PLATFORM,"s390x-linux")) || (0==strcmp(VG_PLATFORM,"mips32-linux")) || (0==strcmp(VG_PLATFORM,"mips64-linux")) || - (0==strcmp(VG_PLATFORM,"nanomips-linux"))) + (0==strcmp(VG_PLATFORM,"nanomips-linux")) || + (0==strcmp(VG_PLATFORM,"loongarch64-linux"))) default_platform = VG_PLATFORM; # elif defined(VGO_solaris) if ((0==strcmp(VG_PLATFORM,"x86-solaris")) || diff --git a/coregrind/m_aspacemgr/aspacemgr-common.c b/coregrind/m_aspacemgr/aspacemgr-common.c index 816d227..0e79d3f 100644 --- a/coregrind/m_aspacemgr/aspacemgr-common.c +++ b/coregrind/m_aspacemgr/aspacemgr-common.c @@ -157,7 +157,8 @@ SysRes VG_(am_do_mmap_NO_NOTIFY)( Addr start, SizeT length, UInt prot, # elif defined(VGP_amd64_linux) \ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \ - || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) + || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ + || defined(VGP_loongarch64_linux) res = VG_(do_syscall6)(__NR_mmap, (UWord)start, length, prot, flags, fd, offset); # elif defined(VGP_x86_darwin) @@ -262,7 +263,8 @@ SysRes ML_(am_do_relocate_nooverlap_mapping_NO_NOTIFY)( SysRes ML_(am_open) ( const HChar* pathname, Int flags, Int mode ) { -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) /* ARM64 wants to use __NR_openat rather than __NR_open. */ SysRes res = VG_(do_syscall4)(__NR_openat, VKI_AT_FDCWD, (UWord)pathname, flags, mode); @@ -291,7 +293,8 @@ void ML_(am_close) ( Int fd ) Int ML_(am_readlink)(const HChar* path, HChar* buf, UInt bufsiz) { SysRes res; -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, (UWord)path, (UWord)buf, bufsiz); # elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) diff --git a/coregrind/m_aspacemgr/aspacemgr-linux.c b/coregrind/m_aspacemgr/aspacemgr-linux.c index 232401e..a88412d 100644 --- a/coregrind/m_aspacemgr/aspacemgr-linux.c +++ b/coregrind/m_aspacemgr/aspacemgr-linux.c @@ -2777,7 +2777,8 @@ static SysRes VG_(am_mmap_file_float_valgrind_flags) ( SizeT length, UInt prot, req.rkind = MAny; req.start = 0; #if defined(VGA_arm) || defined(VGA_arm64) \ - || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) + || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) \ + || defined(VGA_loongarch64) aspacem_assert(VKI_SHMLBA >= VKI_PAGE_SIZE); #else aspacem_assert(VKI_SHMLBA == VKI_PAGE_SIZE); diff --git a/coregrind/m_cache.c b/coregrind/m_cache.c index 428a4df..38fa44e 100644 --- a/coregrind/m_cache.c +++ b/coregrind/m_cache.c @@ -660,6 +660,239 @@ get_cache_info(VexArchInfo *vai) return True; } +#elif defined(VGA_loongarch64) + +/* + * LoongArch method is straightforward, just extract appropriate bits via + * cpucfg instruction (__builtin_loongarch_cpucfg). + * + * 1. Get the properties of the cache from cpucfg16. + * 2. For each level of cache, get the properties from cpucfg17/18/19/20. + * + * It's a bit nasty since we have to get the total number of caches first. + * To avoid duplicating reads, I use "struct cache_status" to store some + * necessary information. + */ + +#define BIT(x) (1UL << (x)) +#define GENMASK(h, l) (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (64 - 1 - (h)))) + +#define LOONGARCH_CPUCFG16 0x10 +#define CPUCFG16_L1_IUPRE BIT(0) +#define CPUCFG16_L1_IUUNIFY BIT(1) +#define CPUCFG16_L1_DPRE BIT(2) +#define CPUCFG16_L2_IUPRE BIT(3) +#define CPUCFG16_L2_IUUNIFY BIT(4) +#define CPUCFG16_L2_DPRE BIT(7) +#define CPUCFG16_L3_IUPRE BIT(10) +#define CPUCFG16_L3_IUUNIFY BIT(11) +#define CPUCFG16_L3_DPRE BIT(14) + +#define LOONGARCH_CPUCFG17 0x11 +#define CPUCFG17_L1I_WAYS_M GENMASK(15, 0) +#define CPUCFG17_L1I_SETS_M GENMASK(23, 16) +#define CPUCFG17_L1I_SIZE_M GENMASK(30, 24) +#define CPUCFG17_L1I_WAYS 0 +#define CPUCFG17_L1I_SETS 16 +#define CPUCFG17_L1I_SIZE 24 + +#define LOONGARCH_CPUCFG18 0x12 +#define CPUCFG18_L1D_WAYS_M GENMASK(15, 0) +#define CPUCFG18_L1D_SETS_M GENMASK(23, 16) +#define CPUCFG18_L1D_SIZE_M GENMASK(30, 24) +#define CPUCFG18_L1D_WAYS 0 +#define CPUCFG18_L1D_SETS 16 +#define CPUCFG18_L1D_SIZE 24 + +#define LOONGARCH_CPUCFG19 0x13 +#define CPUCFG19_L2_WAYS_M GENMASK(15, 0) +#define CPUCFG19_L2_SETS_M GENMASK(23, 16) +#define CPUCFG19_L2_SIZE_M GENMASK(30, 24) +#define CPUCFG19_L2_WAYS 0 +#define CPUCFG19_L2_SETS 16 +#define CPUCFG19_L2_SIZE 24 + +#define LOONGARCH_CPUCFG20 0x14 +#define CPUCFG20_L3_WAYS_M GENMASK(15, 0) +#define CPUCFG20_L3_SETS_M GENMASK(23, 16) +#define CPUCFG20_L3_SIZE_M GENMASK(30, 24) +#define CPUCFG20_L3_WAYS 0 +#define CPUCFG20_L3_SETS 16 +#define CPUCFG20_L3_SIZE 24 + +struct cache_status { + Bool has_iu; + Bool is_u; + Bool has_d; + Bool exist; + UInt num; +}; + +static inline UInt +cpucfg(UInt reg) +{ + return (UInt)__builtin_loongarch_cpucfg(reg); +} + +static void +get_status(struct cache_status status[], UInt n) +{ + Bool has_iu = status[n].has_iu; + Bool is_u = status[n].is_u; + Bool has_d = status[n].has_d; + + /* has_d only works with no ucache */ + status[n].has_d = has_d = toBool(!(has_iu && is_u) && has_d); + + status[n].exist = toBool(has_iu || has_d); + status[n].num = has_iu + has_d; +} + +static void +get_cache(VexCacheInfo *ci, VexCacheKind kind, UInt level, + UInt line_size, UInt sets, UInt ways, UInt index) +{ + UInt assoc = ways; + UInt size = sets * ways * line_size; + ci->caches[index] = VEX_CACHE_INIT(kind, level, size, line_size, assoc); +} + +static void +get_cache_info_for_l1(VexCacheInfo *ci, struct cache_status status[]) +{ + UInt config; + UInt line_size, sets, ways; + UInt index = 0; + + if (!status[0].exist) + return; + + if (status[0].has_iu) { + config = cpucfg(LOONGARCH_CPUCFG17); + line_size = 1 << ((config & CPUCFG17_L1I_SIZE_M) >> CPUCFG17_L1I_SIZE); + sets = 1 << ((config & CPUCFG17_L1I_SETS_M) >> CPUCFG17_L1I_SETS); + ways = ((config & CPUCFG17_L1I_WAYS_M) >> CPUCFG17_L1I_WAYS) + 1; + get_cache(ci, status[0].is_u ? UNIFIED_CACHE : INSN_CACHE, + 1, line_size, sets, ways, index++); + } + + if (status[0].has_d) { + config = cpucfg(LOONGARCH_CPUCFG18); + line_size = 1 << ((config & CPUCFG18_L1D_SIZE_M) >> CPUCFG18_L1D_SIZE); + sets = 1 << ((config & CPUCFG18_L1D_SETS_M) >> CPUCFG18_L1D_SETS); + ways = ((config & CPUCFG18_L1D_WAYS_M) >> CPUCFG18_L1D_WAYS) + 1; + get_cache(ci, DATA_CACHE, 1, line_size, sets, ways, index++); + } + + /* Sanity check */ + vg_assert(index == status[0].num); +} + +static void +get_cache_info_for_l2(VexCacheInfo *ci, struct cache_status status[]) +{ + UInt config; + UInt line_size, sets, ways; + UInt index = status[0].num; + + if (!status[1].exist) + return; + + config = cpucfg(LOONGARCH_CPUCFG19); + line_size = 1 << ((config & CPUCFG19_L2_SIZE_M) >> CPUCFG19_L2_SIZE); + sets = 1 << ((config & CPUCFG19_L2_SETS_M) >> CPUCFG19_L2_SETS); + ways = ((config & CPUCFG19_L2_WAYS_M) >> CPUCFG19_L2_WAYS) + 1; + + if (status[1].has_iu) + get_cache(ci, status[1].is_u ? UNIFIED_CACHE : INSN_CACHE, + 2, line_size, sets, ways, index++); + + if (status[1].has_d) + get_cache(ci, DATA_CACHE, 2, line_size, sets, ways, index++); + + /* Sanity check */ + vg_assert(index == status[0].num + status[1].num); +} + +static void +get_cache_info_for_l3(VexCacheInfo *ci, struct cache_status status[]) +{ + UInt config; + UInt line_size, sets, ways; + UInt index = status[0].num + status[1].num; + + if (!status[2].exist) + return; + + config = cpucfg(LOONGARCH_CPUCFG20); + line_size = 1 << ((config & CPUCFG20_L3_SIZE_M) >> CPUCFG20_L3_SIZE); + sets = 1 << ((config & CPUCFG20_L3_SETS_M) >> CPUCFG20_L3_SETS); + ways = ((config & CPUCFG20_L3_WAYS_M) >> CPUCFG20_L3_WAYS) + 1; + + if (status[2].has_iu) + get_cache(ci, status[2].is_u ? UNIFIED_CACHE : INSN_CACHE, + 3, line_size, sets, ways, index++); + + if (status[2].has_d) + get_cache(ci, DATA_CACHE, 3, line_size, sets, ways, index++); + + /* Sanity check */ + vg_assert(index == status[0].num + status[1].num + status[2].num); +} + +static Bool +get_cache_info_from_cpucfg(VexCacheInfo *ci) +{ + Int i; + struct cache_status status[3]; + UInt config = cpucfg(LOONGARCH_CPUCFG16); + + /* NB: Bool is unsigned char! */ + /* For l1 */ + status[0].has_iu = toBool(config & CPUCFG16_L1_IUPRE); + status[0].is_u = toBool(config & CPUCFG16_L1_IUUNIFY); + status[0].has_d = toBool(config & CPUCFG16_L1_DPRE); + get_status(status, 0); + + /* For l2 */ + status[1].has_iu = toBool(config & CPUCFG16_L2_IUPRE); + status[1].is_u = toBool(config & CPUCFG16_L2_IUUNIFY); + status[1].has_d = toBool(config & CPUCFG16_L2_DPRE); + get_status(status, 1); + + /* For l3 */ + status[2].has_iu = toBool(config & CPUCFG16_L3_IUPRE); + status[2].is_u = toBool(config & CPUCFG16_L3_IUUNIFY); + status[2].has_d = toBool(config & CPUCFG16_L3_DPRE); + get_status(status, 2); + + ci->num_levels = 0; + ci->num_caches = 0; + for (i = 0; i < 3; i++) { + ci->num_levels += status[i].exist; + ci->num_caches += status[i].num; + } + + if (ci->num_caches == 0) { + VG_(debugLog)(1, "cache", "Autodetect failed\n"); + return False; + } + + ci->caches = VG_(malloc)("m_cache", ci->num_caches * sizeof(VexCache)); + get_cache_info_for_l1(ci, status); + get_cache_info_for_l2(ci, status); + get_cache_info_for_l3(ci, status); + return True; +} + +static Bool +get_cache_info(VexArchInfo *vai) +{ + VexCacheInfo *ci = &vai->hwcache_info; + ci->icaches_maintain_coherence = True; + return get_cache_info_from_cpucfg(ci); +} + #else #error "Unknown arch" diff --git a/coregrind/m_coredump/coredump-elf.c b/coregrind/m_coredump/coredump-elf.c index 4a8c29c..82b1b43 100644 --- a/coregrind/m_coredump/coredump-elf.c +++ b/coregrind/m_coredump/coredump-elf.c @@ -489,6 +489,40 @@ static void fill_prstatus(const ThreadState *tst, regs[VKI_MIPS32_EF_CP0_STATUS] = arch->vex.guest_CP0_status; regs[VKI_MIPS32_EF_CP0_EPC] = arch->vex.guest_PC; # undef DO +#elif defined(VGP_loongarch64_linux) + regs->regs[0] = arch->vex.guest_R0; + regs->regs[1] = arch->vex.guest_R1; + regs->regs[2] = arch->vex.guest_R2; + regs->regs[3] = arch->vex.guest_R3; + regs->regs[4] = arch->vex.guest_R4; + regs->regs[5] = arch->vex.guest_R5; + regs->regs[6] = arch->vex.guest_R6; + regs->regs[7] = arch->vex.guest_R7; + regs->regs[8] = arch->vex.guest_R8; + regs->regs[9] = arch->vex.guest_R9; + regs->regs[10] = arch->vex.guest_R10; + regs->regs[11] = arch->vex.guest_R11; + regs->regs[12] = arch->vex.guest_R12; + regs->regs[13] = arch->vex.guest_R13; + regs->regs[14] = arch->vex.guest_R14; + regs->regs[15] = arch->vex.guest_R15; + regs->regs[16] = arch->vex.guest_R16; + regs->regs[17] = arch->vex.guest_R17; + regs->regs[18] = arch->vex.guest_R18; + regs->regs[19] = arch->vex.guest_R19; + regs->regs[20] = arch->vex.guest_R20; + regs->regs[21] = arch->vex.guest_R21; + regs->regs[22] = arch->vex.guest_R22; + regs->regs[23] = arch->vex.guest_R23; + regs->regs[24] = arch->vex.guest_R24; + regs->regs[25] = arch->vex.guest_R25; + regs->regs[26] = arch->vex.guest_R26; + regs->regs[27] = arch->vex.guest_R27; + regs->regs[28] = arch->vex.guest_R28; + regs->regs[29] = arch->vex.guest_R29; + regs->regs[30] = arch->vex.guest_R30; + regs->regs[31] = arch->vex.guest_R31; + regs->csr_era = arch->vex.guest_PC; #elif defined(VGP_amd64_freebsd) regs->rflags = LibVEX_GuestAMD64_get_rflags( &arch->vex ); regs->rsp = arch->vex.guest_RSP; @@ -654,6 +688,14 @@ static void fill_fpu(const ThreadState *tst, vki_elf_fpregset_t *fpu) # undef DO #elif defined(VGP_nanomips_linux) +#elif defined(VGP_loongarch64_linux) +# define DO(n) (*fpu)[n] = *(const double*)(&arch->vex.guest_X##n) + DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); + DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15); + DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23); + DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31); +# undef DO + #elif defined(VGP_x86_freebsd) #elif defined(VGP_amd64_freebsd) diff --git a/coregrind/m_debuginfo/d3basics.c b/coregrind/m_debuginfo/d3basics.c index bcfd456..222496e 100644 --- a/coregrind/m_debuginfo/d3basics.c +++ b/coregrind/m_debuginfo/d3basics.c @@ -555,6 +555,9 @@ static Bool get_Dwarf_Reg( /*OUT*/Addr* a, Word regno, const RegSummary* regs ) # elif defined(VGP_arm64_linux) if (regno == 31) { *a = regs->sp; return True; } if (regno == 29) { *a = regs->fp; return True; } +# elif defined(VGP_loongarch64_linux) + if (regno == 3) { *a = regs->sp; return True; } + if (regno == 22) { *a = regs->fp; return True; } # else # error "Unknown platform" # endif diff --git a/coregrind/m_debuginfo/debuginfo.c b/coregrind/m_debuginfo/debuginfo.c index eed134b..32ac008 100644 --- a/coregrind/m_debuginfo/debuginfo.c +++ b/coregrind/m_debuginfo/debuginfo.c @@ -1300,7 +1300,7 @@ ULong VG_(di_notify_mmap)( Addr a, Bool allow_SkFileV, Int use_fd ) is_ro_map = False; # if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_mips32) \ - || defined(VGA_mips64) || defined(VGA_nanomips) + || defined(VGA_mips64) || defined(VGA_nanomips) || defined(VGA_loongarch64) is_rx_map = seg->hasR && seg->hasX; is_rw_map = seg->hasR && seg->hasW; # elif defined(VGA_amd64) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ @@ -3116,6 +3116,11 @@ UWord evalCfiExpr ( const XArray* exprs, Int ix, case Creg_ARM64_SP: return eec->uregs->sp; case Creg_ARM64_X30: return eec->uregs->x30; case Creg_ARM64_X29: return eec->uregs->x29; +# elif defined(VGA_loongarch64) + case Creg_LOONGARCH64_PC: return eec->uregs->pc; + case Creg_LOONGARCH64_RA: return eec->uregs->ra; + case Creg_LOONGARCH64_SP: return eec->uregs->sp; + case Creg_LOONGARCH64_FP: return eec->uregs->fp; # else # error "Unsupported arch" # endif @@ -3389,6 +3394,13 @@ static Addr compute_cfa ( const D3UnwindRegs* uregs, case CFIC_ARM64_X29REL: cfa = cfsi_m->cfa_off + uregs->x29; break; +# elif defined(VGA_loongarch64) + case CFIC_IA_SPREL: + cfa = cfsi_m->cfa_off + uregs->sp; + break; + case CFIC_IA_BPREL: + cfa = cfsi_m->cfa_off + uregs->fp; + break; # else # error "Unsupported arch" # endif @@ -3460,6 +3472,14 @@ Addr ML_(get_CFA) ( Addr ip, Addr sp, Addr fp, return compute_cfa(&uregs, min_accessible, max_accessible, ce->di, ce->cfsi_m); } +#elif defined(VGA_loongarch64) + { D3UnwindRegs uregs; + uregs.pc = ip; + uregs.sp = sp; + uregs.fp = fp; + return compute_cfa(&uregs, + min_accessible, max_accessible, ce->di, ce->cfsi_m); + } # else return 0; /* indicates failure */ @@ -3511,6 +3531,8 @@ void VG_(ppUnwindInfo) (Addr from, Addr to) For arm64, the unwound registers are: X29(FP) X30(LR) SP PC. For s390, the unwound registers are: R11(FP) R14(LR) R15(SP) F0..F7 PC. + + For loongarch64, the unwound registers are: FP SP PC */ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregsHere, Addr min_accessible, @@ -3534,6 +3556,8 @@ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregsHere, # elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) # elif defined(VGP_arm64_linux) ipHere = uregsHere->pc; +# elif defined(VGA_loongarch64) + ipHere = uregsHere->pc; # else # error "Unknown arch" # endif @@ -3679,6 +3703,10 @@ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregsHere, COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off); COMPUTE(uregsPrev.x30, uregsHere->x30, cfsi_m->x30_how, cfsi_m->x30_off); COMPUTE(uregsPrev.x29, uregsHere->x29, cfsi_m->x29_how, cfsi_m->x29_off); +# elif defined(VGA_loongarch64) + COMPUTE(uregsPrev.pc, uregsHere->ra, cfsi_m->ra_how, cfsi_m->ra_off); + COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off); + COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi_m->fp_how, cfsi_m->fp_off); # else # error "Unknown arch" # endif diff --git a/coregrind/m_debuginfo/priv_storage.h b/coregrind/m_debuginfo/priv_storage.h index 441b379..41224a8 100644 --- a/coregrind/m_debuginfo/priv_storage.h +++ b/coregrind/m_debuginfo/priv_storage.h @@ -367,6 +367,19 @@ typedef Int fp_off; } DiCfSI_m; +#elif defined(VGA_loongarch64) +typedef + struct { + UChar cfa_how; /* a CFIC_ value */ + UChar ra_how; /* a CFIR_ value */ + UChar sp_how; /* a CFIR_ value */ + UChar fp_how; /* a CFIR_ value */ + Int cfa_off; + Int ra_off; + Int sp_off; + Int fp_off; + } + DiCfSI_m; #else # error "Unknown arch" #endif @@ -422,7 +435,11 @@ typedef Creg_S390_SP, Creg_S390_FP, Creg_S390_LR, - Creg_MIPS_RA + Creg_MIPS_RA, + Creg_LOONGARCH64_PC, + Creg_LOONGARCH64_RA, + Creg_LOONGARCH64_SP, + Creg_LOONGARCH64_FP } CfiReg; diff --git a/coregrind/m_debuginfo/readdwarf.c b/coregrind/m_debuginfo/readdwarf.c index 7b8187e..13363ae 100644 --- a/coregrind/m_debuginfo/readdwarf.c +++ b/coregrind/m_debuginfo/readdwarf.c @@ -2066,6 +2066,10 @@ void ML_(read_debuginfo_dwarf1) ( # define FP_REG 30 # define SP_REG 29 # define RA_REG_DEFAULT 31 +#elif defined(VGP_loongarch64_linux) +# define FP_REG 22 +# define SP_REG 3 +# define RA_REG_DEFAULT 1 #else # error "Unknown platform" #endif @@ -2084,6 +2088,8 @@ void ML_(read_debuginfo_dwarf1) ( # define N_CFI_REGS 128 #elif defined(VGP_s390x_linux) # define N_CFI_REGS 66 +#elif defined(VGP_loongarch64_linux) +# define N_CFI_REGS 32 #else # define N_CFI_REGS 20 #endif @@ -2310,6 +2316,10 @@ static void initUnwindContext ( /*OUT*/UnwindContext* ctx ) start out as RR_Same. */ ctx->state[j].reg[29/*FP*/].tag = RR_Same; ctx->state[j].reg[30/*LR*/].tag = RR_Same; +# elif defined(VGA_loongarch64) + /* Registers fp and ra start out implicitly as RR_Same. */ + ctx->state[j].reg[FP_REG].tag = RR_Same; + ctx->state[j].reg[RA_REG_DEFAULT].tag = RR_Same; # endif } } @@ -2392,7 +2402,8 @@ static Bool summarise_context(/*OUT*/Addr* base, if (ctxs->cfa_is_regoff && ctxs->cfa_reg == SP_REG) { si_m->cfa_off = ctxs->cfa_off; # if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) \ - || defined(VGA_mips32) || defined(VGA_nanomips) || defined(VGA_mips64) + || defined(VGA_mips32) || defined(VGA_nanomips) || defined(VGA_mips64) \ + || defined(VGA_loongarch64) si_m->cfa_how = CFIC_IA_SPREL; # elif defined(VGA_arm) si_m->cfa_how = CFIC_ARM_R13REL; @@ -2406,7 +2417,8 @@ static Bool summarise_context(/*OUT*/Addr* base, if (ctxs->cfa_is_regoff && ctxs->cfa_reg == FP_REG) { si_m->cfa_off = ctxs->cfa_off; # if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) \ - || defined(VGA_mips32) || defined(VGA_nanomips) || defined(VGA_mips64) + || defined(VGA_mips32) || defined(VGA_nanomips) || defined(VGA_mips64) \ + || defined(VGA_loongarch64) si_m->cfa_how = CFIC_IA_BPREL; # elif defined(VGA_arm) si_m->cfa_how = CFIC_ARM_R12REL; @@ -2786,6 +2798,30 @@ static Bool summarise_context(/*OUT*/Addr* base, # elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) /* These don't use CFI based unwinding (is that really true?) */ +# elif defined(VGA_loongarch64) + + /* --- entire tail of this fn specialised for loongarch64 --- */ + + SUMMARISE_HOW(si_m->ra_how, si_m->ra_off, ctxs->reg[ctx->ra_reg]); + SUMMARISE_HOW(si_m->fp_how, si_m->fp_off, ctxs->reg[FP_REG]); + + /* on loongarch64, it seems the old sp value before the call is always + the same as the CFA. Therefore ... */ + si_m->sp_how = CFIR_CFAREL; + si_m->sp_off = 0; + + /* bogus looking range? Note, we require that the difference is + representable in 32 bits. */ + if (loc_start >= ctx->loc) + { why = 4; goto failed; } + if (ctx->loc - loc_start > 10000000 /* let's say */) + { why = 5; goto failed; } + + *base = loc_start + ctx->initloc; + *len = (UInt)(ctx->loc - loc_start); + + return True; + # else # error "Unknown arch" # endif @@ -2885,6 +2921,13 @@ static Int copy_convert_CfiExpr_tree ( XArray* dstxa, return ML_(CfiExpr_CfiReg)( dstxa, Creg_ARM64_X30 ); # elif defined(VGA_ppc32) || defined(VGA_ppc64be) \ || defined(VGA_ppc64le) +# elif defined(VGA_loongarch64) + if (dwreg == SP_REG) + return ML_(CfiExpr_CfiReg)( dstxa, Creg_LOONGARCH64_SP ); + if (dwreg == FP_REG) + return ML_(CfiExpr_CfiReg)( dstxa, Creg_LOONGARCH64_FP ); + if (dwreg == srcuc->ra_reg) + return ML_(CfiExpr_CfiReg)( dstxa, Creg_LOONGARCH64_RA ); # else # error "Unknown arch" # endif diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c index fb64ed9..5e77c79 100644 --- a/coregrind/m_debuginfo/readelf.c +++ b/coregrind/m_debuginfo/readelf.c @@ -1781,7 +1781,8 @@ static HChar* readlink_path (const HChar *path) while (tries > 0) { SysRes res; -#if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +#if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, (UWord)path, (UWord)buf, bufsiz); #elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) @@ -2702,8 +2703,9 @@ Bool ML_(read_elf_object) ( struct _DebugInfo* di ) || defined(VGP_arm_linux) || defined (VGP_s390x_linux) \ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) \ || defined(VGP_x86_solaris) || defined(VGP_amd64_solaris) \ - || defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) + || defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) \ /* Accept .plt where mapped as rx (code) */ if (0 == VG_(strcmp)(name, ".plt")) { if (inrx && !di->plt_present) { diff --git a/coregrind/m_debuginfo/storage.c b/coregrind/m_debuginfo/storage.c index 961d767..fbfe027 100644 --- a/coregrind/m_debuginfo/storage.c +++ b/coregrind/m_debuginfo/storage.c @@ -260,6 +260,11 @@ void ML_(ppDiCfSI) ( const XArray* /* of CfiExpr */ exprs, SHOW_HOW(si_m->x30_how, si_m->x30_off); VG_(printf)(" X29="); SHOW_HOW(si_m->x29_how, si_m->x29_off); +# elif defined(VGP_loongarch64_linux) + VG_(printf)(" SP="); + SHOW_HOW(si_m->sp_how, si_m->sp_off); + VG_(printf)(" FP="); + SHOW_HOW(si_m->fp_how, si_m->fp_off); # else # error "Unknown arch" # endif @@ -1010,6 +1015,10 @@ static void ppCfiReg ( CfiReg reg ) case Creg_S390_SP: VG_(printf)("SP"); break; case Creg_S390_FP: VG_(printf)("FP"); break; case Creg_S390_LR: VG_(printf)("LR"); break; + case Creg_LOONGARCH64_PC: VG_(printf)("PC"); break; + case Creg_LOONGARCH64_RA: VG_(printf)("RA"); break; + case Creg_LOONGARCH64_SP: VG_(printf)("SP"); break; + case Creg_LOONGARCH64_FP: VG_(printf)("FP"); break; default: vg_assert(0); } } diff --git a/coregrind/m_debuglog.c b/coregrind/m_debuglog.c index fd6db4b..eacc73b 100644 --- a/coregrind/m_debuglog.c +++ b/coregrind/m_debuglog.c @@ -601,6 +601,41 @@ static UInt local_sys_getpid ( void ) return a0; } +#elif defined(VGP_loongarch64_linux) + +static UInt local_sys_write_stderr ( const HChar* buf, Int n ) +{ + ULong ret; + __asm__ volatile ( + "li.w $a0, 2 \n\t" // stderr + "move $a1, %1 \n\t" + "move $a2, %2 \n\t" + "li.w $a7, " VG_STRINGIFY(__NR_write) " \n\t" + "syscall 0 \n\t" + "move %0, $a0 \n\t" + : "=r" (ret) + : "r" (buf), "r" (n) + : "memory", "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", + "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8" + ); + return ret >= 0 ? (UInt)ret : -1; +} + +static UInt local_sys_getpid ( void ) +{ + ULong ret; + __asm__ volatile ( + "li.w $a7, " VG_STRINGIFY(__NR_getpid) " \n\t" + "syscall 0 \n\t" + "move %0, $a0 \n\t" + : "=r" (ret) + : + : "memory", "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", + "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8" + ); + return (UInt)ret; +} + #elif defined(VGP_x86_solaris) static UInt local_sys_write_stderr ( const HChar* buf, Int n ) { diff --git a/coregrind/m_dispatch/dispatch-loongarch64-linux.S b/coregrind/m_dispatch/dispatch-loongarch64-linux.S new file mode 100644 index 0000000..dec1652 --- /dev/null +++ b/coregrind/m_dispatch/dispatch-loongarch64-linux.S @@ -0,0 +1,314 @@ + +/*--------------------------------------------------------------------*/ +/*--- The core dispatch loop, for jumping to a code address. ---*/ +/*--- dispatch-loongarch64-linux.S ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#include "pub_core_basics_asm.h" + +#if defined(VGP_loongarch64_linux) + +#include "pub_core_dispatch_asm.h" +#include "pub_core_transtab_asm.h" +#include "libvex_guest_offsets.h" /* for OFFSET_loongarch64_* */ + + +/*------------------------------------------------------------*/ +/*--- ---*/ +/*--- The dispatch loop. VG_(disp_run_translations) is ---*/ +/*--- used to run all translations, ---*/ +/*--- including no-redir ones. ---*/ +/*--- ---*/ +/*------------------------------------------------------------*/ + +/*----------------------------------------------------*/ +/*--- Entry and preamble (set everything up) ---*/ +/*----------------------------------------------------*/ + +/* signature: +void VG_(disp_run_translations)( UWord* two_words, + void* guest_state, + Addr host_addr ); +*/ + +.text +.globl VG_(disp_run_translations) +VG_(disp_run_translations): + /* a0 holds two_words */ + /* a1 holds guest_state */ + /* a2 holds host_addr */ + + /* New stack frame. Stack must remain 16 aligned (at least) */ + addi.d $sp, $sp, -96 + + /* Save ra */ + st.d $ra, $sp, 0 + + /* .. and s0 - s8 */ + st.d $s0, $sp, 8 + st.d $s1, $sp, 16 + st.d $s2, $sp, 24 + st.d $s3, $sp, 32 + st.d $s4, $sp, 40 + st.d $s5, $sp, 48 + st.d $s6, $sp, 56 + st.d $s7, $sp, 64 + st.d $s8, $sp, 72 + + /* ... and fp */ + st.d $fp, $sp, 80 + + /* and a0. In postamble it will be restored such that the + return values can be written */ + st.d $a0, $sp, 88 + + /* Load address of guest state into s8 */ + move $s8, $a1 + + /* and jump into the code cache. Chained translations in + the code cache run, until for whatever reason, they can't + continue. When that happens, the translation in question + will jump (or call) to one of the continuation points + VG_(cp_...) below. */ + ibar 0 /* Insn sync barrier */ + jr $a2 + /*NOTREACHED*/ + +/*----------------------------------------------------*/ +/*--- Postamble and exit. ---*/ +/*----------------------------------------------------*/ + +postamble: + /* At this point, a0 and a1 contain two + words to be returned to the caller. a0 + holds a TRC value, and a1 optionally may + hold another word (for CHAIN_ME exits, the + address of the place to patch.) */ + + /* Restore a0 from stack to t0; holds address of two_words */ + ld.d $t0, $sp, 88 + st.d $a0, $t0, 0 /* Store a0 to two_words[0] */ + st.d $a1, $t0, 8 /* Store a1 to two_words[1] */ + + /* Restore ra */ + ld.d $ra, $sp, 0 + + /* ... and s0 - s8 */ + ld.d $s0, $sp, 8 + ld.d $s1, $sp, 16 + ld.d $s2, $sp, 24 + ld.d $s3, $sp, 32 + ld.d $s4, $sp, 40 + ld.d $s5, $sp, 48 + ld.d $s6, $sp, 56 + ld.d $s7, $sp, 64 + ld.d $s8, $sp, 72 + + /* ... and fp */ + ld.d $fp, $sp, 80 + + addi.d $sp, $sp, 96 /* Restore sp */ + jr $ra + /*NOTREACHED*/ + +/*----------------------------------------------------*/ +/*--- Continuation points ---*/ +/*----------------------------------------------------*/ + +/* ------ Chain me to slow entry point ------ */ +.globl VG_(disp_cp_chain_me_to_slowEP) +VG_(disp_cp_chain_me_to_slowEP): + /* We got called. The return address indicates + where the patching needs to happen. Collect + the return address and, exit back to C land, + handing the caller the pair (Chain_me_S, RA) */ + li.w $a0, VG_TRC_CHAIN_ME_TO_SLOW_EP + move $a1, $ra + /* 4 * 4 = mkLoadImm_EXACTLY4 + 4 = jirl $ra, $t0, 0 */ + addi.d $a1, $a1, -20 + b postamble + /*NOTREACHED*/ + +/* ------ Chain me to fast entry point ------ */ +.globl VG_(disp_cp_chain_me_to_fastEP) +VG_(disp_cp_chain_me_to_fastEP): + /* We got called. The return address indicates + where the patching needs to happen. Collect + the return address and, exit back to C land, + handing the caller the pair (Chain_me_S, RA) */ + li.w $a0, VG_TRC_CHAIN_ME_TO_FAST_EP + move $a1, $ra + /* 4 * 4 = mkLoadImm_EXACTLY4 + 4 = jirl $ra, $t0, 0 */ + addi.d $a1, $a1, -20 + b postamble + /*NOTREACHED*/ + +/* ------ Indirect but boring jump ------ */ +.globl VG_(disp_cp_xindir) +VG_(disp_cp_xindir): + /* Where are we going? */ + ld.d $t0, $s8, OFFSET_loongarch64_PC + + /* Stats only */ + la.local $t4, VG_(stats__n_xIndirs_32) + ld.d $t1, $t4, 0 + addi.d $t1, $t1, 1 + st.w $t1, $t4, 0 + + /* LIVE: s8 (guest state ptr), t0 (guest address to go to). + We use 6 temporaries: + t6 (to point at the relevant FastCacheSet), + t1, t2, t3 (scratch, for swapping entries within a set) + t4, t5 (other scratch) + */ + + /* Try a fast lookup in the translation cache. This is pretty much + a handcoded version of VG_(lookupInFastCache). */ + + // Compute t6 = VG_TT_FAST_HASH(guest) + srli.d $t6, $t0, 2 // g2 = guest >> 2 + srli.d $t5, $t0, (VG_TT_FAST_BITS + 2) // (g2 >> VG_TT_FAST_BITS) + xor $t6, $t6, $t5 // (g2 >> VG_TT_FAST_BITS) ^ g2 + li.w $t5, VG_TT_FAST_MASK + and $t6, $t6, $t5 // setNo + + // Compute t6 = &VG_(tt_fast)[t6] + la.local $t5, VG_(tt_fast) + slli.d $t6, $t6, VG_FAST_CACHE_SET_BITS + add.d $t6, $t6, $t5 + + /* LIVE: s8 (guest state ptr), t0 (guest addr), t6 (cache set) */ +0: // try way 0 + ld.d $t4, $t6, FCS_g0 // .guest0 + ld.d $t5, $t6, FCS_h0 // .host0 + bne $t4, $t0, 1f // cmp against .guest0 + // hit at way 0 + // goto .host0 + jr $t5 + /*NOTREACHED*/ + +1: // try way 1 + ld.d $t4, $t6, FCS_g1 + bne $t4, $t0, 2f // cmp against .guest1 + // hit at way 1; swap upwards + ld.d $t1, $t6, FCS_g0 // $t1 = old .guest0 + ld.d $t2, $t6, FCS_h0 // $t2 = old .host0 + ld.d $t3, $t6, FCS_h1 // $t3 = old .host1 + st.d $t0, $t6, FCS_g0 // new .guest0 = guest + st.d $t3, $t6, FCS_h0 // new .host0 = old .host1 + st.d $t1, $t6, FCS_g1 // new .guest1 = old .guest0 + st.d $t2, $t6, FCS_h1 // new .host1 = old .host0 + + // stats only + la.local $t4, VG_(stats__n_xIndir_hits1_32) + ld.d $t5, $t4, 0 + addi.d $t5, $t5, 1 + st.w $t5, $t4, 0 + // goto old .host1 a.k.a. new .host0 + jr $t3 + /*NOTREACHED*/ + +2: // try way 2 + ld.d $t4, $t6, FCS_g2 + bne $t4, $t0, 3f // cmp against .guest2 + // hit at way 2; swap upwards + ld.d $t1, $t6, FCS_g1 + ld.d $t2, $t6, FCS_h1 + ld.d $t3, $t6, FCS_h2 + st.d $t0, $t6, FCS_g1 + st.d $t3, $t6, FCS_h1 + st.d $t1, $t6, FCS_g2 + st.d $t2, $t6, FCS_h2 + + // stats only + la.local $t4, VG_(stats__n_xIndir_hits2_32) + ld.d $t5, $t4, 0 + addi.d $t5, $t5, 1 + st.w $t5, $t4, 0 + // goto old .host2 a.k.a. new .host1 + jr $t3 + /*NOTREACHED*/ + +3: // try way 3 + ld.d $t4, $t6, FCS_g3 + bne $t4, $t0, 4f // cmp against .guest3 + // hit at way 3; swap upwards + ld.d $t1, $t6, FCS_g2 + ld.d $t2, $t6, FCS_h2 + ld.d $t3, $t6, FCS_h3 + st.d $t0, $t6, FCS_g2 + st.d $t3, $t6, FCS_h2 + st.d $t1, $t6, FCS_g3 + st.d $t2, $t6, FCS_h3 + + // stats only + la.local $t4, VG_(stats__n_xIndir_hits3_32) + ld.d $t5, $t4, 0 + addi.d $t5, $t5, 1 + st.w $t5, $t4, 0 + // goto old .host3 a.k.a. new .host2 + jr $t3 + /*NOTREACHED*/ + +4: // fast lookup failed: + /* stats only */ + la.local $t4, VG_(stats__n_xIndir_misses_32) + ld.d $t5, $t4, 0 + addi.d $t5, $t5, 1 + st.w $t5, $t4, 0 + + li.w $a0, VG_TRC_INNER_FASTMISS + move $a1, $zero + b postamble + /*NOTREACHED*/ + +/* ------ Assisted jump ------ */ +.globl VG_(disp_cp_xassisted) +VG_(disp_cp_xassisted): + /* guest-state-pointer contains the TRC. Put the value into the + return register */ + move $a0, $s8 + move $a1, $zero + b postamble + +/* ------ Event check failed ------ */ +.globl VG_(disp_cp_evcheck_fail) +VG_(disp_cp_evcheck_fail): + li.w $a0, VG_TRC_INNER_COUNTERZERO + move $a1, $zero + b postamble + +.size VG_(disp_run_translations), .-VG_(disp_run_translations) + +#endif // defined(VGP_loongarch64_linux) + +/* Let the linker know we don't need an executable stack */ +MARK_STACK_NO_EXEC + +/*--------------------------------------------------------------------*/ +/*--- end dispatch-loongarch64-linux.S ---*/ +/*--------------------------------------------------------------------*/ diff --git a/coregrind/m_gdbserver/loongarch-base64-valgrind-s1.xml b/coregrind/m_gdbserver/loongarch-base64-valgrind-s1.xml new file mode 100644 index 0000000..cab700c --- /dev/null +++ b/coregrind/m_gdbserver/loongarch-base64-valgrind-s1.xml @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/coregrind/m_gdbserver/loongarch-base64-valgrind-s2.xml b/coregrind/m_gdbserver/loongarch-base64-valgrind-s2.xml new file mode 100644 index 0000000..cbacbbb --- /dev/null +++ b/coregrind/m_gdbserver/loongarch-base64-valgrind-s2.xml @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/coregrind/m_gdbserver/loongarch-base64.xml b/coregrind/m_gdbserver/loongarch-base64.xml new file mode 100644 index 0000000..fadca8b --- /dev/null +++ b/coregrind/m_gdbserver/loongarch-base64.xml @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/coregrind/m_gdbserver/loongarch-fpu64-valgrind-s1.xml b/coregrind/m_gdbserver/loongarch-fpu64-valgrind-s1.xml new file mode 100644 index 0000000..b5c7cab --- /dev/null +++ b/coregrind/m_gdbserver/loongarch-fpu64-valgrind-s1.xml @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/coregrind/m_gdbserver/loongarch-fpu64-valgrind-s2.xml b/coregrind/m_gdbserver/loongarch-fpu64-valgrind-s2.xml new file mode 100644 index 0000000..501660e --- /dev/null +++ b/coregrind/m_gdbserver/loongarch-fpu64-valgrind-s2.xml @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/coregrind/m_gdbserver/loongarch-fpu64.xml b/coregrind/m_gdbserver/loongarch-fpu64.xml new file mode 100644 index 0000000..74ab55a --- /dev/null +++ b/coregrind/m_gdbserver/loongarch-fpu64.xml @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/coregrind/m_gdbserver/loongarch64-linux-valgrind.xml b/coregrind/m_gdbserver/loongarch64-linux-valgrind.xml new file mode 100644 index 0000000..8915a72 --- /dev/null +++ b/coregrind/m_gdbserver/loongarch64-linux-valgrind.xml @@ -0,0 +1,18 @@ + + + + + + loongarch + GNU/Linux + + + + + + + diff --git a/coregrind/m_gdbserver/loongarch64-linux.xml b/coregrind/m_gdbserver/loongarch64-linux.xml new file mode 100644 index 0000000..f1eed83 --- /dev/null +++ b/coregrind/m_gdbserver/loongarch64-linux.xml @@ -0,0 +1,14 @@ + + + + + + loongarch + GNU/Linux + + + diff --git a/coregrind/m_gdbserver/target.c b/coregrind/m_gdbserver/target.c index f9f32f4..e97bd64 100644 --- a/coregrind/m_gdbserver/target.c +++ b/coregrind/m_gdbserver/target.c @@ -867,6 +867,8 @@ void valgrind_initialize_target(void) mips64_init_architecture(&the_low_target); #elif defined(VGA_nanomips) nanomips_init_architecture(&the_low_target); +#elif defined(VGA_loongarch64) + loongarch64_init_architecture(&the_low_target); #else #error "architecture missing in target.c valgrind_initialize_target" #endif diff --git a/coregrind/m_gdbserver/valgrind-low-loongarch64.c b/coregrind/m_gdbserver/valgrind-low-loongarch64.c new file mode 100644 index 0000000..6021c79 --- /dev/null +++ b/coregrind/m_gdbserver/valgrind-low-loongarch64.c @@ -0,0 +1,272 @@ +/* Low level interface to valgrind, for the remote server for GDB integrated + in valgrind. + Copyright (C) 2021 + Free Software Foundation, Inc. + + This file is part of VALGRIND. + It has been inspired from files from gdbserver in gdb 13. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#include "server.h" +#include "target.h" +#include "regdef.h" +#include "regcache.h" + +#include "pub_core_machine.h" +#include "pub_core_debuginfo.h" +#include "pub_core_threadstate.h" +#include "pub_core_transtab.h" +#include "pub_core_gdbserver.h" + +#include "valgrind_low.h" + +#include "libvex_guest_loongarch64.h" + +static struct reg regs[] = { + { "r0", 0, 64 }, + { "r1", 64, 64 }, + { "r2", 128, 64 }, + { "r3", 192, 64 }, + { "r4", 256, 64 }, + { "r5", 320, 64 }, + { "r6", 384, 64 }, + { "r7", 448, 64 }, + { "r8", 512, 64 }, + { "r9", 576, 64 }, + { "r10", 640, 64 }, + { "r11", 704, 64 }, + { "r12", 768, 64 }, + { "r13", 832, 64 }, + { "r14", 896, 64 }, + { "r15", 960, 64 }, + { "r16", 1024, 64 }, + { "r17", 1088, 64 }, + { "r18", 1152, 64 }, + { "r19", 1216, 64 }, + { "r20", 1280, 64 }, + { "r21", 1344, 64 }, + { "r22", 1408, 64 }, + { "r23", 1472, 64 }, + { "r24", 1536, 64 }, + { "r25", 1600, 64 }, + { "r26", 1664, 64 }, + { "r27", 1728, 64 }, + { "r28", 1792, 64 }, + { "r29", 1856, 64 }, + { "r30", 1920, 64 }, + { "r31", 1984, 64 }, + { "orig_a0", 2048, 64 }, + { "pc", 2112, 64 }, + { "badv", 2176, 64 }, + { "f0", 2240, 64 }, + { "f1", 2304, 64 }, + { "f2", 2368, 64 }, + { "f3", 2432, 64 }, + { "f4", 2496, 64 }, + { "f5", 2560, 64 }, + { "f6", 2624, 64 }, + { "f7", 2688, 64 }, + { "f8", 2752, 64 }, + { "f9", 2816, 64 }, + { "f10", 2880, 64 }, + { "f11", 2944, 64 }, + { "f12", 3008, 64 }, + { "f13", 3072, 64 }, + { "f14", 3136, 64 }, + { "f15", 3200, 64 }, + { "f16", 3264, 64 }, + { "f17", 3328, 64 }, + { "f18", 3392, 64 }, + { "f19", 3456, 64 }, + { "f20", 3520, 64 }, + { "f21", 3584, 64 }, + { "f22", 3648, 64 }, + { "f23", 3712, 64 }, + { "f24", 3776, 64 }, + { "f25", 3840, 64 }, + { "f26", 3904, 64 }, + { "f27", 3968, 64 }, + { "f28", 4032, 64 }, + { "f29", 4096, 64 }, + { "f30", 4160, 64 }, + { "f31", 4224, 64 }, + { "fcc0", 4288, 8 }, + { "fcc1", 4296, 8 }, + { "fcc2", 4304, 8 }, + { "fcc3", 4312, 8 }, + { "fcc4", 4320, 8 }, + { "fcc5", 4328, 8 }, + { "fcc6", 4336, 8 }, + { "fcc7", 4344, 8 }, + { "fcsr", 4352, 32 } +}; + +#define num_regs (sizeof (regs) / sizeof (regs[0])) + +static const char* expedite_regs[] = { "r3", "pc", NULL }; + +static +CORE_ADDR get_pc (void) +{ + unsigned long pc; + + collect_register_by_name ("pc", &pc); + + dlog(1, "stop pc is %p\n", (void*) pc); + return pc; +} + +static +void set_pc (CORE_ADDR newpc) +{ + supply_register_by_name ("pc", &newpc); +} + +/* store registers in the guest state (gdbserver_to_valgrind) + or fetch register from the guest state (valgrind_to_gdbserver). */ +static +void transfer_register (ThreadId tid, int abs_regno, void* buf, + transfer_direction dir, int size, Bool* mod) +{ + ThreadState* tst = VG_(get_ThreadState)(tid); + int set = abs_regno / num_regs; + int regno = abs_regno % num_regs; + *mod = False; + + VexGuestLOONGARCH64State* loongarch64 = (VexGuestLOONGARCH64State*) get_arch (set, tst); + + switch (regno) { + // numbers here have to match the order of regs above + // Attention: gdb order does not match valgrind order. + case 0: VG_(transfer) (&loongarch64->guest_R0, buf, dir, size, mod); break; + case 1: VG_(transfer) (&loongarch64->guest_R1, buf, dir, size, mod); break; + case 2: VG_(transfer) (&loongarch64->guest_R2, buf, dir, size, mod); break; + case 3: VG_(transfer) (&loongarch64->guest_R3, buf, dir, size, mod); break; + case 4: VG_(transfer) (&loongarch64->guest_R4, buf, dir, size, mod); break; + case 5: VG_(transfer) (&loongarch64->guest_R5, buf, dir, size, mod); break; + case 6: VG_(transfer) (&loongarch64->guest_R6, buf, dir, size, mod); break; + case 7: VG_(transfer) (&loongarch64->guest_R7, buf, dir, size, mod); break; + case 8: VG_(transfer) (&loongarch64->guest_R8, buf, dir, size, mod); break; + case 9: VG_(transfer) (&loongarch64->guest_R9, buf, dir, size, mod); break; + case 10: VG_(transfer) (&loongarch64->guest_R10, buf, dir, size, mod); break; + case 11: VG_(transfer) (&loongarch64->guest_R11, buf, dir, size, mod); break; + case 12: VG_(transfer) (&loongarch64->guest_R12, buf, dir, size, mod); break; + case 13: VG_(transfer) (&loongarch64->guest_R13, buf, dir, size, mod); break; + case 14: VG_(transfer) (&loongarch64->guest_R14, buf, dir, size, mod); break; + case 15: VG_(transfer) (&loongarch64->guest_R15, buf, dir, size, mod); break; + case 16: VG_(transfer) (&loongarch64->guest_R16, buf, dir, size, mod); break; + case 17: VG_(transfer) (&loongarch64->guest_R17, buf, dir, size, mod); break; + case 18: VG_(transfer) (&loongarch64->guest_R18, buf, dir, size, mod); break; + case 19: VG_(transfer) (&loongarch64->guest_R19, buf, dir, size, mod); break; + case 20: VG_(transfer) (&loongarch64->guest_R20, buf, dir, size, mod); break; + case 21: VG_(transfer) (&loongarch64->guest_R21, buf, dir, size, mod); break; + case 22: VG_(transfer) (&loongarch64->guest_R22, buf, dir, size, mod); break; + case 23: VG_(transfer) (&loongarch64->guest_R23, buf, dir, size, mod); break; + case 24: VG_(transfer) (&loongarch64->guest_R24, buf, dir, size, mod); break; + case 25: VG_(transfer) (&loongarch64->guest_R25, buf, dir, size, mod); break; + case 26: VG_(transfer) (&loongarch64->guest_R26, buf, dir, size, mod); break; + case 27: VG_(transfer) (&loongarch64->guest_R27, buf, dir, size, mod); break; + case 28: VG_(transfer) (&loongarch64->guest_R28, buf, dir, size, mod); break; + case 29: VG_(transfer) (&loongarch64->guest_R29, buf, dir, size, mod); break; + case 30: VG_(transfer) (&loongarch64->guest_R30, buf, dir, size, mod); break; + case 31: VG_(transfer) (&loongarch64->guest_R31, buf, dir, size, mod); break; + case 32: *mod = False; break; // GDBTD?? arg0 + case 33: VG_(transfer) (&loongarch64->guest_PC, buf, dir, size, mod); break; + case 34: *mod = False; break; // GDBTD?? badvaddr + case 35: VG_(transfer) (&loongarch64->guest_X0, buf, dir, size, mod); break; + case 36: VG_(transfer) (&loongarch64->guest_X1, buf, dir, size, mod); break; + case 37: VG_(transfer) (&loongarch64->guest_X2, buf, dir, size, mod); break; + case 38: VG_(transfer) (&loongarch64->guest_X3, buf, dir, size, mod); break; + case 39: VG_(transfer) (&loongarch64->guest_X4, buf, dir, size, mod); break; + case 40: VG_(transfer) (&loongarch64->guest_X5, buf, dir, size, mod); break; + case 41: VG_(transfer) (&loongarch64->guest_X6, buf, dir, size, mod); break; + case 42: VG_(transfer) (&loongarch64->guest_X7, buf, dir, size, mod); break; + case 43: VG_(transfer) (&loongarch64->guest_X8, buf, dir, size, mod); break; + case 44: VG_(transfer) (&loongarch64->guest_X9, buf, dir, size, mod); break; + case 45: VG_(transfer) (&loongarch64->guest_X10, buf, dir, size, mod); break; + case 46: VG_(transfer) (&loongarch64->guest_X11, buf, dir, size, mod); break; + case 47: VG_(transfer) (&loongarch64->guest_X12, buf, dir, size, mod); break; + case 48: VG_(transfer) (&loongarch64->guest_X13, buf, dir, size, mod); break; + case 49: VG_(transfer) (&loongarch64->guest_X14, buf, dir, size, mod); break; + case 50: VG_(transfer) (&loongarch64->guest_X15, buf, dir, size, mod); break; + case 51: VG_(transfer) (&loongarch64->guest_X16, buf, dir, size, mod); break; + case 52: VG_(transfer) (&loongarch64->guest_X17, buf, dir, size, mod); break; + case 53: VG_(transfer) (&loongarch64->guest_X18, buf, dir, size, mod); break; + case 54: VG_(transfer) (&loongarch64->guest_X19, buf, dir, size, mod); break; + case 55: VG_(transfer) (&loongarch64->guest_X20, buf, dir, size, mod); break; + case 56: VG_(transfer) (&loongarch64->guest_X21, buf, dir, size, mod); break; + case 57: VG_(transfer) (&loongarch64->guest_X22, buf, dir, size, mod); break; + case 58: VG_(transfer) (&loongarch64->guest_X23, buf, dir, size, mod); break; + case 59: VG_(transfer) (&loongarch64->guest_X24, buf, dir, size, mod); break; + case 60: VG_(transfer) (&loongarch64->guest_X25, buf, dir, size, mod); break; + case 61: VG_(transfer) (&loongarch64->guest_X26, buf, dir, size, mod); break; + case 62: VG_(transfer) (&loongarch64->guest_X27, buf, dir, size, mod); break; + case 63: VG_(transfer) (&loongarch64->guest_X28, buf, dir, size, mod); break; + case 64: VG_(transfer) (&loongarch64->guest_X29, buf, dir, size, mod); break; + case 65: VG_(transfer) (&loongarch64->guest_X30, buf, dir, size, mod); break; + case 66: VG_(transfer) (&loongarch64->guest_X31, buf, dir, size, mod); break; + case 67: VG_(transfer) (&loongarch64->guest_FCC0, buf, dir, size, mod); break; + case 68: VG_(transfer) (&loongarch64->guest_FCC1, buf, dir, size, mod); break; + case 69: VG_(transfer) (&loongarch64->guest_FCC2, buf, dir, size, mod); break; + case 70: VG_(transfer) (&loongarch64->guest_FCC3, buf, dir, size, mod); break; + case 71: VG_(transfer) (&loongarch64->guest_FCC4, buf, dir, size, mod); break; + case 72: VG_(transfer) (&loongarch64->guest_FCC5, buf, dir, size, mod); break; + case 73: VG_(transfer) (&loongarch64->guest_FCC6, buf, dir, size, mod); break; + case 74: VG_(transfer) (&loongarch64->guest_FCC7, buf, dir, size, mod); break; + case 75: VG_(transfer) (&loongarch64->guest_FCSR, buf, dir, size, mod); break; + default: vg_assert(0); + } +} + +static +const char* target_xml (Bool shadow_mode) +{ + if (shadow_mode) { + return "loongarch64-linux-valgrind.xml"; + } else { + return "loongarch64-linux.xml"; + } +} + +static CORE_ADDR** target_get_dtv (ThreadState* tst) +{ + VexGuestLOONGARCH64State* loongarch64 = (VexGuestLOONGARCH64State*)&tst->arch.vex; + // Top of LoongArch tcbhead structure is located 0x0 bytes before the value + // of $r2. Dtv is the first of two pointers in tcbhead structure. + // More details can be found in GLIBC/sysdeps/nptl/tls.h. + return (CORE_ADDR**)((CORE_ADDR)loongarch64->guest_R2 + - 0x0 - 2 * sizeof(CORE_ADDR)); +} + +static struct valgrind_target_ops low_target = { + num_regs, + 3, // SP + regs, + transfer_register, + get_pc, + set_pc, + "loongarch64", + target_xml, + target_get_dtv +}; + +void loongarch64_init_architecture (struct valgrind_target_ops* target) +{ + *target = low_target; + set_register_cache (regs, num_regs); + gdbserver_expedite_regs = expedite_regs; +} diff --git a/coregrind/m_gdbserver/valgrind_low.h b/coregrind/m_gdbserver/valgrind_low.h index d8ae3c9..3393c32 100644 --- a/coregrind/m_gdbserver/valgrind_low.h +++ b/coregrind/m_gdbserver/valgrind_low.h @@ -109,5 +109,6 @@ extern void s390x_init_architecture (struct valgrind_target_ops *target); extern void mips32_init_architecture (struct valgrind_target_ops *target); extern void mips64_init_architecture (struct valgrind_target_ops *target); extern void nanomips_init_architecture (struct valgrind_target_ops *target); +extern void loongarch64_init_architecture (struct valgrind_target_ops *target); #endif diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c index 7a7d453..237a11f 100644 --- a/coregrind/m_initimg/initimg-linux.c +++ b/coregrind/m_initimg/initimg-linux.c @@ -913,7 +913,8 @@ Addr setup_client_stack( void* init_sp, && !defined(VGP_ppc64le_linux) \ && !defined(VGP_mips32_linux) && !defined(VGP_mips64_linux) \ && !defined(VGP_nanomips_linux) \ - && !defined(VGP_s390x_linux) + && !defined(VGP_s390x_linux) \ + && !defined(VGP_loongarch64_linux) case AT_SYSINFO_EHDR: { /* Trash this, because we don't reproduce it */ const NSegment* ehdrseg = VG_(am_find_nsegment)((Addr)auxv->u.a_ptr); @@ -1344,6 +1345,20 @@ void VG_(ii_finalise_image)( IIFinaliseImageInfo iifii ) arch->vex.guest_PC = iifii.initial_client_IP; arch->vex.guest_r31 = iifii.initial_client_SP; +# elif defined(VGP_loongarch64_linux) + vg_assert(0 == sizeof(VexGuestLOONGARCH64State) % LibVEX_GUEST_STATE_ALIGN); + + /* Zero out the initial state, and set up the simulated FPU in a + sane way. */ + LibVEX_GuestLOONGARCH64_initialise(&arch->vex); + + /* Zero out the shadow areas. */ + VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestLOONGARCH64State)); + VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestLOONGARCH64State)); + + arch->vex.guest_R3 = iifii.initial_client_SP; + arch->vex.guest_PC = iifii.initial_client_IP; + # else # error Unknown platform # endif diff --git a/coregrind/m_libcassert.c b/coregrind/m_libcassert.c index 0b04bfc..c95253d 100644 --- a/coregrind/m_libcassert.c +++ b/coregrind/m_libcassert.c @@ -264,6 +264,26 @@ (srP)->misc.MIPS32.r31 = (UInt)ra; \ (srP)->misc.MIPS32.r28 = (UInt)gp; \ } +#elif defined(VGP_loongarch64_linux) +# define GET_STARTREGS(srP) \ + { \ + ULong pc, sp, fp, ra; \ + __asm__ __volatile__( \ + "pcaddi %0, 0 \n\t" \ + "move %1, $sp \n\t" \ + "move %2, $fp \n\t" \ + "move %3, $ra \n\t" \ + : "=r" (pc), \ + "=r" (sp), \ + "=r" (fp), \ + "=r" (ra) \ + : /* reads none */ \ + : /* no trashed */ ); \ + (srP)->r_pc = (ULong)pc; \ + (srP)->r_sp = (ULong)sp; \ + (srP)->misc.LOONGARCH64.r_fp = (ULong)fp; \ + (srP)->misc.LOONGARCH64.r_ra = (ULong)ra; \ + } #else # error Unknown platform #endif diff --git a/coregrind/m_libcfile.c b/coregrind/m_libcfile.c index 5d3a349..bbbd4e7 100644 --- a/coregrind/m_libcfile.c +++ b/coregrind/m_libcfile.c @@ -264,7 +264,8 @@ Bool VG_(resolve_filemode) ( Int fd, Int * result ) SysRes VG_(mknod) ( const HChar* pathname, Int mode, UWord dev ) { -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) /* ARM64 wants to use __NR_mknodat rather than __NR_mknod. */ SysRes res = VG_(do_syscall4)(__NR_mknodat, VKI_AT_FDCWD, (UWord)pathname, mode, dev); @@ -290,7 +291,8 @@ SysRes VG_(mknod) ( const HChar* pathname, Int mode, UWord dev ) SysRes VG_(open) ( const HChar* pathname, Int flags, Int mode ) { -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) /* ARM64 wants to use __NR_openat rather than __NR_open. */ SysRes res = VG_(do_syscall4)(__NR_openat, VKI_AT_FDCWD, (UWord)pathname, flags, mode); @@ -384,7 +386,8 @@ Int VG_(pipe) ( Int fd[2] ) } else { return -1; } -# elif defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# elif defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) SysRes res = VG_(do_syscall2)(__NR_pipe2, (UWord)fd, 0); return sr_isError(res) ? -1 : 0; # elif defined(VGO_linux) @@ -517,12 +520,19 @@ SysRes VG_(stat) ( const HChar* file_name, struct vg_stat* vgbuf ) { struct vki_statx buf; res = VG_(do_syscall5)(__NR_statx, VKI_AT_FDCWD, (UWord)file_name, 0, VKI_STATX_ALL, (UWord)&buf); +# if defined(VGP_loongarch64_linux) + /* On LoongArch64 Linux platform, only statx is available. */ + if (!sr_isError(res)) + TRANSLATE_statx_TO_vg_stat(vgbuf, &buf); + return res; +# else if (!(sr_isError(res) && sr_Err(res) == VKI_ENOSYS)) { /* Success, or any failure except ENOSYS */ if (!sr_isError(res)) TRANSLATE_statx_TO_vg_stat(vgbuf, &buf); return res; } +# endif } # endif # if defined(VGO_linux) || defined(VGO_darwin) @@ -602,12 +612,19 @@ Int VG_(fstat) ( Int fd, struct vg_stat* vgbuf ) const char* file_name = ""; res = VG_(do_syscall5)(__NR_statx, fd, (RegWord)file_name, VKI_AT_EMPTY_PATH, VKI_STATX_ALL, (RegWord)&buf); +# if defined(VGP_loongarch64_linux) + /* On LoongArch64 Linux platform, only statx is available. */ + if (!sr_isError(res)) + TRANSLATE_statx_TO_vg_stat(vgbuf, &buf); + return sr_isError(res) ? (-1) : 0; +# else if (!(sr_isError(res) && sr_Err(res) == VKI_ENOSYS)) { /* Success, or any failure except ENOSYS */ if (!sr_isError(res)) TRANSLATE_statx_TO_vg_stat(vgbuf, &buf); return sr_isError(res) ? (-1) : 0; } +# endif } #endif # if defined(VGO_linux) || defined(VGO_darwin) @@ -731,7 +748,8 @@ SysRes VG_(dup) ( Int oldfd ) SysRes VG_(dup2) ( Int oldfd, Int newfd ) { -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) /* We only have dup3, that means we have to mimic dup2. The only real difference is when oldfd == newfd. dup3 always returns an error, but dup2 returns only an @@ -777,7 +795,7 @@ Int VG_(rename) ( const HChar* old_name, const HChar* new_name ) # if defined(VGO_solaris) || defined(VGP_arm64_linux) SysRes res = VG_(do_syscall4)(__NR_renameat, VKI_AT_FDCWD, (UWord)old_name, VKI_AT_FDCWD, (UWord)new_name); -# elif defined(VGP_nanomips_linux) +# elif defined(VGP_nanomips_linux) || defined(VGP_loongarch64_linux) SysRes res = VG_(do_syscall5)(__NR_renameat2, VKI_AT_FDCWD, (UWord)old_name, VKI_AT_FDCWD, (UWord)new_name, 0); @@ -791,7 +809,8 @@ Int VG_(rename) ( const HChar* old_name, const HChar* new_name ) Int VG_(unlink) ( const HChar* file_name ) { -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) SysRes res = VG_(do_syscall2)(__NR_unlinkat, VKI_AT_FDCWD, (UWord)file_name); # elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) @@ -870,7 +889,8 @@ const HChar *VG_(get_startup_wd) ( void ) SysRes VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout) { SysRes res; -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) /* ARM64 wants to use __NR_ppoll rather than __NR_poll. */ struct vki_timespec timeout_ts; if (timeout >= 0) { @@ -915,7 +935,8 @@ SSizeT VG_(readlink) (const HChar* path, HChar* buf, SizeT bufsiz) { SysRes res; /* res = readlink( path, buf, bufsiz ); */ -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, (UWord)path, (UWord)buf, bufsiz); # elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) @@ -994,7 +1015,8 @@ Int VG_(access) ( const HChar* path, Bool irusr, Bool iwusr, Bool ixusr ) UWord w = (irusr ? VKI_R_OK : 0) | (iwusr ? VKI_W_OK : 0) | (ixusr ? VKI_X_OK : 0); -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) SysRes res = VG_(do_syscall3)(__NR_faccessat, VKI_AT_FDCWD, (UWord)path, w); # elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) SysRes res = VG_(do_syscall2)(__NR_access, (UWord)path, w); @@ -1140,7 +1162,8 @@ SysRes VG_(pread) ( Int fd, void* buf, Int count, OffT offset ) return res; # elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ - || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) + || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ + || defined(VGP_loongarch64_linux) res = VG_(do_syscall4)(__NR_pread64, fd, (UWord)buf, count, offset); return res; # elif defined(VGP_amd64_freebsd) @@ -1404,7 +1427,8 @@ Int VG_(socket) ( Int domain, Int type, Int protocol ) # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ - || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) || defined(VGO_freebsd) + || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGO_freebsd) || defined(VGP_loongarch64_linux) SysRes res; res = VG_(do_syscall3)(__NR_socket, domain, type, protocol ); return sr_isError(res) ? -1 : sr_Res(res); @@ -1459,7 +1483,8 @@ Int my_connect ( Int sockfd, struct vki_sockaddr_in* serv_addr, Int addrlen ) # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ - || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) || defined(VGO_freebsd) + || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGO_freebsd) || defined(VGP_loongarch64_linux) SysRes res; res = VG_(do_syscall3)(__NR_connect, sockfd, (UWord)serv_addr, addrlen); return sr_isError(res) ? -1 : sr_Res(res); @@ -1506,7 +1531,8 @@ Int VG_(write_socket)( Int sd, const void *msg, Int count ) # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ - || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) || defined(VGO_freebsd) + || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGO_freebsd) || defined(VGP_loongarch64_linux) SysRes res; res = VG_(do_syscall6)(__NR_sendto, sd, (UWord)msg, count, VKI_MSG_NOSIGNAL, 0,0); @@ -1544,7 +1570,8 @@ Int VG_(getsockname) ( Int sd, struct vki_sockaddr *name, Int *namelen) # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ || defined(VGP_nanomips_linux) || defined(VGO_freebsd) \ - || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) + || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ + || defined(VGP_loongarch64_linux) SysRes res; res = VG_(do_syscall3)( __NR_getsockname, (UWord)sd, (UWord)name, (UWord)namelen ); @@ -1583,7 +1610,8 @@ Int VG_(getpeername) ( Int sd, struct vki_sockaddr *name, Int *namelen) # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ - || defined(VGP_nanomips_linux) || defined(VGO_freebsd) + || defined(VGP_nanomips_linux) || defined(VGO_freebsd) \ + || defined(VGP_loongarch64_linux) SysRes res; res = VG_(do_syscall3)( __NR_getpeername, (UWord)sd, (UWord)name, (UWord)namelen ); @@ -1625,7 +1653,7 @@ Int VG_(getsockopt) ( Int sd, Int level, Int optname, void *optval, # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ - || defined(VGO_freebsd) + || defined(VGO_freebsd) || defined(VGP_loongarch64_linux) SysRes res; res = VG_(do_syscall5)( __NR_getsockopt, (UWord)sd, (UWord)level, (UWord)optname, @@ -1669,7 +1697,8 @@ Int VG_(setsockopt) ( Int sd, Int level, Int optname, void *optval, # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ - || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) + || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) SysRes res; res = VG_(do_syscall5)( __NR_setsockopt, (UWord)sd, (UWord)level, (UWord)optname, diff --git a/coregrind/m_libcproc.c b/coregrind/m_libcproc.c index 592d69b..61827cb 100644 --- a/coregrind/m_libcproc.c +++ b/coregrind/m_libcproc.c @@ -698,7 +698,8 @@ Int VG_(gettid)(void) * the /proc/self link is pointing... */ -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, (UWord)"/proc/self", (UWord)pid, sizeof(pid)); @@ -753,7 +754,8 @@ Int VG_(getpid) ( void ) Int VG_(getpgrp) ( void ) { /* ASSUMES SYSCALL ALWAYS SUCCEEDS */ -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) return sr_Res( VG_(do_syscall1)(__NR_getpgid, 0) ); # elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) return sr_Res( VG_(do_syscall0)(__NR_getpgrp) ); @@ -850,7 +852,7 @@ Int VG_(getgroups)( Int size, UInt* list ) || defined(VGO_darwin) || defined(VGP_s390x_linux) \ || defined(VGP_mips32_linux) || defined(VGP_arm64_linux) \ || defined(VGO_solaris) || defined(VGP_nanomips_linux) \ - || defined(VGO_freebsd) + || defined(VGO_freebsd) || defined(VGP_loongarch64_linux) SysRes sres; sres = VG_(do_syscall2)(__NR_getgroups, size, (Addr)list); if (sr_isError(sres)) @@ -944,7 +946,8 @@ Int VG_(fork) ( void ) fds[0] = fds[1] = -1; } -# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) +# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) SysRes res; res = VG_(do_syscall5)(__NR_clone, VKI_SIGCHLD, (UWord)NULL, (UWord)NULL, (UWord)NULL, (UWord)NULL); diff --git a/coregrind/m_libcsetjmp.c b/coregrind/m_libcsetjmp.c index f53a223..400f68a 100644 --- a/coregrind/m_libcsetjmp.c +++ b/coregrind/m_libcsetjmp.c @@ -781,6 +781,72 @@ __asm__( ); #endif /* VGP_s390x_linux */ +#if defined(VGP_loongarch64_linux) + +__asm__( +".text \n\t" +".globl VG_MINIMAL_SETJMP; \n\t" +"VG_MINIMAL_SETJMP: \n\t" +" st.d $ra, $a0, 0 \n\t" +" st.d $sp, $a0, 8 \n\t" +" st.d $r21, $a0, 16 \n\t" +" st.d $fp, $a0, 24 \n\t" +" st.d $s0, $a0, 32 \n\t" +" st.d $s1, $a0, 40 \n\t" +" st.d $s2, $a0, 48 \n\t" +" st.d $s3, $a0, 56 \n\t" +" st.d $s4, $a0, 64 \n\t" +" st.d $s5, $a0, 72 \n\t" +" st.d $s6, $a0, 80 \n\t" +" st.d $s7, $a0, 88 \n\t" +" st.d $s8, $a0, 96 \n\t" +#if !defined(__loongarch_soft_float) +" fst.d $f24, $a0, 104 \n\t" +" fst.d $f25, $a0, 112 \n\t" +" fst.d $f26, $a0, 120 \n\t" +" fst.d $f27, $a0, 128 \n\t" +" fst.d $f28, $a0, 136 \n\t" +" fst.d $f29, $a0, 144 \n\t" +" fst.d $f30, $a0, 152 \n\t" +" fst.d $f30, $a0, 160 \n\t" +#endif +" move $a0, $zero \n\t" +" jr $ra \n\t" +" \n\t" +".text \n\t" +".globl VG_MINIMAL_LONGJMP; \n\t" +"VG_MINIMAL_LONGJMP: \n\t" +" ld.d $ra, $a0, 0 \n\t" +" ld.d $sp, $a0, 8 \n\t" +" ld.d $r21, $a0, 16 \n\t" +" ld.d $fp, $a0, 24 \n\t" +" ld.d $s0, $a0, 32 \n\t" +" ld.d $s1, $a0, 40 \n\t" +" ld.d $s2, $a0, 48 \n\t" +" ld.d $s3, $a0, 56 \n\t" +" ld.d $s4, $a0, 64 \n\t" +" ld.d $s5, $a0, 72 \n\t" +" ld.d $s6, $a0, 80 \n\t" +" ld.d $s7, $a0, 88 \n\t" +" ld.d $s8, $a0, 96 \n\t" +#if !defined(__loongarch_soft_float) +" fld.d $f24, $a0, 104 \n\t" +" fld.d $f25, $a0, 112 \n\t" +" fld.d $f26, $a0, 120 \n\t" +" fld.d $f27, $a0, 128 \n\t" +" fld.d $f28, $a0, 136 \n\t" +" fld.d $f29, $a0, 144 \n\t" +" fld.d $f30, $a0, 152 \n\t" +" fld.d $f30, $a0, 160 \n\t" +#endif +" bnez $a1, 1f \n\t" +" addi.d $a1, $a1, 1 \n\t" +"1: \n\t" +" move $a0, $a1 \n\t" +" jr $ra \n\t" +); +#endif /* VGP_loongarch64_linux */ + /*--------------------------------------------------------------------*/ /*--- end ---*/ /*--------------------------------------------------------------------*/ diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index a4c2218..5cfca01 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -152,6 +152,13 @@ void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs, = VG_(threads)[tid].arch.vex.guest_r31; regs->misc.MIPS64.r28 = VG_(threads)[tid].arch.vex.guest_r28; +# elif defined(VGA_loongarch64) + regs->r_pc = VG_(threads)[tid].arch.vex.guest_PC; + regs->r_sp = VG_(threads)[tid].arch.vex.guest_R3; + regs->misc.LOONGARCH64.r_fp + = VG_(threads)[tid].arch.vex.guest_R22; + regs->misc.LOONGARCH64.r_ra + = VG_(threads)[tid].arch.vex.guest_R1; # else # error "Unknown arch" # endif @@ -369,6 +376,39 @@ static void apply_to_GPs_of_tid(ThreadId tid, void (*f)(ThreadId, (*f)(tid, "x28", vex->guest_X28); (*f)(tid, "x29", vex->guest_X29); (*f)(tid, "x30", vex->guest_X30); +#elif defined(VGA_loongarch64) + (*f)(tid, "r0" , vex->guest_R0 ); + (*f)(tid, "r1" , vex->guest_R1 ); + (*f)(tid, "r2" , vex->guest_R2 ); + (*f)(tid, "r3" , vex->guest_R3 ); + (*f)(tid, "r4" , vex->guest_R4 ); + (*f)(tid, "r5" , vex->guest_R5 ); + (*f)(tid, "r6" , vex->guest_R6 ); + (*f)(tid, "r7" , vex->guest_R7 ); + (*f)(tid, "r8" , vex->guest_R8 ); + (*f)(tid, "r9" , vex->guest_R9 ); + (*f)(tid, "r10", vex->guest_R10); + (*f)(tid, "r11", vex->guest_R11); + (*f)(tid, "r12", vex->guest_R12); + (*f)(tid, "r13", vex->guest_R13); + (*f)(tid, "r14", vex->guest_R14); + (*f)(tid, "r15", vex->guest_R15); + (*f)(tid, "r16", vex->guest_R16); + (*f)(tid, "r17", vex->guest_R17); + (*f)(tid, "r18", vex->guest_R18); + (*f)(tid, "r19", vex->guest_R19); + (*f)(tid, "r20", vex->guest_R20); + (*f)(tid, "r21", vex->guest_R21); + (*f)(tid, "r22", vex->guest_R22); + (*f)(tid, "r23", vex->guest_R23); + (*f)(tid, "r24", vex->guest_R24); + (*f)(tid, "r25", vex->guest_R25); + (*f)(tid, "r26", vex->guest_R26); + (*f)(tid, "r27", vex->guest_R27); + (*f)(tid, "r28", vex->guest_R28); + (*f)(tid, "r29", vex->guest_R29); + (*f)(tid, "r30", vex->guest_R30); + (*f)(tid, "r31", vex->guest_R31); #else # error Unknown arch #endif @@ -479,7 +519,7 @@ Int VG_(machine_arm_archlevel) = 4; testing, so we need a VG_MINIMAL_JMP_BUF. */ #if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ || defined(VGA_arm) || defined(VGA_s390x) || defined(VGA_mips32) \ - || defined(VGA_mips64) || defined(VGA_arm64) + || defined(VGA_mips64) || defined(VGA_arm64) || defined(VGA_loongarch64) #include "pub_core_libcsetjmp.h" static VG_MINIMAL_JMP_BUF(env_unsup_insn); static void handler_unsup_insn ( Int x ) { @@ -861,6 +901,105 @@ static Bool VG_(parse_cpuinfo)(void) #endif /* defined(VGP_arm64_linux) */ +#if defined(VGA_loongarch64) + +/* + * Initialize hwcaps by parsing /proc/cpuinfo. Returns False if it can not + * determine what CPU it is (it searches only for the models that are or may be + * supported by Valgrind). + */ +static Bool VG_(parse_cpuinfo)(void) +{ + Int n, fh; + SysRes fd; + SizeT num_bytes, file_buf_size; + HChar *file_buf; + + const char *search_Loongson_str = "Model Name\t\t: Loongson"; + + /* Slurp contents of /proc/cpuinfo into FILE_BUF */ + fd = VG_(open)("/proc/cpuinfo", 0, VKI_S_IRUSR); + if (sr_isError(fd)) + return False; + + fh = sr_Res(fd); + + /* Determine the size of /proc/cpuinfo. + Work around broken-ness in /proc file system implementation. + fstat returns a zero size for /proc/cpuinfo although it is + claimed to be a regular file. */ + num_bytes = 0; + file_buf_size = 1000; + file_buf = VG_(malloc)("cpuinfo", file_buf_size + 1); + while (True) { + n = VG_(read)(fh, file_buf, file_buf_size); + if (n < 0) + break; + + num_bytes += n; + if (n < file_buf_size) + break; /* reached EOF */ + } + + if (n < 0) + num_bytes = 0; /* read error; ignore contents */ + + if (num_bytes > file_buf_size) { + VG_(free)(file_buf); + VG_(lseek)(fh, 0, VKI_SEEK_SET); + file_buf = VG_(malloc)("cpuinfo", num_bytes + 1); + n = VG_(read)(fh, file_buf, num_bytes); + if (n < 0) + num_bytes = 0; + } + + file_buf[num_bytes] = '\0'; + VG_(close)(fh); + + /* Parse file */ + vai.hwcaps = 0; + if (VG_(strstr)(file_buf, search_Loongson_str) == NULL) { + /* Did not find string in the proc file. */ + VG_(free)(file_buf); + return False; + } + + if (VG_(strstr)(file_buf, "loongarch32") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_ISA_32BIT; + if (VG_(strstr)(file_buf, "loongarch64") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_ISA_64BIT; + + if (VG_(strstr)(file_buf, "cpucfg") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_CPUCFG; + if (VG_(strstr)(file_buf, "lam") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_LAM; + if (VG_(strstr)(file_buf, "ual") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_UAL; + if (VG_(strstr)(file_buf, "fpu") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_FP; + if (VG_(strstr)(file_buf, "lsx") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_LSX; + if (VG_(strstr)(file_buf, "lasx") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_LASX; + if (VG_(strstr)(file_buf, "complex") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_COMPLEX; + if (VG_(strstr)(file_buf, "crypto") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_CRYPTO; + if (VG_(strstr)(file_buf, "lvz") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_LVZP; + if (VG_(strstr)(file_buf, "lbt_x86") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_X86BT; + if (VG_(strstr)(file_buf, "lbt_arm") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_ARMBT; + if (VG_(strstr)(file_buf, "lbt_mips") != NULL) + vai.hwcaps |= VEX_HWCAPS_LOONGARCH_MIPSBT; + + VG_(free)(file_buf); + return True; +} + +#endif /* defined(VGP_loongarch64) */ + Bool VG_(machine_get_hwcaps)( void ) { vg_assert(hwcaps_done == False); @@ -2230,6 +2369,54 @@ Bool VG_(machine_get_hwcaps)( void ) return True; } + +#elif defined(VGA_loongarch64) + { + va = VexArchLOONGARCH64; + vai.endness = VexEndnessLE; + vai.hwcaps = 0; + + if (!VG_(parse_cpuinfo)()) + return False; + + /* Same instruction set detection algorithm as for ppc32/arm... */ + vki_sigset_t saved_set, tmp_set; + vki_sigaction_fromK_t saved_sigill_act; + vki_sigaction_toK_t tmp_sigill_act; + + vg_assert(sizeof(vki_sigaction_fromK_t) == sizeof(vki_sigaction_toK_t)); + + VG_(sigemptyset)(&tmp_set); + VG_(sigaddset)(&tmp_set, VKI_SIGILL); + + Int r; + r = VG_(sigprocmask)(VKI_SIG_UNBLOCK, &tmp_set, &saved_set); + vg_assert(r == 0); + + r = VG_(sigaction)(VKI_SIGILL, NULL, &saved_sigill_act); + vg_assert(r == 0); + tmp_sigill_act = saved_sigill_act; + + /* NODEFER: signal handler does not return (from the kernel's point of + view), hence if it is to successfully catch a signal more than once, + we need the NODEFER flag. */ + tmp_sigill_act.sa_flags &= ~VKI_SA_RESETHAND; + tmp_sigill_act.sa_flags &= ~VKI_SA_SIGINFO; + tmp_sigill_act.sa_flags |= VKI_SA_NODEFER; + tmp_sigill_act.ksa_handler = handler_unsup_insn; + VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL); + + VG_(convert_sigaction_fromK_to_toK)(&saved_sigill_act, &tmp_sigill_act); + VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL); + VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL); + + VG_(debugLog)(1, "machine", "hwcaps = 0x%x\n", vai.hwcaps); + + VG_(machine_get_cache_info)(&vai); + + return True; + } + #else # error "Unknown arch" #endif @@ -2370,6 +2557,9 @@ Int VG_(machine_get_size_of_largest_guest_register) ( void ) # elif defined(VGA_mips64) return 8; +# elif defined(VGA_loongarch64) + return 8; + # else # error "Unknown arch" # endif @@ -2386,7 +2576,7 @@ void* VG_(fnptr_to_fnentry)( void* f ) || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ || defined(VGP_x86_solaris) || defined(VGP_amd64_solaris) \ - || defined(VGP_nanomips_linux) + || defined(VGP_nanomips_linux) || defined(VGP_loongarch64_linux) return f; # elif defined(VGP_ppc64be_linux) /* ppc64-linux uses the AIX scheme, in which f is a pointer to a diff --git a/coregrind/m_main.c b/coregrind/m_main.c index bb4a0ca..b2b7415 100644 --- a/coregrind/m_main.c +++ b/coregrind/m_main.c @@ -1481,6 +1481,7 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) "AMD Athlon or above)\n"); VG_(printf)(" * AMD Athlon64/Opteron\n"); VG_(printf)(" * ARM (armv7)\n"); + VG_(printf)(" * LoongArch (3A5000 and above)\n"); VG_(printf)(" * MIPS (mips32 and above; mips64 and above)\n"); VG_(printf)(" * PowerPC (most; ppc405 and above)\n"); VG_(printf)(" * System z (64bit only - s390x; z990 and above)\n"); @@ -2536,6 +2537,11 @@ static void final_tidyup(ThreadId tid) VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, offsetof(VexGuestS390XState, guest_r2), sizeof(VG_(threads)[tid].arch.vex.guest_r2)); +# elif defined(VGA_loongarch64) + VG_(threads)[tid].arch.vex.guest_R4 = to_run; + VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, + offsetof(VexGuestLOONGARCH64State, guest_R4), + sizeof(VG_(threads)[tid].arch.vex.guest_R4)); #else I_die_here : architecture missing in m_main.c #endif @@ -3064,6 +3070,29 @@ asm( ".set pop \n\t" ".previous \n\t" ); +#elif defined(VGP_loongarch64_linux) +asm(" \n\t" + ".text \n\t" + ".globl _start \n\t" + ".type _start,@function \n\t" + "_start: \n\t" + /* t0 = &vgPlain_interim_stack + VG_STACK_GUARD_SZB + + VG_DEFAULT_STACK_ACTIVE_SZB */ + "la.local $t0, vgPlain_interim_stack \n\t" + "li.w $t1, "VG_STRINGIFY(VG_STACK_GUARD_SZB)" \n\t" + "add.d $t0, $t0, $t1 \n\t" + "li.w $t2, "VG_STRINGIFY(VG_DEFAULT_STACK_ACTIVE_SZB)" \n\t" + "add.d $t0, $t0, $t2 \n\t" + /* allocate 16 bytes on the new stack in t0, and aligned */ + "addi.d $t0, $t0, -16 \n\t" + "bstrins.d $t0, $zero, 3, 0 \n\t" + /* a0 = sp, sp = t0, and then call _start_in_C_linux */ + "move $a0, $sp \n\t" + "move $sp, $t0 \n\t" + "la.local $t0, _start_in_C_linux \n\t" + "jr $t0 \n\t" + ".previous \n\t" +); #else # error "Unknown platform" #endif @@ -3109,11 +3138,11 @@ void _start_in_C_linux ( UWord* pArgc ) # if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ || defined(VGP_ppc64le_linux) || defined(VGP_arm64_linux) \ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ - || defined(VGP_nanomips_linux) + || defined(VGP_nanomips_linux) || defined(VGP_loongarch64_linux) { - /* ppc32/ppc64, arm64, mips32/64 can be configured with different - page sizes. Determine this early. This is an ugly hack and really - should be moved into valgrind_main. */ + /* ppc32/ppc64, arm64, mips32/64, loongarch64 can be configured with + different page sizes. Determine this early. This is an ugly hack + and really should be moved into valgrind_main. */ UWord *sp = &pArgc[1+argc+1]; while (*sp++ != 0) ; diff --git a/coregrind/m_options.c b/coregrind/m_options.c index 1483af2..640af71 100644 --- a/coregrind/m_options.c +++ b/coregrind/m_options.c @@ -203,7 +203,8 @@ UInt VG_(clo_unw_stack_scan_frames) = 5; VgSmc VG_(clo_smc_check) = Vg_SmcAllNonFile; #elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ || defined(VGA_arm) || defined(VGA_arm64) \ - || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) + || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) \ + || defined(VGA_loongarch64) VgSmc VG_(clo_smc_check) = Vg_SmcStack; #else # error "Unknown arch" diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c index cef241b..fa513a0 100644 --- a/coregrind/m_redir.c +++ b/coregrind/m_redir.c @@ -1240,6 +1240,7 @@ Bool VG_(is_soname_ld_so) (const HChar *soname) if (VG_STREQ(soname, VG_U_LD_LINUX_AARCH64_SO_1)) return True; if (VG_STREQ(soname, VG_U_LD_LINUX_ARMHF_SO_3)) return True; if (VG_STREQ(soname, VG_U_LD_LINUX_MIPSN8_S0_1)) return True; + if (VG_STREQ(soname, VG_U_LD_LINUX_LOONGARCH_LP64D_SO_1)) return True; # elif defined(VGO_freebsd) if (VG_STREQ(soname, VG_U_LD_ELF_SO_1)) return True; if (VG_STREQ(soname, VG_U_LD_ELF32_SO_1)) return True; @@ -1679,6 +1680,22 @@ void VG_(redir_initialise) ( void ) ); } +#elif defined(VGP_loongarch64_linux) + /* If we're using memcheck, use these intercepts right from + the start, otherwise ld.so makes a lot of noise. */ + if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { + add_hardwired_spec( + "ld-linux-loongarch-lp64d.so.1", "strlen", + (Addr)&VG_(loongarch64_linux_REDIR_FOR_strlen), + complain_about_stripped_glibc_ldso + ); + add_hardwired_spec( + "ld-linux-loongarch-lp64d.so.1", "strchr", + (Addr)&VG_(loongarch64_linux_REDIR_FOR_strchr), + complain_about_stripped_glibc_ldso + ); + } + # elif defined(VGP_x86_solaris) /* If we're using memcheck, use these intercepts right from the start, otherwise ld.so makes a lot of noise. */ diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c index f8b3b46..e3b3b63 100644 --- a/coregrind/m_scheduler/scheduler.c +++ b/coregrind/m_scheduler/scheduler.c @@ -271,6 +271,7 @@ const HChar* name_of_sched_event ( UInt event ) case VEX_TRC_JMP_SIGBUS: return "SIGBUS"; case VEX_TRC_JMP_SIGFPE_INTOVF: case VEX_TRC_JMP_SIGFPE_INTDIV: return "SIGFPE"; + case VEX_TRC_JMP_SIGSYS: return "SIGSYS"; case VEX_TRC_JMP_EMWARN: return "EMWARN"; case VEX_TRC_JMP_EMFAIL: return "EMFAIL"; case VEX_TRC_JMP_CLIENTREQ: return "CLIENTREQ"; @@ -1657,6 +1658,10 @@ VgSchedReturnCode VG_(scheduler) ( ThreadId tid ) VG_(synth_sigfpe)(tid, VKI_FPE_INTOVF); break; + case VEX_TRC_JMP_SIGSYS: + VG_(synth_sigsys)(tid); + break; + case VEX_TRC_JMP_NODECODE: { Addr addr = VG_(get_IP)(tid); @@ -1821,6 +1826,9 @@ void VG_(nuke_all_threads_except) ( ThreadId me, VgSchedReturnCode src ) #elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) # define VG_CLREQ_ARGS guest_r12 # define VG_CLREQ_RET guest_r11 +#elif defined(VGA_loongarch64) +# define VG_CLREQ_ARGS guest_R12 +# define VG_CLREQ_RET guest_R11 #else # error Unknown arch #endif diff --git a/coregrind/m_sigframe/sigframe-loongarch64-linux.c b/coregrind/m_sigframe/sigframe-loongarch64-linux.c new file mode 100644 index 0000000..eda6c88 --- /dev/null +++ b/coregrind/m_sigframe/sigframe-loongarch64-linux.c @@ -0,0 +1,285 @@ + +/*--------------------------------------------------------------------*/ +/*--- Create/destroy signal delivery frames. ---*/ +/*--- sigframe-loongarch64-linux.c ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#if defined(VGP_loongarch64_linux) + +#include "pub_core_basics.h" +#include "pub_core_vki.h" +#include "pub_core_vkiscnums.h" +#include "pub_core_threadstate.h" +#include "pub_core_aspacemgr.h" +#include "pub_core_libcbase.h" +#include "pub_core_libcassert.h" +#include "pub_core_libcprint.h" +#include "pub_core_machine.h" +#include "pub_core_options.h" +#include "pub_core_sigframe.h" +#include "pub_core_signals.h" +#include "pub_core_tooliface.h" +#include "pub_core_trampoline.h" +#include "priv_sigframe.h" + + +/*------------------------------------------------------------*/ +/*--- Signal frame layouts ---*/ +/*------------------------------------------------------------*/ + +struct vg_sig_private { + UInt magicPI; + UInt sigNo_private; + VexGuestLOONGARCH64State vex_shadow1; + VexGuestLOONGARCH64State vex_shadow2; +}; + +struct rt_sigframe { + struct vki_siginfo rs_info; + struct vki_ucontext rs_uctx; + struct vg_sig_private priv; +}; + + +/*------------------------------------------------------------*/ +/*--- Creating signal frames ---*/ +/*------------------------------------------------------------*/ + +static void create_siginfo ( ThreadId tid, + struct rt_sigframe *frame, + const vki_siginfo_t *si) +{ + VG_TRACK(pre_mem_write, Vg_CoreSignal, tid, "signal frame siginfo", + (Addr)&frame->rs_info, sizeof(frame->rs_info)); + + VG_(memcpy)(&frame->rs_info, si, sizeof(vki_siginfo_t)); + + VG_TRACK(post_mem_write, Vg_CoreSignal, tid, + (Addr)&frame->rs_info, sizeof(frame->rs_info)); +} + +static void create_sigcontext ( ThreadState *tst, + struct vki_sigcontext **sc) +{ + struct vki_sigcontext *sctx = *sc; + + VG_TRACK(pre_mem_write, Vg_CoreSignal, tst->tid, "signal frame mcontext", + (Addr)sctx, sizeof(ULong) * 32); + + sctx->sc_regs[1] = tst->arch.vex.guest_R1; + sctx->sc_regs[2] = tst->arch.vex.guest_R2; + sctx->sc_regs[3] = tst->arch.vex.guest_R3; + sctx->sc_regs[4] = tst->arch.vex.guest_R4; + sctx->sc_regs[5] = tst->arch.vex.guest_R5; + sctx->sc_regs[6] = tst->arch.vex.guest_R6; + sctx->sc_regs[7] = tst->arch.vex.guest_R7; + sctx->sc_regs[8] = tst->arch.vex.guest_R8; + sctx->sc_regs[9] = tst->arch.vex.guest_R9; + sctx->sc_regs[10] = tst->arch.vex.guest_R10; + sctx->sc_regs[11] = tst->arch.vex.guest_R11; + sctx->sc_regs[12] = tst->arch.vex.guest_R12; + sctx->sc_regs[13] = tst->arch.vex.guest_R13; + sctx->sc_regs[14] = tst->arch.vex.guest_R14; + sctx->sc_regs[15] = tst->arch.vex.guest_R15; + sctx->sc_regs[16] = tst->arch.vex.guest_R16; + sctx->sc_regs[17] = tst->arch.vex.guest_R17; + sctx->sc_regs[18] = tst->arch.vex.guest_R18; + sctx->sc_regs[19] = tst->arch.vex.guest_R19; + sctx->sc_regs[20] = tst->arch.vex.guest_R20; + sctx->sc_regs[21] = tst->arch.vex.guest_R21; + sctx->sc_regs[22] = tst->arch.vex.guest_R22; + sctx->sc_regs[23] = tst->arch.vex.guest_R23; + sctx->sc_regs[24] = tst->arch.vex.guest_R24; + sctx->sc_regs[25] = tst->arch.vex.guest_R25; + sctx->sc_regs[26] = tst->arch.vex.guest_R26; + sctx->sc_regs[27] = tst->arch.vex.guest_R27; + sctx->sc_regs[28] = tst->arch.vex.guest_R28; + sctx->sc_regs[29] = tst->arch.vex.guest_R29; + sctx->sc_regs[30] = tst->arch.vex.guest_R30; + sctx->sc_regs[31] = tst->arch.vex.guest_R31; + sctx->sc_pc = tst->arch.vex.guest_PC; +} + +static void create_ucontext ( ThreadState *tst, + ThreadId tid, + struct vki_ucontext *uc, + const vki_sigset_t *mask, + struct vki_sigcontext **sc, + const vki_siginfo_t *siginfo) +{ + VG_TRACK(pre_mem_write, Vg_CoreSignal, tid, "signal frame ucontext", + (Addr)uc, offsetof(struct vki_ucontext, uc_mcontext)); + + uc->uc_flags = 0; + uc->uc_link = 0; + uc->uc_stack = tst->altstack; + uc->uc_sigmask = *mask; + + VG_TRACK(post_mem_write, Vg_CoreSignal, tid, (Addr)uc, + offsetof(struct vki_ucontext, uc_mcontext)); + + create_sigcontext(tst, sc); +} + +/* EXPORTED */ +void VG_(sigframe_create) ( ThreadId tid, + Bool on_altstack, + Addr sp_top_of_frame, + const vki_siginfo_t *siginfo, + const struct vki_ucontext *siguc, + void *handler, + UInt flags, + const vki_sigset_t *mask, + void *restorer ) +{ + UInt size = sizeof(struct rt_sigframe); + Addr sp = VG_ROUNDDN(sp_top_of_frame - size, 16); + + ThreadState *tst = VG_(get_ThreadState)(tid); + if (! ML_(sf_maybe_extend_stack)(tst, sp, size, flags)) + return; + + struct rt_sigframe *frame = (struct rt_sigframe *)sp; + create_siginfo(tid, frame, siginfo); + + struct vki_ucontext *uctx = &frame->rs_uctx; + struct vki_sigcontext *sctx = &(frame->rs_uctx.uc_mcontext); + create_ucontext(tst, tid, uctx, mask, &sctx, siginfo); + + /* + Arguments to signal handler: + + a0 = signal number + a1 = pointer to siginfo + a2 = pointer to ucontext + + csr_era point to the signal handler, $r3 (sp) points to + the struct rt_sigframe. + */ + + Int sigNo = siginfo->si_signo; + tst->arch.vex.guest_R4 = sigNo; + tst->arch.vex.guest_R5 = (Addr) &frame->rs_info; + tst->arch.vex.guest_R6 = (Addr) &frame->rs_uctx; + tst->arch.vex.guest_R3 = (Addr) frame; + tst->arch.vex.guest_R1 = (Addr) &VG_(loongarch64_linux_SUBST_FOR_rt_sigreturn); + + struct vg_sig_private *priv = &frame->priv; + priv->magicPI = 0x31415927; + priv->sigNo_private = sigNo; + priv->vex_shadow1 = tst->arch.vex_shadow1; + priv->vex_shadow2 = tst->arch.vex_shadow2; + + /* Set the thread so it will next run the handler. */ + VG_TRACK(post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR, sizeof(Addr)); + + if (VG_(clo_trace_signals)) + VG_(printf)("handler = %p\n", handler); + + tst->arch.vex.guest_PC = (Addr) handler; + /* This thread needs to be marked runnable, but we leave that + the caller to do. */ +} + + +/*------------------------------------------------------------*/ +/*--- Destroying signal frames ---*/ +/*------------------------------------------------------------*/ + +static void restore_regs ( ThreadState *tst, + struct vki_sigcontext *mc) +{ + tst->arch.vex.guest_R1 = mc->sc_regs[1]; + tst->arch.vex.guest_R2 = mc->sc_regs[2]; + tst->arch.vex.guest_R3 = mc->sc_regs[3]; + tst->arch.vex.guest_R4 = mc->sc_regs[4]; + tst->arch.vex.guest_R5 = mc->sc_regs[5]; + tst->arch.vex.guest_R6 = mc->sc_regs[6]; + tst->arch.vex.guest_R7 = mc->sc_regs[7]; + tst->arch.vex.guest_R8 = mc->sc_regs[8]; + tst->arch.vex.guest_R9 = mc->sc_regs[9]; + tst->arch.vex.guest_R10 = mc->sc_regs[10]; + tst->arch.vex.guest_R11 = mc->sc_regs[11]; + tst->arch.vex.guest_R12 = mc->sc_regs[12]; + tst->arch.vex.guest_R13 = mc->sc_regs[13]; + tst->arch.vex.guest_R14 = mc->sc_regs[14]; + tst->arch.vex.guest_R15 = mc->sc_regs[15]; + tst->arch.vex.guest_R16 = mc->sc_regs[16]; + tst->arch.vex.guest_R17 = mc->sc_regs[17]; + tst->arch.vex.guest_R18 = mc->sc_regs[18]; + tst->arch.vex.guest_R19 = mc->sc_regs[19]; + tst->arch.vex.guest_R20 = mc->sc_regs[20]; + tst->arch.vex.guest_R21 = mc->sc_regs[21]; + tst->arch.vex.guest_R22 = mc->sc_regs[22]; + tst->arch.vex.guest_R23 = mc->sc_regs[23]; + tst->arch.vex.guest_R24 = mc->sc_regs[24]; + tst->arch.vex.guest_R25 = mc->sc_regs[25]; + tst->arch.vex.guest_R26 = mc->sc_regs[26]; + tst->arch.vex.guest_R27 = mc->sc_regs[27]; + tst->arch.vex.guest_R28 = mc->sc_regs[28]; + tst->arch.vex.guest_R29 = mc->sc_regs[29]; + tst->arch.vex.guest_R30 = mc->sc_regs[30]; + tst->arch.vex.guest_R31 = mc->sc_regs[31]; + tst->arch.vex.guest_PC = mc->sc_pc; +} + +/* EXPORTED */ +void VG_(sigframe_destroy)( ThreadId tid, Bool isRT ) +{ + vg_assert(VG_(is_valid_tid)(tid)); + + ThreadState *tst = VG_(get_ThreadState)(tid); + Addr sp = tst->arch.vex.guest_R3; + struct rt_sigframe *frame = (struct rt_sigframe *)sp; + struct vki_ucontext *uc = &frame->rs_uctx; + + tst->sig_mask = uc->uc_sigmask; + tst->tmp_sig_mask = uc->uc_sigmask; + + struct vki_sigcontext *mc = &uc->uc_mcontext; + restore_regs(tst, mc); + + struct vg_sig_private *priv = &frame->priv; + vg_assert(priv->magicPI == 0x31415927); + tst->arch.vex_shadow1 = priv->vex_shadow1; + tst->arch.vex_shadow2 = priv->vex_shadow2; + + UInt frame_size = sizeof(*frame); + VG_TRACK(die_mem_stack_signal, sp, frame_size); + + if (VG_(clo_trace_signals)) + VG_(message)(Vg_DebugMsg, + "VG_(signal_return) (thread %u): isRT=%d valid magic; PC=%#llx\n", + tid, isRT, tst->arch.vex.guest_PC); + + Int sigNo = priv->sigNo_private; + VG_TRACK( post_deliver_signal, tid, sigNo ); +} + +#endif /* defined(VGP_loongarch64_linux) */ + +/*--------------------------------------------------------------------*/ +/*--- end sigframe-loongarch64-linux.c ---*/ +/*--------------------------------------------------------------------*/ diff --git a/coregrind/m_signals.c b/coregrind/m_signals.c index b3c94fc..62c689b 100644 --- a/coregrind/m_signals.c +++ b/coregrind/m_signals.c @@ -628,6 +628,22 @@ VgHashTable *ht_sigchld_ignore = NULL; (srP)->misc.MIPS32.r28 = (uc)->uc_mcontext.sc_regs[28]; \ } +#elif defined(VGP_loongarch64_linux) +# define VG_UCONTEXT_INSTR_PTR(uc) (((uc)->uc_mcontext.sc_pc)) +# define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.sc_regs[3]) +# define VG_UCONTEXT_FRAME_PTR(uc) ((uc)->uc_mcontext.sc_regs[22]) +# define VG_UCONTEXT_SYSCALL_NUM(uc) ((uc)->uc_mcontext.sc_regs[11]) +# define VG_UCONTEXT_SYSCALL_SYSRES(uc) \ + /* Convert the value in uc_mcontext.regs[4] into a SysRes. */ \ + VG_(mk_SysRes_loongarch64_linux)((uc)->uc_mcontext.sc_regs[4]) + +# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \ + { (srP)->r_pc = (uc)->uc_mcontext.sc_pc; \ + (srP)->r_sp = (uc)->uc_mcontext.sc_regs[3]; \ + (srP)->misc.LOONGARCH64.r_fp = (uc)->uc_mcontext.sc_regs[22]; \ + (srP)->misc.LOONGARCH64.r_ra = (uc)->uc_mcontext.sc_regs[1]; \ + } + #elif defined(VGP_x86_solaris) # define VG_UCONTEXT_INSTR_PTR(uc) ((Addr)(uc)->uc_mcontext.gregs[VKI_EIP]) # define VG_UCONTEXT_STACK_PTR(uc) ((Addr)(uc)->uc_mcontext.gregs[VKI_UESP]) @@ -899,8 +915,10 @@ void calculate_SKSS_from_SCSS ( SKSS* dst ) if (skss_handler != VKI_SIG_IGN && skss_handler != VKI_SIG_DFL) skss_flags |= VKI_SA_SIGINFO; +# if !defined(VGP_loongarch64_linux) /* use our own restorer */ skss_flags |= VKI_SA_RESTORER; +# endif /* Create SKSS entry for this signal. */ if (sig != VKI_SIGKILL && sig != VKI_SIGSTOP) @@ -1052,6 +1070,15 @@ extern void my_sigreturn(void); " li $t4, " #name "\n" \ " syscall[32]\n" \ ".previous\n" + +#elif defined(VGP_loongarch64_linux) +# define _MY_SIGRETURN(name) \ + ".text\n" \ + "my_sigreturn:\n" \ + " li.w $a7, " #name "\n" \ + " syscall 0\n" \ + ".previous\n" + #elif defined(VGP_x86_solaris) || defined(VGP_amd64_solaris) /* Not used on Solaris. */ # define _MY_SIGRETURN(name) \ @@ -1111,7 +1138,8 @@ static void handle_SCSS_change ( Bool force_update ) ksa.sa_flags = skss.skss_per_sig[sig].skss_flags; # if !defined(VGP_ppc32_linux) && \ !defined(VGP_x86_darwin) && !defined(VGP_amd64_darwin) && \ - !defined(VGP_mips32_linux) && !defined(VGO_solaris) && !defined(VGO_freebsd) + !defined(VGP_mips32_linux) && !defined(VGO_solaris) && \ + !defined(VGO_freebsd) && !defined(VGP_loongarch64_linux) ksa.sa_restorer = my_sigreturn; # endif /* Re above ifdef (also the assertion below), PaulM says: @@ -1159,7 +1187,7 @@ static void handle_SCSS_change ( Bool force_update ) !defined(VGP_x86_darwin) && !defined(VGP_amd64_darwin) && \ !defined(VGP_mips32_linux) && !defined(VGP_mips64_linux) && \ !defined(VGP_nanomips_linux) && !defined(VGO_solaris) && \ - !defined(VGO_freebsd) + !defined(VGO_freebsd) && !defined(VGP_loongarch64_linux) vg_assert(ksa_old.sa_restorer == my_sigreturn); # endif VG_(sigaddset)( &ksa_old.sa_mask, VKI_SIGKILL ); @@ -1280,7 +1308,7 @@ SysRes VG_(do_sys_sigaction) ( Int signo, old_act->sa_flags = scss.scss_per_sig[signo].scss_flags; old_act->sa_mask = scss.scss_per_sig[signo].scss_mask; # if !defined(VGO_darwin) && !defined(VGO_freebsd) && \ - !defined(VGO_solaris) + !defined(VGO_solaris) && !defined(VGP_loongarch64_linux) old_act->sa_restorer = scss.scss_per_sig[signo].scss_restorer; # endif } @@ -1293,7 +1321,7 @@ SysRes VG_(do_sys_sigaction) ( Int signo, scss.scss_per_sig[signo].scss_restorer = NULL; # if !defined(VGO_darwin) && !defined(VGO_freebsd) && \ - !defined(VGO_solaris) + !defined(VGO_solaris) && !defined(VGP_loongarch64_linux) scss.scss_per_sig[signo].scss_restorer = new_act->sa_restorer; # endif @@ -1653,7 +1681,7 @@ void VG_(kill_self)(Int sigNo) sa.ksa_handler = VKI_SIG_DFL; sa.sa_flags = 0; # if !defined(VGO_darwin) && !defined(VGO_freebsd) && \ - !defined(VGO_solaris) + !defined(VGO_solaris) && !defined(VGP_loongarch64_linux) sa.sa_restorer = 0; # endif VG_(sigemptyset)(&sa.sa_mask); @@ -2296,8 +2324,9 @@ void VG_(synth_sigtrap)(ThreadId tid) // Synthesise a SIGFPE. void VG_(synth_sigfpe)(ThreadId tid, UInt code) { -// Only tested on mips32, mips64, s390x and nanomips. -#if !defined(VGA_mips32) && !defined(VGA_mips64) && !defined(VGA_s390x) && !defined(VGA_nanomips) +// Only tested on mips32, mips64, s390x, nanomips and loongarch64. +#if !defined(VGA_mips32) && !defined(VGA_mips64) && !defined(VGA_s390x) \ + && !defined(VGA_nanomips) && !defined(VGA_loongarch64) vg_assert(0); #else vki_siginfo_t info; @@ -2319,6 +2348,30 @@ void VG_(synth_sigfpe)(ThreadId tid, UInt code) #endif } +// Synthesise a SIGSYS. +void VG_(synth_sigsys)(ThreadId tid) +{ +// Only tested on loongarch64-linux. +#if !defined(VGP_loongarch64_linux) + vg_assert(0); +#else + vki_siginfo_t info; + + vg_assert(VG_(threads)[tid].status == VgTs_Runnable); + + VG_(memset)(&info, 0, sizeof(info)); + info.si_signo = VKI_SIGSYS; + info.si_code = VKI_SI_KERNEL; + + if (VG_(gdbserver_report_signal) (&info, tid)) { + resume_scheduler(tid); + deliver_signal(tid, &info, NULL); + } + else + resume_scheduler(tid); +#endif +} + /* Make a signal pending for a thread, for later delivery. VG_(poll_signals) will arrange for it to be delivered at the right time. @@ -3043,7 +3096,7 @@ void pp_ksigaction ( vki_sigaction_toK_t* sa ) sa->ksa_handler, (UInt)sa->sa_flags, # if !defined(VGO_darwin) && !defined(VGO_freebsd) && \ - !defined(VGO_solaris) + !defined(VGO_solaris) && !defined(VGP_loongarch64_linux) sa->sa_restorer # else (void*)0 @@ -3066,7 +3119,7 @@ void VG_(set_default_handler)(Int signo) sa.ksa_handler = VKI_SIG_DFL; sa.sa_flags = 0; # if !defined(VGO_darwin) && !defined(VGO_freebsd) && \ - !defined(VGO_solaris) + !defined(VGO_solaris) && !defined(VGP_loongarch64_linux) sa.sa_restorer = 0; # endif VG_(sigemptyset)(&sa.sa_mask); @@ -3188,7 +3241,7 @@ void VG_(sigstartup_actions) ( void ) tsa.ksa_handler = (void *)sync_signalhandler; tsa.sa_flags = VKI_SA_SIGINFO; # if !defined(VGO_darwin) && !defined(VGO_freebsd) && \ - !defined(VGO_solaris) + !defined(VGO_solaris) && !defined(VGP_loongarch64_linux) tsa.sa_restorer = 0; # endif VG_(sigfillset)(&tsa.sa_mask); @@ -3216,7 +3269,7 @@ void VG_(sigstartup_actions) ( void ) scss.scss_per_sig[i].scss_restorer = NULL; # if !defined(VGO_darwin) && !defined(VGO_freebsd) && \ - !defined(VGO_solaris) + !defined(VGO_solaris) && !defined(VGP_loongarch64_linux) scss.scss_per_sig[i].scss_restorer = sa.sa_restorer; # endif diff --git a/coregrind/m_stacktrace.c b/coregrind/m_stacktrace.c index 0ec6f59..0f89b63 100644 --- a/coregrind/m_stacktrace.c +++ b/coregrind/m_stacktrace.c @@ -1505,6 +1505,100 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, #endif +/* ---------------------- loongarch64 ----------------------- */ + +#if defined(VGP_loongarch64_linux) +UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, + /*OUT*/Addr* ips, UInt max_n_ips, + /*OUT*/Addr* sps, /*OUT*/Addr* fps, + const UnwindStartRegs* startRegs, + Addr fp_max_orig ) +{ + Bool debug = False; + Int i; + Addr fp_max; + UInt n_found = 0; + const Int cmrf = VG_(clo_merge_recursive_frames); + + vg_assert(sizeof(Addr) == sizeof(UWord)); + vg_assert(sizeof(Addr) == sizeof(void*)); + + D3UnwindRegs uregs; + uregs.pc = startRegs->r_pc; + uregs.sp = startRegs->r_sp; + uregs.fp = startRegs->misc.LOONGARCH64.r_fp; + uregs.ra = startRegs->misc.LOONGARCH64.r_ra; + Addr fp_min = uregs.sp - VG_STACK_REDZONE_SZB; + + /* Snaffle IPs from the client's stack into ips[0 .. max_n_ips-1], + stopping when the trail goes cold, which we guess to be + when FP is not a reasonable stack location. */ + + fp_max = VG_PGROUNDUP(fp_max_orig); + if (fp_max >= sizeof(Addr)) + fp_max -= sizeof(Addr); + + if (debug) + VG_(printf)("\nmax_n_ips=%u fp_min=0x%lx fp_max_orig=0x%lx, " + "fp_max=0x%lx pc=0x%lx sp=0x%lx fp=0x%lx ra=0x%lx\n", + max_n_ips, fp_min, fp_max_orig, fp_max, + uregs.pc, uregs.sp, uregs.fp, uregs.ra); + + if (sps) sps[0] = uregs.sp; + if (fps) fps[0] = uregs.fp; + ips[0] = uregs.pc; + i = 1; + + /* Loop unwinding the stack, using CFI. */ + while (True) { + if (debug) + VG_(printf)("i: %d, pc: 0x%lx, sp: 0x%lx, fp: 0x%lx, ra: 0x%lx\n", + i, uregs.pc, uregs.sp, uregs.fp, uregs.ra); + if (i >= max_n_ips) + break; + + if (VG_(use_CF_info)( &uregs, fp_min, fp_max )) { + if (sps) sps[i] = uregs.sp; + if (fps) fps[i] = uregs.fp; + ips[i++] = uregs.pc - 1; + if (debug) + VG_(printf)( + "USING CFI: pc: 0x%lx, sp: 0x%lx, fp: 0x%lx, ra: 0x%lx\n", + uregs.pc, uregs.sp, uregs.fp, uregs.ra); + uregs.pc = uregs.pc - 1; + RECURSIVE_MERGE(cmrf,ips,i); + continue; + } + + /* A problem on the first frame? Lets assume it was a bad jump. + We will use the link register and the current stack and frame + pointers and see if we can use the CFI in the next round. */ + if (i == 1) { + uregs.pc = uregs.ra; + uregs.ra = 0; + + if (sps) sps[i] = uregs.sp; + if (fps) fps[i] = uregs.fp; + ips[i++] = uregs.pc - 1; + if (debug) + VG_(printf)( + "USING bad-jump: pc: 0x%lx, sp: 0x%lx, fp: 0x%lx, ra: 0x%lx\n", + uregs.pc, uregs.sp, uregs.fp, uregs.ra); + uregs.pc = uregs.pc - 1; + RECURSIVE_MERGE(cmrf,ips,i); + continue; + } + + /* No luck. We have to give up. */ + break; + } + + n_found = i; + return n_found; +} + +#endif + /*------------------------------------------------------------*/ /*--- ---*/ /*--- END platform-dependent unwinder worker functions ---*/ diff --git a/coregrind/m_syscall.c b/coregrind/m_syscall.c index 1e49ed4..84d30b9 100644 --- a/coregrind/m_syscall.c +++ b/coregrind/m_syscall.c @@ -204,6 +204,17 @@ SysRes VG_(mk_SysRes_arm64_linux) ( Long val ) { return res; } +SysRes VG_(mk_SysRes_loongarch64_linux) ( UWord val ) { + SysRes res; + res._isError = val >= -4095 && val <= -1; + if (res._isError) { + res._val = (UWord)(-val); + } else { + res._val = (UWord)val; + } + return res; +} + /* Generic constructors. */ SysRes VG_(mk_SysRes_Success) ( UWord res ) { SysRes r; @@ -1034,6 +1045,22 @@ asm ( ".previous \n\t" ); +#elif defined(VGP_loongarch64_linux) +extern UWord do_syscall_WRK (UWord a1, UWord a2, UWord a3, /* $a0, $a1, $a2 */ + UWord a4, UWord a5, UWord a6, /* $a3, $a4, $a5 */ + UWord syscall_no); /* $a6 */ +asm ( + ".text \n\t" + ".globl do_syscall_WRK \n\t" + ".type do_syscall_WRK, @function \n\t" + "do_syscall_WRK: \n\t" + " move $a7, $a6 \n\t" /* a7 = syscall_no */ + " syscall 0 \n\t" + " jr $ra \n\t" + ".size do_syscall_WRK, .-do_syscall_WRK \n\t" + ".previous \n\t" +); + #elif defined(VGP_x86_solaris) extern ULong @@ -1274,6 +1301,11 @@ SysRes VG_(do_syscall) ( UWord sysno, RegWord a1, RegWord a2, RegWord a3, do_syscall_WRK(a1, a2, a3, a4, a5, a6, sysno, ®_a0); return VG_(mk_SysRes_nanomips_linux)(reg_a0); +#elif defined(VGP_loongarch64_linux) + UWord val = 0; + val = do_syscall_WRK(a1, a2, a3, a4, a5, a6, sysno); + return VG_(mk_SysRes_loongarch64_linux)(val); + # elif defined(VGP_x86_solaris) UInt val, val2, err = False; Bool restart; diff --git a/coregrind/m_syswrap/priv_syswrap-linux.h b/coregrind/m_syswrap/priv_syswrap-linux.h index 7c9decf..a247334 100644 --- a/coregrind/m_syswrap/priv_syswrap-linux.h +++ b/coregrind/m_syswrap/priv_syswrap-linux.h @@ -509,6 +509,13 @@ extern UInt do_syscall_clone_nanomips_linux ( Word (*fn) (void *), /* a0 - 4 */ Int* child_tid, /* a4 - 8 */ Int* parent_tid, /* a5 - 9 */ void* tls_ptr); /* a6 - 10 */ +extern UInt do_syscall_clone_loongarch64_linux ( Word (*fn) (void *), /* a0 */ + void* stack, /* a1 */ + Int flags, /* a2 */ + void* arg, /* a3 */ + Int* child_tid, /* a4 */ + Int* parent_tid, /* a5 */ + void* tls_ptr); /* a6 */ #endif // __PRIV_SYSWRAP_LINUX_H /*--------------------------------------------------------------------*/ diff --git a/coregrind/m_syswrap/priv_types_n_macros.h b/coregrind/m_syswrap/priv_types_n_macros.h index dd24183..11a9d5e 100644 --- a/coregrind/m_syswrap/priv_types_n_macros.h +++ b/coregrind/m_syswrap/priv_types_n_macros.h @@ -94,7 +94,8 @@ typedef || defined(VGP_ppc32_linux) \ || defined(VGP_arm_linux) || defined(VGP_s390x_linux) \ || defined(VGP_arm64_linux) \ - || defined(VGP_nanomips_linux) + || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) Int o_arg1; Int o_arg2; Int o_arg3; diff --git a/coregrind/m_syswrap/syscall-loongarch64-linux.S b/coregrind/m_syswrap/syscall-loongarch64-linux.S new file mode 100644 index 0000000..5c18041 --- /dev/null +++ b/coregrind/m_syswrap/syscall-loongarch64-linux.S @@ -0,0 +1,143 @@ + +/*--------------------------------------------------------------------*/ +/*--- Support for doing system calls. syscall-loongarch64-linux.S ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#include "pub_core_basics_asm.h" + +#if defined(VGP_loongarch64_linux) + +#include "pub_core_vkiscnums_asm.h" +#include "libvex_guest_offsets.h" + +/*----------------------------------------------------------------*/ +/* + Perform a syscall for the client. This will run a syscall + with the client's specific per-thread signal mask. + + The structure of this function is such that, if the syscall is + interrupted by a signal, we can determine exactly what + execution state we were in with respect to the execution of + the syscall by examining the value of PC in the signal + handler. This means that we can always do the appropriate + thing to precisely emulate the kernel's signal/syscall + interactions. + + The syscall number is taken from the argument, even though it + should also be in guest_state->guest_R11. The syscall result + is written back to guest_state->guest_R4 on completion. + + VG_(fixup_guest_state_after_syscall_interrupted) does the + thread state fixup in the case where we were interrupted by a + signal. + + Prototype: + + UWord ML_(do_syscall_for_client_WRK)( + Int syscallno, // $r4 - a0 + void* guest_state, // $r5 - a1 + const vki_sigset_t *sysmask, // $r6 - a2 + const vki_sigset_t *postmask, // $r7 - a3 + Int nsigwords) // $r8 - a4 +*/ + +/* from vki-loongarch64-linux.h */ +#define VKI_SIG_SETMASK 2 + +.globl ML_(do_syscall_for_client_WRK) +ML_(do_syscall_for_client_WRK): + + /* Save regs on stack */ + addi.d $sp, $sp, -24 + st.d $a1, $sp, 0 /* guest_state */ + st.d $a3, $sp, 8 /* postmask */ + st.d $a4, $sp, 16 /* sigsetSzB */ + +1: li.w $a7, __NR_rt_sigprocmask + li.w $a0, VKI_SIG_SETMASK + move $a1, $a2 /* syscall_mask */ + move $a2, $a3 /* postmask */ + move $a3, $a4 /* sigsetSzB */ + syscall 0 + + bnez $a0, 5f + + /* Actually do the client syscall */ + ld.d $a6, $sp, 0 /* guest_state */ + + ld.d $a0, $a6, OFFSET_loongarch64_R4 /* a0 */ + ld.d $a1, $a6, OFFSET_loongarch64_R5 /* a1 */ + ld.d $a2, $a6, OFFSET_loongarch64_R6 /* a2 */ + ld.d $a3, $a6, OFFSET_loongarch64_R7 /* a3 */ + ld.d $a4, $a6, OFFSET_loongarch64_R8 /* a4 */ + ld.d $a5, $a6, OFFSET_loongarch64_R9 /* a5 */ + + ld.d $a7, $a6, OFFSET_loongarch64_R11 /* syscallno */ + +2: syscall 0 + + /* Saving return values into guest state */ +3: st.d $a0, $a6, OFFSET_loongarch64_R4 /* a0 */ + +4: li.w $a7, __NR_rt_sigprocmask + li.w $a0, VKI_SIG_SETMASK + ld.d $a1, $sp, 8 /* postmask */ + move $a2, $zero /* 0 (zero) */ + ld.d $a3, $sp, 16 /* sigsetSzB */ + syscall 0 + + beqz $a0, 6f + +5: /* error */ + li.w $a0, 0x8000 + +6: /* Restore sp and return */ + addi.d $sp, $sp, 24 + jr $ra + +.section .rodata +/* export the ranges so that + VG_(fixup_guest_state_after_syscall_interrupted) can do the + right thing */ + +.globl ML_(blksys_setup) +.globl ML_(blksys_restart) +.globl ML_(blksys_complete) +.globl ML_(blksys_committed) +.globl ML_(blksys_finished) +ML_(blksys_setup): .quad 1b +ML_(blksys_restart): .quad 2b +ML_(blksys_complete): .quad 3b +ML_(blksys_committed): .quad 4b +ML_(blksys_finished): .quad 5b + +#endif // defined(VGP_loongarch64_linux) + +/* Let the linker know we don't need an executable stack */ +MARK_STACK_NO_EXEC + +/*--------------------------------------------------------------------*/ +/*--- end syscall-loongarch64-linux.S ---*/ +/*--------------------------------------------------------------------*/ diff --git a/coregrind/m_syswrap/syswrap-generic.c b/coregrind/m_syswrap/syswrap-generic.c index d2ff8c0..f3c2317 100644 --- a/coregrind/m_syswrap/syswrap-generic.c +++ b/coregrind/m_syswrap/syswrap-generic.c @@ -3440,7 +3440,7 @@ POST(sys_newfstat) #endif #if !defined(VGO_solaris) && !defined(VGP_arm64_linux) && \ - !defined(VGP_nanomips_linux) + !defined(VGP_nanomips_linux) && !defined(VGP_loongarch64_linux) static vki_sigset_t fork_saved_mask; // In Linux, the sys_fork() function varies across architectures, but we diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c index d571fc3..02a62e4 100644 --- a/coregrind/m_syswrap/syswrap-linux.c +++ b/coregrind/m_syswrap/syswrap-linux.c @@ -310,6 +310,16 @@ static void run_a_thread_NORETURN ( Word tidW ) : "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode) : "memory" , "$t4", "$a0" ); +#elif defined(VGP_loongarch64_linux) + asm volatile ( + "st.w %1, %0 \n\t" /* set tst->status = VgTs_Empty */ + "li.w $a7, %2 \n\t" /* set a7 = __NR_exit */ + "ld.w $a0, %3 \n\t" /* set a0 = tst->os_state.exitcode */ + "syscall 0 \n\t" /* exit(tst->os_state.exitcode) */ + : "=m" (tst->status) + : "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode) + : "memory", "a0", "a7" + ); #else # error Unknown platform #endif @@ -535,6 +545,13 @@ static SysRes clone_new_thread ( Word (*fn)(void *), (ML_(start_thread_NORETURN), stack, flags, ctst, child_tidptr, parent_tidptr, NULL); res = VG_ (mk_SysRes_nanomips_linux) (ret); +#elif defined(VGP_loongarch64_linux) + UInt ret = 0; + ctst->arch.vex.guest_R4 = 0; + ret = do_syscall_clone_loongarch64_linux + (ML_(start_thread_NORETURN), stack, flags, ctst, + child_tidptr, parent_tidptr, NULL); + res = VG_(mk_SysRes_loongarch64_linux)(ret); #else # error Unknown platform #endif @@ -597,6 +614,8 @@ static SysRes setup_child_tls (ThreadId ctid, Addr tlsaddr) #elif defined(VGP_mips32_linux) || defined(VGP_nanomips_linux) ctst->arch.vex.guest_ULR = tlsaddr; ctst->arch.vex.guest_r27 = tlsaddr; +#elif defined(VGP_loongarch64_linux) + ctst->arch.vex.guest_R2 = tlsaddr; #else # error Unknown platform #endif @@ -755,7 +774,7 @@ static SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ || defined(VGP_arm_linux) || defined(VGP_mips32_linux) \ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ - || defined(VGP_nanomips_linux) + || defined(VGP_nanomips_linux) || defined(VGP_loongarch64_linux) res = VG_(do_syscall5)( __NR_clone, flags, (UWord)NULL, (UWord)parent_tidptr, (UWord)NULL, (UWord)child_tidptr ); @@ -828,7 +847,8 @@ PRE(sys_clone) #define PRA_CHILD_TIDPTR PRA5 #define ARG_TLS ARG4 #define PRA_TLS PRA4 -#elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) +#elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \ + || defined(VGP_loongarch64_linux) #define ARG_CHILD_TIDPTR ARG4 #define PRA_CHILD_TIDPTR PRA4 #define ARG_TLS ARG5 @@ -4342,9 +4362,11 @@ PRE(sys_sigaction) PRE_MEM_READ( "sigaction(act->sa_handler)", (Addr)&sa->ksa_handler, sizeof(sa->ksa_handler)); PRE_MEM_READ( "sigaction(act->sa_mask)", (Addr)&sa->sa_mask, sizeof(sa->sa_mask)); PRE_MEM_READ( "sigaction(act->sa_flags)", (Addr)&sa->sa_flags, sizeof(sa->sa_flags)); +#if !defined(VGP_loongarch64_linux) if (ML_(safe_to_deref)(sa,sizeof(struct vki_old_sigaction)) && (sa->sa_flags & VKI_SA_RESTORER)) PRE_MEM_READ( "sigaction(act->sa_restorer)", (Addr)&sa->sa_restorer, sizeof(sa->sa_restorer)); +#endif } if (ARG3 != 0) { @@ -4374,7 +4396,9 @@ PRE(sys_sigaction) new.ksa_handler = oldnew->ksa_handler; new.sa_flags = oldnew->sa_flags; +#if !defined(VGP_loongarch64_linux) new.sa_restorer = oldnew->sa_restorer; +#endif convert_sigset_to_rt(&oldnew->sa_mask, &new.sa_mask); newp = &new; } @@ -4387,7 +4411,9 @@ PRE(sys_sigaction) oldold->ksa_handler = oldp->ksa_handler; oldold->sa_flags = oldp->sa_flags; +#if !defined(VGP_loongarch64_linux) oldold->sa_restorer = oldp->sa_restorer; +#endif oldold->sa_mask = oldp->sa_mask.sig[0]; } } @@ -4460,10 +4486,13 @@ PRE(sys_rt_sigaction) PRE_MEM_READ( "rt_sigaction(act->sa_handler)", (Addr)&sa->ksa_handler, sizeof(sa->ksa_handler)); PRE_MEM_READ( "rt_sigaction(act->sa_mask)", (Addr)&sa->sa_mask, sizeof(sa->sa_mask)); PRE_MEM_READ( "rt_sigaction(act->sa_flags)", (Addr)&sa->sa_flags, sizeof(sa->sa_flags)); +#if !defined(VGP_loongarch64_linux) if (ML_(safe_to_deref)(sa,sizeof(vki_sigaction_toK_t)) && (sa->sa_flags & VKI_SA_RESTORER)) PRE_MEM_READ( "rt_sigaction(act->sa_restorer)", (Addr)&sa->sa_restorer, sizeof(sa->sa_restorer)); +#endif } + if (ARG3 != 0) PRE_MEM_WRITE( "rt_sigaction(oldact)", ARG3, sizeof(vki_sigaction_fromK_t)); @@ -6815,7 +6844,8 @@ POST(sys_lookup_dcookie) #endif #if defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \ - || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) + || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) PRE(sys_lookup_dcookie) { *flags |= SfMayBlock; diff --git a/coregrind/m_syswrap/syswrap-loongarch64-linux.c b/coregrind/m_syswrap/syswrap-loongarch64-linux.c new file mode 100644 index 0000000..c684112 --- /dev/null +++ b/coregrind/m_syswrap/syswrap-loongarch64-linux.c @@ -0,0 +1,644 @@ + +/*---------------------------------------------------------------------*/ +/*--- Platform-specific syscalls stuff. syswrap-loongarch64-linux.c ---*/ +/*---------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#if defined(VGP_loongarch64_linux) + +#include "pub_core_basics.h" +#include "pub_core_vki.h" +#include "pub_core_vkiscnums.h" +#include "pub_core_threadstate.h" +#include "pub_core_aspacemgr.h" +#include "pub_core_libcbase.h" +#include "pub_core_libcassert.h" +#include "pub_core_libcprint.h" +#include "pub_core_libcsignal.h" +#include "pub_core_options.h" +#include "pub_core_scheduler.h" +#include "pub_core_sigframe.h" // For VG_(sigframe_destroy)() +#include "pub_core_syscall.h" +#include "pub_core_syswrap.h" +#include "pub_core_tooliface.h" + +#include "priv_types_n_macros.h" +#include "priv_syswrap-generic.h" /* for decls of generic wrappers */ +#include "priv_syswrap-linux.h" /* for decls of linux-ish wrappers */ +#include "priv_syswrap-main.h" + + +/* --------------------------------------------------------------------- + clone() handling + ------------------------------------------------------------------ */ + +/* Call f(arg1), but first switch stacks, using 'stack' as the new + stack, and use 'retaddr' as f's return-to address. Also, clear all + the integer registers before entering f. */ +__attribute__((noreturn)) +void ML_(call_on_new_stack_0_1) ( Addr stack, + Addr retaddr, + void (*f) (Word), + Word arg1 ); +asm ( +".text\n" +".globl vgModuleLocal_call_on_new_stack_0_1 \n\t" +"vgModuleLocal_call_on_new_stack_0_1: \n\t" +" move $sp, $a0 \n\t" /* sp = stack */ +" move $ra, $a1 \n\t" /* ra = retaddr */ +" move $t0, $a2 \n\t" /* t0 = f */ +" move $a0, $a3 \n\t" /* a0 = arg1 */ +" move $a1, $zero \n\t" /* zero all GP regs */ +" move $a2, $zero \n\t" +" move $a3, $zero \n\t" +" move $a4, $zero \n\t" +" move $a5, $zero \n\t" +" move $a6, $zero \n\t" +" move $a7, $zero \n\t" +/* don't zero out t0 */ +" move $t1, $zero \n\t" +" move $t2, $zero \n\t" +" move $t3, $zero \n\t" +" move $t4, $zero \n\t" +" move $t5, $zero \n\t" +" move $t6, $zero \n\t" +" move $t7, $zero \n\t" +" move $t8, $zero \n\t" +" jr $t0 \n\t" /* jump to f */ +".previous \n\t" +); + +/* + Perform a clone system call. clone is strange because it has + fork()-like return-twice semantics, so it needs special + handling here. + + Upon entry, we have: + + Word (*fn)(void*) in a0 + void* child_stack in a1 + int flags in a2 + void* arg in a3 + pid_t* child_tid in a4 + pid_t* parent_tid in a5 + void* tls_ptr in a6 + + System call requires: + + unsigned long clone_flags in a0 + unsigned long newsp in a1 + int* parent_tidptr in a2 + int* child_tidptr in a3 + unsigned long tls in a4 + int __NR_clone in a7 +*/ + +#define __NR_CLONE VG_STRINGIFY(__NR_clone) +#define __NR_EXIT VG_STRINGIFY(__NR_exit) + +// See priv_syswrap-linux.h for arg profile. +asm( +".text \n\t" +".globl do_syscall_clone_loongarch64_linux \n\t" +"do_syscall_clone_loongarch64_linux: \n\t" +/* Save ra */ +" addi.d $sp, $sp, -16 \n\t" +" st.d $ra, $sp, 0 \n\t" + +/* Save fn and arg */ +" addi.d $a1, $a1, -16 \n\t" +" st.d $a0, $a1, 0 \n\t" /* fn */ +" st.d $a3, $a1, 8 \n\t" /* arg */ + +/* Call sys_clone */ +" move $a0, $a2 \n\t" /* flags */ +" move $a2, $a5 \n\t" /* parent */ +" move $a3, $a4 \n\t" /* child */ +" move $a4, $a6 \n\t" /* tls */ +" li.w $a7, " __NR_CLONE " \n\t" +" syscall 0 \n\t" + +/* If we are a child? */ +" bnez $a0, 1f \n\t" + +/* Restore fn and arg */ +" ld.d $a1, $sp, 0 \n\t" /* fn */ +" ld.d $a0, $sp, 8 \n\t" /* arg */ + +/* Call fn(arg) */ +" jr $a1 \n\t" + +/* Call exit(a0) */ +" li.w $a7, " __NR_EXIT" \n\t" +" syscall 0 \n\t" + +/* If we are parent or error, just return to caller */ +"1: \n\t" +" ld.d $ra, $sp, 0 \n\t" +" addi.d $sp, $sp, 16 \n\t" +" jr $ra \n\t" +".previous \n\t" +); + +#undef __NR_CLONE +#undef __NR_EXIT + +/* --------------------------------------------------------------------- + More thread stuff + ------------------------------------------------------------------ */ + +// loongarch64 doesn't have any architecture specific thread stuff that +// needs to be cleaned up +void VG_(cleanup_thread) ( ThreadArchState* arch ) +{ +} + +/* --------------------------------------------------------------------- + PRE/POST wrappers for loongarch64/Linux-specific syscalls + ------------------------------------------------------------------ */ + +#define PRE(name) DEFN_PRE_TEMPLATE(loongarch64_linux, name) +#define POST(name) DEFN_POST_TEMPLATE(loongarch64_linux, name) + +/* Add prototypes for the wrappers declared here, so that gcc doesn't + harass us for not having prototypes. Really this is a kludge -- + the right thing to do is to make these wrappers 'static' since they + aren't visible outside this file, but that requires even more macro + magic. */ +DECL_TEMPLATE(loongarch64_linux, sys_ptrace); +DECL_TEMPLATE(loongarch64_linux, sys_mmap); +DECL_TEMPLATE(loongarch64_linux, sys_rt_sigreturn); + +PRE(sys_ptrace) +{ + PRINT("sys_ptrace ( %ld, %ld, %lx, %lx )", + SARG1, SARG2, ARG3, ARG4); + PRE_REG_READ4(int, "ptrace", + long, request, + long, pid, + unsigned long, addr, + unsigned long, data); + switch (ARG1) { + case VKI_PTRACE_PEEKTEXT: + case VKI_PTRACE_PEEKDATA: + case VKI_PTRACE_PEEKUSR: + PRE_MEM_WRITE("ptrace(peek)", ARG4, sizeof(long)); + break; + case VKI_PTRACE_GETEVENTMSG: + PRE_MEM_WRITE("ptrace(geteventmsg)", ARG4, sizeof(unsigned long)); + break; + case VKI_PTRACE_GETSIGINFO: + PRE_MEM_WRITE("ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t)); + break; + case VKI_PTRACE_SETSIGINFO: + PRE_MEM_READ("ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t)); + break; + case VKI_PTRACE_GETREGSET: + ML_(linux_PRE_getregset)(tid, ARG3, ARG4); + break; + default: + break; + } +} + +POST(sys_ptrace) +{ + switch (ARG1) { + case VKI_PTRACE_TRACEME: + ML_(linux_POST_traceme)(tid); + break; + case VKI_PTRACE_PEEKTEXT: + case VKI_PTRACE_PEEKDATA: + case VKI_PTRACE_PEEKUSR: + POST_MEM_WRITE (ARG4, sizeof(long)); + break; + case VKI_PTRACE_GETEVENTMSG: + POST_MEM_WRITE (ARG4, sizeof(unsigned long)); + break; + case VKI_PTRACE_GETSIGINFO: + POST_MEM_WRITE (ARG4, sizeof(vki_siginfo_t)); + break; + case VKI_PTRACE_GETREGSET: + ML_(linux_POST_getregset)(tid, ARG3, ARG4); + break; + default: + break; + } +} + +PRE(sys_mmap) +{ + SysRes r; + + PRINT("sys_mmap ( %#lx, %lu, %lu, %#lx, %lu, %lu )", + ARG1, ARG2, ARG3, ARG4, ARG5, ARG6 ); + PRE_REG_READ6(long, "mmap", + unsigned long, addr, unsigned long, len, + unsigned long, prot, unsigned long, flags, + unsigned long, fd, vki_off_t, offset); + + r = ML_(generic_PRE_sys_mmap)( tid, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6 ); + SET_STATUS_from_SysRes(r); +} + +PRE(sys_rt_sigreturn) +{ + /* See comments on PRE(sys_rt_sigreturn) in syswrap-loongarch64-linux.c for + an explanation of what follows. */ + ThreadState* tst; + PRINT("rt_sigreturn ( )"); + + vg_assert(VG_(is_valid_tid)(tid)); + vg_assert(tid >= 1 && tid < VG_N_THREADS); + vg_assert(VG_(is_running_thread)(tid)); + + tst = VG_(get_ThreadState)(tid); + + /* This is only so that the PC is (might be) useful to report if + something goes wrong in the sigreturn */ + ML_(fixup_guest_state_to_restart_syscall)(&tst->arch); + + /* Restore register state from frame and remove it */ + VG_(sigframe_destroy)(tid, True); + + /* Tell the driver not to update the guest state with the "result", + and set a bogus result to keep it happy. */ + *flags |= SfNoWriteResult; + SET_STATUS_Success(0); + + /* Check to see if any signals arose as a result of this. */ + *flags |= SfPollAfter; +} + +#undef PRE +#undef POST + +/* --------------------------------------------------------------------- + The loongarch64/Linux syscall table + ------------------------------------------------------------------ */ + +#define PLAX_(sysno, name) WRAPPER_ENTRY_X_(loongarch64_linux, sysno, name) +#define PLAXY(sysno, name) WRAPPER_ENTRY_XY(loongarch64_linux, sysno, name) + +// This table maps from __NR_xxx syscall numbers (from +// linux/include/uapi/asm-generic/unistd.h) to the appropriate PRE/POST +// sys_foo() wrappers on loongarch64 (as per sys_call_table in +// linux/arch/loongarch/kernel/syscall.c). +// +// For those syscalls not handled by Valgrind, the annotation indicate its +// arch/OS combination, eg. */* (generic), */Linux (Linux only), ?/? +// (unknown). + +static SyscallTableEntry syscall_main_table[] = { + LINXY(__NR_io_setup, sys_io_setup), // 0 + LINX_(__NR_io_destroy, sys_io_destroy), // 1 + LINX_(__NR_io_submit, sys_io_submit), // 2 + LINXY(__NR_io_cancel, sys_io_cancel), // 3 + LINXY(__NR_io_getevents, sys_io_getevents), // 4 + LINX_(__NR_setxattr, sys_setxattr), // 5 + LINX_(__NR_lsetxattr, sys_lsetxattr), // 6 + LINX_(__NR_fsetxattr, sys_fsetxattr), // 7 + LINXY(__NR_getxattr, sys_getxattr), // 8 + LINXY(__NR_lgetxattr, sys_lgetxattr), // 9 + LINXY(__NR_fgetxattr, sys_fgetxattr), // 10 + LINXY(__NR_listxattr, sys_listxattr), // 11 + LINXY(__NR_llistxattr, sys_llistxattr), // 12 + LINXY(__NR_flistxattr, sys_flistxattr), // 13 + LINX_(__NR_removexattr, sys_removexattr), // 14 + LINX_(__NR_lremovexattr, sys_lremovexattr), // 15 + LINX_(__NR_fremovexattr, sys_fremovexattr), // 16 + GENXY(__NR_getcwd, sys_getcwd), // 17 + LINXY(__NR_lookup_dcookie, sys_lookup_dcookie), // 18 + LINXY(__NR_eventfd2, sys_eventfd2), // 19 + LINXY(__NR_epoll_create1, sys_epoll_create1), // 20 + LINX_(__NR_epoll_ctl, sys_epoll_ctl), // 21 + LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 22 + GENXY(__NR_dup, sys_dup), // 23 + LINXY(__NR_dup3, sys_dup3), // 24 + LINXY(__NR3264_fcntl, sys_fcntl), // 25 + LINXY(__NR_inotify_init1, sys_inotify_init1), // 26 + LINX_(__NR_inotify_add_watch, sys_inotify_add_watch), // 27 + LINX_(__NR_inotify_rm_watch, sys_inotify_rm_watch), // 28 + LINXY(__NR_ioctl, sys_ioctl), // 29 + LINX_(__NR_ioprio_set, sys_ioprio_set), // 30 + LINX_(__NR_ioprio_get, sys_ioprio_get), // 31 + GENX_(__NR_flock, sys_flock), // 32 + LINX_(__NR_mknodat, sys_mknodat), // 33 + LINX_(__NR_mkdirat, sys_mkdirat), // 34 + LINX_(__NR_unlinkat, sys_unlinkat), // 35 + LINX_(__NR_symlinkat, sys_symlinkat), // 36 + LINX_(__NR_linkat, sys_linkat), // 37 + // (__NR_renameat, sys_renameat), // 38 + LINX_(__NR_umount2, sys_umount), // 39 + LINX_(__NR_mount, sys_mount), // 40 + LINX_(__NR_pivot_root, sys_pivot_root), // 41 + // (__NR_nfsservctl, sys_ni_syscall), // 42 + GENXY(__NR3264_statfs, sys_statfs), // 43 + GENXY(__NR3264_fstatfs, sys_fstatfs), // 44 + GENX_(__NR3264_truncate, sys_truncate), // 45 + GENX_(__NR3264_ftruncate, sys_ftruncate), // 46 + LINX_(__NR_fallocate, sys_fallocate), // 47 + LINX_(__NR_faccessat, sys_faccessat), // 48 + GENX_(__NR_chdir, sys_chdir), // 49 + GENX_(__NR_fchdir, sys_fchdir), // 50 + GENX_(__NR_chroot, sys_chroot), // 51 + GENX_(__NR_fchmod, sys_fchmod), // 52 + LINX_(__NR_fchmodat, sys_fchmodat), // 53 + LINX_(__NR_fchownat, sys_fchownat), // 54 + GENX_(__NR_fchown, sys_fchown), // 55 + LINXY(__NR_openat, sys_openat), // 56 + GENXY(__NR_close, sys_close), // 57 + LINX_(__NR_vhangup, sys_vhangup), // 58 + LINXY(__NR_pipe2, sys_pipe2), // 59 + LINX_(__NR_quotactl, sys_quotactl), // 60 + GENXY(__NR_getdents64, sys_getdents64), // 61 + LINX_(__NR3264_lseek, sys_lseek), // 62 + GENXY(__NR_read, sys_read), // 63 + GENX_(__NR_write, sys_write), // 64 + GENXY(__NR_readv, sys_readv), // 65 + GENX_(__NR_writev, sys_writev), // 66 + GENXY(__NR_pread64, sys_pread64), // 67 + GENX_(__NR_pwrite64, sys_pwrite64), // 68 + LINXY(__NR_preadv, sys_preadv), // 69 + LINX_(__NR_pwritev, sys_pwritev), // 70 + LINXY(__NR3264_sendfile, sys_sendfile), // 71 + LINXY(__NR_pselect6, sys_pselect6), // 72 + LINXY(__NR_ppoll, sys_ppoll), // 73 + LINXY(__NR_signalfd4, sys_signalfd4), // 74 + LINX_(__NR_vmsplice, sys_vmsplice), // 75 + LINX_(__NR_splice, sys_splice), // 76 + LINX_(__NR_tee, sys_tee), // 77 + LINX_(__NR_readlinkat, sys_readlinkat), // 78 + LINXY(__NR3264_fstatat, sys_newfstatat), // 79 + GENXY(__NR3264_fstat, sys_newfstat), // 80 + GENX_(__NR_sync, sys_sync), // 81 + GENX_(__NR_fsync, sys_fsync), // 82 + GENX_(__NR_fdatasync, sys_fdatasync), // 83 + LINX_(__NR_sync_file_range, sys_sync_file_range), // 84 + LINXY(__NR_timerfd_create, sys_timerfd_create), // 85 + LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 86 + LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 87 + LINX_(__NR_utimensat, sys_utimensat), // 88 + GENX_(__NR_acct, sys_acct), // 89 + LINXY(__NR_capget, sys_capget), // 90 + LINX_(__NR_capset, sys_capset), // 91 + LINX_(__NR_personality, sys_personality), // 92 + GENX_(__NR_exit, sys_exit), // 93 + LINX_(__NR_exit_group, sys_exit_group), // 94 + LINXY(__NR_waitid, sys_waitid), // 95 + LINX_(__NR_set_tid_address, sys_set_tid_address), // 96 + LINX_(__NR_unshare, sys_unshare), // 97 + LINXY(__NR_futex, sys_futex), // 98 + LINX_(__NR_set_robust_list, sys_set_robust_list), // 99 + LINXY(__NR_get_robust_list, sys_get_robust_list), // 100 + GENXY(__NR_nanosleep, sys_nanosleep), // 101 + GENXY(__NR_getitimer, sys_getitimer), // 102 + GENXY(__NR_setitimer, sys_setitimer), // 103 + // (__NR_kexec_load, sys_kexec_load), // 104 + LINX_(__NR_init_module, sys_init_module), // 105 + LINX_(__NR_delete_module, sys_delete_module), // 106 + LINXY(__NR_timer_create, sys_timer_create), // 107 + LINXY(__NR_timer_gettime, sys_timer_gettime), // 108 + LINX_(__NR_timer_getoverrun, sys_timer_getoverrun), // 109 + LINXY(__NR_timer_settime, sys_timer_settime), // 110 + LINX_(__NR_timer_delete, sys_timer_delete), // 111 + LINX_(__NR_clock_settime, sys_clock_settime), // 112 + LINXY(__NR_clock_gettime, sys_clock_gettime), // 113 + LINXY(__NR_clock_getres, sys_clock_getres), // 114 + LINXY(__NR_clock_nanosleep, sys_clock_nanosleep), // 115 + LINXY(__NR_syslog, sys_syslog), // 116 + PLAXY(__NR_ptrace, sys_ptrace), // 117 + LINXY(__NR_sched_setparam, sys_sched_setparam), // 118 + LINX_(__NR_sched_setscheduler, sys_sched_setscheduler), // 119 + LINX_(__NR_sched_getscheduler, sys_sched_getscheduler), // 120 + LINXY(__NR_sched_getparam, sys_sched_getparam), // 121 + LINX_(__NR_sched_setaffinity, sys_sched_setaffinity), // 122 + LINXY(__NR_sched_getaffinity, sys_sched_getaffinity), // 123 + LINX_(__NR_sched_yield, sys_sched_yield), // 124 + LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max), // 125 + LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min), // 126 + LINXY(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 127 + // (__NR_restart_syscall, sys_restart_syscall), // 128 + GENX_(__NR_kill, sys_kill), // 129 + LINXY(__NR_tkill, sys_tkill), // 130 + LINX_(__NR_tgkill, sys_tgkill), // 131 + GENXY(__NR_sigaltstack, sys_sigaltstack), // 132 + LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 133 + LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 134 + LINXY(__NR_rt_sigprocmask, sys_rt_sigprocmask), // 135 + LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 136 + LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait), // 137 + LINXY(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo), // 138 + PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 139 + GENX_(__NR_setpriority, sys_setpriority), // 140 + GENX_(__NR_getpriority, sys_getpriority), // 141 + // (__NR_reboot, sys_reboot), // 142 + GENX_(__NR_setregid, sys_setregid), // 143 + GENX_(__NR_setgid, sys_setgid), // 144 + GENX_(__NR_setreuid, sys_setreuid), // 145 + GENX_(__NR_setuid, sys_setuid), // 146 + LINX_(__NR_setresuid, sys_setresuid), // 147 + LINXY(__NR_getresuid, sys_getresuid), // 148 + LINX_(__NR_setresgid, sys_setresgid), // 149 + LINXY(__NR_getresgid, sys_getresgid), // 150 + LINX_(__NR_setfsuid, sys_setfsuid), // 151 + LINX_(__NR_setfsgid, sys_setfsgid), // 152 + GENXY(__NR_times, sys_times), // 153 + GENX_(__NR_setpgid, sys_setpgid), // 154 + GENX_(__NR_getpgid, sys_getpgid), // 155 + GENX_(__NR_getsid, sys_getsid), // 156 + GENX_(__NR_setsid, sys_setsid), // 157 + GENXY(__NR_getgroups, sys_getgroups), // 158 + GENX_(__NR_setgroups, sys_setgroups), // 159 + GENXY(__NR_uname, sys_newuname), // 160 + GENX_(__NR_sethostname, sys_sethostname), // 161 + // (__NR_setdomainname, sys_setdomainname), // 162 + // (__NR_getrlimit, sys_old_getrlimit), // 163 + // (__NR_setrlimit, sys_setrlimit), // 164 + GENXY(__NR_getrusage, sys_getrusage), // 165 + GENX_(__NR_umask, sys_umask), // 166 + LINXY(__NR_prctl, sys_prctl), // 167 + LINXY(__NR_getcpu, sys_getcpu), // 168 + GENXY(__NR_gettimeofday, sys_gettimeofday), // 169 + GENX_(__NR_settimeofday, sys_settimeofday), // 170 + LINXY(__NR_adjtimex, sys_adjtimex), // 171 + GENX_(__NR_getpid, sys_getpid), // 172 + GENX_(__NR_getppid, sys_getppid), // 173 + GENX_(__NR_getuid, sys_getuid), // 174 + GENX_(__NR_geteuid, sys_geteuid), // 175 + GENX_(__NR_getgid, sys_getgid), // 176 + GENX_(__NR_getegid, sys_getegid), // 177 + LINX_(__NR_gettid, sys_gettid), // 178 + LINXY(__NR_sysinfo, sys_sysinfo), // 179 + LINXY(__NR_mq_open, sys_mq_open), // 180 + LINX_(__NR_mq_unlink, sys_mq_unlink), // 181 + LINX_(__NR_mq_timedsend, sys_mq_timedsend), // 182 + LINXY(__NR_mq_timedreceive, sys_mq_timedreceive), // 183 + LINX_(__NR_mq_notify, sys_mq_notify), // 184 + LINXY(__NR_mq_getsetattr, sys_mq_getsetattr), // 185 + LINX_(__NR_msgget, sys_msgget), // 186 + LINXY(__NR_msgctl, sys_msgctl), // 187 + LINXY(__NR_msgrcv, sys_msgrcv), // 188 + LINX_(__NR_msgsnd, sys_msgsnd), // 189 + LINX_(__NR_semget, sys_semget), // 190 + LINXY(__NR_semctl, sys_semctl), // 191 + LINX_(__NR_semtimedop, sys_semtimedop), // 192 + LINX_(__NR_semop, sys_semop), // 193 + LINX_(__NR_shmget, sys_shmget), // 194 + LINXY(__NR_shmctl, sys_shmctl), // 195 + LINXY(__NR_shmat, sys_shmat), // 196 + LINXY(__NR_shmdt, sys_shmdt), // 197 + LINXY(__NR_socket, sys_socket), // 198 + LINXY(__NR_socketpair, sys_socketpair), // 199 + LINX_(__NR_bind, sys_bind), // 200 + LINX_(__NR_listen, sys_listen), // 201 + LINXY(__NR_accept, sys_accept), // 202 + LINX_(__NR_connect, sys_connect), // 203 + LINXY(__NR_getsockname, sys_getsockname), // 204 + LINXY(__NR_getpeername, sys_getpeername), // 205 + LINX_(__NR_sendto, sys_sendto), // 206 + LINXY(__NR_recvfrom, sys_recvfrom), // 207 + LINX_(__NR_setsockopt, sys_setsockopt), // 208 + LINXY(__NR_getsockopt, sys_getsockopt), // 209 + LINX_(__NR_shutdown, sys_shutdown), // 210 + LINX_(__NR_sendmsg, sys_sendmsg), // 211 + LINXY(__NR_recvmsg, sys_recvmsg), // 212 + LINX_(__NR_readahead, sys_readahead), // 213 + GENX_(__NR_brk, sys_brk), // 214 + GENXY(__NR_munmap, sys_munmap), // 215 + GENX_(__NR_mremap, sys_mremap), // 216 + LINX_(__NR_add_key, sys_add_key), // 217 + LINX_(__NR_request_key, sys_request_key), // 218 + LINXY(__NR_keyctl, sys_keyctl), // 219 + LINX_(__NR_clone, sys_clone), // 220 + GENX_(__NR_execve, sys_execve), // 221 + PLAX_(__NR3264_mmap, sys_mmap), // 222 + LINX_(__NR3264_fadvise64, sys_fadvise64), // 223 + // (__NR_swapon, sys_swapon), // 224 + // (__NR_swapoff, sys_swapoff), // 225 + GENXY(__NR_mprotect, sys_mprotect), // 226 + GENX_(__NR_msync, sys_msync), // 227 + GENX_(__NR_mlock, sys_mlock), // 228 + GENX_(__NR_munlock, sys_munlock), // 229 + GENX_(__NR_mlockall, sys_mlockall), // 230 + LINX_(__NR_munlockall, sys_munlockall), // 231 + GENXY(__NR_mincore, sys_mincore), // 232 + GENX_(__NR_madvise, sys_madvise), // 233 + // (__NR_remap_file_pages, sys_remap_file_pages), // 234 + LINX_(__NR_mbind, sys_mbind), // 235 + LINXY(__NR_get_mempolicy, sys_get_mempolicy), // 236 + LINX_(__NR_set_mempolicy, sys_set_mempolicy), // 237 + // (__NR_migrate_pages, sys_migrate_pages), // 238 + LINXY(__NR_move_pages, sys_move_pages), // 239 + LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo), // 240 + LINXY(__NR_perf_event_open, sys_perf_event_open), // 241 + LINXY(__NR_accept4, sys_accept4), // 242 + LINXY(__NR_recvmmsg, sys_recvmmsg), // 243 + + GENXY(__NR_wait4, sys_wait4), // 260 + LINXY(__NR_prlimit64, sys_prlimit64), // 261 + LINXY(__NR_fanotify_init, sys_fanotify_init), // 262 + LINX_(__NR_fanotify_mark, sys_fanotify_mark), // 263 + LINXY(__NR_name_to_handle_at, sys_name_to_handle_at), // 264 + LINXY(__NR_open_by_handle_at, sys_open_by_handle_at), // 265 + LINXY(__NR_clock_adjtime, sys_clock_adjtime), // 266 + LINX_(__NR_syncfs, sys_syncfs), // 267 + LINX_(__NR_setns, sys_setns), // 268 + LINXY(__NR_sendmmsg, sys_sendmmsg), // 269 + LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 270 + LINX_(__NR_process_vm_writev, sys_process_vm_writev), // 271 + LINX_(__NR_kcmp, sys_kcmp), // 272 + LINX_(__NR_finit_module, sys_finit_module), // 273 + // (__NR_sched_setattr, sys_sched_setattr), // 274 + // (__NR_sched_getattr, sys_sched_getattr), // 275 + LINX_(__NR_renameat2, sys_renameat2), // 276 + // (__NR_seccomp, sys_seccomp), // 277 + LINXY(__NR_getrandom, sys_getrandom), // 278 + LINXY(__NR_memfd_create, sys_memfd_create), // 279 + LINXY(__NR_bpf, sys_bpf), // 280 + // (__NR_execveat, sys_execveat), // 281 + // (__NR_userfaultfd, sys_userfaultfd), // 282 + LINX_(__NR_membarrier, sys_membarrier), // 283 + // (__NR_mlock2, sys_mlock2), // 284 + LINX_(__NR_copy_file_range, sys_copy_file_range), // 285 + LINXY(__NR_preadv2, sys_preadv2), // 286 + LINX_(__NR_pwritev2, sys_pwritev2), // 287 + // (__NR_pkey_mprotect, sys_pkey_mprotect), // 288 + // (__NR_pkey_alloc, sys_pkey_alloc), // 289 + // (__NR_pkey_free, sys_pkey_free), // 290 + LINXY(__NR_statx, sys_statx), // 291 + // (__NR_io_pgetevents, sys_io_pgetevents), // 292 + // (__NR_rseq, sys_rseq), // 293 + // (__NR_kexec_file_load, sys_kexec_file_load), // 294 + + // (__NR_pidfd_send_signal, sys_pidfd_send_signal), // 424 + LINXY(__NR_io_uring_setup, sys_io_uring_setup), // 425 + LINXY(__NR_io_uring_enter, sys_io_uring_enter), // 426 + LINXY(__NR_io_uring_register, sys_io_uring_register), // 427 + // (__NR_open_tree, sys_open_tree), // 428 + // (__NR_move_mount, sys_move_mount), // 429 + // (__NR_fsopen, sys_fsopen), // 430 + // (__NR_fsconfig, sys_fsconfig), // 431 + // (__NR_fsmount, sys_fsmount), // 432 + // (__NR_fspick, sys_fspick), // 433 + // (__NR_pidfd_open, sys_pidfd_open), // 434 + GENX_(__NR_clone3, sys_ni_syscall), // 435 + // (__NR_close_range, sys_close_range), // 436 + // (__NR_openat2, sys_openat2), // 437 + // (__NR_pidfd_getfd, sys_pidfd_getfd), // 438 + // (__NR_faccessat2, sys_faccessat2), // 439 + // (__NR_process_madvise, sys_process_madvise), // 440 + // (__NR_epoll_pwait2, sys_epoll_pwait2), // 441 + // (__NR_mount_setattr, sys_mount_setattr), // 442 + // (__NR_quotactl_fd, sys_quotactl_fd), // 443 + // (__NR_landlock_create_ruleset, sys_landlock_create_ruleset), // 444 + // (__NR_landlock_add_rule, sys_landlock_add_rule), // 445 + // (__NR_landlock_restrict_self, sys_landlock_restrict_self), // 446 + // (__NR_memfd_secret, sys_memfd_secret), // 447 + // (__NR_process_mrelease, sys_process_mrelease), // 448 +}; + +SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno ) +{ + const UInt syscall_main_table_size + = sizeof(syscall_main_table) / sizeof(syscall_main_table[0]); + + /* Is it in the contiguous initial section of the table? */ + if (sysno < syscall_main_table_size) { + SyscallTableEntry* sys = &syscall_main_table[sysno]; + if (sys->before == NULL) + return NULL; /* no entry */ + else + return sys; + } + + /* Can't find a wrapper */ + return NULL; +} + +#endif /* defined(VGP_loongarch64_linux) */ + +/*--------------------------------------------------------------------*/ +/*--- end syswrap-loongarch64-linux.c ---*/ +/*--------------------------------------------------------------------*/ diff --git a/coregrind/m_syswrap/syswrap-main.c b/coregrind/m_syswrap/syswrap-main.c index 91a1f7e..cd32e39 100644 --- a/coregrind/m_syswrap/syswrap-main.c +++ b/coregrind/m_syswrap/syswrap-main.c @@ -60,20 +60,21 @@ /* Useful info which needs to be recorded somewhere: Use of registers in syscalls is: - NUM ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 ARG8 RESULT + NUM ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 ARG8 RESULT LINUX: - x86 eax ebx ecx edx esi edi ebp n/a n/a eax (== NUM) - amd64 rax rdi rsi rdx r10 r8 r9 n/a n/a rax (== NUM) - ppc32 r0 r3 r4 r5 r6 r7 r8 n/a n/a r3+CR0.SO (== ARG1) - ppc64 r0 r3 r4 r5 r6 r7 r8 n/a n/a r3+CR0.SO (== ARG1) - arm r7 r0 r1 r2 r3 r4 r5 n/a n/a r0 (== ARG1) - mips32 v0 a0 a1 a2 a3 stack stack n/a n/a v0 (== NUM) - mips64 v0 a0 a1 a2 a3 a4 a5 a6 a7 v0 (== NUM) - arm64 x8 x0 x1 x2 x3 x4 x5 n/a n/a x0 ?? (== ARG1??) + x86 eax ebx ecx edx esi edi ebp n/a n/a eax (== NUM) + amd64 rax rdi rsi rdx r10 r8 r9 n/a n/a rax (== NUM) + ppc32 r0 r3 r4 r5 r6 r7 r8 n/a n/a r3+CR0.SO (== ARG1) + ppc64 r0 r3 r4 r5 r6 r7 r8 n/a n/a r3+CR0.SO (== ARG1) + arm r7 r0 r1 r2 r3 r4 r5 n/a n/a r0 (== ARG1) + mips32 v0 a0 a1 a2 a3 stack stack n/a n/a v0 (== NUM) + mips64 v0 a0 a1 a2 a3 a4 a5 a6 a7 v0 (== NUM) + arm64 x8 x0 x1 x2 x3 x4 x5 n/a n/a x0 ?? (== ARG1??) + loongarch64 r11 r4 r5 r6 r7 r8 r9 n/a n/a r4 (== ARG1) FreeBSD: - x86 eax +4 +8 +12 +16 +20 +24 +28 +32 edx:eax, eflags.c - amd64 rax rdi rsi rdx rcx r8 r9 +8 +16 rdx:rax, rflags.c + x86 eax +4 +8 +12 +16 +20 +24 +28 +32 edx:eax, eflags.c + amd64 rax rdi rsi rdx rcx r8 r9 +8 +16 rdx:rax, rflags.c On s390x the svc instruction is used for system calls. The system call number is encoded in the instruction (8 bit immediate field). Since Linux @@ -703,6 +704,17 @@ void getSyscallArgsFromGuestState ( /*OUT*/SyscallArgs* canonical, canonical->arg6 = gst->guest_r9; // a5 canonical->arg7 = gst->guest_r10; // a6 canonical->arg8 = gst->guest_r11; // a7 + +#elif defined(VGP_loongarch64_linux) + VexGuestLOONGARCH64State* gst = (VexGuestLOONGARCH64State*)gst_vanilla; + canonical->sysno = gst->guest_R11; // a7 + canonical->arg1 = gst->guest_R4; // a0 + canonical->arg2 = gst->guest_R5; // a1 + canonical->arg3 = gst->guest_R6; // a2 + canonical->arg4 = gst->guest_R7; // a3 + canonical->arg5 = gst->guest_R8; // a4 + canonical->arg6 = gst->guest_R9; // a5 + #elif defined(VGP_x86_darwin) VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; UWord *stack = (UWord *)gst->guest_ESP; @@ -1126,6 +1138,16 @@ void putSyscallArgsIntoGuestState ( /*IN*/ SyscallArgs* canonical, gst->guest_r10 = canonical->arg7; gst->guest_r11 = canonical->arg8; +#elif defined(VGP_loongarch64_linux) + VexGuestLOONGARCH64State* gst = (VexGuestLOONGARCH64State*)gst_vanilla; + gst->guest_R11 = canonical->sysno; + gst->guest_R4 = canonical->arg1; + gst->guest_R5 = canonical->arg2; + gst->guest_R6 = canonical->arg3; + gst->guest_R7 = canonical->arg4; + gst->guest_R8 = canonical->arg5; + gst->guest_R9 = canonical->arg6; + #elif defined(VGP_x86_solaris) VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; UWord *stack = (UWord *)gst->guest_ESP; @@ -1240,6 +1262,13 @@ void getSyscallStatusFromGuestState ( /*OUT*/SyscallStatus* canonical, RegWord a0 = gst->guest_r4; // a0 canonical->sres = VG_(mk_SysRes_nanomips_linux)(a0); canonical->what = SsComplete; + +# elif defined(VGP_loongarch64_linux) + VexGuestLOONGARCH64State* gst = (VexGuestLOONGARCH64State*)gst_vanilla; + ULong a0 = gst->guest_R4; // a0 + canonical->sres = VG_(mk_SysRes_loongarch64_linux)(a0); + canonical->what = SsComplete; + # elif defined(VGP_amd64_freebsd) /* duplicates logic in m_signals.VG_UCONTEXT_SYSCALL_SYSRES */ VexGuestAMD64State* gst = (VexGuestAMD64State*)gst_vanilla; @@ -1606,6 +1635,20 @@ void putSyscallStatusIntoGuestState ( /*IN*/ ThreadId tid, VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, OFFSET_mips32_r4, sizeof(UWord) ); +# elif defined(VGP_loongarch64_linux) + VexGuestLOONGARCH64State* gst = (VexGuestLOONGARCH64State*)gst_vanilla; + vg_assert(canonical->what == SsComplete); + if (sr_isError(canonical->sres)) { + /* This isn't exactly right, in that really a Failure with res + not in the range 1 .. 4095 is unrepresentable in the + Linux-loongarch64 scheme. Oh well. */ + gst->guest_R4 = - (Long)sr_Err(canonical->sres); + } else { + gst->guest_R4 = sr_Res(canonical->sres); + } + VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, + OFFSET_loongarch64_R4, sizeof(UWord) ); + # elif defined(VGP_x86_solaris) VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; SysRes sres = canonical->sres; @@ -1855,6 +1898,15 @@ void getSyscallArgLayout ( /*OUT*/SyscallArgLayout* layout ) layout->s_arg7 = sizeof(UWord) * 1; layout->s_arg8 = sizeof(UWord) * 2; +#elif defined(VGP_loongarch64_linux) + layout->o_sysno = OFFSET_loongarch64_R11; + layout->o_arg1 = OFFSET_loongarch64_R4; + layout->o_arg2 = OFFSET_loongarch64_R5; + layout->o_arg3 = OFFSET_loongarch64_R6; + layout->o_arg4 = OFFSET_loongarch64_R7; + layout->o_arg5 = OFFSET_loongarch64_R8; + layout->o_arg6 = OFFSET_loongarch64_R9; + #else # error "getSyscallLayout: unknown arch" #endif @@ -2899,6 +2951,25 @@ void ML_(fixup_guest_state_to_restart_syscall) ( ThreadArchState* arch ) arch->vex.guest_PC -= 2; } } + +#elif defined(VGP_loongarch64_linux) + arch->vex.guest_PC -= 4; // sizeof(loongarch instr) + + /* Make sure our caller is actually sane, and we're really backing + back over a syscall. + + syscall 0 == 00 2B 00 00 + */ + { + UChar *p = (UChar *)(Addr)(arch->vex.guest_PC); + if (p[0] != 0x00 || p[1] != 0x00 || p[2] != 0x2B || p[3] != 0x00) + VG_(message)(Vg_DebugMsg, + "?! restarting over syscall at %#llx %02x %02x %02x %02x\n", + (ULong)arch->vex.guest_PC, p[0], p[1], p[2], p[3]); + + vg_assert(p[0] == 0x00 && p[1] == 0x00 && p[2] == 0x2B && p[3] == 0x00); + } + #elif defined(VGP_x86_solaris) arch->vex.guest_EIP -= 2; // sizeof(int $0x91) or sizeof(syscall) diff --git a/coregrind/m_trampoline.S b/coregrind/m_trampoline.S index da96972..f02d53f 100644 --- a/coregrind/m_trampoline.S +++ b/coregrind/m_trampoline.S @@ -1520,6 +1520,53 @@ VG_(trampoline_stuff_end): # undef UD2_1024 # undef UD2_PAGE +/*------------------- loongarch64-linux -------------------*/ +#else +#if defined(VGP_loongarch64_linux) + +.global VG_(trampoline_stuff_start) +VG_(trampoline_stuff_start): + +.global VG_(loongarch64_linux_SUBST_FOR_rt_sigreturn) +VG_(loongarch64_linux_SUBST_FOR_rt_sigreturn): + li.w $a7, __NR_rt_sigreturn + syscall 0 + .long 0 /*illegal insn*/ + +/* There's no particular reason that this needs to be handwritten + assembly, but since that's what this file contains, here's a + simple strlen() and strchr() implementations. +*/ + +.global VG_(loongarch64_linux_REDIR_FOR_strlen) +.type VG_(loongarch64_linux_REDIR_FOR_strlen), @function +VG_(loongarch64_linux_REDIR_FOR_strlen): + move $t0, $a0 + strlen_loop: + ld.bu $t1, $a0, 0 + addi.d $a0, $a0, 1 + bne $t1, $zero, strlen_loop + sub.d $a0, $a0, $t0 + addi.d $a0, $a0, -1 + jr $ra +.size VG_(loongarch64_linux_REDIR_FOR_strlen), .-VG_(loongarch64_linux_REDIR_FOR_strlen) + +.global VG_(loongarch64_linux_REDIR_FOR_strchr) +.type VG_(loongarch64_linux_REDIR_FOR_strchr), @function +VG_(loongarch64_linux_REDIR_FOR_strchr): + strchr_loop: + ld.bu $t0, $a0, 0 + beq $t0, $a1, strchr_end + addi.d $a0, $a0, 1 + bne $t0, $zero, strchr_loop + move $a0, $zero + strchr_end: + jr $ra +.size VG_(loongarch64_linux_REDIR_FOR_strchr), .-VG_(loongarch64_linux_REDIR_FOR_strchr) + +.global VG_(trampoline_stuff_end) +VG_(trampoline_stuff_end): + /*---------------- x86-solaris ----------------*/ #else #if defined(VGP_x86_solaris) @@ -1719,6 +1766,7 @@ VG_(trampoline_stuff_end): #endif #endif #endif +#endif /* Let the linker know we don't need an executable stack */ MARK_STACK_NO_EXEC diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c index 0dd3608..1ae200b 100644 --- a/coregrind/m_translate.c +++ b/coregrind/m_translate.c @@ -1750,6 +1750,11 @@ Bool VG_(translate) ( ThreadId tid, vex_archinfo.arm64_requires_fallback_LLSC; # endif +# if defined(VGP_loongarch64_linux) + /* For now, we only use fallback LLSC */ + vex_abiinfo.guest__use_fallback_LLSC = True; +# endif + /* Set up closure args. */ closure.tid = tid; closure.nraddr = nraddr; diff --git a/coregrind/m_vki.c b/coregrind/m_vki.c index 0cc1882..11c5fe3 100644 --- a/coregrind/m_vki.c +++ b/coregrind/m_vki.c @@ -37,13 +37,13 @@ describing the kernel interface, so this file is nearly empty. */ -/* ppc32/64, arm64 and mips32/64 (linux) determine page size at startup, - hence m_vki is the logical place to store that info. */ +/* ppc32/64, arm64, mips32/64 and loongarch64 (linux) determine page size + at startup, hence m_vki is the logical place to store that info. */ #if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ || defined(VGP_ppc64le_linux) || defined(VGP_arm64_linux) \ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ - || defined(VGP_nanomips_linux) + || defined(VGP_nanomips_linux) || defined(VGP_loongarch64_linux) unsigned long VKI_PAGE_SHIFT = 12; unsigned long VKI_PAGE_SIZE = 1UL << 12; #endif diff --git a/coregrind/pub_core_aspacemgr.h b/coregrind/pub_core_aspacemgr.h index b867108..a2b41f3 100644 --- a/coregrind/pub_core_aspacemgr.h +++ b/coregrind/pub_core_aspacemgr.h @@ -335,7 +335,8 @@ extern Bool VG_(am_relocate_nooverlap_client)( /*OUT*/Bool* need_discard, #if defined(VGP_ppc32_linux) \ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ - || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) + || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ + || defined(VGP_loongarch64_linux) # define VG_STACK_GUARD_SZB 65536 // 1 or 16 pages #else # define VG_STACK_GUARD_SZB 8192 // 2 pages diff --git a/coregrind/pub_core_basics.h b/coregrind/pub_core_basics.h index abc5a06..1325451 100644 --- a/coregrind/pub_core_basics.h +++ b/coregrind/pub_core_basics.h @@ -55,8 +55,8 @@ typedef struct { - ULong r_pc; /* x86:EIP, amd64:RIP, ppc:CIA, arm:R15, mips:pc */ - ULong r_sp; /* x86:ESP, amd64:RSP, ppc:R1, arm:R13, mips:sp */ + ULong r_pc; /* x86:EIP, amd64:RIP, ppc:CIA, arm:R15, mips:pc, loongarch64:pc */ + ULong r_sp; /* x86:ESP, amd64:RSP, ppc:R1, arm:R13, mips:sp, loongarch64:sp */ union { struct { UInt r_ebp; @@ -102,6 +102,10 @@ typedef ULong r31; /* Return address of the last subroutine call */ ULong r28; } MIPS64; + struct { + ULong r_fp; /* Stack frame pointer or static variable */ + ULong r_ra; /* Return address of the last subroutine call */ + } LOONGARCH64; } misc; } UnwindStartRegs; diff --git a/coregrind/pub_core_debuginfo.h b/coregrind/pub_core_debuginfo.h index 4d6ebda..115afff 100644 --- a/coregrind/pub_core_debuginfo.h +++ b/coregrind/pub_core_debuginfo.h @@ -137,6 +137,10 @@ typedef typedef struct { Addr pc; Addr sp; Addr fp; Addr ra; } D3UnwindRegs; +#elif defined(VGA_loongarch64) +typedef + struct { Addr pc; Addr ra; Addr sp; Addr fp; } + D3UnwindRegs; #else # error "Unsupported arch" #endif diff --git a/coregrind/pub_core_machine.h b/coregrind/pub_core_machine.h index a9b7dd8..4793d59 100644 --- a/coregrind/pub_core_machine.h +++ b/coregrind/pub_core_machine.h @@ -126,6 +126,11 @@ # define VG_ELF_MACHINE EM_NANOMIPS # define VG_ELF_CLASS ELFCLASS32 # undef VG_PLAT_USES_PPCTOC +#elif defined(VGP_loongarch64_linux) +# define VG_ELF_DATA2XXX ELFDATA2LSB +# define VG_ELF_MACHINE EM_LOONGARCH +# define VG_ELF_CLASS ELFCLASS64 +# undef VG_PLAT_USES_PPCTOC #else # error Unknown platform #endif @@ -163,6 +168,10 @@ # define VG_INSTR_PTR guest_PC # define VG_STACK_PTR guest_r29 # define VG_FRAME_PTR guest_r30 +#elif defined(VGA_loongarch64) +# define VG_INSTR_PTR guest_PC +# define VG_STACK_PTR guest_R3 +# define VG_FRAME_PTR guest_R22 #else # error Unknown arch #endif @@ -234,6 +243,10 @@ void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs, s390x: initially: call VG_(machine_get_hwcaps) then safe to use VG_(machine_get_VexArchInfo) + ------------- + loongarch64: initially: call VG_(machine_get_hwcaps) + + then safe to use VG_(machine_get_VexArchInfo) VG_(machine_get_hwcaps) may use signals (although it attempts to leave signal state unchanged) and therefore should only be diff --git a/coregrind/pub_core_mallocfree.h b/coregrind/pub_core_mallocfree.h index b5922ca..d285caa 100644 --- a/coregrind/pub_core_mallocfree.h +++ b/coregrind/pub_core_mallocfree.h @@ -78,6 +78,7 @@ typedef Int ArenaId; defined(VGP_ppc64le_linux) || \ defined(VGP_s390x_linux) || \ (defined(VGP_mips64_linux) && !defined(VGABI_N32)) || \ + defined(VGP_loongarch64_linux) || \ defined(VGP_x86_freebsd) || \ defined(VGP_amd64_freebsd) || \ defined(VGP_x86_darwin) || \ diff --git a/coregrind/pub_core_signals.h b/coregrind/pub_core_signals.h index ae8555b..c53323f 100644 --- a/coregrind/pub_core_signals.h +++ b/coregrind/pub_core_signals.h @@ -77,6 +77,7 @@ extern void VG_(synth_sigill) (ThreadId tid, Addr addr); extern void VG_(synth_sigtrap) (ThreadId tid); extern void VG_(synth_sigbus) (ThreadId tid); extern void VG_(synth_sigfpe) (ThreadId tid, UInt code); +extern void VG_(synth_sigsys) (ThreadId tid); /* Extend the stack to cover addr, if possible */ extern Bool VG_(extend_stack)(ThreadId tid, Addr addr); diff --git a/coregrind/pub_core_syscall.h b/coregrind/pub_core_syscall.h index 6c4f825..5d7ff44 100644 --- a/coregrind/pub_core_syscall.h +++ b/coregrind/pub_core_syscall.h @@ -105,6 +105,7 @@ extern SysRes VG_(mk_SysRes_mips32_linux)( UWord v0, UWord v1, extern SysRes VG_(mk_SysRes_mips64_linux)( ULong v0, ULong v1, ULong a3 ); extern SysRes VG_(mk_SysRes_nanomips_linux)( UWord a0); +extern SysRes VG_(mk_SysRes_loongarch64_linux)( UWord a0 ); extern SysRes VG_(mk_SysRes_x86_solaris) ( Bool isErr, UInt val, UInt val2 ); extern SysRes VG_(mk_SysRes_amd64_solaris) ( Bool isErr, ULong val, ULong val2 ); extern SysRes VG_(mk_SysRes_Error) ( UWord val ); diff --git a/coregrind/pub_core_trampoline.h b/coregrind/pub_core_trampoline.h index 54c575a..3700acb 100644 --- a/coregrind/pub_core_trampoline.h +++ b/coregrind/pub_core_trampoline.h @@ -171,6 +171,12 @@ extern Char* VG_(nanomips_linux_REDIR_FOR_index)( const Char*, Int ); extern UInt VG_(nanomips_linux_REDIR_FOR_strlen)( void* ); #endif +#if defined(VGP_loongarch64_linux) +extern Addr VG_(loongarch64_linux_SUBST_FOR_rt_sigreturn); +extern UInt VG_(loongarch64_linux_REDIR_FOR_strlen)( void* ); +extern Char* VG_(loongarch64_linux_REDIR_FOR_strchr)( const Char*, Int ); +#endif + #if defined(VGP_x86_solaris) extern SizeT VG_(x86_solaris_REDIR_FOR_strcmp)(const HChar *, const HChar *); extern SizeT VG_(x86_solaris_REDIR_FOR_strlen)(const HChar *); diff --git a/coregrind/pub_core_transtab.h b/coregrind/pub_core_transtab.h index 6cc11f6..fe93926 100644 --- a/coregrind/pub_core_transtab.h +++ b/coregrind/pub_core_transtab.h @@ -81,7 +81,8 @@ static inline UWord VG_TT_FAST_HASH ( Addr guest ) { } #elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ - || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) + || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) \ + || defined(VGA_loongarch64) static inline UWord VG_TT_FAST_HASH ( Addr guest ) { // Instructions are 4-byte aligned. UWord merged = ((UWord)guest) >> 2; diff --git a/coregrind/pub_core_transtab_asm.h b/coregrind/pub_core_transtab_asm.h index 8b585f1..e73c89a 100644 --- a/coregrind/pub_core_transtab_asm.h +++ b/coregrind/pub_core_transtab_asm.h @@ -83,7 +83,7 @@ #if defined(VGA_amd64) || defined(VGA_arm64) \ || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ || (defined(VGA_mips64) && defined(VGABI_64)) \ - || defined(VGA_s390x) + || defined(VGA_s390x) || defined(VGA_loongarch64) // And all other 64-bit hosts # define VG_FAST_CACHE_SET_BITS 6 // These FCS_{g,h}{0,1,2,3} are the values of diff --git a/coregrind/vgdb-invoker-ptrace.c b/coregrind/vgdb-invoker-ptrace.c index 78a6a16..798fe5f 100644 --- a/coregrind/vgdb-invoker-ptrace.c +++ b/coregrind/vgdb-invoker-ptrace.c @@ -50,9 +50,10 @@ // Rather we use PTRACE_GETREGS or PTRACE_PEEKUSER. // The only platform on which we must use PTRACE_GETREGSET is arm64. +// We use PTRACE_GETREGSET on loongarch64 as well. // The resulting vgdb cannot work in a bi-arch setup. // -1 means we will check that PTRACE_GETREGSET works. -# if defined(VGA_arm64) +# if defined(VGA_arm64) || defined(VGA_loongarch64) #define USE_PTRACE_GETREGSET # endif #endif @@ -529,6 +530,9 @@ static struct user_regs_struct user_save; # else static struct user_pt_regs user_save; # endif +# elif defined(VGA_loongarch64) +/* loongarch64 is extra special, glibc only defined user_regs_struct. */ +static struct user_regs_struct user_save; # else static struct user user_save; # endif @@ -805,6 +809,9 @@ Bool invoker_invoke_gdbserver (pid_t pid) # else struct user_pt_regs user_mod; # endif +# elif defined(VGA_loongarch64) +/* loongarch64 is extra special, glibc only defined user_regs_struct. */ + struct user_regs_struct user_mod; # else struct user user_mod; # endif @@ -874,6 +881,8 @@ Bool invoker_invoke_gdbserver (pid_t pid) sp = p[29]; #elif defined(VGA_mips64) sp = user_mod.regs[29]; +#elif defined(VGA_loongarch64) + sp = user_mod.regs[3]; #else I_die_here : (sp) architecture missing in vgdb-invoker-ptrace.c #endif @@ -961,6 +970,8 @@ Bool invoker_invoke_gdbserver (pid_t pid) #elif defined(VGA_mips64) assert(0); // cannot vgdb a 32 bits executable with a 64 bits exe +#elif defined(VGA_loongarch64) + assert(0); // cannot vgdb a 32 bits executable with a 64 bits exe #else I_die_here : architecture missing in vgdb-invoker-ptrace.c #endif @@ -1068,6 +1079,12 @@ Bool invoker_invoke_gdbserver (pid_t pid) user_mod.regs[31] = bad_return; user_mod.regs[34] = shared64->invoke_gdbserver; user_mod.regs[25] = shared64->invoke_gdbserver; +#elif defined(VGA_loongarch64) + /* put check arg in register a0 */ + user_mod.regs[4] = check; + /* put NULL return address in ra */ + user_mod.regs[1] = bad_return; + user_mod.csr_era = shared64->invoke_gdbserver; #else I_die_here: architecture missing in vgdb-invoker-ptrace.c #endif diff --git a/dhat/Makefile.in b/dhat/Makefile.in index 9b9f943..ee93cc5 100644 --- a/dhat/Makefile.in +++ b/dhat/Makefile.in @@ -686,6 +686,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -733,6 +739,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -823,6 +830,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -883,6 +894,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -955,6 +969,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/dhat/tests/Makefile.in b/dhat/tests/Makefile.in index 433a72b..58ee764 100644 --- a/dhat/tests/Makefile.in +++ b/dhat/tests/Makefile.in @@ -623,6 +623,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -670,6 +676,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/drd/Makefile.in b/drd/Makefile.in index 989dcae..cb7f41a 100644 --- a/drd/Makefile.in +++ b/drd/Makefile.in @@ -767,6 +767,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -814,6 +820,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -904,6 +911,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -964,6 +975,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -1036,6 +1050,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/drd/drd_bitmap.h b/drd/drd_bitmap.h index 3b71d74..1f11f23 100644 --- a/drd/drd_bitmap.h +++ b/drd/drd_bitmap.h @@ -140,7 +140,7 @@ Addr make_address(const UWord a1, const UWord a0) #define BITS_PER_BITS_PER_UWORD 5 #elif defined(VGA_amd64) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ || defined(VGA_s390x) || (defined(VGA_mips64) && !defined(VGABI_N32)) \ - || defined(VGA_arm64) + || defined(VGA_arm64) || defined(VGA_loongarch64) #define BITS_PER_BITS_PER_UWORD 6 #else #error Unknown platform. diff --git a/drd/drd_load_store.c b/drd/drd_load_store.c index 80d326a..da6283b 100644 --- a/drd/drd_load_store.c +++ b/drd/drd_load_store.c @@ -53,6 +53,8 @@ #define STACK_POINTER_OFFSET OFFSET_mips32_r29 #elif defined(VGA_mips64) #define STACK_POINTER_OFFSET OFFSET_mips64_r29 +#elif defined(VGA_loongarch64) +#define STACK_POINTER_OFFSET OFFSET_loongarch64_R3 #else #error Unknown architecture. #endif @@ -634,6 +636,8 @@ IRSB* DRD_(instrument)(VgCallbackClosure* const closure, break; /* not interesting to DRD */ case Imbe_CancelReservation: break; /* not interesting to DRD */ + case Imbe_InsnFence: + break; /* not interesting to DRD */ default: tl_assert(0); } diff --git a/drd/tests/Makefile.in b/drd/tests/Makefile.in index 80833e7..320e589 100644 --- a/drd/tests/Makefile.in +++ b/drd/tests/Makefile.in @@ -1195,6 +1195,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -1242,6 +1248,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/drd/tests/pth_barrier_thr_cr.supp b/drd/tests/pth_barrier_thr_cr.supp index 653b2d2..34482cc 100644 --- a/drd/tests/pth_barrier_thr_cr.supp +++ b/drd/tests/pth_barrier_thr_cr.supp @@ -9,3 +9,14 @@ fun:pthread_barrier_wait_intercept fun:pthread_barrier_wait } +{ + number-of-concurrent-pthead_barrier_wait()-calls-exceeds-barrier-count + drd:BarrierErr + fun:pthread_barrier_wait@* +} +{ + number-of-concurrent-pthead_barrier_wait()-calls-exceeds-barrier-count + drd:BarrierErr + fun:pthread_barrier_wait_intercept + fun:pthread_barrier_wait@* +} diff --git a/exp-bbv/Makefile.in b/exp-bbv/Makefile.in index 39f9cf9..d79f54f 100644 --- a/exp-bbv/Makefile.in +++ b/exp-bbv/Makefile.in @@ -621,6 +621,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -668,6 +674,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -758,6 +765,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -818,6 +829,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -890,6 +904,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/exp-bbv/tests/Makefile.in b/exp-bbv/tests/Makefile.in index 686a369..d36f4ee 100644 --- a/exp-bbv/tests/Makefile.in +++ b/exp-bbv/tests/Makefile.in @@ -594,6 +594,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -641,6 +647,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/exp-bbv/tests/amd64-linux/Makefile.in b/exp-bbv/tests/amd64-linux/Makefile.in index f9a6cc7..a5e711a 100644 --- a/exp-bbv/tests/amd64-linux/Makefile.in +++ b/exp-bbv/tests/amd64-linux/Makefile.in @@ -615,6 +615,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -662,6 +668,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/exp-bbv/tests/arm-linux/Makefile.in b/exp-bbv/tests/arm-linux/Makefile.in index 911a02c..a8886b9 100644 --- a/exp-bbv/tests/arm-linux/Makefile.in +++ b/exp-bbv/tests/arm-linux/Makefile.in @@ -575,6 +575,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -622,6 +628,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/exp-bbv/tests/ppc32-linux/Makefile.in b/exp-bbv/tests/ppc32-linux/Makefile.in index f5bd96b..7d6107c 100644 --- a/exp-bbv/tests/ppc32-linux/Makefile.in +++ b/exp-bbv/tests/ppc32-linux/Makefile.in @@ -575,6 +575,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -622,6 +628,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/exp-bbv/tests/x86-linux/Makefile.in b/exp-bbv/tests/x86-linux/Makefile.in index ee3baa5..702f33f 100644 --- a/exp-bbv/tests/x86-linux/Makefile.in +++ b/exp-bbv/tests/x86-linux/Makefile.in @@ -575,6 +575,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -622,6 +628,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/exp-bbv/tests/x86/Makefile.in b/exp-bbv/tests/x86/Makefile.in index b1557c3..dbecbe3 100644 --- a/exp-bbv/tests/x86/Makefile.in +++ b/exp-bbv/tests/x86/Makefile.in @@ -586,6 +586,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -633,6 +639,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/gdbserver_tests/Makefile.am b/gdbserver_tests/Makefile.am index fbcb659..30e17c0 100755 --- a/gdbserver_tests/Makefile.am +++ b/gdbserver_tests/Makefile.am @@ -15,6 +15,7 @@ dist_noinst_SCRIPTS = \ filter_gdb filter_make_empty \ filter_memcheck_monitor filter_stderr filter_vgdb \ filter_helgrind_monitor filter_helgrind_monitor_solaris \ + filter_helgrind_monitor_loongarch64 \ filter_passsigalrm \ send_signal diff --git a/gdbserver_tests/Makefile.in b/gdbserver_tests/Makefile.in index 712e8b2..7c9a353 100644 --- a/gdbserver_tests/Makefile.in +++ b/gdbserver_tests/Makefile.in @@ -664,6 +664,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -711,6 +717,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ @@ -740,6 +747,7 @@ dist_noinst_SCRIPTS = \ filter_gdb filter_make_empty \ filter_memcheck_monitor filter_stderr filter_vgdb \ filter_helgrind_monitor filter_helgrind_monitor_solaris \ + filter_helgrind_monitor_loongarch64 \ filter_passsigalrm \ send_signal diff --git a/gdbserver_tests/filter_helgrind_monitor b/gdbserver_tests/filter_helgrind_monitor index 4fc2e9a..21bf6be 100755 --- a/gdbserver_tests/filter_helgrind_monitor +++ b/gdbserver_tests/filter_helgrind_monitor @@ -14,6 +14,8 @@ if $dir/../tests/os_test solaris; then $dir/filter_helgrind_monitor_solaris elif $dir/../tests/os_test freebsd; then gsed -e '/\(rtld_start.S\|kill.S\|_exit.S\|_select.S\): No such file or directory/d' +elif $dir/../tests/arch_test loongarch64; then + $dir/filter_helgrind_monitor_loongarch64 else cat fi | diff --git a/gdbserver_tests/filter_helgrind_monitor_loongarch64 b/gdbserver_tests/filter_helgrind_monitor_loongarch64 new file mode 100755 index 0000000..cda73e4 --- /dev/null +++ b/gdbserver_tests/filter_helgrind_monitor_loongarch64 @@ -0,0 +1,43 @@ +#!/usr/bin/env perl +# From gdbserver_tests/filter_helgrind_monitor_solaris + +# +# Filter out all helgrind information about locks except the one named "mx". +# One lock record looks like: +# Lock ga 0x........ { +# Address 0x........ is 2648 bytes inside data symbol "_rtld_local" +# kind mbRec +# } + +use strict; +use warnings; + +my $lock_start_line = undef; +my $skip_to_closing_line = 0; +while () { + my $line = $_; + chomp($line); + if ($line =~ /^Lock ga 0x[\.]+\s+{$/) { + $lock_start_line = $line; + $skip_to_closing_line = 1; + } elsif (($lock_start_line) && + ($line =~ /\s*Address 0x[\.]+ is \d+ bytes inside data symbol "(\S+)"/)) { + if ($1 eq "mx") { + print "$lock_start_line\n"; + print "$line\n"; + $skip_to_closing_line = 0; + } + } elsif ($line =~ /^}$/) { + if ($skip_to_closing_line == 0) { + print "$line\n"; + } + undef($lock_start_line); + $skip_to_closing_line = 0; + } else { + if ($skip_to_closing_line == 0) { + print "$line\n"; + } + } +} + +exit 0; diff --git a/gdbserver_tests/solaris/Makefile.in b/gdbserver_tests/solaris/Makefile.in index 374e279..341f7bf 100644 --- a/gdbserver_tests/solaris/Makefile.in +++ b/gdbserver_tests/solaris/Makefile.in @@ -529,6 +529,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -576,6 +582,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/helgrind/Makefile.in b/helgrind/Makefile.in index bd6cfdb..a85320e 100644 --- a/helgrind/Makefile.in +++ b/helgrind/Makefile.in @@ -709,6 +709,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -756,6 +762,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -846,6 +853,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -906,6 +917,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -978,6 +992,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/helgrind/hg_main.c b/helgrind/hg_main.c index 3146cc4..ee80472 100644 --- a/helgrind/hg_main.c +++ b/helgrind/hg_main.c @@ -4870,6 +4870,7 @@ IRSB* hg_instrument ( VgCallbackClosure* closure, switch (st->Ist.MBE.event) { case Imbe_Fence: case Imbe_CancelReservation: + case Imbe_InsnFence: break; /* not interesting */ default: goto unhandled; diff --git a/helgrind/tests/Makefile.in b/helgrind/tests/Makefile.in index 8f23215..e011962 100644 --- a/helgrind/tests/Makefile.in +++ b/helgrind/tests/Makefile.in @@ -920,6 +920,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -967,6 +973,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/helgrind/tests/annotate_hbefore.c b/helgrind/tests/annotate_hbefore.c index 259d3b6..3200c6c 100644 --- a/helgrind/tests/annotate_hbefore.c +++ b/helgrind/tests/annotate_hbefore.c @@ -314,6 +314,36 @@ UWord do_acasW ( UWord* addr, UWord expected, UWord nyu ) return success; } +#elif defined(VGA_loongarch64) + +// loongarch64 +/* return 1 if success, 0 if failure */ +UWord do_acasW ( UWord* addr, UWord expected, UWord nyu ) +{ + UWord success; + UWord block[3] = { (UWord)addr, nyu, expected }; + + __asm__ __volatile__( + " ld.d $t0, %1, 0 \n\t" + " ld.d $t2, %1, 16 \n\t" + " ld.d $t3, %1, 8 \n\t" + " ll.d $t1, $t0, 0 \n\t" + " bne $t1, $t2, 1f \n\t" + " sc.d $t3, $t0, 0 \n\t" + " move %0, $t3 \n\t" + " b 2f \n\t" + "1: \n\t" + " move %0, $zero \n\t" + "2: \n\t" + : /*out*/ "=r" (success) + : /*in*/ "r" (&block[0]) + : /*trash*/ "t0", "t1", "t2", "t3", "memory" + ); + + assert(success == 0 || success == 1); + return success; +} + #endif void atomic_incW ( UWord* w ) diff --git a/helgrind/tests/tc07_hbl1.c b/helgrind/tests/tc07_hbl1.c index 54297de..246d13c 100644 --- a/helgrind/tests/tc07_hbl1.c +++ b/helgrind/tests/tc07_hbl1.c @@ -18,6 +18,7 @@ #undef PLAT_arm64_linux #undef PLAT_s390x_linux #undef PLAT_mips32_linux +#undef PLAT_loongarch64_linux #undef PLAT_x86_solaris #undef PLAT_amd64_solaris @@ -47,6 +48,8 @@ # define PLAT_mips32_linux 1 #elif defined(__linux__) && defined(__nanomips__) # define PLAT_nanomips_linux 1 +#elif defined(__linux__) && defined(__loongarch__) && (__loongarch_grlen == 64) +# define PLAT_loongarch64_linux 1 #elif defined(__sun__) && defined(__i386__) # define PLAT_x86_solaris 1 #elif defined(__sun__) && defined(__x86_64__) @@ -131,6 +134,20 @@ : /*out*/ : /*in*/ "r"(&(_lval)) \ : /*trash*/ "$t0", "$t1", "memory" \ ) +#elif defined(PLAT_loongarch64_linux) +# define INC(_lval,_lqual) \ + __asm__ __volatile__ ( \ + "1: \n" \ + " move $t0, %0 \n" \ + " ll.w $t1, $t0, 0 \n" \ + " addi.w $t1, $t1, 1 \n" \ + " sc.w $t1, $t0, 0 \n" \ + " li.w $t2, 1 \n" \ + " bne $t1, $t2, 1b \n" \ + : /*out*/ \ + : /*in*/ "r" (&(_lval)) \ + : /*trash*/ "$t0", "$t1", "$t2", "memory" \ + ) #else # error "Fix Me for this platform" #endif diff --git a/helgrind/tests/tc08_hbl2.c b/helgrind/tests/tc08_hbl2.c index c3a2ec7..8683168 100644 --- a/helgrind/tests/tc08_hbl2.c +++ b/helgrind/tests/tc08_hbl2.c @@ -35,6 +35,7 @@ #undef PLAT_s390x_linux #undef PLAT_mips32_linux #undef PLAT_mips64_linux +#undef PLAT_loongarch64_linux #undef PLAT_x86_solaris #undef PLAT_amd64_solaris @@ -68,6 +69,8 @@ #endif #elif defined(__linux__) && defined(__nanomips__) # define PLAT_nanomips_linux 1 +#elif defined(__linux__) && defined(__loongarch__) && (__loongarch_grlen == 64) +# define PLAT_loongarch64_linux 1 #elif defined(__sun__) && defined(__i386__) # define PLAT_x86_solaris 1 #elif defined(__sun__) && defined(__x86_64__) @@ -151,6 +154,20 @@ : /*out*/ : /*in*/ "r"(&(_lval)) \ : /*trash*/ "$t0", "$t1", "memory" \ ) +#elif defined(PLAT_loongarch64_linux) +# define INC(_lval,_lqual) \ + __asm__ __volatile__ ( \ + "1: \n" \ + " move $t0, %0 \n" \ + " ll.w $t1, $t0, 0 \n" \ + " addi.w $t1, $t1, 1 \n" \ + " sc.w $t1, $t0, 0 \n" \ + " li.w $t2, 1 \n" \ + " bne $t1, $t2, 1b \n" \ + : /*out*/ \ + : /*in*/ "r" (&(_lval)) \ + : /*trash*/ "$t0", "$t1", "$t2", "memory" \ + ) #else # error "Fix Me for this platform" #endif diff --git a/helgrind/tests/tc11_XCHG.c b/helgrind/tests/tc11_XCHG.c index 08e34a0..64b3d2b 100644 --- a/helgrind/tests/tc11_XCHG.c +++ b/helgrind/tests/tc11_XCHG.c @@ -20,6 +20,7 @@ #undef PLAT_arm_linux #undef PLAT_s390x_linux #undef PLAT_mips32_linux +#undef PLAT_loongarch64_linux #undef PLAT_x86_solaris #undef PLAT_amd64_solaris @@ -49,6 +50,8 @@ # define PLAT_mips32_linux 1 #elif defined(__linux__) && defined(__nanomips__) # define PLAT_nanomips_linux 1 +#elif defined(__linux__) && defined(__loongarch__) && (__loongarch_grlen == 64) +# define PLAT_loongarch64_linux 1 #elif defined(__sun__) && defined(__i386__) # define PLAT_x86_solaris 1 #elif defined(__sun__) && defined(__x86_64__) @@ -146,6 +149,21 @@ # define XCHG_M_R_with_redundant_LOCK(_addr,_lval) \ XCHG_M_R(_addr,_lval) +#elif defined(PLAT_loongarch64_linux) +# define XCHG_M_R(_addr,_lval) \ + __asm__ __volatile__( \ + "move $t0, %2 \n\t" \ + "ll.w $t1, %1 \n\t" \ + "sc.w $t0, %1 \n\t" \ + "move %0, $t1 \n\t" \ + : /*out*/ "=r"(_lval), "+ZC"(_addr) \ + : /*in*/ "r"(_lval) \ + : "$t0", "$t1", "memory" \ + ) + +# define XCHG_M_R_with_redundant_LOCK(_addr,_lval) \ + XCHG_M_R(_addr,_lval) + #else # error "Unsupported architecture" diff --git a/include/Makefile.am b/include/Makefile.am index 972d394..abfa2c9 100644 --- a/include/Makefile.am +++ b/include/Makefile.am @@ -63,6 +63,7 @@ nobase_pkginclude_HEADERS = \ vki/vki-posixtypes-mips32-linux.h \ vki/vki-posixtypes-mips64-linux.h \ vki/vki-posixtypes-nanomips-linux.h \ + vki/vki-posixtypes-loongarch64-linux.h \ vki/vki-amd64-linux.h \ vki/vki-arm64-linux.h \ vki/vki-ppc32-linux.h \ @@ -75,6 +76,7 @@ nobase_pkginclude_HEADERS = \ vki/vki-mips32-linux.h \ vki/vki-mips64-linux.h \ vki/vki-nanomips-linux.h \ + vki/vki-loongarch64-linux.h \ vki/vki-scnums-amd64-linux.h \ vki/vki-scnums-arm64-linux.h \ vki/vki-scnums-ppc32-linux.h \ @@ -86,6 +88,7 @@ nobase_pkginclude_HEADERS = \ vki/vki-scnums-mips32-linux.h \ vki/vki-scnums-mips64-linux.h \ vki/vki-scnums-nanomips-linux.h \ + vki/vki-scnums-loongarch64-linux.h \ vki/vki-scnums-darwin.h \ vki/vki-scnums-solaris.h \ vki/vki-scnums-shared-linux.h \ diff --git a/include/Makefile.in b/include/Makefile.in index e292939..0653f8f 100644 --- a/include/Makefile.in +++ b/include/Makefile.in @@ -449,6 +449,7 @@ nobase_pkginclude_HEADERS = \ vki/vki-posixtypes-mips32-linux.h \ vki/vki-posixtypes-mips64-linux.h \ vki/vki-posixtypes-nanomips-linux.h \ + vki/vki-posixtypes-loongarch64-linux.h \ vki/vki-amd64-linux.h \ vki/vki-arm64-linux.h \ vki/vki-ppc32-linux.h \ @@ -461,6 +462,7 @@ nobase_pkginclude_HEADERS = \ vki/vki-mips32-linux.h \ vki/vki-mips64-linux.h \ vki/vki-nanomips-linux.h \ + vki/vki-loongarch64-linux.h \ vki/vki-scnums-amd64-linux.h \ vki/vki-scnums-arm64-linux.h \ vki/vki-scnums-ppc32-linux.h \ @@ -472,6 +474,7 @@ nobase_pkginclude_HEADERS = \ vki/vki-scnums-mips32-linux.h \ vki/vki-scnums-mips64-linux.h \ vki/vki-scnums-nanomips-linux.h \ + vki/vki-scnums-loongarch64-linux.h \ vki/vki-scnums-darwin.h \ vki/vki-scnums-solaris.h \ vki/vki-scnums-shared-linux.h \ diff --git a/include/pub_tool_basics.h b/include/pub_tool_basics.h index bf5a5ba..da90ea7 100644 --- a/include/pub_tool_basics.h +++ b/include/pub_tool_basics.h @@ -437,7 +437,8 @@ static inline Bool sr_EQ ( UInt sysno, SysRes sr1, SysRes sr2 ) { #if defined(VGA_x86) || defined(VGA_amd64) || defined (VGA_arm) \ || ((defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips)) \ - && defined (_MIPSEL)) || defined(VGA_arm64) || defined(VGA_ppc64le) + && defined (_MIPSEL)) || defined(VGA_arm64) || defined(VGA_ppc64le) \ + || defined (VGA_loongarch64) # define VG_LITTLEENDIAN 1 #elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_s390x) \ || ((defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips)) \ @@ -485,7 +486,8 @@ static inline Bool sr_EQ ( UInt sysno, SysRes sr1, SysRes sr2 ) { || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ || defined(VGA_arm) || defined(VGA_s390x) \ || defined(VGA_mips32) || defined(VGA_mips64) \ - || defined(VGA_arm64) || defined(VGA_nanomips) + || defined(VGA_arm64) || defined(VGA_nanomips) \ + || defined(VGA_loongarch64) # define VG_REGPARM(n) /* */ #else # error Unknown arch diff --git a/include/pub_tool_guest.h b/include/pub_tool_guest.h index 08a72ef..87e8cc2 100644 --- a/include/pub_tool_guest.h +++ b/include/pub_tool_guest.h @@ -62,6 +62,9 @@ #elif defined(VGA_mips64) # include "libvex_guest_mips64.h" typedef VexGuestMIPS64State VexGuestArchState; +#elif defined(VGA_loongarch64) +# include "libvex_guest_loongarch64.h" + typedef VexGuestLOONGARCH64State VexGuestArchState; #else # error Unknown arch #endif diff --git a/include/pub_tool_libcsetjmp.h b/include/pub_tool_libcsetjmp.h index a3a386f..69bed7c 100644 --- a/include/pub_tool_libcsetjmp.h +++ b/include/pub_tool_libcsetjmp.h @@ -134,6 +134,14 @@ UWord VG_MINIMAL_SETJMP(VG_MINIMAL_JMP_BUF(_env)); __attribute__((noreturn)) void VG_MINIMAL_LONGJMP(VG_MINIMAL_JMP_BUF(_env)); +#elif defined(VGP_loongarch64_linux) + +#define VG_MINIMAL_JMP_BUF(_name) ULong _name [13+8+1] +__attribute__((returns_twice)) +UWord VG_MINIMAL_SETJMP(VG_MINIMAL_JMP_BUF(_env)); +__attribute__((noreturn)) +void VG_MINIMAL_LONGJMP(VG_MINIMAL_JMP_BUF(_env)); + #else /* The default implementation. */ diff --git a/include/pub_tool_machine.h b/include/pub_tool_machine.h index 9bdd4f5..12377f9 100644 --- a/include/pub_tool_machine.h +++ b/include/pub_tool_machine.h @@ -108,6 +108,12 @@ # define VG_CLREQ_SZB 20 # define VG_STACK_REDZONE_SZB 0 +#elif defined(VGP_loongarch64_linux) +# define VG_MIN_INSTR_SZB 4 +# define VG_MAX_INSTR_SZB 8 +# define VG_CLREQ_SZB 20 +# define VG_STACK_REDZONE_SZB 0 + #else # error Unknown platform #endif diff --git a/include/pub_tool_redir.h b/include/pub_tool_redir.h index f88d3b5..d1bb8cb 100644 --- a/include/pub_tool_redir.h +++ b/include/pub_tool_redir.h @@ -321,6 +321,8 @@ #define VG_U_LD_LINUX_MIPSN8_S0_1 "ld-linux-mipsn8.so.1" +#define VG_U_LD_LINUX_LOONGARCH_LP64D_SO_1 "ld-linux-loongarch-lp64d.so.1" + #endif /* --- Sonames for FreeBSD ELF linkers, plus unencoded versions. --- */ diff --git a/include/pub_tool_vkiscnums_asm.h b/include/pub_tool_vkiscnums_asm.h index 14b483c..b2222aa 100644 --- a/include/pub_tool_vkiscnums_asm.h +++ b/include/pub_tool_vkiscnums_asm.h @@ -74,6 +74,10 @@ # include "vki/vki-scnums-shared-linux.h" # include "vki/vki-scnums-mips64-linux.h" +#elif defined(VGP_loongarch64_linux) +# include "vki/vki-scnums-shared-linux.h" +# include "vki/vki-scnums-loongarch64-linux.h" + #elif defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) # include "vki/vki-scnums-freebsd.h" diff --git a/include/valgrind.h b/include/valgrind.h index bd63d55..ce89195 100644 --- a/include/valgrind.h +++ b/include/valgrind.h @@ -125,6 +125,7 @@ #undef PLAT_mips32_linux #undef PLAT_mips64_linux #undef PLAT_nanomips_linux +#undef PLAT_loongarch64_linux #undef PLAT_x86_solaris #undef PLAT_amd64_solaris @@ -169,6 +170,8 @@ # define PLAT_mips32_linux 1 #elif defined(__linux__) && defined(__nanomips__) # define PLAT_nanomips_linux 1 +#elif defined(__linux__) && defined(__loongarch__) && (__loongarch_grlen == 64) +# define PLAT_loongarch64_linux 1 #elif defined(__sun) && defined(__i386__) # define PLAT_x86_solaris 1 #elif defined(__sun) && defined(__x86_64__) @@ -1125,7 +1128,75 @@ typedef ); \ } while (0) -#endif +#endif /* PLAT_nanomips_linux */ + +/* --------------------- loongarch64-linux --------------------- */ +#if defined(PLAT_loongarch64_linux) + +typedef + struct { + unsigned long nraddr; /* where's the code? */ + } + OrigFn; + +#define __SPECIAL_INSTRUCTION_PREAMBLE \ + "srli.d $zero, $zero, 3 \n\t" \ + "srli.d $zero, $zero, 13 \n\t" \ + "srli.d $zero, $zero, 29 \n\t" \ + "srli.d $zero, $zero, 19 \n\t" + +#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \ + _zzq_default, _zzq_request, \ + _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ + __extension__ \ + ({ \ + volatile unsigned long int _zzq_args[6]; \ + volatile unsigned long int _zzq_result; \ + _zzq_args[0] = (unsigned long int)(_zzq_request); \ + _zzq_args[1] = (unsigned long int)(_zzq_arg1); \ + _zzq_args[2] = (unsigned long int)(_zzq_arg2); \ + _zzq_args[3] = (unsigned long int)(_zzq_arg3); \ + _zzq_args[4] = (unsigned long int)(_zzq_arg4); \ + _zzq_args[5] = (unsigned long int)(_zzq_arg5); \ + __asm__ volatile("move $a7, %1 \n\t" /*default*/ \ + "move $t0, %2 \n\t" /*ptr*/ \ + __SPECIAL_INSTRUCTION_PREAMBLE \ + /* $a7 = client_request ( $t0 ) */ \ + "or $t1, $t1, $t1 \n\t" \ + "move %0, $a7 \n\t" /*result*/ \ + : "=r" (_zzq_result) \ + : "r" (_zzq_default), "r" (&_zzq_args[0]) \ + : "$a7", "$t0", "memory"); \ + _zzq_result; \ + }) + +#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \ + { \ + volatile OrigFn* _zzq_orig = &(_zzq_rlval); \ + volatile unsigned long int __addr; \ + __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ + /* $a7 = guest_NRADDR */ \ + "or $t2, $t2, $t2 \n\t" \ + "move %0, $a7 \n\t" /*result*/ \ + : "=r" (__addr) \ + : \ + : "$a7"); \ + _zzq_orig->nraddr = __addr; \ + } + +#define VALGRIND_CALL_NOREDIR_T8 \ + __SPECIAL_INSTRUCTION_PREAMBLE \ + /* call-noredir $t8 */ \ + "or $t3, $t3, $t3 \n\t" + +#define VALGRIND_VEX_INJECT_IR() \ + do { \ + __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ + "or $t4, $t4, $t4 \n\t" \ + ); \ + } while (0) + +#endif /* PLAT_loongarch64_linux */ /* Insert assembly code for other platforms here... */ #endif /* NVALGRIND */ @@ -6603,6 +6674,457 @@ typedef #endif /* PLAT_mips64_linux */ +/* --------------------- loongarch64-linux --------------------- */ + +#if defined(PLAT_loongarch64_linux) + +/* These regs are trashed by the hidden call. */ +#define __CALLER_SAVED_REGS \ + "$ra", "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", \ + "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8", \ + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23" + +/* $s0 is callee-saved, so we can use it to save and restore SP around + the hidden call. */ +#define VALGRIND_ALIGN_STACK \ + "move $s0, $sp \n\t" \ + "bstrins.d $sp, $zero, 3, 0 \n\t" +#define VALGRIND_RESTORE_STACK \ + "move $sp, $s0 \n\t" + +/* These CALL_FN_ macros assume that on loongarch64-linux, + sizeof(unsigned long) == 8. */ + +#define CALL_FN_W_v(lval, orig) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[1]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_W(lval, orig, arg1) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[2]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_WW(lval, orig, arg1, arg2) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[3]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_WWW(lval, orig, arg1, arg2, arg3) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[4]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_WWWW(lval, orig, arg1, arg2, arg3, arg4) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[5]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_5W(lval, orig, arg1, arg2, arg3, arg4, arg5) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[6]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_6W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[7]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_7W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[8]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_8W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7, arg8) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[9]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $a7, %1, 64 \n\t" /* arg8 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_9W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7, arg8, arg9) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[10]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "addi.d $sp, $sp, -8 \n\t" \ + "ld.d $a0, %1, 72 \n\t" \ + "st.d $a0, $sp, 0 \n\t" /* arg9 */ \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $a7, %1, 64 \n\t" /* arg8 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_10W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7, arg8, arg9, arg10) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[11]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + _argvec[10] = (unsigned long)(arg10); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "addi.d $sp, $sp, -16 \n\t" \ + "ld.d $a0, %1, 72 \n\t" \ + "st.d $a0, $sp, 0 \n\t" /* arg9 */ \ + "ld.d $a0, %1, 80 \n\t" \ + "st.d $a0, $sp, 8 \n\t" /* arg10 */ \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $a7, %1, 64 \n\t" /* arg8 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_11W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7, arg8, arg9, arg10, \ + arg11) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[12]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + _argvec[10] = (unsigned long)(arg10); \ + _argvec[11] = (unsigned long)(arg11); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "addi.d $sp, $sp, -24 \n\t" \ + "ld.d $a0, %1, 72 \n\t" \ + "st.d $a0, $sp, 0 \n\t" /* arg9 */ \ + "ld.d $a0, %1, 80 \n\t" \ + "st.d $a0, $sp, 8 \n\t" /* arg10 */ \ + "ld.d $a0, %1, 88 \n\t" \ + "st.d $a0, $sp, 16 \n\t" /* arg11 */ \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $a7, %1, 64 \n\t" /* arg8 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_12W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7, arg8, arg9, arg10, \ + arg11, arg12) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[13]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + _argvec[10] = (unsigned long)(arg10); \ + _argvec[11] = (unsigned long)(arg11); \ + _argvec[12] = (unsigned long)(arg12); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "addi.d $sp, $sp, -32 \n\t" \ + "ld.d $a0, %1, 72 \n\t" \ + "st.d $a0, $sp, 0 \n\t" /* arg9 */ \ + "ld.d $a0, %1, 80 \n\t" \ + "st.d $a0, $sp, 8 \n\t" /* arg10 */ \ + "ld.d $a0, %1, 88 \n\t" \ + "st.d $a0, $sp, 16 \n\t" /* arg11 */ \ + "ld.d $a0, %1, 96 \n\t" \ + "st.d $a0, $sp, 24 \n\t" /* arg12 */ \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $a7, %1, 64 \n\t" /* arg8 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#endif /* PLAT_loongarch64_linux */ + /* ------------------------------------------------------------------ */ /* ARCHITECTURE INDEPENDENT MACROS for CLIENT REQUESTS. */ /* */ @@ -7159,6 +7681,7 @@ VALGRIND_PRINTF_BACKTRACE(const char *format, ...) #undef PLAT_mips32_linux #undef PLAT_mips64_linux #undef PLAT_nanomips_linux +#undef PLAT_loongarch64_linux #undef PLAT_x86_solaris #undef PLAT_amd64_solaris diff --git a/include/valgrind.h.in b/include/valgrind.h.in index 45f6522..3e1967a 100644 --- a/include/valgrind.h.in +++ b/include/valgrind.h.in @@ -125,6 +125,7 @@ #undef PLAT_mips32_linux #undef PLAT_mips64_linux #undef PLAT_nanomips_linux +#undef PLAT_loongarch64_linux #undef PLAT_x86_solaris #undef PLAT_amd64_solaris @@ -169,6 +170,8 @@ # define PLAT_mips32_linux 1 #elif defined(__linux__) && defined(__nanomips__) # define PLAT_nanomips_linux 1 +#elif defined(__linux__) && defined(__loongarch__) && (__loongarch_grlen == 64) +# define PLAT_loongarch64_linux 1 #elif defined(__sun) && defined(__i386__) # define PLAT_x86_solaris 1 #elif defined(__sun) && defined(__x86_64__) @@ -1125,7 +1128,75 @@ typedef ); \ } while (0) -#endif +#endif /* PLAT_nanomips_linux */ + +/* --------------------- loongarch64-linux --------------------- */ +#if defined(PLAT_loongarch64_linux) + +typedef + struct { + unsigned long nraddr; /* where's the code? */ + } + OrigFn; + +#define __SPECIAL_INSTRUCTION_PREAMBLE \ + "srli.d $zero, $zero, 3 \n\t" \ + "srli.d $zero, $zero, 13 \n\t" \ + "srli.d $zero, $zero, 29 \n\t" \ + "srli.d $zero, $zero, 19 \n\t" + +#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \ + _zzq_default, _zzq_request, \ + _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ + __extension__ \ + ({ \ + volatile unsigned long int _zzq_args[6]; \ + volatile unsigned long int _zzq_result; \ + _zzq_args[0] = (unsigned long int)(_zzq_request); \ + _zzq_args[1] = (unsigned long int)(_zzq_arg1); \ + _zzq_args[2] = (unsigned long int)(_zzq_arg2); \ + _zzq_args[3] = (unsigned long int)(_zzq_arg3); \ + _zzq_args[4] = (unsigned long int)(_zzq_arg4); \ + _zzq_args[5] = (unsigned long int)(_zzq_arg5); \ + __asm__ volatile("move $a7, %1 \n\t" /*default*/ \ + "move $t0, %2 \n\t" /*ptr*/ \ + __SPECIAL_INSTRUCTION_PREAMBLE \ + /* $a7 = client_request ( $t0 ) */ \ + "or $t1, $t1, $t1 \n\t" \ + "move %0, $a7 \n\t" /*result*/ \ + : "=r" (_zzq_result) \ + : "r" (_zzq_default), "r" (&_zzq_args[0]) \ + : "$a7", "$t0", "memory"); \ + _zzq_result; \ + }) + +#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \ + { \ + volatile OrigFn* _zzq_orig = &(_zzq_rlval); \ + volatile unsigned long int __addr; \ + __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ + /* $a7 = guest_NRADDR */ \ + "or $t2, $t2, $t2 \n\t" \ + "move %0, $a7 \n\t" /*result*/ \ + : "=r" (__addr) \ + : \ + : "$a7"); \ + _zzq_orig->nraddr = __addr; \ + } + +#define VALGRIND_CALL_NOREDIR_T8 \ + __SPECIAL_INSTRUCTION_PREAMBLE \ + /* call-noredir $t8 */ \ + "or $t3, $t3, $t3 \n\t" + +#define VALGRIND_VEX_INJECT_IR() \ + do { \ + __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ + "or $t4, $t4, $t4 \n\t" \ + ); \ + } while (0) + +#endif /* PLAT_loongarch64_linux */ /* Insert assembly code for other platforms here... */ #endif /* NVALGRIND */ @@ -6603,6 +6674,457 @@ typedef #endif /* PLAT_mips64_linux */ +/* --------------------- loongarch64-linux --------------------- */ + +#if defined(PLAT_loongarch64_linux) + +/* These regs are trashed by the hidden call. */ +#define __CALLER_SAVED_REGS \ + "$ra", "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", \ + "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8", \ + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23" + +/* $s0 is callee-saved, so we can use it to save and restore SP around + the hidden call. */ +#define VALGRIND_ALIGN_STACK \ + "move $s0, $sp \n\t" \ + "bstrins.d $sp, $zero, 3, 0 \n\t" +#define VALGRIND_RESTORE_STACK \ + "move $sp, $s0 \n\t" + +/* These CALL_FN_ macros assume that on loongarch64-linux, + sizeof(unsigned long) == 8. */ + +#define CALL_FN_W_v(lval, orig) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[1]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_W(lval, orig, arg1) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[2]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_WW(lval, orig, arg1, arg2) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[3]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_WWW(lval, orig, arg1, arg2, arg3) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[4]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_WWWW(lval, orig, arg1, arg2, arg3, arg4) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[5]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_5W(lval, orig, arg1, arg2, arg3, arg4, arg5) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[6]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_6W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[7]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_7W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[8]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_8W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7, arg8) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[9]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $a7, %1, 64 \n\t" /* arg8 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_9W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7, arg8, arg9) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[10]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "addi.d $sp, $sp, -8 \n\t" \ + "ld.d $a0, %1, 72 \n\t" \ + "st.d $a0, $sp, 0 \n\t" /* arg9 */ \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $a7, %1, 64 \n\t" /* arg8 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_10W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7, arg8, arg9, arg10) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[11]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + _argvec[10] = (unsigned long)(arg10); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "addi.d $sp, $sp, -16 \n\t" \ + "ld.d $a0, %1, 72 \n\t" \ + "st.d $a0, $sp, 0 \n\t" /* arg9 */ \ + "ld.d $a0, %1, 80 \n\t" \ + "st.d $a0, $sp, 8 \n\t" /* arg10 */ \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $a7, %1, 64 \n\t" /* arg8 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_11W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7, arg8, arg9, arg10, \ + arg11) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[12]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + _argvec[10] = (unsigned long)(arg10); \ + _argvec[11] = (unsigned long)(arg11); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "addi.d $sp, $sp, -24 \n\t" \ + "ld.d $a0, %1, 72 \n\t" \ + "st.d $a0, $sp, 0 \n\t" /* arg9 */ \ + "ld.d $a0, %1, 80 \n\t" \ + "st.d $a0, $sp, 8 \n\t" /* arg10 */ \ + "ld.d $a0, %1, 88 \n\t" \ + "st.d $a0, $sp, 16 \n\t" /* arg11 */ \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $a7, %1, 64 \n\t" /* arg8 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#define CALL_FN_W_12W(lval, orig, arg1, arg2, arg3, arg4, arg5, \ + arg6, arg7, arg8, arg9, arg10, \ + arg11, arg12) \ + do { \ + volatile OrigFn _orig = (orig); \ + volatile unsigned long _argvec[13]; \ + volatile unsigned long _res; \ + _argvec[0] = (unsigned long)_orig.nraddr; \ + _argvec[1] = (unsigned long)(arg1); \ + _argvec[2] = (unsigned long)(arg2); \ + _argvec[3] = (unsigned long)(arg3); \ + _argvec[4] = (unsigned long)(arg4); \ + _argvec[5] = (unsigned long)(arg5); \ + _argvec[6] = (unsigned long)(arg6); \ + _argvec[7] = (unsigned long)(arg7); \ + _argvec[8] = (unsigned long)(arg8); \ + _argvec[9] = (unsigned long)(arg9); \ + _argvec[10] = (unsigned long)(arg10); \ + _argvec[11] = (unsigned long)(arg11); \ + _argvec[12] = (unsigned long)(arg12); \ + __asm__ volatile( \ + VALGRIND_ALIGN_STACK \ + "addi.d $sp, $sp, -32 \n\t" \ + "ld.d $a0, %1, 72 \n\t" \ + "st.d $a0, $sp, 0 \n\t" /* arg9 */ \ + "ld.d $a0, %1, 80 \n\t" \ + "st.d $a0, $sp, 8 \n\t" /* arg10 */ \ + "ld.d $a0, %1, 88 \n\t" \ + "st.d $a0, $sp, 16 \n\t" /* arg11 */ \ + "ld.d $a0, %1, 96 \n\t" \ + "st.d $a0, $sp, 24 \n\t" /* arg12 */ \ + "ld.d $a0, %1, 8 \n\t" /* arg1 */ \ + "ld.d $a1, %1, 16 \n\t" /* arg2 */ \ + "ld.d $a2, %1, 24 \n\t" /* arg3 */ \ + "ld.d $a3, %1, 32 \n\t" /* arg4 */ \ + "ld.d $a4, %1, 40 \n\t" /* arg5 */ \ + "ld.d $a5, %1, 48 \n\t" /* arg6 */ \ + "ld.d $a6, %1, 56 \n\t" /* arg7 */ \ + "ld.d $a7, %1, 64 \n\t" /* arg8 */ \ + "ld.d $t8, %1, 0 \n\t" /* target->t8 */ \ + VALGRIND_CALL_NOREDIR_T8 \ + VALGRIND_RESTORE_STACK \ + "move %0, $a0 \n\t" \ + : /*out*/ "=r" (_res) \ + : /*in*/ "r" (&_argvec[0]) \ + : /*trash*/ "memory", __CALLER_SAVED_REGS, "$s0" \ + ); \ + lval = (__typeof__(lval)) _res; \ + } while (0) + +#endif /* PLAT_loongarch64_linux */ + /* ------------------------------------------------------------------ */ /* ARCHITECTURE INDEPENDENT MACROS for CLIENT REQUESTS. */ /* */ @@ -7159,6 +7681,7 @@ VALGRIND_PRINTF_BACKTRACE(const char *format, ...) #undef PLAT_mips32_linux #undef PLAT_mips64_linux #undef PLAT_nanomips_linux +#undef PLAT_loongarch64_linux #undef PLAT_x86_solaris #undef PLAT_amd64_solaris diff --git a/include/vki/vki-linux.h b/include/vki/vki-linux.h index be3d766..0a60c0a 100644 --- a/include/vki/vki-linux.h +++ b/include/vki/vki-linux.h @@ -97,6 +97,8 @@ # include "vki-posixtypes-mips64-linux.h" #elif defined(VGA_nanomips) # include "vki-posixtypes-nanomips-linux.h" +#elif defined(VGA_loongarch64) +# include "vki-posixtypes-loongarch64-linux.h" #else # error Unknown platform #endif @@ -225,6 +227,8 @@ typedef unsigned int vki_uint; # include "vki-mips64-linux.h" #elif defined(VGA_nanomips) # include "vki-nanomips-linux.h" +#elif defined(VGA_loongarch64) +# include "vki-loongarch64-linux.h" #else # error Unknown platform #endif @@ -531,6 +535,7 @@ typedef struct vki_siginfo { * Digital reserves positive values for kernel-generated signals. */ #define VKI_SI_USER 0 /* sent by kill, sigsend, raise */ +#define VKI_SI_KERNEL 0x80 /* sent by the kernel from somewhere */ #define VKI_SI_TKILL -6 /* sent by tkill system call */ /* diff --git a/include/vki/vki-loongarch64-linux.h b/include/vki/vki-loongarch64-linux.h new file mode 100644 index 0000000..97d3f66 --- /dev/null +++ b/include/vki/vki-loongarch64-linux.h @@ -0,0 +1,811 @@ + +/*--------------------------------------------------------------------*/ +/*--- loongarch/Linux-specific kernel interface. ---*/ +/*--- vki-loongarch64-linux.h ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . +*/ + +#ifndef __VKI_LOONGARCH64_LINUX_H +#define __VKI_LOONGARCH64_LINUX_H + +// loongarch64 is little-endian. +#define VKI_LITTLE_ENDIAN 1 + +//---------------------------------------------------------------------- +// From linux-5.15.2/include/uapi/asm-generic/int-ll64.h +//---------------------------------------------------------------------- + +typedef __signed__ char __vki_s8; +typedef unsigned char __vki_u8; + +typedef __signed__ short __vki_s16; +typedef unsigned short __vki_u16; + +typedef __signed__ int __vki_s32; +typedef unsigned int __vki_u32; + +typedef __signed__ long long __vki_s64; +typedef unsigned long long __vki_u64; + +//---------------------------------------------------------------------- +// From linux-5.15.2/include/asm-generic/int-ll64.h +//---------------------------------------------------------------------- + +typedef __vki_s8 vki_s8; +typedef __vki_u8 vki_u8; +typedef __vki_s16 vki_s16; +typedef __vki_u16 vki_u16; +typedef __vki_s32 vki_s32; +typedef __vki_u32 vki_u32; +typedef __vki_s64 vki_s64; +typedef __vki_u64 vki_u64; + +//---------------------------------------------------------------------- +// From linux-5.15.2/include/linux/types.h +//---------------------------------------------------------------------- + +typedef vki_u8 vki_u_int8_t; +typedef vki_s8 vki_int8_t; +typedef vki_u16 vki_u_int16_t; +typedef vki_s16 vki_int16_t; +typedef vki_u32 vki_u_int32_t; +typedef vki_s32 vki_int32_t; + +typedef vki_u8 vki_uint8_t; +typedef vki_u16 vki_uint16_t; +typedef vki_u32 vki_uint32_t; + +typedef vki_u64 vki_uint64_t; +typedef vki_u64 vki_u_int64_t; +typedef vki_s64 vki_int64_t; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/arch/loongarch/include/asm/page.h +//---------------------------------------------------------------------- + +/* loongarch64 uses runtime pagesize detection */ +extern UWord VKI_PAGE_SHIFT; +extern UWord VKI_PAGE_SIZE; +#define VKI_PAGE_MASK (~(PAGE_SIZE - 1)) +#define VKI_MAX_PAGE_SHIFT 16 +#define VKI_MAX_PAGE_SIZE (1UL << VKI_MAX_PAGE_SHIFT) + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/arch/loongarch/include/asm/shmparam.h +//---------------------------------------------------------------------- + +#define VKI_SHMLBA 0x00010000 // SZ_64K + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/arch/loongarch/include/uapi/asm/signal.h +//---------------------------------------------------------------------- + +#define VKI_MINSIGSTKSZ 4096 +#define VKI_SIGSTKSZ 16384 + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/signal-defs.h +//---------------------------------------------------------------------- + +#define VKI_SA_NOCLDSTOP 0x00000001 +#define VKI_SA_NOCLDWAIT 0x00000002 +#define VKI_SA_SIGINFO 0x00000004 +/* 0x00000008 used on alpha, mips, parisc */ +/* 0x00000010 used on alpha, parisc */ +/* 0x00000020 used on alpha, parisc, sparc */ +/* 0x00000040 used on alpha, parisc */ +/* 0x00000080 used on parisc */ +/* 0x00000100 used on sparc */ +/* 0x00000200 used on sparc */ +#define VKI_SA_UNSUPPORTED 0x00000400 +#define VKI_SA_EXPOSE_TAGBITS 0x00000800 +/* 0x00010000 used on mips */ +/* 0x00800000 used for internal SA_IMMUTABLE */ +/* 0x01000000 used on x86 */ +/* 0x02000000 used on x86 */ +/* + * New architectures should not define the obsolete + * VKI_SA_RESTORER 0x04000000 + */ +#define VKI_SA_ONSTACK 0x08000000 +#define VKI_SA_RESTART 0x10000000 +#define VKI_SA_NODEFER 0x40000000 +#define VKI_SA_RESETHAND 0x80000000 + +#define VKI_SA_NOMASK VKI_SA_NODEFER +#define VKI_SA_ONESHOT VKI_SA_RESETHAND + +#define VKI_SIG_BLOCK 0 /* for blocking signals */ +#define VKI_SIG_UNBLOCK 1 /* for unblocking signals */ +#define VKI_SIG_SETMASK 2 /* for setting the signal mask */ + +typedef void __vki_signalfn_t(int); +typedef __vki_signalfn_t __user *__vki_sighandler_t; + +typedef void __vki_restorefn_t(void); +typedef __vki_restorefn_t __user *__vki_igrestore_t; + +#define VKI_SIG_DFL ((__vki_sighandler_t)0) /* default signal handling */ +#define VKI_SIG_IGN ((__vki_sighandler_t)1) /* ignore signal */ +#define VKI_SIG_ERR ((__vki_sighandler_t)-1) /* error return from signal */ + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/signal.h +//---------------------------------------------------------------------- + +#define _VKI_NSIG 64 +#define _VKI_NSIG_BPW 64 // __BITS_PER_LONG == 64 +#define _VKI_NSIG_WORDS (_VKI_NSIG / _VKI_NSIG_BPW) + +#define VKI_SIGHUP 1 +#define VKI_SIGINT 2 +#define VKI_SIGQUIT 3 +#define VKI_SIGILL 4 +#define VKI_SIGTRAP 5 +#define VKI_SIGABRT 6 +#define VKI_SIGIOT 6 +#define VKI_SIGBUS 7 +#define VKI_SIGFPE 8 +#define VKI_SIGKILL 9 +#define VKI_SIGUSR1 10 +#define VKI_SIGSEGV 11 +#define VKI_SIGUSR2 12 +#define VKI_SIGPIPE 13 +#define VKI_SIGALRM 14 +#define VKI_SIGTERM 15 +#define VKI_SIGSTKFLT 16 +#define VKI_SIGCHLD 17 +#define VKI_SIGCONT 18 +#define VKI_SIGSTOP 19 +#define VKI_SIGTSTP 20 +#define VKI_SIGTTIN 21 +#define VKI_SIGTTOU 22 +#define VKI_SIGURG 23 +#define VKI_SIGXCPU 24 +#define VKI_SIGXFSZ 25 +#define VKI_SIGVTALRM 26 +#define VKI_SIGPROF 27 +#define VKI_SIGWINCH 28 +#define VKI_SIGIO 29 +#define VKI_SIGPOLL VKI_SIGIO +/* +#define VKI_SIGLOST 29 +*/ +#define VKI_SIGPWR 30 +#define VKI_SIGSYS 31 +#define VKI_SIGUNUSED 31 + +#define VKI_SIGRTMIN 32 +#define VKI_SIGRTMAX _VKI_NSIG + +typedef struct { + unsigned long sig[_VKI_NSIG_WORDS]; +} vki_sigset_t; + +typedef unsigned long vki_old_sigset_t; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/linux/signal.h +//---------------------------------------------------------------------- + +#define VKI_SS_ONSTACK 1 +#define VKI_SS_DISABLE 2 + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/linux/signal_types.h +//---------------------------------------------------------------------- + +struct vki_sigaction { + __vki_sighandler_t sa_handler; + unsigned long sa_flags; + vki_sigset_t sa_mask; /* mask last for extensibility */ +}; + +struct vki_sigaction_base { + // [[Nb: a 'k' prefix is added to "sa_handler" because + // bits/sigaction.h (which gets dragged in somehow via signal.h) + // #defines it as something else. Since that is done for glibc's + // purposes, which we don't care about here, we use our own name.]] + __vki_sighandler_t ksa_handler; + unsigned long sa_flags; + vki_sigset_t sa_mask; /* mask last for extensibility */ +}; + +/* On Linux we use the same type for passing sigactions to + and from the kernel. Hence: */ +typedef struct vki_sigaction_base vki_sigaction_toK_t; +typedef struct vki_sigaction_base vki_sigaction_fromK_t; + +typedef struct vki_sigaltstack { + void __user *ss_sp; + int ss_flags; + __vki_kernel_size_t ss_size; +} vki_stack_t; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/arch/loongarch/include/uapi/asm/sigcontext.h +//---------------------------------------------------------------------- + +struct vki_sigcontext { + __vki_u64 sc_pc; + __vki_u64 sc_regs[32]; + __vki_u32 sc_flags; + __vki_u64 sc_extcontext[0] __attribute__((__aligned__(16))); +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/linux/mman.h +//---------------------------------------------------------------------- + +#define VKI_MAP_SHARED 0x01 /* Share changes */ +#define VKI_MAP_PRIVATE 0x02 /* Changes are private */ +#define VKI_MAP_SHARED_VALIDATE 0x03 /* share + validate extension flags */ + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/mman-common.h +//---------------------------------------------------------------------- + +#define VKI_PROT_READ 0x1 /* page can be read */ +#define VKI_PROT_WRITE 0x2 /* page can be written */ +#define VKI_PROT_EXEC 0x4 /* page can be executed */ +#define VKI_PROT_SEM 0x8 /* page may be used for atomic ops */ +/* 0x10 reserved for arch-specific use */ +/* 0x20 reserved for arch-specific use */ +#define VKI_PROT_NONE 0x0 /* page can not be accessed */ +#define VKI_PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */ +#define VKI_PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */ + +/* 0x01 - 0x03 are defined in linux/mman.h */ +#define VKI_MAP_TYPE 0x0f /* Mask for type of mapping */ +#define VKI_MAP_FIXED 0x10 /* Interpret addr exactly */ +#define VKI_MAP_ANONYMOUS 0x20 /* don't use a file */ + +/* 0x0100 - 0x4000 flags are defined in asm-generic/mman.h */ +#define VKI_MAP_POPULATE 0x008000 /* populate (prefault) pagetables */ +#define VKI_MAP_NONBLOCK 0x010000 /* do not block on IO */ +#define VKI_MAP_STACK 0x020000 /* give out an address that is best suited for process/thread stacks */ +#define VKI_MAP_HUGETLB 0x040000 /* create a huge page mapping */ +#define VKI_MAP_SYNC 0x080000 /* perform synchronous page faults for the mapping */ +#define VKI_MAP_FIXED_NOREPLACE 0x100000 /* MAP_FIXED which doesn't unmap underlying mapping */ + +#define VKI_MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be uninitialized */ + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/fcntl.h +//---------------------------------------------------------------------- + +#define VKI_O_ACCMODE 00000003 +#define VKI_O_RDONLY 00000000 +#define VKI_O_WRONLY 00000001 +#define VKI_O_RDWR 00000002 +#define VKI_O_CREAT 00000100 /* not fcntl */ +#define VKI_O_EXCL 00000200 /* not fcntl */ +#define VKI_O_NOCTTY 00000400 /* not fcntl */ +#define VKI_O_TRUNC 00001000 /* not fcntl */ +#define VKI_O_APPEND 00002000 +#define VKI_O_NONBLOCK 00004000 +#define VKI_O_DSYNC 00010000 /* used to be O_SYNC, see below */ +#define VKI_FASYNC 00020000 /* fcntl, for BSD compatibility */ +#define VKI_O_DIRECT 00040000 /* direct disk access hint */ +#define VKI_O_LARGEFILE 00100000 + +#define VKI_F_DUPFD 0 /* dup */ +#define VKI_F_GETFD 1 /* get close_on_exec */ +#define VKI_F_SETFD 2 /* set/clear close_on_exec */ +#define VKI_F_GETFL 3 /* get file->f_flags */ +#define VKI_F_SETFL 4 /* set file->f_flags */ +#define VKI_F_GETLK 5 +#define VKI_F_SETLK 6 +#define VKI_F_SETLKW 7 +#define VKI_F_SETOWN 8 /* for sockets. */ +#define VKI_F_GETOWN 9 /* for sockets. */ +#define VKI_F_SETSIG 10 /* for sockets. */ +#define VKI_F_GETSIG 11 /* for sockets. */ + +#define VKI_F_SETOWN_EX 15 +#define VKI_F_GETOWN_EX 16 + +#define VKI_F_GETOWNER_UIDS 17 + +#define VKI_F_OFD_GETLK 36 +#define VKI_F_OFD_SETLK 37 +#define VKI_F_OFD_SETLKW 38 + +#define VKI_F_OWNER_TID 0 +#define VKI_F_OWNER_PID 1 +#define VKI_F_OWNER_PGRP 2 + +struct vki_f_owner_ex { + int type; + __vki_kernel_pid_t pid; +}; + +#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */ + +#define VKI_F_RDLCK 0 +#define VKI_F_WRLCK 1 +#define VKI_F_UNLCK 2 + +#define VKI_F_EXLCK 4 /* or 3 */ +#define VKI_F_SHLCK 8 /* or 4 */ + +#define VKI_LOCK_SH 1 /* shared lock */ +#define VKI_LOCK_EX 2 /* exclusive lock */ +#define VKI_LOCK_NB 4 /* or'd with one of the above to prevent blocking */ +#define VKI_LOCK_UN 8 /* remove lock */ + +#define VKI_LOCK_MAND 32 /* This is a mandatory flock ... */ +#define VKI_LOCK_READ 64 /* which allows concurrent read operations */ +#define VKI_LOCK_WRITE 128 /* which allows concurrent write operations */ +#define VKI_LOCK_RW 192 /* which allows concurrent read & write ops */ + +#define VKI_F_LINUX_SPECIFIC_BASE 1024 + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/linux/fcntl.h +//---------------------------------------------------------------------- + +#define VKI_AT_FDCWD -100 /* Special value used to indicate + openat should use the current + working directory. */ + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/resource.h +//---------------------------------------------------------------------- + +#define VKI_RLIMIT_DATA 2 /* max data size */ +#define VKI_RLIMIT_STACK 3 /* max stack size */ +#define VKI_RLIMIT_CORE 4 /* max core file size */ +#define VKI_RLIMIT_NOFILE 7 /* max number of open files */ + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/socket.h +//---------------------------------------------------------------------- + +#define VKI_SOL_SOCKET 1 +#define VKI_SO_TYPE 3 + +#define VKI_SO_ATTACH_FILTER 26 + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/sockios.h +//---------------------------------------------------------------------- + +#define VKI_FIOSETOWN 0x8901 +#define VKI_SIOCSPGRP 0x8902 +#define VKI_FIOGETOWN 0x8903 +#define VKI_SIOCGPGRP 0x8904 +#define VKI_SIOCATMARK 0x8905 +#define VKI_SIOCGSTAMP_OLD 0x8906 /* Get stamp (timeval) */ +#define VKI_SIOCGSTAMPNS_OLD 0x8907 /* Get stamp (timespec) */ + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/linux/sockios.h +//---------------------------------------------------------------------- + +#define VKI_SIOCGSTAMP VKI_SIOCGSTAMP_OLD +#define VKI_SIOCGSTAMPNS VKI_SIOCGSTAMPNS_OLD + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/stat.h +//---------------------------------------------------------------------- + +struct vki_stat { + unsigned long st_dev; /* Device. */ + unsigned long st_ino; /* File serial number. */ + unsigned int st_mode; /* File mode. */ + unsigned int st_nlink; /* Link count. */ + unsigned int st_uid; /* User ID of the file's owner. */ + unsigned int st_gid; /* Group ID of the file's group. */ + unsigned long st_rdev; /* Device number, if device. */ + unsigned long __pad1; + long st_size; /* Size of file, in bytes. */ + int st_blksize; /* Optimal block size for I/O. */ + int __pad2; + long st_blocks; /* Number 512-byte blocks allocated. */ + long st_atime; /* Time of last access. */ + unsigned long st_atime_nsec; + long st_mtime; /* Time of last modification. */ + unsigned long st_mtime_nsec; + long st_ctime; /* Time of last status change. */ + unsigned long st_ctime_nsec; + unsigned int __unused4; + unsigned int __unused5; +}; + +struct vki_stat64 { + unsigned long long st_dev; /* Device. */ + unsigned long long st_ino; /* File serial number. */ + unsigned int st_mode; /* File mode. */ + unsigned int st_nlink; /* Link count. */ + unsigned int st_uid; /* User ID of the file's owner. */ + unsigned int st_gid; /* Group ID of the file's group. */ + unsigned long long st_rdev; /* Device number, if device. */ + unsigned long long __pad1; + long long st_size; /* Size of file, in bytes. */ + int st_blksize; /* Optimal block size for I/O. */ + int __pad2; + long long st_blocks; /* Number 512-byte blocks allocated. */ + int st_atime; /* Time of last access. */ + unsigned int st_atime_nsec; + int st_mtime; /* Time of last modification. */ + unsigned int st_mtime_nsec; + int st_ctime; /* Time of last status change. */ + unsigned int st_ctime_nsec; + unsigned int __unused4; + unsigned int __unused5; +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/statfs.h +//---------------------------------------------------------------------- + +#define __vki_statfs_word __vki_kernel_long_t + +struct vki_statfs { + __vki_statfs_word f_type; + __vki_statfs_word f_bsize; + __vki_statfs_word f_blocks; + __vki_statfs_word f_bfree; + __vki_statfs_word f_bavail; + __vki_statfs_word f_files; + __vki_statfs_word f_ffree; + __vki_kernel_fsid_t f_fsid; + __vki_statfs_word f_namelen; + __vki_statfs_word f_frsize; + __vki_statfs_word f_flags; + __vki_statfs_word f_spare[4]; +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/termios.h +//---------------------------------------------------------------------- + +struct vki_winsize { + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; +}; + +#define VKI_NCC 8 +struct vki_termio { + unsigned short c_iflag; /* input mode flags */ + unsigned short c_oflag; /* output mode flags */ + unsigned short c_cflag; /* control mode flags */ + unsigned short c_lflag; /* local mode flags */ + unsigned char c_line; /* line discipline */ + unsigned char c_cc[VKI_NCC]; /* control characters */ +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/termbits.h +//---------------------------------------------------------------------- + +typedef unsigned char vki_cc_t; +typedef unsigned int vki_speed_t; +typedef unsigned int vki_tcflag_t; + +#define VKI_NCCS 19 +struct vki_termios { + vki_tcflag_t c_iflag; /* input mode flags */ + vki_tcflag_t c_oflag; /* output mode flags */ + vki_tcflag_t c_cflag; /* control mode flags */ + vki_tcflag_t c_lflag; /* local mode flags */ + vki_cc_t c_line; /* line discipline */ + vki_cc_t c_cc[VKI_NCCS]; /* control characters */ +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/ioctl.h +//---------------------------------------------------------------------- + +#define _VKI_IOC_NRBITS 8 +#define _VKI_IOC_TYPEBITS 8 +#define _VKI_IOC_SIZEBITS 14 +#define _VKI_IOC_DIRBITS 2 + +#define _VKI_IOC_NRMASK ((1 << _VKI_IOC_NRBITS)-1) +#define _VKI_IOC_TYPEMASK ((1 << _VKI_IOC_TYPEBITS)-1) +#define _VKI_IOC_SIZEMASK ((1 << _VKI_IOC_SIZEBITS)-1) +#define _VKI_IOC_DIRMASK ((1 << _VKI_IOC_DIRBITS)-1) + +#define _VKI_IOC_NRSHIFT 0 +#define _VKI_IOC_TYPESHIFT (_VKI_IOC_NRSHIFT+_VKI_IOC_NRBITS) +#define _VKI_IOC_SIZESHIFT (_VKI_IOC_TYPESHIFT+_VKI_IOC_TYPEBITS) +#define _VKI_IOC_DIRSHIFT (_VKI_IOC_SIZESHIFT+_VKI_IOC_SIZEBITS) + +#define _VKI_IOC_NONE 0U +#define _VKI_IOC_WRITE 1U +#define _VKI_IOC_READ 2U + +#define _VKI_IOC(dir,type,nr,size) \ + (((dir) << _VKI_IOC_DIRSHIFT) | \ + ((type) << _VKI_IOC_TYPESHIFT) | \ + ((nr) << _VKI_IOC_NRSHIFT) | \ + ((size) << _VKI_IOC_SIZESHIFT)) + +#define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0) +#define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size))) +#define _VKI_IOW(type,nr,size) _VKI_IOC(_VKI_IOC_WRITE,(type),(nr),(_VKI_IOC_TYPECHECK(size))) +#define _VKI_IOWR(type,nr,size) _VKI_IOC(_VKI_IOC_READ|_VKI_IOC_WRITE,(type),(nr),(_VKI_IOC_TYPECHECK(size))) +#define _VKI_IOR_BAD(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),sizeof(size)) +#define _VKI_IOW_BAD(type,nr,size) _VKI_IOC(_VKI_IOC_WRITE,(type),(nr),sizeof(size)) +#define _VKI_IOWR_BAD(type,nr,size) _VKI_IOC(_VKI_IOC_READ|_VKI_IOC_WRITE,(type),(nr),sizeof(size)) + +#define _VKI_IOC_DIR(nr) (((nr) >> _VKI_IOC_DIRSHIFT) & _VKI_IOC_DIRMASK) +#define _VKI_IOC_TYPE(nr) (((nr) >> _VKI_IOC_TYPESHIFT) & _VKI_IOC_TYPEMASK) +#define _VKI_IOC_NR(nr) (((nr) >> _VKI_IOC_NRSHIFT) & _VKI_IOC_NRMASK) +#define _VKI_IOC_SIZE(nr) (((nr) >> _VKI_IOC_SIZESHIFT) & _VKI_IOC_SIZEMASK) + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/ioctls.h +//---------------------------------------------------------------------- + +#define VKI_TCGETS 0x5401 +#define VKI_TCSETS 0x5402 +#define VKI_TCSETSW 0x5403 +#define VKI_TCSETSF 0x5404 +#define VKI_TCGETA 0x5405 +#define VKI_TCSETA 0x5406 +#define VKI_TCSETAW 0x5407 +#define VKI_TCSETAF 0x5408 +#define VKI_TCSBRK 0x5409 +#define VKI_TCXONC 0x540A +#define VKI_TCFLSH 0x540B +#define VKI_TIOCEXCL 0x540C +#define VKI_TIOCNXCL 0x540D +#define VKI_TIOCSCTTY 0x540E +#define VKI_TIOCGPGRP 0x540F +#define VKI_TIOCSPGRP 0x5410 +#define VKI_TIOCOUTQ 0x5411 +#define VKI_TIOCSTI 0x5412 +#define VKI_TIOCGWINSZ 0x5413 +#define VKI_TIOCSWINSZ 0x5414 +#define VKI_TIOCMGET 0x5415 +#define VKI_TIOCMBIS 0x5416 +#define VKI_TIOCMBIC 0x5417 +#define VKI_TIOCMSET 0x5418 +#define VKI_TIOCGSOFTCAR 0x5419 +#define VKI_TIOCSSOFTCAR 0x541A +#define VKI_FIONREAD 0x541B +#define VKI_TIOCINQ VKI_FIONREAD +#define VKI_TIOCLINUX 0x541C +#define VKI_TIOCCONS 0x541D +#define VKI_TIOCGSERIAL 0x541E +#define VKI_TIOCSSERIAL 0x541F +#define VKI_TIOCPKT 0x5420 +#define VKI_FIONBIO 0x5421 +#define VKI_TIOCNOTTY 0x5422 +#define VKI_TIOCSETD 0x5423 +#define VKI_TIOCGETD 0x5424 +#define VKI_TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ +#define VKI_TIOCSBRK 0x5427 /* BSD compatibility */ +#define VKI_TIOCCBRK 0x5428 /* BSD compatibility */ +#define VKI_TIOCGSID 0x5429 /* Return the session ID of FD */ +#define VKI_TCGETS2 _VKI_IOR('T', 0x2A, struct termios2) +#define VKI_TCSETS2 _VKI_IOW('T', 0x2B, struct termios2) +#define VKI_TCSETSW2 _VKI_IOW('T', 0x2C, struct termios2) +#define VKI_TCSETSF2 _VKI_IOW('T', 0x2D, struct termios2) +#define VKI_TIOCGRS485 0x542E +#define VKI_TIOCSRS485 0x542F +#define VKI_TIOCGPTN _VKI_IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ +#define VKI_TIOCSPTLCK _VKI_IOW('T', 0x31, int) /* Lock/unlock Pty */ +#define VKI_TIOCGDEV _VKI_IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */ +#define VKI_TCGETX 0x5432 /* SYS5 TCGETX compatibility */ +#define VKI_TCSETX 0x5433 +#define VKI_TCSETXF 0x5434 +#define VKI_TCSETXW 0x5435 +#define VKI_TIOCSIG _VKI_IOW('T', 0x36, int) /* pty: generate signal */ +#define VKI_TIOCVHANGUP 0x5437 +#define VKI_TIOCGPKT _VKI_IOR('T', 0x38, int) /* Get packet mode state */ +#define VKI_TIOCGPTLCK _VKI_IOR('T', 0x39, int) /* Get Pty lock state */ +#define VKI_TIOCGEXCL _VKI_IOR('T', 0x40, int) /* Get exclusive mode state */ +#define VKI_TIOCGPTPEER _VKI_IO('T', 0x41) /* Safely open the slave */ +#define VKI_TIOCGISO7816 _VKI_IOR('T', 0x42, struct serial_iso7816) +#define VKI_TIOCSISO7816 _VKI_IOWR('T', 0x43, struct serial_iso7816) + +#define VKI_FIONCLEX 0x5450 +#define VKI_FIOCLEX 0x5451 +#define VKI_FIOASYNC 0x5452 +#define VKI_TIOCSERCONFIG 0x5453 +#define VKI_TIOCSERGWILD 0x5454 +#define VKI_TIOCSERSWILD 0x5455 +#define VKI_TIOCGLCKTRMIOS 0x5456 +#define VKI_TIOCSLCKTRMIOS 0x5457 +#define VKI_TIOCSERGSTRUCT 0x5458 /* For debugging only */ +#define VKI_TIOCSERGETLSR 0x5459 /* Get line status register */ +#define VKI_TIOCSERGETMULTI 0x545A /* Get multiport config */ +#define VKI_TIOCSERSETMULTI 0x545B /* Set multiport config */ + +#define VKI_TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ +#define VKI_TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ + +#define VKI_FIOQSIZE 0x5460 + +#define VKI_TIOCPKT_DATA 0 +#define VKI_TIOCPKT_FLUSHREAD 1 +#define VKI_TIOCPKT_FLUSHWRITE 2 +#define VKI_TIOCPKT_STOP 4 +#define VKI_TIOCPKT_START 8 +#define VKI_TIOCPKT_NOSTOP 16 +#define VKI_TIOCPKT_DOSTOP 32 +#define VKI_TIOCPKT_IOCTL 64 + +#define VKI_TIOCSER_TEMT 0x01 /* Transmitter physically empty */ + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/poll.h +//---------------------------------------------------------------------- + +#define VKI_POLLIN 0x0001 + +struct vki_pollfd { + int fd; + short events; + short revents; +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/arch/loongarch/include/asm/elf.h +//---------------------------------------------------------------------- + +#define VKI_ELF_NGREG 45 +#define VKI_ELF_NFPREG 34 + +typedef unsigned long vki_elf_greg_t; +typedef vki_elf_greg_t vki_elf_gregset_t[VKI_ELF_NGREG]; + +typedef double vki_elf_fpreg_t; +typedef vki_elf_fpreg_t vki_elf_fpregset_t[VKI_ELF_NFPREG]; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/arch/loongarch/include/uapi/asm/ucontext.h +//---------------------------------------------------------------------- + +struct vki_ucontext { + unsigned long uc_flags; + struct vki_ucontext *uc_link; + vki_stack_t uc_stack; + vki_sigset_t uc_sigmask; + __vki_u8 __unused[1024 / 8 - sizeof(vki_sigset_t)]; + struct vki_sigcontext uc_mcontext; +}; + +typedef char vki_modify_ldt_t; + + + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/ipcbuf.h +//---------------------------------------------------------------------- + +struct vki_ipc64_perm { + __vki_kernel_key_t key; + __vki_kernel_uid32_t uid; + __vki_kernel_gid32_t gid; + __vki_kernel_uid32_t cuid; + __vki_kernel_gid32_t cgid; + __vki_kernel_mode_t mode; + unsigned char __pad1[4 - sizeof(__vki_kernel_mode_t)]; /* pad if mode_t is u16: */ + unsigned short seq; + unsigned short __pad2; + __vki_kernel_ulong_t __unused1; + __vki_kernel_ulong_t __unused2; +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/sembuf.h +//---------------------------------------------------------------------- +struct vki_semid64_ds { + struct vki_ipc64_perm sem_perm; /* permissions .. see ipc.h */ + long sem_otime; /* last semop time */ + long sem_ctime; /* last change time */ + unsigned long sem_nsems; /* no. of semaphores in array */ + unsigned long __unused3; + unsigned long __unused4; +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/msgbuf.h +//---------------------------------------------------------------------- + +struct vki_msqid64_ds { + struct vki_ipc64_perm msg_perm; + long msg_stime; /* last msgsnd time */ + long msg_rtime; /* last msgrcv time */ + long msg_ctime; /* last change time */ + unsigned long msg_cbytes; /* current number of bytes on queue */ + unsigned long msg_qnum; /* number of messages in queue */ + unsigned long msg_qbytes; /* max number of bytes on queue */ + __vki_kernel_pid_t msg_lspid; /* pid of last msgsnd */ + __vki_kernel_pid_t msg_lrpid; /* last receive pid */ + unsigned long __unused4; + unsigned long __unused5; +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/shmbuf.h +//---------------------------------------------------------------------- + +struct vki_shmid64_ds { + struct vki_ipc64_perm shm_perm; /* operation perms */ + vki_size_t shm_segsz; /* size of segment (bytes) */ + long shm_atime; /* last attach time */ + long shm_dtime; /* last detach time */ + long shm_ctime; /* last change time */ + __vki_kernel_pid_t shm_cpid; /* pid of creator */ + __vki_kernel_pid_t shm_lpid; /* pid of last operator */ + unsigned long shm_nattch; /* no. of current attaches */ + unsigned long __unused4; + unsigned long __unused5; +}; + +struct vki_shminfo64 { + unsigned long shmmax; + unsigned long shmmin; + unsigned long shmmni; + unsigned long shmseg; + unsigned long shmall; + unsigned long __unused1; + unsigned long __unused2; + unsigned long __unused3; + unsigned long __unused4; +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/arch/loongarch/include/uapi/asm/ptrace.h +//---------------------------------------------------------------------- + +struct vki_user_pt_regs { + /* Saved main processor registers. */ + unsigned long regs[32]; + + /* Original syscall arg0. */ + unsigned long orig_a0; + + /* Saved special registers. */ + unsigned long csr_era; + unsigned long csr_badv; + unsigned long reserved[10]; +} __attribute__((aligned(8))); + +#define vki_user_regs_struct vki_user_pt_regs + +struct vki_user_fp_state { + vki_uint64_t fpr[32]; + vki_uint64_t fcc; + vki_uint32_t fcsr; +}; + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/errno.h +//---------------------------------------------------------------------- + +#define VKI_ENOSYS 38 /* Invalid system call number */ +#define VKI_EOVERFLOW 75 /* Value too large for defined data type */ + +#endif // __VKI_LOONGARCH64_LINUX_H + +/*--------------------------------------------------------------------*/ +/*--- end vki-loongarch64-linux.h ---*/ +/*--------------------------------------------------------------------*/ diff --git a/include/vki/vki-posixtypes-loongarch64-linux.h b/include/vki/vki-posixtypes-loongarch64-linux.h new file mode 100644 index 0000000..0282a2a --- /dev/null +++ b/include/vki/vki-posixtypes-loongarch64-linux.h @@ -0,0 +1,76 @@ + +/*--------------------------------------------------------------------*/ +/*--- loongarch/Linux-specific kernel interface: posix types. ---*/ +/*--- vki-posixtypes-loongarch64-linux.h ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#ifndef __VKI_POSIXTYPES_LOONGARCH64_LINUX_H +#define __VKI_POSIXTYPES_LOONGARCH64_LINUX_H + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/posix_types.h +//---------------------------------------------------------------------- + +typedef long __vki_kernel_long_t; +typedef unsigned long __vki_kernel_ulong_t; +typedef __vki_kernel_ulong_t __vki_kernel_ino_t; +typedef unsigned int __vki_kernel_mode_t; +typedef int __vki_kernel_pid_t; +typedef int __vki_kernel_ipc_pid_t; +typedef unsigned int __vki_kernel_uid_t; +typedef unsigned int __vki_kernel_gid_t; +typedef __vki_kernel_long_t __vki_kernel_suseconds_t; +typedef int __vki_kernel_daddr_t; +typedef unsigned int __vki_kernel_uid32_t; +typedef unsigned int __vki_kernel_gid32_t; +typedef __vki_kernel_uid_t __vki_kernel_old_uid_t; +typedef __vki_kernel_gid_t __vki_kernel_old_gid_t; +typedef unsigned int __vki_kernel_old_dev_t; + +typedef __vki_kernel_ulong_t __vki_kernel_size_t; +typedef __vki_kernel_long_t __vki_kernel_ssize_t; +typedef __vki_kernel_long_t __vki_kernel_ptrdiff_t; + +typedef struct { + int val[2]; +} __vki_kernel_fsid_t; + +typedef __vki_kernel_long_t __vki_kernel_off_t; +typedef long long __vki_kernel_loff_t; +typedef __vki_kernel_long_t __vki_kernel_old_time_t; +typedef __vki_kernel_long_t __vki_kernel_time_t; +typedef long long __vki_kernel_time64_t; +typedef __vki_kernel_long_t __vki_kernel_clock_t; +typedef int __vki_kernel_timer_t; +typedef int __vki_kernel_clockid_t; +typedef char * __vki_kernel_caddr_t; +typedef unsigned short __vki_kernel_uid16_t; +typedef unsigned short __vki_kernel_gid16_t; + +#endif // __VKI_POSIXTYPES_LOONGARCH64_LINUX_H + +/*--------------------------------------------------------------------*/ +/*--- end vki-posixtypes-loongarch64-linux.h ---*/ +/*--------------------------------------------------------------------*/ diff --git a/include/vki/vki-scnums-loongarch64-linux.h b/include/vki/vki-scnums-loongarch64-linux.h new file mode 100644 index 0000000..b7ac621 --- /dev/null +++ b/include/vki/vki-scnums-loongarch64-linux.h @@ -0,0 +1,356 @@ +/*--------------------------------------------------------------------*/ +/*--- System call numbers for loongarch-linux. ---*/ +/*--- vki-scnums-loongarch64-linux.h ---*/ +/*--------------------------------------------------------------------*/ + +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + Copyright (C) 2021-2022 Loongson Technology Corporation Limited + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#ifndef __VKI_SCNUMS_LOONGARCH64_LINUX_H +#define __VKI_SCNUMS_LOONGARCH64_LINUX_H + +//---------------------------------------------------------------------- +// From linux-5.19-rc1/include/uapi/asm-generic/unistd.h +//---------------------------------------------------------------------- + +#define __NR_io_setup 0 +#define __NR_io_destroy 1 +#define __NR_io_submit 2 +#define __NR_io_cancel 3 +#define __NR_io_getevents 4 +#define __NR_setxattr 5 +#define __NR_lsetxattr 6 +#define __NR_fsetxattr 7 +#define __NR_getxattr 8 +#define __NR_lgetxattr 9 +#define __NR_fgetxattr 10 +#define __NR_listxattr 11 +#define __NR_llistxattr 12 +#define __NR_flistxattr 13 +#define __NR_removexattr 14 +#define __NR_lremovexattr 15 +#define __NR_fremovexattr 16 +#define __NR_getcwd 17 +#define __NR_lookup_dcookie 18 +#define __NR_eventfd2 19 +#define __NR_epoll_create1 20 +#define __NR_epoll_ctl 21 +#define __NR_epoll_pwait 22 +#define __NR_dup 23 +#define __NR_dup3 24 +#define __NR3264_fcntl 25 +#define __NR_inotify_init1 26 +#define __NR_inotify_add_watch 27 +#define __NR_inotify_rm_watch 28 +#define __NR_ioctl 29 +#define __NR_ioprio_set 30 +#define __NR_ioprio_get 31 +#define __NR_flock 32 +#define __NR_mknodat 33 +#define __NR_mkdirat 34 +#define __NR_unlinkat 35 +#define __NR_symlinkat 36 +#define __NR_linkat 37 +// #define __NR_renameat 38 +#define __NR_umount2 39 +#define __NR_mount 40 +#define __NR_pivot_root 41 +#define __NR_nfsservctl 42 +#define __NR3264_statfs 43 +#define __NR3264_fstatfs 44 +#define __NR3264_truncate 45 +#define __NR3264_ftruncate 46 +#define __NR_fallocate 47 +#define __NR_faccessat 48 +#define __NR_chdir 49 +#define __NR_fchdir 50 +#define __NR_chroot 51 +#define __NR_fchmod 52 +#define __NR_fchmodat 53 +#define __NR_fchownat 54 +#define __NR_fchown 55 +#define __NR_openat 56 +#define __NR_close 57 +#define __NR_vhangup 58 +#define __NR_pipe2 59 +#define __NR_quotactl 60 +#define __NR_getdents64 61 +#define __NR3264_lseek 62 +#define __NR_read 63 +#define __NR_write 64 +#define __NR_readv 65 +#define __NR_writev 66 +#define __NR_pread64 67 +#define __NR_pwrite64 68 +#define __NR_preadv 69 +#define __NR_pwritev 70 +#define __NR3264_sendfile 71 +#define __NR_pselect6 72 +#define __NR_ppoll 73 +#define __NR_signalfd4 74 +#define __NR_vmsplice 75 +#define __NR_splice 76 +#define __NR_tee 77 +#define __NR_readlinkat 78 +#define __NR3264_fstatat 79 +#define __NR3264_fstat 80 +#define __NR_sync 81 +#define __NR_fsync 82 +#define __NR_fdatasync 83 +#define __NR_sync_file_range 84 +#define __NR_timerfd_create 85 +#define __NR_timerfd_settime 86 +#define __NR_timerfd_gettime 87 +#define __NR_utimensat 88 +#define __NR_acct 89 +#define __NR_capget 90 +#define __NR_capset 91 +#define __NR_personality 92 +#define __NR_exit 93 +#define __NR_exit_group 94 +#define __NR_waitid 95 +#define __NR_set_tid_address 96 +#define __NR_unshare 97 +#define __NR_futex 98 +#define __NR_set_robust_list 99 +#define __NR_get_robust_list 100 +#define __NR_nanosleep 101 +#define __NR_getitimer 102 +#define __NR_setitimer 103 +#define __NR_kexec_load 104 +#define __NR_init_module 105 +#define __NR_delete_module 106 +#define __NR_timer_create 107 +#define __NR_timer_gettime 108 +#define __NR_timer_getoverrun 109 +#define __NR_timer_settime 110 +#define __NR_timer_delete 111 +#define __NR_clock_settime 112 +#define __NR_clock_gettime 113 +#define __NR_clock_getres 114 +#define __NR_clock_nanosleep 115 +#define __NR_syslog 116 +#define __NR_ptrace 117 +#define __NR_sched_setparam 118 +#define __NR_sched_setscheduler 119 +#define __NR_sched_getscheduler 120 +#define __NR_sched_getparam 121 +#define __NR_sched_setaffinity 122 +#define __NR_sched_getaffinity 123 +#define __NR_sched_yield 124 +#define __NR_sched_get_priority_max 125 +#define __NR_sched_get_priority_min 126 +#define __NR_sched_rr_get_interval 127 +#define __NR_restart_syscall 128 +#define __NR_kill 129 +#define __NR_tkill 130 +#define __NR_tgkill 131 +#define __NR_sigaltstack 132 +#define __NR_rt_sigsuspend 133 +#define __NR_rt_sigaction 134 +#define __NR_rt_sigprocmask 135 +#define __NR_rt_sigpending 136 +#define __NR_rt_sigtimedwait 137 +#define __NR_rt_sigqueueinfo 138 +#define __NR_rt_sigreturn 139 +#define __NR_setpriority 140 +#define __NR_getpriority 141 +#define __NR_reboot 142 +#define __NR_setregid 143 +#define __NR_setgid 144 +#define __NR_setreuid 145 +#define __NR_setuid 146 +#define __NR_setresuid 147 +#define __NR_getresuid 148 +#define __NR_setresgid 149 +#define __NR_getresgid 150 +#define __NR_setfsuid 151 +#define __NR_setfsgid 152 +#define __NR_times 153 +#define __NR_setpgid 154 +#define __NR_getpgid 155 +#define __NR_getsid 156 +#define __NR_setsid 157 +#define __NR_getgroups 158 +#define __NR_setgroups 159 +#define __NR_uname 160 +#define __NR_sethostname 161 +#define __NR_setdomainname 162 +// #define __NR_getrlimit 163 +// #define __NR_setrlimit 164 +#define __NR_getrusage 165 +#define __NR_umask 166 +#define __NR_prctl 167 +#define __NR_getcpu 168 +#define __NR_gettimeofday 169 +#define __NR_settimeofday 170 +#define __NR_adjtimex 171 +#define __NR_getpid 172 +#define __NR_getppid 173 +#define __NR_getuid 174 +#define __NR_geteuid 175 +#define __NR_getgid 176 +#define __NR_getegid 177 +#define __NR_gettid 178 +#define __NR_sysinfo 179 +#define __NR_mq_open 180 +#define __NR_mq_unlink 181 +#define __NR_mq_timedsend 182 +#define __NR_mq_timedreceive 183 +#define __NR_mq_notify 184 +#define __NR_mq_getsetattr 185 +#define __NR_msgget 186 +#define __NR_msgctl 187 +#define __NR_msgrcv 188 +#define __NR_msgsnd 189 +#define __NR_semget 190 +#define __NR_semctl 191 +#define __NR_semtimedop 192 +#define __NR_semop 193 +#define __NR_shmget 194 +#define __NR_shmctl 195 +#define __NR_shmat 196 +#define __NR_shmdt 197 +#define __NR_socket 198 +#define __NR_socketpair 199 +#define __NR_bind 200 +#define __NR_listen 201 +#define __NR_accept 202 +#define __NR_connect 203 +#define __NR_getsockname 204 +#define __NR_getpeername 205 +#define __NR_sendto 206 +#define __NR_recvfrom 207 +#define __NR_setsockopt 208 +#define __NR_getsockopt 209 +#define __NR_shutdown 210 +#define __NR_sendmsg 211 +#define __NR_recvmsg 212 +#define __NR_readahead 213 +#define __NR_brk 214 +#define __NR_munmap 215 +#define __NR_mremap 216 +#define __NR_add_key 217 +#define __NR_request_key 218 +#define __NR_keyctl 219 +#define __NR_clone 220 +#define __NR_execve 221 +#define __NR3264_mmap 222 +#define __NR3264_fadvise64 223 +#define __NR_swapon 224 +#define __NR_swapoff 225 +#define __NR_mprotect 226 +#define __NR_msync 227 +#define __NR_mlock 228 +#define __NR_munlock 229 +#define __NR_mlockall 230 +#define __NR_munlockall 231 +#define __NR_mincore 232 +#define __NR_madvise 233 +#define __NR_remap_file_pages 234 +#define __NR_mbind 235 +#define __NR_get_mempolicy 236 +#define __NR_set_mempolicy 237 +#define __NR_migrate_pages 238 +#define __NR_move_pages 239 +#define __NR_rt_tgsigqueueinfo 240 +#define __NR_perf_event_open 241 +#define __NR_accept4 242 +#define __NR_recvmmsg 243 + +#define __NR_wait4 260 +#define __NR_prlimit64 261 +#define __NR_fanotify_init 262 +#define __NR_fanotify_mark 263 +#define __NR_name_to_handle_at 264 +#define __NR_open_by_handle_at 265 +#define __NR_clock_adjtime 266 +#define __NR_syncfs 267 +#define __NR_setns 268 +#define __NR_sendmmsg 269 +#define __NR_process_vm_readv 270 +#define __NR_process_vm_writev 271 +#define __NR_kcmp 272 +#define __NR_finit_module 273 +#define __NR_sched_setattr 274 +#define __NR_sched_getattr 275 +#define __NR_renameat2 276 +#define __NR_seccomp 277 +#define __NR_getrandom 278 +#define __NR_memfd_create 279 +#define __NR_bpf 280 +#define __NR_execveat 281 +#define __NR_userfaultfd 282 +#define __NR_membarrier 283 +#define __NR_mlock2 284 +#define __NR_copy_file_range 285 +#define __NR_preadv2 286 +#define __NR_pwritev2 287 +#define __NR_pkey_mprotect 288 +#define __NR_pkey_alloc 289 +#define __NR_pkey_free 290 +#define __NR_statx 291 +#define __NR_io_pgetevents 292 +#define __NR_rseq 293 +#define __NR_kexec_file_load 294 + +#define __NR_pidfd_send_signal 424 +#define __NR_io_uring_setup 425 +#define __NR_io_uring_enter 426 +#define __NR_io_uring_register 427 +#define __NR_open_tree 428 +#define __NR_move_mount 429 +#define __NR_fsopen 430 +#define __NR_fsconfig 431 +#define __NR_fsmount 432 +#define __NR_fspick 433 +#define __NR_pidfd_open 434 +#define __NR_clone3 435 +#define __NR_close_range 436 +#define __NR_openat2 437 +#define __NR_pidfd_getfd 438 +#define __NR_faccessat2 439 +#define __NR_process_madvise 440 +#define __NR_epoll_pwait2 441 +#define __NR_mount_setattr 442 +#define __NR_quotactl_fd 443 +#define __NR_landlock_create_ruleset 444 +#define __NR_landlock_add_rule 445 +#define __NR_landlock_restrict_self 446 +// #define __NR_memfd_secret 447 +#define __NR_process_mrelease 448 + +#define __NR_fcntl __NR3264_fcntl +#define __NR_statfs __NR3264_statfs +#define __NR_fstatfs __NR3264_fstatfs +#define __NR_truncate __NR3264_truncate +#define __NR_ftruncate __NR3264_ftruncate +#define __NR_lseek __NR3264_lseek +#define __NR_sendfile __NR3264_sendfile +#define __NR_mmap __NR3264_mmap +#define __NR_fadvise64 __NR3264_fadvise64 + +#endif /* __VKI_SCNUMS_LOONGARCH64_LINUX_H */ + +/*--------------------------------------------------------------------*/ +/*--- end vki-scnums-loongarch64-linux.h ---*/ +/*--------------------------------------------------------------------*/ diff --git a/lackey/Makefile.in b/lackey/Makefile.in index f08a302..39e01ca 100644 --- a/lackey/Makefile.in +++ b/lackey/Makefile.in @@ -621,6 +621,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -668,6 +674,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -758,6 +765,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -818,6 +829,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -890,6 +904,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/massif/Makefile.in b/massif/Makefile.in index ddedba7..8f983c1 100644 --- a/massif/Makefile.in +++ b/massif/Makefile.in @@ -676,6 +676,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -723,6 +729,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -813,6 +820,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -873,6 +884,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -945,6 +959,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/massif/tests/Makefile.am b/massif/tests/Makefile.am index 636bc8f..b16d73d 100644 --- a/massif/tests/Makefile.am +++ b/massif/tests/Makefile.am @@ -11,6 +11,7 @@ EXTRA_DIST = \ big-alloc.post.exp big-alloc.post.exp-64bit big-alloc.post.exp-ppc64 \ big-alloc.stderr.exp big-alloc.vgtest \ big-alloc.post.exp-x86-freebsd \ + big-alloc.post.exp-loongarch64 \ bug469146.post.exp bug469146.stderr.exp bug469146.vgtest \ deep-A.post.exp deep-A.stderr.exp deep-A.vgtest \ deep-B.post.exp deep-B.stderr.exp deep-B.vgtest \ diff --git a/massif/tests/Makefile.in b/massif/tests/Makefile.in index 0e20293..3ee79f4 100644 --- a/massif/tests/Makefile.in +++ b/massif/tests/Makefile.in @@ -717,6 +717,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -764,6 +770,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ @@ -795,6 +802,7 @@ EXTRA_DIST = \ big-alloc.post.exp big-alloc.post.exp-64bit big-alloc.post.exp-ppc64 \ big-alloc.stderr.exp big-alloc.vgtest \ big-alloc.post.exp-x86-freebsd \ + big-alloc.post.exp-loongarch64 \ bug469146.post.exp bug469146.stderr.exp bug469146.vgtest \ deep-A.post.exp deep-A.stderr.exp deep-A.vgtest \ deep-B.post.exp deep-B.stderr.exp deep-B.vgtest \ diff --git a/massif/tests/big-alloc.post.exp-loongarch64 b/massif/tests/big-alloc.post.exp-loongarch64 new file mode 100644 index 0000000..4dac2a6 --- /dev/null +++ b/massif/tests/big-alloc.post.exp-loongarch64 @@ -0,0 +1,54 @@ +-------------------------------------------------------------------------------- +Command: ./big-alloc +Massif arguments: --stacks=no --time-unit=B --massif-out-file=massif.out --ignore-fn=__part_load_locale --ignore-fn=__time_load_locale --ignore-fn=dwarf2_unwind_dyld_add_image_hook --ignore-fn=get_or_create_key_element --alloc-fn=_xpc_malloc --ignore-fn=_xpc_dictionary_insert --ignore-fn=map_images_nolock --ignore-fn=allocBuckets(void*, unsigned int) --ignore-fn=realizeClass(objc_class*) --ignore-fn=_NXHashRehashToCapacity --ignore-fn=NXCreateHashTableFromZone --ignore-fn=NXCreateMapTableFromZone --ignore-fn=NXHashInsert --ignore-fn=add_class_to_loadable_list --ignore-fn=class_createInstance --ignore-fn=xpc_string_create --alloc-fn=strdup --alloc-fn=_xpc_calloc --ignore-fn=xpc_array_create +ms_print arguments: massif.out +-------------------------------------------------------------------------------- + + + MB +100.2^ : + | : + | @@@@@@@: + | @ : + | :::::::@ : + | : @ : + | :::::::: @ : + | : : @ : + | :::::::: : @ : + | : : : @ : + | :::::::: : : @ : + | : : : : @ : + | ::::::::: : : : @ : + | : : : : : @ : + | :::::::: : : : : @ : + | : : : : : : @ : + | :::::::: : : : : : @ : + | : : : : : : : @ : + | :::::::: : : : : : : @ : + | : : : : : : : : @ : + 0 +----------------------------------------------------------------------->MB + 0 100.2 + +Number of snapshots: 11 + Detailed snapshots: [9] + +-------------------------------------------------------------------------------- + n time(B) total(B) useful-heap(B) extra-heap(B) stacks(B) +-------------------------------------------------------------------------------- + 0 0 0 0 0 0 + 1 10,502,088 10,502,088 10,485,760 16,328 0 + 2 21,004,176 21,004,176 20,971,520 32,656 0 + 3 31,506,264 31,506,264 31,457,280 48,984 0 + 4 42,008,352 42,008,352 41,943,040 65,312 0 + 5 52,510,440 52,510,440 52,428,800 81,640 0 + 6 63,012,528 63,012,528 62,914,560 97,968 0 + 7 73,514,616 73,514,616 73,400,320 114,296 0 + 8 84,016,704 84,016,704 83,886,080 130,624 0 + 9 94,518,792 94,518,792 94,371,840 146,952 0 +99.84% (94,371,840B) (heap allocation functions) malloc/new/new[], --alloc-fns, etc. +->99.84% (94,371,840B) 0x........: main (big-alloc.c:12) + +-------------------------------------------------------------------------------- + n time(B) total(B) useful-heap(B) extra-heap(B) stacks(B) +-------------------------------------------------------------------------------- + 10 105,020,880 105,020,880 104,857,600 163,280 0 diff --git a/memcheck/Makefile.in b/memcheck/Makefile.in index 39b34c9..cc8fd2b 100644 --- a/memcheck/Makefile.in +++ b/memcheck/Makefile.in @@ -709,6 +709,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -756,6 +762,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -846,6 +853,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -906,6 +917,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -978,6 +992,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c index 176c8e5..49f9894 100644 --- a/memcheck/mc_machine.c +++ b/memcheck/mc_machine.c @@ -1394,6 +1394,118 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) offset,szB); tl_assert(0); # undef GOF +# undef SZB + + /* ----------------- loongarch64 ----------------- */ + +# elif defined(VGA_loongarch64) + +# define GOF(_fieldname) \ + (offsetof(VexGuestLOONGARCH64State,guest_##_fieldname)) +# define SZB(_fieldname) \ + (sizeof(((VexGuestLOONGARCH64State*)0)->guest_##_fieldname)) + + Int o = offset; + Int sz = szB; + Bool is48 = sz == 8 || sz == 4; + Bool is1248 = sz == 8 || sz == 4 || sz == 2 || sz == 1; + + tl_assert(sz > 0); + tl_assert(host_is_little_endian()); + + if (o == GOF(R0) && is1248) return o; + if (o == GOF(R1) && is1248) return o; + if (o == GOF(R2) && is1248) return o; + if (o == GOF(R3) && is1248) return o; + if (o == GOF(R4) && is1248) return o; + if (o == GOF(R5) && is1248) return o; + if (o == GOF(R6) && is1248) return o; + if (o == GOF(R7) && is1248) return o; + if (o == GOF(R8) && is1248) return o; + if (o == GOF(R9) && is1248) return o; + if (o == GOF(R10) && is1248) return o; + if (o == GOF(R11) && is1248) return o; + if (o == GOF(R12) && is1248) return o; + if (o == GOF(R13) && is1248) return o; + if (o == GOF(R14) && is1248) return o; + if (o == GOF(R15) && is1248) return o; + if (o == GOF(R16) && is1248) return o; + if (o == GOF(R17) && is1248) return o; + if (o == GOF(R18) && is1248) return o; + if (o == GOF(R19) && is1248) return o; + if (o == GOF(R20) && is1248) return o; + if (o == GOF(R21) && is1248) return o; + if (o == GOF(R22) && is1248) return o; + if (o == GOF(R23) && is1248) return o; + if (o == GOF(R24) && is1248) return o; + if (o == GOF(R25) && is1248) return o; + if (o == GOF(R26) && is1248) return o; + if (o == GOF(R27) && is1248) return o; + if (o == GOF(R28) && is1248) return o; + if (o == GOF(R29) && is1248) return o; + if (o == GOF(R30) && is1248) return o; + if (o == GOF(R31) && is1248) return o; + + if (o == GOF(PC) && sz == 8) return -1; /* slot unused */ + + if (o >= GOF(X0) && o + sz <= GOF(X0) + SZB(X0)) return GOF(X0); + if (o >= GOF(X1) && o + sz <= GOF(X1) + SZB(X1)) return GOF(X1); + if (o >= GOF(X2) && o + sz <= GOF(X2) + SZB(X2)) return GOF(X2); + if (o >= GOF(X3) && o + sz <= GOF(X3) + SZB(X3)) return GOF(X3); + if (o >= GOF(X4) && o + sz <= GOF(X4) + SZB(X4)) return GOF(X4); + if (o >= GOF(X5) && o + sz <= GOF(X5) + SZB(X5)) return GOF(X5); + if (o >= GOF(X6) && o + sz <= GOF(X6) + SZB(X6)) return GOF(X6); + if (o >= GOF(X7) && o + sz <= GOF(X7) + SZB(X7)) return GOF(X7); + if (o >= GOF(X8) && o + sz <= GOF(X8) + SZB(X8)) return GOF(X8); + if (o >= GOF(X9) && o + sz <= GOF(X9) + SZB(X9)) return GOF(X9); + if (o >= GOF(X10) && o + sz <= GOF(X10) + SZB(X10)) return GOF(X10); + if (o >= GOF(X11) && o + sz <= GOF(X11) + SZB(X11)) return GOF(X11); + if (o >= GOF(X12) && o + sz <= GOF(X12) + SZB(X12)) return GOF(X12); + if (o >= GOF(X13) && o + sz <= GOF(X13) + SZB(X13)) return GOF(X13); + if (o >= GOF(X14) && o + sz <= GOF(X14) + SZB(X14)) return GOF(X14); + if (o >= GOF(X15) && o + sz <= GOF(X15) + SZB(X15)) return GOF(X15); + if (o >= GOF(X16) && o + sz <= GOF(X16) + SZB(X16)) return GOF(X16); + if (o >= GOF(X17) && o + sz <= GOF(X17) + SZB(X17)) return GOF(X17); + if (o >= GOF(X18) && o + sz <= GOF(X18) + SZB(X18)) return GOF(X18); + if (o >= GOF(X19) && o + sz <= GOF(X19) + SZB(X19)) return GOF(X19); + if (o >= GOF(X20) && o + sz <= GOF(X20) + SZB(X20)) return GOF(X20); + if (o >= GOF(X21) && o + sz <= GOF(X21) + SZB(X21)) return GOF(X21); + if (o >= GOF(X22) && o + sz <= GOF(X22) + SZB(X22)) return GOF(X22); + if (o >= GOF(X23) && o + sz <= GOF(X23) + SZB(X23)) return GOF(X23); + if (o >= GOF(X24) && o + sz <= GOF(X24) + SZB(X24)) return GOF(X24); + if (o >= GOF(X25) && o + sz <= GOF(X25) + SZB(X25)) return GOF(X25); + if (o >= GOF(X26) && o + sz <= GOF(X26) + SZB(X26)) return GOF(X26); + if (o >= GOF(X27) && o + sz <= GOF(X27) + SZB(X27)) return GOF(X27); + if (o >= GOF(X28) && o + sz <= GOF(X28) + SZB(X28)) return GOF(X28); + if (o >= GOF(X29) && o + sz <= GOF(X29) + SZB(X29)) return GOF(X29); + if (o >= GOF(X30) && o + sz <= GOF(X30) + SZB(X30)) return GOF(X30); + if (o >= GOF(X31) && o + sz <= GOF(X31) + SZB(X31)) return GOF(X31); + + if (o == GOF(FCC0) && sz == 1) return -1; /* slot unused */ + if (o == GOF(FCC1) && sz == 1) return -1; /* slot unused */ + if (o == GOF(FCC2) && sz == 1) return -1; /* slot unused */ + if (o == GOF(FCC3) && sz == 1) return -1; /* slot unused */ + if (o == GOF(FCC4) && sz == 1) return -1; /* slot unused */ + if (o == GOF(FCC5) && sz == 1) return -1; /* slot unused */ + if (o == GOF(FCC6) && sz == 1) return -1; /* slot unused */ + if (o == GOF(FCC7) && sz == 1) return -1; /* slot unused */ + if (o == GOF(FCSR) && sz == 4) return -1; /* slot unused */ + + if (o == GOF(EMNOTE) && sz == 4) return -1; /* slot unused */ + + if (o == GOF(CMSTART) && sz == 8) return -1; /* slot unused */ + if (o == GOF(CMLEN) && sz == 8) return -1; /* slot unused */ + + if (o == GOF(NRADDR) && sz == 8) return -1; /* slot unused */ + + if (o == GOF(LLSC_SIZE) && sz == 8) return -1; /* slot unused */ + if (o == GOF(LLSC_ADDR) && sz == 8) return -1; /* slot unused */ + if (o == GOF(LLSC_DATA) && is48) return -1; /* slot unused */ + + VG_(printf)("MC_(get_otrack_shadow_offset)(loongarch64)(off=%d,sz=%d)\n", + offset,szB); + tl_assert(0); +# undef GOF # undef SZB # else @@ -1517,6 +1629,13 @@ IRType MC_(get_otrack_reg_array_equiv_int_type) ( IRRegArray* arr ) VG_(printf)("\n"); tl_assert(0); + /* ----------------- loongarch64 ----------------- */ +# elif defined(VGA_loongarch64) + VG_(printf)("get_reg_array_equiv_int_type(loongarch64): unhandled: "); + ppIRRegArray(arr); + VG_(printf)("\n"); + tl_assert(0); + # else # error "FIXME: not implemented for this architecture" # endif diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c index ec8ac53..fa58fc5 100644 --- a/memcheck/mc_translate.c +++ b/memcheck/mc_translate.c @@ -3505,6 +3505,7 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce, case Iop_MulD64: case Iop_MulF64r32: case Iop_DivF64: + case Iop_ScaleBF64: case Iop_DivD64: case Iop_DivF64r32: case Iop_ScaleF64: @@ -3524,6 +3525,7 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce, case Iop_SubF32: case Iop_MulF32: case Iop_DivF32: + case Iop_ScaleBF32: /* I32(rm) x F32 x F32 -> I32 */ return mkLazy3(mce, Ity_I32, vatom1, vatom2, vatom3); case Iop_AddF16: @@ -4532,6 +4534,8 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_TanF64: case Iop_2xm1F64: case Iop_SqrtF64: + case Iop_RSqrtF64: + case Iop_LogBF64: case Iop_RecpExpF64: /* I32(rm) x I64/F64 -> I64/F64 */ return mkLazy2(mce, Ity_I64, vatom1, vatom2); @@ -4593,6 +4597,8 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_RoundF32toInt: case Iop_SqrtF32: + case Iop_RSqrtF32: + case Iop_LogBF32: case Iop_RecpExpF32: /* I32(rm) x I32/F32 -> I32/F32 */ return mkLazy2(mce, Ity_I32, vatom1, vatom2); @@ -4675,11 +4681,15 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_MaxNumF32: case Iop_MinNumF32: + case Iop_MaxNumAbsF32: + case Iop_MinNumAbsF32: /* F32 x F32 -> F32 */ return mkLazy2(mce, Ity_I32, vatom1, vatom2); case Iop_MaxNumF64: case Iop_MinNumF64: + case Iop_MaxNumAbsF64: + case Iop_MinNumAbsF64: /* F64 x F64 -> F64 */ return mkLazy2(mce, Ity_I64, vatom1, vatom2); @@ -5026,6 +5036,10 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_Add64x4: case Iop_CmpEQ64x4: case Iop_CmpGT64Sx4: + case Iop_Max64Sx4: + case Iop_Max64Ux4: + case Iop_Min64Sx4: + case Iop_Min64Ux4: return binary64Ix4(mce, vatom1, vatom2); case Iop_I32StoF32x8: @@ -8763,6 +8777,9 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure, mce.dlbo.dl_CmpEQ64_CmpNE64 = DLexpensive; # elif defined(VGA_arm) mce.dlbo.dl_CmpEQ32_CmpNE32 = DLexpensive; +# elif defined(VGA_loongarch64) + mce.dlbo.dl_CmpEQ32_CmpNE32 = DLexpensive; + mce.dlbo.dl_CmpEQ64_CmpNE64 = DLexpensive; # endif /* preInstrumentationAnalysis() will allocate &mce.tmpHowUsed and then diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am index 47b5384..c9710e9 100644 --- a/memcheck/tests/Makefile.am +++ b/memcheck/tests/Makefile.am @@ -50,6 +50,9 @@ endif if VGCONF_PLATFORMS_INCLUDE_ARM64_LINUX SUBDIRS += arm64-linux endif +if VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX +SUBDIRS += loongarch64-linux +endif if VGCONF_PLATFORMS_INCLUDE_X86_SOLARIS SUBDIRS += x86-solaris endif @@ -65,7 +68,7 @@ endif DIST_SUBDIRS = x86 amd64 ppc32 ppc64 s390x linux \ darwin solaris x86-linux amd64-linux arm64-linux \ - x86-solaris amd64-solaris mips32 mips64 \ + loongarch64-linux x86-solaris amd64-solaris mips32 mips64 \ freebsd amd64-freebsd x86-freebsd \ common . diff --git a/memcheck/tests/Makefile.in b/memcheck/tests/Makefile.in index f992408..3fe71b6 100644 --- a/memcheck/tests/Makefile.in +++ b/memcheck/tests/Makefile.in @@ -145,10 +145,11 @@ host_triplet = @host@ @VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_23 = x86-linux @VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_24 = amd64-linux @VGCONF_PLATFORMS_INCLUDE_ARM64_LINUX_TRUE@am__append_25 = arm64-linux -@VGCONF_PLATFORMS_INCLUDE_X86_SOLARIS_TRUE@am__append_26 = x86-solaris -@VGCONF_PLATFORMS_INCLUDE_AMD64_SOLARIS_TRUE@am__append_27 = amd64-solaris -@VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD_TRUE@am__append_28 = x86-freebsd -@VGCONF_PLATFORMS_INCLUDE_AMD64_FREEBSD_TRUE@am__append_29 = amd64-freebsd +@VGCONF_PLATFORMS_INCLUDE_LOONGARCH64_LINUX_TRUE@am__append_26 = loongarch64-linux +@VGCONF_PLATFORMS_INCLUDE_X86_SOLARIS_TRUE@am__append_27 = x86-solaris +@VGCONF_PLATFORMS_INCLUDE_AMD64_SOLARIS_TRUE@am__append_28 = amd64-solaris +@VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD_TRUE@am__append_29 = x86-freebsd +@VGCONF_PLATFORMS_INCLUDE_AMD64_FREEBSD_TRUE@am__append_30 = amd64-freebsd check_PROGRAMS = accounting$(EXEEXT) addressable$(EXEEXT) \ atomic_incs$(EXEEXT) badaddrvalue$(EXEEXT) badfree$(EXEEXT) \ badjump$(EXEEXT) badjump2$(EXEEXT) badloop$(EXEEXT) \ @@ -215,31 +216,31 @@ check_PROGRAMS = accounting$(EXEEXT) addressable$(EXEEXT) \ $(am__EXEEXT_9) $(am__EXEEXT_10) # Sun Studio assembler fails on "IDENT too long" -@SOLARIS_SUN_STUDIO_AS_FALSE@am__append_30 = long_namespace_xml -@DWARF4_TRUE@am__append_31 = dw4 -@GZ_ZLIB_TRUE@am__append_32 = cdebug_zlib -@GZ_ZLIB_GNU_TRUE@am__append_33 = cdebug_zlib_gnu -@HAVE_ALIGNED_CXX_ALLOC_TRUE@am__append_34 = cxx17_aligned_new sized_aligned_new_delete_args \ +@SOLARIS_SUN_STUDIO_AS_FALSE@am__append_31 = long_namespace_xml +@DWARF4_TRUE@am__append_32 = dw4 +@GZ_ZLIB_TRUE@am__append_33 = cdebug_zlib +@GZ_ZLIB_GNU_TRUE@am__append_34 = cdebug_zlib_gnu +@HAVE_ALIGNED_CXX_ALLOC_TRUE@am__append_35 = cxx17_aligned_new sized_aligned_new_delete_args \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ new_aligned_delete_default \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ sized_aligned_new_delete_misaligned1 \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ sized_aligned_new_delete_misaligned2 \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ sized_aligned_new_delete_misaligned3 -@HAVE_PTHREAD_BARRIER_TRUE@am__append_35 = reach_thread_register -@HAVE_FSIZED_DEALLOCATION_TRUE@am__append_36 = sized_delete new_delete_mismatch_size -@HAVE_GNU_STPNCPY_TRUE@am__append_37 = stpncpy -@HAVE_PTHREAD_SETNAME_NP_TRUE@am__append_38 = threadname +@HAVE_PTHREAD_BARRIER_TRUE@am__append_36 = reach_thread_register +@HAVE_FSIZED_DEALLOCATION_TRUE@am__append_37 = sized_delete new_delete_mismatch_size +@HAVE_GNU_STPNCPY_TRUE@am__append_38 = stpncpy +@HAVE_PTHREAD_SETNAME_NP_TRUE@am__append_39 = threadname # are there still pre-C99 C compilers? -@HAVE_WCSNCPY_TRUE@am__append_39 = wcsncpy -@COMPILER_IS_CLANG_TRUE@@HAVE_ALIGNED_CXX_ALLOC_TRUE@am__append_40 = -fsized-deallocation +@HAVE_WCSNCPY_TRUE@am__append_40 = wcsncpy @COMPILER_IS_CLANG_TRUE@@HAVE_ALIGNED_CXX_ALLOC_TRUE@am__append_41 = -fsized-deallocation @COMPILER_IS_CLANG_TRUE@@HAVE_ALIGNED_CXX_ALLOC_TRUE@am__append_42 = -fsized-deallocation @COMPILER_IS_CLANG_TRUE@@HAVE_ALIGNED_CXX_ALLOC_TRUE@am__append_43 = -fsized-deallocation @COMPILER_IS_CLANG_TRUE@@HAVE_ALIGNED_CXX_ALLOC_TRUE@am__append_44 = -fsized-deallocation -@VGCONF_OS_IS_SOLARIS_TRUE@am__append_45 = -D_XOPEN_SOURCE=600 -@VGCONF_OS_IS_SOLARIS_TRUE@am__append_46 = -D__EXTENSIONS__ -@VGCONF_OS_IS_SOLARIS_TRUE@am__append_47 = -D_XOPEN_SOURCE=600 +@COMPILER_IS_CLANG_TRUE@@HAVE_ALIGNED_CXX_ALLOC_TRUE@am__append_45 = -fsized-deallocation +@VGCONF_OS_IS_SOLARIS_TRUE@am__append_46 = -D_XOPEN_SOURCE=600 +@VGCONF_OS_IS_SOLARIS_TRUE@am__append_47 = -D__EXTENSIONS__ +@VGCONF_OS_IS_SOLARIS_TRUE@am__append_48 = -D_XOPEN_SOURCE=600 subdir = memcheck/tests ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac @@ -1687,6 +1688,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -1734,6 +1741,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ @@ -1761,10 +1769,11 @@ SUBDIRS = . $(am__append_12) $(am__append_13) $(am__append_14) \ $(am__append_18) $(am__append_19) $(am__append_20) \ $(am__append_21) $(am__append_22) $(am__append_23) \ $(am__append_24) $(am__append_25) $(am__append_26) \ - $(am__append_27) $(am__append_28) $(am__append_29) + $(am__append_27) $(am__append_28) $(am__append_29) \ + $(am__append_30) DIST_SUBDIRS = x86 amd64 ppc32 ppc64 s390x linux \ darwin solaris x86-linux amd64-linux arm64-linux \ - x86-solaris amd64-solaris mips32 mips64 \ + loongarch64-linux x86-solaris amd64-solaris mips32 mips64 \ freebsd amd64-freebsd x86-freebsd \ common . @@ -2174,27 +2183,27 @@ bug340392_CFLAGS = $(AM_CFLAGS) -O3 @FLAG_W_NO_MAYBE_UNINITIALIZED@ @HAVE_ALIGNED_CXX_ALLOC_TRUE@cxx17_aligned_new_SOURCES = cxx17_aligned_new.cpp @HAVE_ALIGNED_CXX_ALLOC_TRUE@cxx17_aligned_new_CXXFLAGS = -std=c++17 \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ @FLAG_W_NO_MISMATCHED_NEW_DELETE@ \ -@HAVE_ALIGNED_CXX_ALLOC_TRUE@ $(am__append_40) +@HAVE_ALIGNED_CXX_ALLOC_TRUE@ $(am__append_41) @HAVE_ALIGNED_CXX_ALLOC_TRUE@new_aligned_delete_default_SOURCES = new_aligned_delete_default.cpp @HAVE_ALIGNED_CXX_ALLOC_TRUE@new_aligned_delete_default_CXXFLAGS = ${AM_CXXFLAGS} -std=c++17 @HAVE_ALIGNED_CXX_ALLOC_TRUE@sized_aligned_new_delete_args_SOURCES = sized_aligned_new_delete_args.cpp @HAVE_ALIGNED_CXX_ALLOC_TRUE@sized_aligned_new_delete_args_CXXFLAGS = \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ ${AM_CXXFLAGS} -std=c++17 \ -@HAVE_ALIGNED_CXX_ALLOC_TRUE@ $(am__append_41) +@HAVE_ALIGNED_CXX_ALLOC_TRUE@ $(am__append_42) @HAVE_ALIGNED_CXX_ALLOC_TRUE@sized_aligned_new_delete_misaligned1_SOURCES = sized_aligned_new_delete_misaligned1.cpp @HAVE_ALIGNED_CXX_ALLOC_TRUE@sized_aligned_new_delete_misaligned1_CXXFLAGS = \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ ${AM_CXXFLAGS} -std=c++17 \ -@HAVE_ALIGNED_CXX_ALLOC_TRUE@ $(am__append_42) +@HAVE_ALIGNED_CXX_ALLOC_TRUE@ $(am__append_43) @HAVE_ALIGNED_CXX_ALLOC_TRUE@sized_aligned_new_delete_misaligned2_SOURCES = sized_aligned_new_delete_misaligned2.cpp @HAVE_ALIGNED_CXX_ALLOC_TRUE@sized_aligned_new_delete_misaligned2_CXXFLAGS = \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ ${AM_CXXFLAGS} -std=c++17 \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ @FLAG_W_NO_UNUSED_VARIABLE@ \ -@HAVE_ALIGNED_CXX_ALLOC_TRUE@ $(am__append_43) +@HAVE_ALIGNED_CXX_ALLOC_TRUE@ $(am__append_44) @HAVE_ALIGNED_CXX_ALLOC_TRUE@sized_aligned_new_delete_misaligned3_SOURCES = sized_aligned_new_delete_misaligned3.cpp @HAVE_ALIGNED_CXX_ALLOC_TRUE@sized_aligned_new_delete_misaligned3_CXXFLAGS = \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ ${AM_CXXFLAGS} -std=c++17 \ @HAVE_ALIGNED_CXX_ALLOC_TRUE@ @FLAG_W_NO_UNUSED_VARIABLE@ \ -@HAVE_ALIGNED_CXX_ALLOC_TRUE@ $(am__append_44) +@HAVE_ALIGNED_CXX_ALLOC_TRUE@ $(am__append_45) demangle_SOURCES = demangle.cpp demangle_rust_SOURCES = demangle-rust.c demangle_rust_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_USE_AFTER_FREE@ @@ -2202,7 +2211,7 @@ dw4_CFLAGS = $(AM_CFLAGS) -gdwarf-4 -fdebug-types-section descr_belowsp_LDADD = -lpthread err_disable3_LDADD = -lpthread err_disable4_LDADD = -lpthread -err_disable4_CFLAGS = $(AM_CFLAGS) $(am__append_45) +err_disable4_CFLAGS = $(AM_CFLAGS) $(am__append_46) error_counts_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@ @FLAG_W_NO_UNUSED_BUT_SET_VARIABLE@ execve1_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ execve2_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ @@ -2217,7 +2226,7 @@ malloc1_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_USE_AFTER_FREE@ manuel1_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@ manuel3_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@ memalign2_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NON_POWER_OF_TWO_ALIGNMENT@ \ - $(am__append_46) + $(am__append_47) memcmptest_CFLAGS = $(AM_CFLAGS) -fno-builtin-memcmp mismatches_SOURCES = mismatches.cpp mismatches_CXXFLAGS = $(AM_CXXFLAGS) @FLAG_W_NO_MISMATCHED_NEW_DELETE@ @@ -2250,7 +2259,7 @@ realloc_size_zero_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_INCOMPATIBLE_POINTER_TYPES_DI realloc_size_zero_mismatch_SOURCES = realloc_size_zero_mismatch.cpp realloc_size_zero_mismatch_CXXFLAGS = $(AM_CXXFLAGS) @FLAG_W_NO_MISMATCHED_NEW_DELETE@ resvn_stack_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@ -sendmsg_CFLAGS = $(AM_CFLAGS) $(am__append_47) +sendmsg_CFLAGS = $(AM_CFLAGS) $(am__append_48) @VGCONF_OS_IS_SOLARIS_TRUE@sendmsg_LDADD = -lsocket -lnsl @HAVE_FSIZED_DEALLOCATION_TRUE@sized_delete_SOURCES = sized_delete.cpp @HAVE_FSIZED_DEALLOCATION_TRUE@sized_delete_CXXFLAGS = $(AM_CXXFLAGS) @FLAG_FSIZED_DEALLOCATION@ diff --git a/memcheck/tests/amd64-freebsd/Makefile.in b/memcheck/tests/amd64-freebsd/Makefile.in index 2d1b884..5fa1665 100644 --- a/memcheck/tests/amd64-freebsd/Makefile.in +++ b/memcheck/tests/amd64-freebsd/Makefile.in @@ -583,6 +583,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -630,6 +636,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/amd64-linux/Makefile.in b/memcheck/tests/amd64-linux/Makefile.in index 1b3d479..8e273ea 100644 --- a/memcheck/tests/amd64-linux/Makefile.in +++ b/memcheck/tests/amd64-linux/Makefile.in @@ -582,6 +582,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -629,6 +635,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/amd64-solaris/Makefile.in b/memcheck/tests/amd64-solaris/Makefile.in index 8d2cc23..f497e2b 100644 --- a/memcheck/tests/amd64-solaris/Makefile.in +++ b/memcheck/tests/amd64-solaris/Makefile.in @@ -597,6 +597,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -644,6 +650,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/amd64/Makefile.in b/memcheck/tests/amd64/Makefile.in index 0a89e7e..045a9d8 100644 --- a/memcheck/tests/amd64/Makefile.in +++ b/memcheck/tests/amd64/Makefile.in @@ -668,6 +668,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -715,6 +721,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/arm64-linux/Makefile.in b/memcheck/tests/arm64-linux/Makefile.in index 20084ba..361c356 100644 --- a/memcheck/tests/arm64-linux/Makefile.in +++ b/memcheck/tests/arm64-linux/Makefile.in @@ -568,6 +568,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -615,6 +621,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/atomic_incs.c b/memcheck/tests/atomic_incs.c index 1c738c5..8c00550 100644 --- a/memcheck/tests/atomic_incs.c +++ b/memcheck/tests/atomic_incs.c @@ -245,6 +245,29 @@ __attribute__((noinline)) void atomic_add_8bit ( char* p, int n ) ); } while (block[2] != 1); #endif +#elif defined(VGA_loongarch64) + unsigned long long int block[3] + = { (unsigned long long int)(Addr)p, (unsigned long long int)n, 0x0ULL }; + do { + __asm__ __volatile__( + "move $t0, %0 \n\t" + "ld.d $t1, $t0, 0 \n\t" // p + "ld.d $t2, $t0, 8 \n\t" // n + "andi $t2, $t2, 0xff \n\t" // n = n & 0xff + "li.d $s0, 0xff \n\t" + "nor $s0, $s0, $zero \n\t" // $s0 = 0xffffff00 + "ll.d $t3, $t1, 0 \n\t" // $t3 = old value + "and $s0, $s0, $t3 \n\t" // $s0 = $t3 & 0xffffff00 + "add.d $t3, $t3, $t2 \n\t" // $t3 = $t3 + n + "andi $t3, $t3, 0xff \n\t" // $t3 = $t3 & 0xff + "or $t3, $t3, $s0 \n\t" // $t3 = $t3 | $s0 + "sc.d $t3, $t1, 0 \n\t" + "st.d $t3, $t0, 16 \n\t" // save result + : /*out*/ + : /*in*/ "r" (&block[0]) + : /*trash*/ "t0", "t1", "t2", "t3", "s0", "memory" + ); + } while (block[2] != 1); #else # error "Unsupported arch" #endif @@ -461,6 +484,30 @@ __attribute__((noinline)) void atomic_add_16bit ( short* p, int n ) ); } while (block[2] != 1); #endif +#elif defined(VGA_loongarch64) + unsigned long long int block[3] + = { (unsigned long long int)(Addr)p, (unsigned long long int)n, 0x0ULL }; + do { + __asm__ __volatile__( + "move $t0, %0 \n\t" + "ld.d $t1, $t0, 0 \n\t" // p + "ld.d $t2, $t0, 8 \n\t" // n + "li.d $s0, 0xffff \n\t" + "and $t2, $t2, $s0 \n\t" // n = n & 0xffff + "nor $s0, $s0, $zero \n\t" // $s0= 0xffff0000 + "ll.d $t3, $t1, 0 \n\t" // $t3 = old value + "and $s0, $s0, $t3 \n\t" // $s0 = $t3 & 0xffff0000 + "add.d $t3, $t3, $t2 \n\t" // $t3 = $t3 + n + "li.d $t2, 0xffff \n\t" + "and $t3, $t3, $t2 \n\t" // $t3 = $t3 & 0xffff + "or $t3, $t3, $s0 \n\t" // $t3 = $t3 | $s0 + "sc.d $t3, $t1, 0 \n\t" + "st.d $t3, $t0, 16 \n\t" // save result + : /*out*/ + : /*in*/ "r" (&block[0]) + : /*trash*/ "t0", "t1", "t2", "t3", "s0", "memory" + ); + } while (block[2] != 1); #else # error "Unsupported arch" #endif @@ -616,6 +663,23 @@ __attribute__((noinline)) void atomic_add_32bit ( int* p, int n ) : /*trash*/ "memory", "t0", "t1", "t2", "t3" ); } while (block[2] != 1); +#elif defined(VGA_loongarch64) + unsigned long long int block[3] + = { (unsigned long long int)(Addr)p, (unsigned long long int)n, 0x0ULL }; + do { + __asm__ __volatile__( + "move $t0, %0 \n\t" + "ld.d $t1, $t0, 0 \n\t" // p + "ld.d $t2, $t0, 8 \n\t" // n + "ll.d $t3, $t1, 0 \n\t" + "add.d $t3, $t3, $t2 \n\t" + "sc.d $t3, $t1, 0 \n\t" + "st.d $t3, $t0, 16 \n\t" + : /*out*/ + : /*in*/ "r" (&block[0]) + : /*trash*/ "t0", "t1", "t2", "t3", "memory" + ); + } while (block[2] != 1); #else # error "Unsupported arch" #endif @@ -718,6 +782,23 @@ __attribute__((noinline)) void atomic_add_64bit ( long long int* p, int n ) : /*trash*/ "memory", "t0", "t1", "t2", "t3" ); } while (block[2] != 1); +#elif defined(VGA_loongarch64) + unsigned long long int block[3] + = { (unsigned long long int)(Addr)p, (unsigned long long int)n, 0x0ULL }; + do { + __asm__ __volatile__( + "move $t0, %0 \n\t" + "ld.d $t1, $t0, 0 \n\t" // p + "ld.d $t2, $t0, 8 \n\t" // n + "ll.d $t3, $t1, 0 \n\t" + "add.d $t3, $t3, $t2 \n\t" + "sc.d $t3, $t1, 0 \n\t" + "st.d $t3, $t0, 16 \n\t" + : /*out*/ + : /*in*/ "r" (&block[0]) + : /*trash*/ "t0", "t1", "t2", "t3", "memory" + ); + } while (block[2] != 1); #else # error "Unsupported arch" #endif @@ -731,7 +812,8 @@ __attribute__((noinline)) void atomic_add_128bit ( MyU128* p, || defined(VGA_amd64) \ || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ || defined(VGA_arm) \ - || defined(VGA_s390x) + || defined(VGA_s390x) \ + || defined(VGA_loongarch64) /* do nothing; is not supported */ #elif defined(VGA_arm64) unsigned long long int block[3] diff --git a/memcheck/tests/common/Makefile.in b/memcheck/tests/common/Makefile.in index 71f2d86..3b6e554 100644 --- a/memcheck/tests/common/Makefile.in +++ b/memcheck/tests/common/Makefile.in @@ -526,6 +526,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -573,6 +579,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/darwin/Makefile.in b/memcheck/tests/darwin/Makefile.in index 9886522..9f0df9d 100644 --- a/memcheck/tests/darwin/Makefile.in +++ b/memcheck/tests/darwin/Makefile.in @@ -614,6 +614,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -661,6 +667,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/freebsd/Makefile.in b/memcheck/tests/freebsd/Makefile.in index 87c2a15..d391d1d 100644 --- a/memcheck/tests/freebsd/Makefile.in +++ b/memcheck/tests/freebsd/Makefile.in @@ -824,6 +824,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -871,6 +877,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/leak-segv-jmp.c b/memcheck/tests/leak-segv-jmp.c index 97bddaf..4890f5b 100644 --- a/memcheck/tests/leak-segv-jmp.c +++ b/memcheck/tests/leak-segv-jmp.c @@ -182,6 +182,19 @@ extern UWord do_syscall_WRK ( return out; } +#elif defined(VGP_loongarch64_linux) +extern UWord do_syscall_WRK (UWord a1, UWord a2, UWord a3, /* $a0, $a1, $a2 */ + UWord a4, UWord a5, UWord a6, /* $a3, $a4, $a5 */ + UWord syscall_no); /* $a6 */ +asm ( + ".text \n\t" + ".globl do_syscall_WRK \n\t" + "do_syscall_WRK: \n\t" + " move $a7, $a6 \n\t" /* a7 = syscall_no */ + " syscall 0 \n\t" + " jr $ra \n\t" +); + #elif defined(VGP_x86_solaris) extern ULong do_syscall_WRK(UWord a1, UWord a2, UWord a3, @@ -338,7 +351,7 @@ static void non_simd_mprotect (long tid, void* addr, long len) &err); if (err) mprotect_result = -1; -#elif defined(VGP_arm64_linux) +#elif defined(VGP_arm64_linux) || defined (VGP_loongarch64_linux) mprotect_result = do_syscall_WRK((UWord) addr, len, PROT_NONE, 0, 0, 0, __NR_mprotect); diff --git a/memcheck/tests/leak-segv-jmp.stderr.exp b/memcheck/tests/leak-segv-jmp.stderr.exp index b30fd76..0eea178 100644 --- a/memcheck/tests/leak-segv-jmp.stderr.exp +++ b/memcheck/tests/leak-segv-jmp.stderr.exp @@ -14,8 +14,8 @@ To see them, rerun with: --leak-check=full --show-leak-kinds=all expecting a leak 1,000 bytes in 1 blocks are definitely lost in loss record ... of ... at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: f (leak-segv-jmp.c:389) - by 0x........: main (leak-segv-jmp.c:464) + by 0x........: f (leak-segv-jmp.c:402) + by 0x........: main (leak-segv-jmp.c:477) LEAK SUMMARY: definitely lost: 1,000 bytes in 1 blocks @@ -30,8 +30,8 @@ mprotect result 0 expecting a leak again 1,000 bytes in 1 blocks are definitely lost in loss record ... of ... at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: f (leak-segv-jmp.c:389) - by 0x........: main (leak-segv-jmp.c:464) + by 0x........: f (leak-segv-jmp.c:402) + by 0x........: main (leak-segv-jmp.c:477) LEAK SUMMARY: definitely lost: 1,000 bytes in 1 blocks @@ -46,8 +46,8 @@ full mprotect result 0 expecting a leak again after full mprotect 1,000 bytes in 1 blocks are definitely lost in loss record ... of ... at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: f (leak-segv-jmp.c:389) - by 0x........: main (leak-segv-jmp.c:464) + by 0x........: f (leak-segv-jmp.c:402) + by 0x........: main (leak-segv-jmp.c:477) LEAK SUMMARY: definitely lost: 1,000 bytes in 1 blocks @@ -62,13 +62,13 @@ mprotect result 0 expecting heuristic not to crash after full mprotect 1,000 bytes in 1 blocks are definitely lost in loss record ... of ... at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: f (leak-segv-jmp.c:389) - by 0x........: main (leak-segv-jmp.c:464) + by 0x........: f (leak-segv-jmp.c:402) + by 0x........: main (leak-segv-jmp.c:477) 200,000 bytes in 1 blocks are possibly lost in loss record ... of ... at 0x........: calloc (vg_replace_malloc.c:...) - by 0x........: f (leak-segv-jmp.c:436) - by 0x........: main (leak-segv-jmp.c:464) + by 0x........: f (leak-segv-jmp.c:449) + by 0x........: main (leak-segv-jmp.c:477) LEAK SUMMARY: definitely lost: 1,000 bytes in 1 blocks diff --git a/memcheck/tests/leak.h b/memcheck/tests/leak.h index 79e3cd6..df9d2e7 100644 --- a/memcheck/tests/leak.h +++ b/memcheck/tests/leak.h @@ -148,6 +148,27 @@ do { \ __asm__ __volatile__ ("movl $0, %ecx\n\t"); \ } while (0) +#elif defined (VGA_loongarch64) +#define CLEAR_CALLER_SAVED_REGS \ + do { \ + __asm__ __volatile__ ("move $a0, $zero \n\t" \ + "move $a1, $zero \n\t" \ + "move $a2, $zero \n\t" \ + "move $a3, $zero \n\t" \ + "move $a4, $zero \n\t" \ + "move $a5, $zero \n\t" \ + "move $a6, $zero \n\t" \ + "move $a7, $zero \n\t" \ + "move $t0, $zero \n\t" \ + "move $t1, $zero \n\t" \ + "move $t2, $zero \n\t" \ + "move $t3, $zero \n\t" \ + "move $t4, $zero \n\t" \ + "move $t5, $zero \n\t" \ + "move $t6, $zero \n\t" \ + "move $t7, $zero \n\t" \ + "move $t8, $zero \n\t"); \ + } while (0) #else #define CLEAR_CALLER_SAVED_REGS /*nothing*/ #endif diff --git a/memcheck/tests/linux/Makefile.in b/memcheck/tests/linux/Makefile.in index 2631f0e..86eedbb 100644 --- a/memcheck/tests/linux/Makefile.in +++ b/memcheck/tests/linux/Makefile.in @@ -723,6 +723,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -770,6 +776,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/loongarch64-linux/Makefile.am b/memcheck/tests/loongarch64-linux/Makefile.am new file mode 100644 index 0000000..5afcaa4 --- /dev/null +++ b/memcheck/tests/loongarch64-linux/Makefile.am @@ -0,0 +1,17 @@ + +include $(top_srcdir)/Makefile.tool-tests.am + +dist_noinst_SCRIPTS = \ + filter_stderr + +noinst_HEADERS = scalar.h + +EXTRA_DIST = \ + scalar.stderr.exp scalar.vgtest + +check_PROGRAMS = \ + scalar + +AM_CFLAGS += @FLAG_M64@ +AM_CXXFLAGS += @FLAG_M64@ +AM_CCASFLAGS += @FLAG_M64@ diff --git a/memcheck/tests/loongarch64-linux/filter_stderr b/memcheck/tests/loongarch64-linux/filter_stderr new file mode 100755 index 0000000..a778e97 --- /dev/null +++ b/memcheck/tests/loongarch64-linux/filter_stderr @@ -0,0 +1,3 @@ +#! /bin/sh + +../filter_stderr "$@" diff --git a/memcheck/tests/loongarch64-linux/scalar.c b/memcheck/tests/loongarch64-linux/scalar.c new file mode 100644 index 0000000..e390692 --- /dev/null +++ b/memcheck/tests/loongarch64-linux/scalar.c @@ -0,0 +1,1296 @@ +/* This is the loongarch64 variant of memcheck/tests/x86-linux/scalar.c. + Syscalls are in x86 number order to make exp comparison easier. */ +#define _GNU_SOURCE +#include "../../memcheck.h" +#include "scalar.h" +#include +#include +#include +#include // MREMAP_FIXED + +// Here we are trying to trigger every syscall error (scalar errors and +// memory errors) for every syscall. We do this by passing a lot of bogus +// arguments, mostly 0 and 1 (often it's 1 because NULL ptr args often aren't +// checked for memory errors, or in order to have a non-zero length used +// with some buffer). So most of the syscalls don't actually succeed and do +// anything. +// +// Occasionally we have to be careful not to cause Valgrind to seg fault in +// its pre-syscall wrappers; it does so because it can't know in general +// when memory is unaddressable, and so tries to dereference it when doing +// PRE_MEM_READ/PRE_MEM_WRITE calls. (Note that Memcheck will +// always issue an error message immediately before these seg faults occur). +// +// The output has numbers like "3s 2m" for each syscall. "s" is short for +// "scalar", ie. the argument itself is undefined. "m" is short for "memory", +// ie. the argument points to memory which is unaddressable. +int main(void) +{ + // uninitialised, but we know px[0] is 0x0 + long* px = malloc(sizeof(long)); + long x0 = px[0]; + long res; + + // All __NR_xxx numbers are taken from x86 + + // __NR_restart_syscall 0 // XXX: not yet handled, perhaps should be... + GO(__NR_restart_syscall, "n/a"); + //SY(__NR_restart_syscall); // (Not yet handled by Valgrind) FAIL; + + // __NR_exit 1 + GO(__NR_exit, "below"); + // (see below) + + // __NR_fork 2 + //GO(__NR_fork, "other"); + // (sse scalar_fork.c) + + // __NR_read 3 + // Nb: here we are also getting an error from the syscall arg itself. + GO(__NR_read, "1+3s 1m"); + SY(__NR_read+x0, x0, x0, x0+1); FAILx(EFAULT); + + // __NR_write 4 + GO(__NR_write, "3s 1m"); + SY(__NR_write, x0, x0, x0+1); FAIL; + + // __NR_open 5 + //GO(__NR_open, "(2-args) 2s 1m"); + //SY(__NR_open, x0, x0); FAIL; + + // Only 1s 0m errors -- the other 2s 1m have been checked in the previous + // open test, and if we test them they may be commoned up but they also + // may not. + //GO(__NR_open, "(3-args) 1s 0m"); + //SY(__NR_open, "scalar.c", O_CREAT|O_EXCL, x0); FAIL; + + // __NR_close 6 + GO(__NR_close, "1s 0m"); + SY(__NR_close, x0-1); FAIL; + + // __NR_waitpid 7 + //GO(__NR_waitpid, "3s 1m"); + //SY(__NR_waitpid, x0, x0+1, x0); FAIL; + + // __NR_creat 8 + //GO(__NR_creat, "2s 1m"); + //SY(__NR_creat, x0, x0); FAIL; + + // __NR_link 9 + //GO(__NR_link, "2s 2m"); + //SY(__NR_link, x0, x0); FAIL; + + // __NR_unlink 10 + //GO(__NR_unlink, "1s 1m"); + //SY(__NR_unlink, x0); FAIL; + + // __NR_execve 11 + GO(__NR_execve, "3s 1m"); + SY(__NR_execve, x0 + 1, x0 + 1, x0); FAIL; + + GO(__NR_execve, "3s 1m"); + SY(__NR_execve, x0 + 1, x0, x0 + 1); FAIL; + + char *argv_envp[] = {(char *) (x0 + 1), NULL}; + GO(__NR_execve, "4s 2m"); + SY(__NR_execve, x0 + 1, x0 + argv_envp, x0); FAIL; + char *argv_ok[] = {"frob", NULL}; + GO(__NR_execve, "4s 2m"); + SY(__NR_execve, x0 + 1, x0 + argv_ok, x0 + argv_envp); FAIL; + + // __NR_chdir 12 + GO(__NR_chdir, "1s 1m"); + SY(__NR_chdir, x0); FAIL; + + // __NR_time 13 + //GO(__NR_time, "1s 1m"); + //SY(__NR_time, x0+1); FAIL; + + // __NR_mknod 14 + //O(__NR_mknod, "3s 1m"); + //Y(__NR_mknod, x0, x0, x0); FAIL; + + // __NR_chmod 15 + //GO(__NR_chmod, "2s 1m"); + //SY(__NR_chmod, x0, x0); FAIL; + + // __NR_lchown 16 + //GO(__NR_lchown, "n/a"); + //SY(__NR_lchown); // (Not yet handled by Valgrind) FAIL; + + // __NR_break 17 + //GO(__NR_break, "ni"); + //SY(__NR_break); FAIL; + + // __NR_oldstat 18 + //GO(__NR_oldstat, "n/a"); + // (obsolete, not handled by Valgrind) + + // __NR_lseek 19 + GO(__NR_lseek, "3s 0m"); + SY(__NR_lseek, x0-1, x0, x0); FAILx(EBADF); + + // __NR_getpid 20 + GO(__NR_getpid, "0s 0m"); + SY(__NR_getpid); SUCC; + + // __NR_mount 21 + GO(__NR_mount, "5s 3m"); + SY(__NR_mount, x0, x0, x0, x0, x0); FAIL; + + // __NR_umount 22 + //GO(__NR_umount, "1s 1m"); + //SY(__NR_umount, x0); FAIL; + + // __NR_setuid 23 + GO(__NR_setuid, "1s 0m"); + SY(__NR_setuid, x0-1); FAIL; + + // __NR_getuid 24 + GO(__NR_getuid, "0s 0m"); + SY(__NR_getuid); SUCC; + + // __NR_stime 25 + //GO(__NR_stime, "n/a"); + //SY(__NR_stime); // (Not yet handled by Valgrind) FAIL; + + // __NR_ptrace 26 + // XXX: memory pointed to be arg3 goes unchecked... otherwise would be 2m + //GO(__NR_ptrace, "4s 1m"); + //SY(__NR_ptrace, x0+PTRACE_GETREGS, x0, x0, x0); FAIL; + + // __NR_alarm 27 + //GO(__NR_alarm, "1s 0m"); + //SY(__NR_alarm, x0); SUCC; + + // __NR_oldfstat 28 + //GO(__NR_oldfstat, "n/a"); + // (obsolete, not handled by Valgrind) + + // __NR_pause 29 + //GO(__NR_pause, "ignore"); + // (hard to test, and no args so not much to be gained -- don't bother) + + // __NR_utime 30 + //GO(__NR_utime, "2s 2m"); + //SY(__NR_utime, x0, x0+1); FAIL; + + // __NR_stty 31 + //GO(__NR_stty, "ni"); + //SY(__NR_stty); FAIL; + + // __NR_gtty 32 + //GO(__NR_gtty, "ni"); + //SY(__NR_gtty); FAIL; + + // __NR_access 33 + //GO(__NR_access, "2s 1m"); + //SY(__NR_access, x0, x0); FAIL; + + // __NR_nice 34 + //GO(__NR_nice, "1s 0m"); + //SY(__NR_nice, x0); SUCC; + + // __NR_ftime 35 + //GO(__NR_ftime, "ni"); + //SY(__NR_ftime); FAIL; + + // __NR_sync 36 + GO(__NR_sync, "0s 0m"); + SY(__NR_sync); SUCC; + + // __NR_kill 37 + GO(__NR_kill, "2s 0m"); + SY(__NR_kill, x0, x0); SUCC; + + // __NR_rename 38 + //GO(__NR_rename, "2s 2m"); + //SY(__NR_rename, x0, x0); FAIL; + + // __NR_mkdir 39 + //GO(__NR_mkdir, "2s 1m"); + //SY(__NR_mkdir, x0, x0); FAIL; + + // __NR_rmdir 40 + //GO(__NR_rmdir, "1s 1m"); + //SY(__NR_rmdir, x0); FAIL; + + // __NR_dup 41 + GO(__NR_dup, "1s 0m"); + SY(__NR_dup, x0-1); FAIL; + + // __NR_pipe 42 + //GO(__NR_pipe, "1s 1m"); + //SY(__NR_pipe, x0); FAIL; + + // __NR_times 43 + GO(__NR_times, "1s 1m"); + SY(__NR_times, x0+1); FAIL; + + // __NR_prof 44 + //GO(__NR_prof, "ni"); + //SY(__NR_prof); FAIL; + + // __NR_brk 45 + GO(__NR_brk, "1s 0m"); + SY(__NR_brk, x0); SUCC; + + // __NR_setgid 46 + GO(__NR_setgid, "1s 0m"); + SY(__NR_setgid, x0-1); FAIL; + + // __NR_getgid 47 + GO(__NR_getgid, "0s 0m"); + SY(__NR_getgid); SUCC; + + // __NR_signal 48 + //GO(__NR_signal, "n/a"); + //SY(__NR_signal); // (Not yet handled by Valgrind) FAIL; + + // __NR_geteuid 49 + GO(__NR_geteuid, "0s 0m"); + SY(__NR_geteuid); SUCC; + + // __NR_getegid 50 + GO(__NR_getegid, "0s 0m"); + SY(__NR_getegid); SUCC; + + // __NR_acct 51 + GO(__NR_acct, "1s 1m"); + SY(__NR_acct, x0-1); FAIL; + + // __NR_umount2 52 + GO(__NR_umount2, "2s 1m"); + SY(__NR_umount2, x0, x0); FAIL; + + // __NR_lock 53 + //GO(__NR_lock, "ni"); + //SY(__NR_lock); FAIL; + + // __NR_ioctl 54 +#include + GO(__NR_ioctl, "3s 1m"); + SY(__NR_ioctl, x0, x0+TCSETS, x0); FAIL; + + // __NR_fcntl 55 + // As with sys_open(), the 'fd' error is suppressed for the later ones. + // For F_GETFD the 3rd arg is ignored + GO(__NR_fcntl, "(GETFD) 2s 0m"); + SY(__NR_fcntl, x0-1, x0+F_GETFD, x0); FAILx(EBADF); + + // For F_DUPFD the 3rd arg is 'arg'. We don't check the 1st two args + // because any errors may or may not be commoned up with the ones from + // the previous fcntl call. + GO(__NR_fcntl, "(DUPFD) 1s 0m"); + SY(__NR_fcntl, -1, F_DUPFD, x0); FAILx(EBADF); + + // For F_GETLK the 3rd arg is 'lock'. On x86, this fails w/EBADF. But + // on amd64 in 32-bit mode it fails w/EFAULT. We don't check the 1st two + // args for the reason given above. + GO(__NR_fcntl, "(GETLK) 1s 5m"); + SY(__NR_fcntl, -1, F_GETLK, x0); FAIL; //FAILx(EBADF); + + // __NR_mpx 56 + //GO(__NR_mpx, "ni"); + //SY(__NR_mpx); FAIL; + + // __NR_setpgid 57 + GO(__NR_setpgid, "2s 0m"); + SY(__NR_setpgid, x0, x0-1); FAIL; + + // __NR_ulimit 58 + //GO(__NR_ulimit, "ni"); + //SY(__NR_ulimit); FAIL; + + // __NR_oldolduname 59 + //GO(__NR_oldolduname, "n/a"); + // (obsolete, not handled by Valgrind) + + // __NR_umask 60 + GO(__NR_umask, "1s 0m"); + SY(__NR_umask, x0+022); SUCC; + + // __NR_chroot 61 + GO(__NR_chroot, "1s 1m"); + SY(__NR_chroot, x0); FAIL; + + // __NR_ustat 62 + //GO(__NR_ustat, "n/a"); + // (deprecated, not handled by Valgrind) + + // __NR_dup2 63 + //GO(__NR_dup2, "2s 0m"); + //SY(__NR_dup2, x0-1, x0); FAIL; + + // __NR_getppid 64 + GO(__NR_getppid, "0s 0m"); + SY(__NR_getppid); SUCC; + + // __NR_getpgrp 65 + //GO(__NR_getpgrp, "0s 0m"); + //SY(__NR_getpgrp); SUCC; + + // __NR_setsid 66 + GO(__NR_setsid, "0s 0m"); + SY(__NR_setsid); SUCC_OR_FAIL; + + // __NR_sigaction 67 + //GO(__NR_sigaction, "3s 4m"); + //SY(__NR_sigaction, x0, x0+&px[1], x0+&px[1]); FAIL; + + // __NR_sgetmask 68 sys_sgetmask() + //GO(__NR_sgetmask, "n/a"); + //SY(__NR_sgetmask); // (Not yet handled by Valgrind) FAIL; + + // __NR_ssetmask 69 + //GO(__NR_ssetmask, "n/a"); + //SY(__NR_ssetmask); // (Not yet handled by Valgrind) FAIL; + + // __NR_setreuid 70 + GO(__NR_setreuid, "2s 0m"); + SY(__NR_setreuid, x0-1, x0-1); SUCC; + + // __NR_setregid 71 + GO(__NR_setregid, "2s 0m"); + SY(__NR_setregid, x0-1, x0-1); SUCC; + + // __NR_sigsuspend 72 + // XXX: how do you use this function? + //GO(__NR_sigsuspend, "ignore"); + // (I don't know how to test this...) + + // __NR_sigpending 73 + //GO(__NR_sigpending, "1s 1m"); + //SY(__NR_sigpending, x0); FAIL; + + // __NR_sethostname 74 + GO(__NR_sethostname, "n/a"); + //SY(__NR_sethostname); // (Not yet handled by Valgrind) FAIL; + + // __NR_setrlimit 75 + //GO(__NR_setrlimit, "2s 1m"); + //SY(__NR_setrlimit, x0, x0); FAIL; + + // __NR_getrlimit 76 + //GO(__NR_getrlimit, "2s 1m"); + //SY(__NR_getrlimit, x0, x0); FAIL; + + // __NR_getrusage 77 + GO(__NR_getrusage, "2s 1m"); + SY(__NR_getrusage, x0, x0); FAIL; + + // __NR_gettimeofday 78 + GO(__NR_gettimeofday, "2s 2m"); + SY(__NR_gettimeofday, x0+1, x0+1); FAIL; + + // __NR_settimeofday 79 + GO(__NR_settimeofday, "2s 2m"); + SY(__NR_settimeofday, x0+1, x0+1); FAIL; + + // __NR_getgroups 80 + GO(__NR_getgroups, "2s 1m"); + SY(__NR_getgroups, x0+1, x0+1); FAIL; + + // __NR_setgroups 81 + GO(__NR_setgroups, "2s 1m"); + SY(__NR_setgroups, x0+1, x0+1); FAIL; + + // __NR_select 82 + //{ + // long args[5] = { x0+8, x0+0xffffffee, x0+1, x0+1, x0+1 }; + // GO(__NR_select, "1s 5m"); + // SY(__NR_select, args+x0); FAIL; + //} + + // __NR_symlink 83 + //GO(__NR_symlink, "2s 2m"); + //SY(__NR_symlink, x0, x0); FAIL; + + // __NR_oldlstat 84 + //GO(__NR_oldlstat, "n/a"); + // (obsolete, not handled by Valgrind) + + // __NR_readlink 85 + //GO(__NR_readlink, "3s 2m"); + //SY(__NR_readlink, x0+1, x0+1, x0+1); FAIL; + + // __NR_uselib 86 + //GO(__NR_uselib, "n/a"); + //SY(__NR_uselib); // (Not yet handled by Valgrind) FAIL; + + // __NR_swapon 87 + GO(__NR_swapon, "n/a"); + //SY(__NR_swapon); // (Not yet handled by Valgrind) FAIL; + + // __NR_reboot 88 + GO(__NR_reboot, "n/a"); + //SY(__NR_reboot); // (Not yet handled by Valgrind) FAIL; + + // __NR_readdir 89 + //GO(__NR_readdir, "n/a"); + // (superseded, not handled by Valgrind) + + // __NR_mmap 90 + { + long args[6] = { x0, x0, x0, x0, x0-1, x0 }; + GO(__NR_mmap, "1s 1m"); + SY(__NR_mmap, args+x0); FAIL; + } + + // __NR_munmap 91 + GO(__NR_munmap, "2s 0m"); + SY(__NR_munmap, x0, x0); FAIL; + + // __NR_truncate 92 + GO(__NR_truncate, "2s 1m"); + SY(__NR_truncate, x0, x0); FAIL; + + // __NR_ftruncate 93 + GO(__NR_ftruncate, "2s 0m"); + SY(__NR_ftruncate, x0, x0); FAIL; + + // __NR_fchmod 94 + GO(__NR_fchmod, "2s 0m"); + SY(__NR_fchmod, x0-1, x0); FAIL; + + // __NR_fchown 95 + GO(__NR_fchown, "3s 0m"); + SY(__NR_fchown, x0-1, x0, x0); FAIL; + + // __NR_getpriority 96 + GO(__NR_getpriority, "2s 0m"); + SY(__NR_getpriority, x0-1, x0); FAIL; + + // __NR_setpriority 97 + GO(__NR_setpriority, "3s 0m"); + SY(__NR_setpriority, x0-1, x0, x0); FAIL; + + // __NR_profil 98 + //GO(__NR_profil, "ni"); + //SY(__NR_profil); FAIL; + + // __NR_statfs 99 + GO(__NR_statfs, "2s 2m"); + SY(__NR_statfs, x0, x0); FAIL; + + // __NR_fstatfs 100 + GO(__NR_fstatfs, "2s 1m"); + SY(__NR_fstatfs, x0, x0); FAIL; + + // __NR_ioperm 101 + //GO(__NR_ioperm, "3s 0m"); + //SY(__NR_ioperm, x0, x0, x0); FAIL; + + // __NR_socketcall 102 + //GO(__NR_socketcall, "XXX"); + // (XXX: need to do all sub-cases properly) + + // __NR_syslog 103 + GO(__NR_syslog, "3s 1m"); + SY(__NR_syslog, x0+2, x0, x0+1); FAIL; + + // __NR_setitimer 104 + GO(__NR_setitimer, "3s 2m"); + SY(__NR_setitimer, x0, x0+1, x0+1); FAIL; + + // __NR_getitimer 105 + GO(__NR_getitimer, "2s 1m"); + SY(__NR_getitimer, x0, x0, x0); FAIL; + + // __NR_stat 106 + //GO(__NR_stat, "2s 2m"); + //SY(__NR_stat, x0, x0); FAIL; + + // __NR_lstat 107 + //GO(__NR_lstat, "2s 2m"); + //SY(__NR_lstat, x0, x0); FAIL; + + // __NR_fstat 108 + //GO(__NR_fstat, "2s 1m"); + //SY(__NR_fstat, x0, x0); FAIL; + + // __NR_olduname 109 + //GO(__NR_olduname, "n/a"); + // (obsolete, not handled by Valgrind) + + // __NR_iopl 110 + //GO(__NR_iopl, "1s 0m"); + //SY(__NR_iopl, x0+100); FAIL; + + // __NR_vhangup 111 + GO(__NR_vhangup, "0s 0m"); + SY(__NR_vhangup); SUCC_OR_FAIL; // Will succeed for superuser + + // __NR_idle 112 + //GO(__NR_idle, "ni"); + //SY(__NR_idle); FAIL; + + // __NR_vm86old 113 + //GO(__NR_vm86old, "n/a"); + // (will probably never be handled by Valgrind) + + // __NR_wait4 114 + GO(__NR_wait4, "4s 2m"); + SY(__NR_wait4, x0, x0+1, x0, x0+1); FAIL; + + // __NR_swapoff 115 + GO(__NR_swapoff, "n/a"); + //SY(__NR_swapoff); // (Not yet handled by Valgrind) FAIL; + + // __NR_sysinfo 116 + GO(__NR_sysinfo, "1s 1m"); + SY(__NR_sysinfo, x0); FAIL; + + // __NR_ipc 117 + // XXX: This is simplistic -- need to do all the sub-cases properly. + // XXX: Also, should be 6 scalar errors, except glibc's syscall() doesn't + // use the 6th one! + //GO(__NR_ipc, "5s 0m"); + //SY(__NR_ipc, x0+4, x0, x0, x0, x0, x0); FAIL; + + // __NR_fsync 118 + GO(__NR_fsync, "1s 0m"); + SY(__NR_fsync, x0-1); FAIL; + + // __NR_sigreturn 119 + //GO(__NR_sigreturn, "n/a"); + //SY(__NR_sigreturn); // (Not yet handled by Valgrind) FAIL; + + // __NR_clone 120 +#ifndef CLONE_PARENT_SETTID +#define CLONE_PARENT_SETTID 0x00100000 +#endif + GO(__NR_clone, "5s 3m"); + SY(__NR_clone, x0|CLONE_PARENT_SETTID|CLONE_SETTLS|CLONE_CHILD_SETTID|SIGCHLD, x0, x0, x0, x0); FAIL; + if (0 == res) { + SY(__NR_exit, 0); FAIL; + } + + // __NR_setdomainname 121 + GO(__NR_setdomainname, "n/a"); + //SY(__NR_setdomainname); // (Not yet handled by Valgrind) FAIL; + + // __NR_uname 122 + GO(__NR_uname, "1s 1m"); + SY(__NR_uname, x0); FAIL; + + // __NR_modify_ldt 123 + //GO(__NR_modify_ldt, "3s 1m"); + //SY(__NR_modify_ldt, x0+1, x0, x0+1); FAILx(EINVAL); + + // __NR_adjtimex 124 + // XXX: need to do properly, but deref'ing NULL causing Valgrind to crash... + GO(__NR_adjtimex, "XXX"); + //SY(__NR_adjtimex, x0); FAIL; + + // __NR_mprotect 125 + GO(__NR_mprotect, "3s 0m"); + SY(__NR_mprotect, x0+1, x0, x0); FAILx(EINVAL); + + // __NR_sigprocmask 126 + //GO(__NR_sigprocmask, "3s 2m"); + //SY(__NR_sigprocmask, x0, x0+&px[1], x0+&px[1]); SUCC; + + // __NR_create_module 127 + //GO(__NR_create_module, "ni"); + //SY(__NR_create_module); FAIL; + + // __NR_init_module 128 + GO(__NR_init_module, "3s 2m"); + SY(__NR_init_module, x0, x0+1, x0); FAIL; + + // __NR_delete_module 129 + GO(__NR_delete_module, "n/a"); + //SY(__NR_delete_module); // (Not yet handled by Valgrind) FAIL; + + // __NR_get_kernel_syms 130 + //GO(__NR_get_kernel_syms, "ni"); + //SY(__NR_get_kernel_syms); FAIL; + + // __NR_quotactl 131 + GO(__NR_quotactl, "4s 1m"); + SY(__NR_quotactl, x0, x0, x0, x0); FAIL; + + // __NR_getpgid 132 + GO(__NR_getpgid, "1s 0m"); + SY(__NR_getpgid, x0-1); FAIL; + + // __NR_fchdir 133 + GO(__NR_fchdir, "1s 0m"); + SY(__NR_fchdir, x0-1); FAIL; + + // __NR_bdflush 134 + //GO(__NR_bdflush, "n/a"); + //SY(__NR_bdflush); // (Not yet handled by Valgrind) FAIL; + + // __NR_sysfs 135 + //GO(__NR_sysfs, "n/a"); + //SY(__NR_sysfs); // (Not yet handled by Valgrind) FAIL; + + // __NR_personality 136 + GO(__NR_personality, "1s 0m"); + SY(__NR_personality, x0+0xffffffff); SUCC; + + // __NR_afs_syscall 137 + //GO(__NR_afs_syscall, "ni"); + //SY(__NR_afs_syscall); FAIL; + + // __NR_setfsuid 138 + GO(__NR_setfsuid, "1s 0m"); + SY(__NR_setfsuid, x0); SUCC; // This syscall has a stupid return value + + // __NR_setfsgid 139 + GO(__NR_setfsgid, "1s 0m"); + SY(__NR_setfsgid, x0); SUCC; // This syscall has a stupid return value + + // __NR__llseek 140 + //GO(__NR__llseek, "5s 1m"); + //SY(__NR__llseek, x0, x0, x0, x0, x0); FAIL; + + // __NR_getdents 141 + //GO(__NR_getdents, "3s 1m"); + //SY(__NR_getdents, x0, x0, x0+1); FAIL; + + // __NR__newselect 142 + //GO(__NR__newselect, "5s 4m"); + //SY(__NR__newselect, x0+8, x0+0xffffffff, x0+1, x0+1, x0+1); FAIL; + + // __NR_flock 143 + GO(__NR_flock, "2s 0m"); + SY(__NR_flock, x0, x0); FAIL; + + // __NR_msync 144 + GO(__NR_msync, "3s 1m"); + SY(__NR_msync, x0, x0+1, x0); FAIL; + + // __NR_readv 145 + GO(__NR_readv, "3s 1m"); + SY(__NR_readv, x0, x0, x0+1); FAIL; + + // __NR_writev 146 + GO(__NR_writev, "3s 1m"); + SY(__NR_writev, x0, x0, x0+1); FAIL; + + // __NR_getsid 147 + GO(__NR_getsid, "1s 0m"); + SY(__NR_getsid, x0-1); FAIL; + + // __NR_fdatasync 148 + GO(__NR_fdatasync, "1s 0m"); + SY(__NR_fdatasync, x0-1); FAIL; + + // __NR__sysctl 149 + //GO(__NR__sysctl, "1s 1m"); + //SY(__NR__sysctl, x0); FAIL; + + // __NR_mlock 150 + GO(__NR_mlock, "2s 0m"); + SY(__NR_mlock, x0, x0+1); FAIL; + + // __NR_munlock 151 + GO(__NR_munlock, "2s 0m"); + SY(__NR_munlock, x0, x0+1); FAIL; + + // __NR_mlockall 152 + GO(__NR_mlockall, "1s 0m"); + SY(__NR_mlockall, x0-1); FAIL; + + // __NR_munlockall 153 + GO(__NR_munlockall, "0s 0m"); + SY(__NR_munlockall); SUCC_OR_FAILx(EPERM); + + // __NR_sched_setparam 154 + GO(__NR_sched_setparam, "2s 1m"); + SY(__NR_sched_setparam, x0, x0); FAIL; + + // __NR_sched_getparam 155 + GO(__NR_sched_getparam, "2s 1m"); + SY(__NR_sched_getparam, x0, x0); FAIL; + + // __NR_sched_setscheduler 156 + GO(__NR_sched_setscheduler, "3s 1m"); + SY(__NR_sched_setscheduler, x0-1, x0, x0+1); FAIL; + + // __NR_sched_getscheduler 157 + GO(__NR_sched_getscheduler, "1s 0m"); + SY(__NR_sched_getscheduler, x0-1); FAIL; + + // __NR_sched_yield 158 + GO(__NR_sched_yield, "0s 0m"); + SY(__NR_sched_yield); SUCC; + + // __NR_sched_get_priority_max 159 + GO(__NR_sched_get_priority_max, "1s 0m"); + SY(__NR_sched_get_priority_max, x0-1); FAIL; + + // __NR_sched_get_priority_min 160 + GO(__NR_sched_get_priority_min, "1s 0m"); + SY(__NR_sched_get_priority_min, x0-1); FAIL; + + // __NR_sched_rr_get_interval 161 + GO(__NR_sched_rr_get_interval, "n/a"); + //SY(__NR_sched_rr_get_interval); // (Not yet handled by Valgrind) FAIL; + + // __NR_nanosleep 162 + GO(__NR_nanosleep, "2s 2m"); + SY(__NR_nanosleep, x0, x0+1); FAIL; + + // __NR_mremap 163 + GO(__NR_mremap, "5s 0m"); + SY(__NR_mremap, x0+1, x0, x0, x0+MREMAP_FIXED, x0); FAILx(EINVAL); + + // __NR_setresuid 164 + GO(__NR_setresuid, "3s 0m"); + SY(__NR_setresuid, x0-1, x0-1, x0-1); SUCC; + + // __NR_getresuid 165 + GO(__NR_getresuid, "3s 3m"); + SY(__NR_getresuid, x0, x0, x0); FAIL; + + // __NR_vm86 166 + //GO(__NR_vm86, "n/a"); + // (will probably never be handled by Valgrind) + + // __NR_query_module 167 + //GO(__NR_query_module, "ni"); + //SY(__NR_query_module); FAIL; + + // __NR_poll 168 + //GO(__NR_poll, "3s 1m"); + //SY(__NR_poll, x0, x0+1, x0); FAIL; + + // __NR_nfsservctl 169 + GO(__NR_nfsservctl, "n/a"); + //SY(__NR_nfsservctl); // (Not yet handled by Valgrind) FAIL; + + // __NR_setresgid 170 + GO(__NR_setresgid, "3s 0m"); + SY(__NR_setresgid, x0-1, x0-1, x0-1); SUCC; + + // __NR_getresgid 171 + GO(__NR_getresgid, "3s 3m"); + SY(__NR_getresgid, x0, x0, x0); FAIL; + + // __NR_prctl 172 +#include + GO(__NR_prctl, "5s 0m"); + SY(__NR_prctl, x0, x0, x0, x0, x0); FAIL; + + char buf16[16] = "123456789012345."; + buf16[15] = x0; // this will cause 'using unitialised value' + GO(__NR_prctl, "2s 0m"); + SY(__NR_prctl, x0 + PR_SET_NAME, buf16); SUCC; + + char buf17[17] = "1234567890123456."; + buf17[16] = x0; // this must not cause 'using unitialised value' + GO(__NR_prctl, "1s 0m"); + SY(__NR_prctl, x0 + PR_SET_NAME, buf17); SUCC; + + // __NR_rt_sigreturn 173 + GO(__NR_rt_sigreturn, "n/a"); + //SY(__NR_rt_sigreturn); // (Not yet handled by Valgrind) FAIL; + + // __NR_rt_sigaction 174 + GO(__NR_rt_sigaction, "4s 4m"); + SY(__NR_rt_sigaction, x0, x0+&px[2], x0+&px[2], x0); FAIL; + + // __NR_rt_sigprocmask 175 + GO(__NR_rt_sigprocmask, "4s 2m"); + SY(__NR_rt_sigprocmask, x0, x0+1, x0+1, x0); FAIL; + + // __NR_rt_sigpending 176 + GO(__NR_rt_sigpending, "2s 1m"); + SY(__NR_rt_sigpending, x0, x0+1); FAIL; + + // __NR_rt_sigtimedwait 177 + GO(__NR_rt_sigtimedwait, "4s 3m"); + SY(__NR_rt_sigtimedwait, x0+1, x0+1, x0+1, x0); FAIL; + + // __NR_rt_sigqueueinfo 178 + GO(__NR_rt_sigqueueinfo, "3s 1m"); + SY(__NR_rt_sigqueueinfo, x0, x0+1, x0); FAIL; + + // __NR_rt_sigsuspend 179 + GO(__NR_rt_sigsuspend, "2s 1m"); + SY(__NR_rt_sigsuspend, x0 + 1, x0 + sizeof(sigset_t)); FAILx(EFAULT); + + // __NR_pread64 180 + GO(__NR_pread64, "5s 1m"); + SY(__NR_pread64, x0, x0, x0+1, x0, x0); FAIL; + + // __NR_pwrite64 181 + GO(__NR_pwrite64, "5s 1m"); + SY(__NR_pwrite64, x0, x0, x0+1, x0, x0); FAIL; + + // __NR_chown 182 + //GO(__NR_chown, "3s 1m"); + //SY(__NR_chown, x0, x0, x0); FAIL; + + // __NR_getcwd 183 + GO(__NR_getcwd, "2s 1m"); + SY(__NR_getcwd, x0, x0+1); FAIL; + + // __NR_capget 184 + GO(__NR_capget, "2s 2m"); + SY(__NR_capget, x0, x0+1); FAIL; + + // __NR_capset 185 + GO(__NR_capset, "2s 2m"); + SY(__NR_capset, x0, x0); FAIL; + + // __NR_sigaltstack 186 + { + struct our_sigaltstack { + void *ss_sp; + int ss_flags; + size_t ss_size; + } ss; + ss.ss_sp = NULL; + ss.ss_flags = 0; + ss.ss_size = 0; + VALGRIND_MAKE_MEM_NOACCESS(& ss, sizeof(struct our_sigaltstack)); + GO(__NR_sigaltstack, "2s 2m"); + SY(__NR_sigaltstack, x0+&ss, x0+&ss); SUCC; + } + + // __NR_sendfile 187 + GO(__NR_sendfile, "4s 1m"); + SY(__NR_sendfile, x0, x0, x0+1, x0); FAIL; + + // __NR_getpmsg 188 + // Could do 5s 4m with more effort, but I can't be bothered for this + // crappy non-standard syscall. + //GO(__NR_getpmsg, "5s 0m"); + //SY(__NR_getpmsg, x0, x0, x0, x0); FAIL; + + // __NR_putpmsg 189 + // Could do 5s 2m with more effort, but I can't be bothered for this + // crappy non-standard syscall. + //GO(__NR_putpmsg, "5s 0m"); + //SY(__NR_putpmsg, x0, x0, x0, x0, x0); FAIL; + + // __NR_vfork 190 + //GO(__NR_vfork, "other"); + // (sse scalar_vfork.c) + + // __NR_ugetrlimit 191 + //GO(__NR_ugetrlimit, "2s 1m"); + //SY(__NR_ugetrlimit, x0, x0); FAIL; + + // __NR_mmap2 192 + //GO(__NR_mmap2, "6s 0m"); + //SY(__NR_mmap2, x0, x0, x0, x0, x0-1, x0); FAIL; + + // __NR_truncate64 193 + //GO(__NR_truncate64, "3s 1m"); + //SY(__NR_truncate64, x0, x0, x0); FAIL; + + // __NR_ftruncate64 194 + //GO(__NR_ftruncate64, "3s 0m"); + //SY(__NR_ftruncate64, x0, x0, x0); FAIL; + + // __NR_stat64 195 + //GO(__NR_stat64, "2s 2m"); + //SY(__NR_stat64, x0, x0); FAIL; + + // __NR_lstat64 196 + //GO(__NR_lstat64, "2s 2m"); + //SY(__NR_lstat64, x0, x0); FAIL; + + // __NR_fstat64 197 + //GO(__NR_fstat64, "2s 1m"); + //SY(__NR_fstat64, x0, x0); FAIL; + + // __NR_lchown32 198 + //GO(__NR_lchown32, "3s 1m"); + //SY(__NR_lchown32, x0, x0, x0); FAIL; + + // __NR_getuid32 199 + //GO(__NR_getuid32, "0s 0m"); + //SY(__NR_getuid32); SUCC; + + // __NR_getgid32 200 + //GO(__NR_getgid32, "0s 0m"); + //SY(__NR_getgid32); SUCC; + + // __NR_geteuid32 201 + //GO(__NR_geteuid32, "0s 0m"); + //SY(__NR_geteuid32); SUCC; + + // __NR_getegid32 202 + //GO(__NR_getegid32, "0s 0m"); + //SY(__NR_getegid32); SUCC; + + // __NR_setreuid32 203 + //GO(__NR_setreuid32, "2s 0m"); + //SY(__NR_setreuid32, x0-1, x0-1); SUCC; + + // __NR_setregid32 204 + //GO(__NR_setregid32, "2s 0m"); + //SY(__NR_setregid32, x0-1, x0-1); SUCC; + + // __NR_getgroups32 205 + //GO(__NR_getgroups32, "2s 1m"); + //SY(__NR_getgroups32, x0+1, x0+1); FAIL; + + // __NR_setgroups32 206 + //GO(__NR_setgroups32, "2s 1m"); + //SY(__NR_setgroups32, x0+1, x0+1); FAIL; + + // __NR_fchown32 207 + //GO(__NR_fchown32, "3s 0m"); + //SY(__NR_fchown32, x0-1, x0, x0); FAIL; + + // __NR_setresuid32 208 + //GO(__NR_setresuid32, "3s 0m"); + //SY(__NR_setresuid32, x0-1, x0-1, x0-1); SUCC; + + // __NR_getresuid32 209 + //GO(__NR_getresuid32, "3s 3m"); + //SY(__NR_getresuid32, x0, x0, x0); FAIL; + + // __NR_setresgid32 210 + //GO(__NR_setresgid32, "3s 0m"); + //SY(__NR_setresgid32, x0-1, x0-1, x0-1); SUCC; + + // __NR_getresgid32 211 + //GO(__NR_getresgid32, "3s 3m"); + //SY(__NR_getresgid32, x0, x0, x0); FAIL; + + // __NR_chown32 212 + //GO(__NR_chown32, "3s 1m"); + //SY(__NR_chown32, x0, x0, x0); FAIL; + + // __NR_setuid32 213 + //GO(__NR_setuid32, "1s 0m"); + //SY(__NR_setuid32, x0-1); FAIL; + + // __NR_setgid32 214 + //GO(__NR_setgid32, "1s 0m"); + //SY(__NR_setgid32, x0-1); FAIL; + + // __NR_setfsuid32 215 + //GO(__NR_setfsuid32, "1s 0m"); + //SY(__NR_setfsuid32, x0); SUCC; // This syscall has a stupid return value + + // __NR_setfsgid32 216 + //GO(__NR_setfsgid32, "1s 0m"); + //SY(__NR_setfsgid32, x0); SUCC; // This syscall has a stupid return value + + // __NR_pivot_root 217 + GO(__NR_pivot_root, "n/a"); + //SY(__NR_pivot_root); // (Not yet handled by Valgrind) FAIL; + + // __NR_mincore 218 + GO(__NR_mincore, "3s 1m"); + SY(__NR_mincore, x0, x0+40960, x0); FAIL; + + // __NR_madvise 219 + GO(__NR_madvise, "3s 0m"); + SY(__NR_madvise, x0, x0+1, x0); FAILx(ENOMEM); + + // __NR_getdents64 220 + GO(__NR_getdents64, "3s 1m"); + SY(__NR_getdents64, x0, x0, x0+1); FAIL; + + // __NR_fcntl64 221 + // As with sys_open(), we don't trigger errors for the 1st two args for + // the later ones. + // For F_GETFD the 3rd arg is ignored. + //GO(__NR_fcntl64, "(GETFD) 2s 0m"); + //SY(__NR_fcntl64, x0-1, x0+F_GETFD, x0); FAILx(EBADF); + + // For F_DUPFD the 3rd arg is 'arg' + //GO(__NR_fcntl64, "(DUPFD) 1s 0m"); + //SY(__NR_fcntl64, -1, F_DUPFD, x0); FAILx(EBADF); + + // For F_GETLK the 3rd arg is 'lock'. + // On x86, this fails w/EBADF. But on amd64 in 32-bit mode it fails + // w/EFAULT. + //GO(__NR_fcntl64, "(GETLK) 1s 0m"); + //SY(__NR_fcntl64, -1, +F_GETLK, x0); FAIL; //FAILx(EBADF); + + // 222 + GO(222, "ni"); + SY(222); FAIL; + + // 223 + GO(223, "ni"); + SY(223); FAIL; + + // __NR_gettid 224 + GO(__NR_gettid, "n/a"); + //SY(__NR_gettid); // (Not yet handled by Valgrind) FAIL; + + // __NR_readahead 225 + GO(__NR_readahead, "n/a"); + //SY(__NR_readahead); // (Not yet handled by Valgrind) FAIL; + + // __NR_setxattr 226 + GO(__NR_setxattr, "5s 3m"); + SY(__NR_setxattr, x0, x0, x0, x0+1, x0); FAIL; + + // __NR_lsetxattr 227 + GO(__NR_lsetxattr, "5s 3m"); + SY(__NR_lsetxattr, x0, x0, x0, x0+1, x0); FAIL; + + // __NR_fsetxattr 228 + GO(__NR_fsetxattr, "5s 2m"); + SY(__NR_fsetxattr, x0, x0, x0, x0+1, x0); FAIL; + + // __NR_getxattr 229 + GO(__NR_getxattr, "4s 3m"); + SY(__NR_getxattr, x0, x0, x0, x0+1); FAIL; + + // __NR_lgetxattr 230 + GO(__NR_lgetxattr, "4s 3m"); + SY(__NR_lgetxattr, x0, x0, x0, x0+1); FAIL; + + // __NR_fgetxattr 231 + GO(__NR_fgetxattr, "4s 2m"); + SY(__NR_fgetxattr, x0, x0, x0, x0+1); FAIL; + + // __NR_listxattr 232 + GO(__NR_listxattr, "3s 2m"); + SY(__NR_listxattr, x0, x0, x0+1); FAIL; + + // __NR_llistxattr 233 + GO(__NR_llistxattr, "3s 2m"); + SY(__NR_llistxattr, x0, x0, x0+1); FAIL; + + // __NR_flistxattr 234 + GO(__NR_flistxattr, "3s 1m"); + SY(__NR_flistxattr, x0-1, x0, x0+1); FAIL; /* kernel returns EBADF, but both seem correct */ + + // __NR_removexattr 235 + GO(__NR_removexattr, "2s 2m"); + SY(__NR_removexattr, x0, x0); FAIL; + + // __NR_lremovexattr 236 + GO(__NR_lremovexattr, "2s 2m"); + SY(__NR_lremovexattr, x0, x0); FAIL; + + // __NR_fremovexattr 237 + GO(__NR_fremovexattr, "2s 1m"); + SY(__NR_fremovexattr, x0, x0); FAIL; + + // __NR_tkill 238 + GO(__NR_tkill, "n/a"); + //SY(__NR_tkill); // (Not yet handled by Valgrind) FAIL; + + // __NR_sendfile64 239 + //GO(__NR_sendfile64, "4s 1m"); + //SY(__NR_sendfile64, x0, x0, x0+1, x0); FAIL; + + // __NR_futex 240 +#ifndef FUTEX_WAIT +#define FUTEX_WAIT 0 +#endif + // XXX: again, glibc not doing 6th arg means we have only 5s errors + GO(__NR_futex, "4s 2m"); + SY(__NR_futex, x0+FUTEX_WAIT, x0, x0, x0+1); FAIL; + + // __NR_sched_setaffinity 241 + GO(__NR_sched_setaffinity, "3s 1m"); + SY(__NR_sched_setaffinity, x0, x0+1, x0); FAIL; + + // __NR_sched_getaffinity 242 + GO(__NR_sched_getaffinity, "3s 1m"); + SY(__NR_sched_getaffinity, x0, x0+1, x0); FAIL; + + // __NR_set_thread_area 243 + //GO(__NR_set_thread_area, "1s 1m"); + //SY(__NR_set_thread_area, x0); FAILx(EFAULT); + + // __NR_get_thread_area 244 + //GO(__NR_get_thread_area, "1s 1m"); + //SY(__NR_get_thread_area, x0); FAILx(EFAULT); + + // __NR_io_setup 245 + GO(__NR_io_setup, "2s 1m"); + SY(__NR_io_setup, x0, x0); FAIL; + + // __NR_io_destroy 246 + { + // jump through hoops to prevent the PRE(io_destroy) wrapper crashing. + struct fake_aio_ring { + unsigned id; /* kernel internal index number */ + unsigned nr; /* number of io_events */ + // There are more fields in the real aio_ring, but the 'nr' field is + // the only one used by the PRE() wrapper. + } ring = { 0, 0 }; + struct fake_aio_ring* ringptr = ˚ + GO(__NR_io_destroy, "1s 0m"); + SY(__NR_io_destroy, x0+&ringptr); FAIL; + } + + // __NR_io_getevents 247 + GO(__NR_io_getevents, "5s 2m"); + SY(__NR_io_getevents, x0, x0, x0+1, x0, x0+1); FAIL; + + // __NR_io_submit 248 + GO(__NR_io_submit, "3s 1m"); + SY(__NR_io_submit, x0, x0+1, x0); FAIL; + + // __NR_io_cancel 249 + GO(__NR_io_cancel, "3s 2m"); + SY(__NR_io_cancel, x0, x0, x0); FAIL; + + // __NR_fadvise64 250 + GO(__NR_fadvise64, "n/a"); + //SY(__NR_fadvise64); // (Not yet handled by Valgrind) FAIL; + + // 251 + GO(251, "ni"); + SY(251); FAIL; + + // __NR_exit_group 252 + GO(__NR_exit_group, "other"); + // (see scalar_exit_group.c) + + // __NR_lookup_dcookie 253 + GO(__NR_lookup_dcookie, "4s 1m"); + SY(__NR_lookup_dcookie, x0, x0, x0, x0+1); FAIL; + + // __NR_epoll_create 254 + //GO(__NR_epoll_create, "1s 0m"); + //SY(__NR_epoll_create, x0); SUCC_OR_FAIL; + + // __NR_epoll_ctl 255 + GO(__NR_epoll_ctl, "4s 1m"); + SY(__NR_epoll_ctl, x0, x0, x0, x0); FAIL; + + // __NR_epoll_wait 256 + //GO(__NR_epoll_wait, "4s 1m"); + //SY(__NR_epoll_wait, x0, x0, x0+1, x0); FAIL; + + // __NR_remap_file_pages 257 + GO(__NR_remap_file_pages, "n/a"); + //SY(__NR_remap_file_pages); // (Not yet handled by Valgrind) FAIL; + + // __NR_set_tid_address 258 + GO(__NR_set_tid_address, "1s 0m"); + SY(__NR_set_tid_address, x0); SUCC_OR_FAILx(ENOSYS); + + // __NR_timer_create 259 + GO(__NR_timer_create, "3s 2m"); + SY(__NR_timer_create, x0, x0+1, x0); FAIL; + + // __NR_timer_settime (__NR_timer_create+1) + GO(__NR_timer_settime, "4s 2m"); + SY(__NR_timer_settime, x0, x0, x0, x0+1); FAIL; + + // __NR_timer_gettime (__NR_timer_create+2) + GO(__NR_timer_gettime, "2s 1m"); + SY(__NR_timer_gettime, x0, x0); FAIL; + + // __NR_timer_getoverrun (__NR_timer_create+3) + GO(__NR_timer_getoverrun, "1s 0m"); + SY(__NR_timer_getoverrun, x0); FAIL; + + // __NR_timer_delete (__NR_timer_create+4) + GO(__NR_timer_delete, "1s 0m"); + SY(__NR_timer_delete, x0); FAIL; + + // __NR_clock_settime (__NR_timer_create+5) + GO(__NR_clock_settime, "2s 1m"); + SY(__NR_clock_settime, x0, x0); FAIL; FAIL; + + // __NR_clock_gettime (__NR_timer_create+6) + GO(__NR_clock_gettime, "2s 1m"); + SY(__NR_clock_gettime, x0, x0); FAIL; + + // __NR_clock_getres (__NR_timer_create+7) + GO(__NR_clock_getres, "2s 1m"); + SY(__NR_clock_getres, x0+1, x0+1); FAIL; FAIL; + + // __NR_clock_nanosleep (__NR_timer_create+8) + GO(__NR_clock_nanosleep, "n/a"); + //SY(__NR_clock_nanosleep); // (Not yet handled by Valgrind) FAIL; + + // __NR_statfs64 268 + //GO(__NR_statfs64, "3s 2m"); + //SY(__NR_statfs64, x0, x0+1, x0); FAIL; + + // __NR_fstatfs64 269 + //GO(__NR_fstatfs64, "3s 1m"); + //SY(__NR_fstatfs64, x0, x0+1, x0); FAIL; + + // __NR_tgkill 270 + GO(__NR_tgkill, "n/a"); + //SY(__NR_tgkill); // (Not yet handled by Valgrind) FAIL; + + // __NR_utimes 271 + //GO(__NR_utimes, "2s 2m"); + //SY(__NR_utimes, x0, x0+1); FAIL; + + // __NR_fadvise64_64 272 + //GO(__NR_fadvise64_64, "n/a"); + //SY(__NR_fadvise64_64); // (Not yet handled by Valgrind) FAIL; + + // __NR_vserver 273 + //GO(__NR_vserver, "ni"); + //SY(__NR_vserver); FAIL; + + // __NR_mbind 274 + GO(__NR_mbind, "n/a"); + //SY(__NR_mbind); // (Not yet handled by Valgrind) FAIL; + + // __NR_get_mempolicy 275 + GO(__NR_get_mempolicy, "n/a"); + //SY(__NR_get_mempolicy); // (Not yet handled by Valgrind) FAIL; + + // __NR_set_mempolicy 276 + GO(__NR_set_mempolicy, "n/a"); + //SY(__NR_set_mempolicy); // (Not yet handled by Valgrind) FAIL; + + // __NR_mq_open 277 + GO(__NR_mq_open, "4s 3m"); + SY(__NR_mq_open, x0, x0+O_CREAT, x0, x0+1); FAIL; + + // __NR_mq_unlink (__NR_mq_open+1) + GO(__NR_mq_unlink, "1s 1m"); + SY(__NR_mq_unlink, x0); FAIL; + + // __NR_mq_timedsend (__NR_mq_open+2) + GO(__NR_mq_timedsend, "5s 2m"); + SY(__NR_mq_timedsend, x0, x0, x0+1, x0, x0+1); FAIL; + + // __NR_mq_timedreceive (__NR_mq_open+3) + GO(__NR_mq_timedreceive, "5s 3m"); + SY(__NR_mq_timedreceive, x0, x0, x0+1, x0+1, x0+1); FAIL; + + // __NR_mq_notify (__NR_mq_open+4) + GO(__NR_mq_notify, "2s 1m"); + SY(__NR_mq_notify, x0, x0+1); FAIL; + + // __NR_mq_getsetattr (__NR_mq_open+5) + GO(__NR_mq_getsetattr, "3s 2m"); + SY(__NR_mq_getsetattr, x0, x0+1, x0+1); FAIL; + + // __NR_sys_kexec_load 283 + //GO(__NR_sys_kexec_load, "ni"); + //SY(__NR_sys_kexec_load); FAIL; + + // __NR_epoll_create1 329 + GO(__NR_epoll_create1, "1s 0m"); + SY(__NR_epoll_create1, x0); SUCC_OR_FAIL; + + // __NR_process_vm_readv 347 + GO(__NR_process_vm_readv, "6s 2m"); + SY(__NR_process_vm_readv, x0, x0, x0+1, x0, x0+1, x0); FAIL; + + // __NR_process_vm_writev 348 + GO(__NR_process_vm_writev, "6s 2m"); + SY(__NR_process_vm_writev, x0, x0, x0+1, x0, x0+1, x0); FAIL; + + // no such syscall... + GO(9999, "1e"); + SY(9999); FAIL; + + // __NR_exit 1 + GO(__NR_exit, "1s 0m"); + SY(__NR_exit, x0); FAIL; + + assert(0); +} diff --git a/memcheck/tests/loongarch64-linux/scalar.h b/memcheck/tests/loongarch64-linux/scalar.h new file mode 100644 index 0000000..4d86d2c --- /dev/null +++ b/memcheck/tests/loongarch64-linux/scalar.h @@ -0,0 +1,62 @@ +/* This is the loongarch64 variant of memcheck/tests/x86-linux/scalar.h */ +#include "../../../include/vki/vki-scnums-loongarch64-linux.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// Since we use vki_unistd.h, we can't include . So we have to +// declare this ourselves. +extern long int syscall (long int __sysno, ...) __THROW; + +// Thorough syscall scalar arg checking. Also serves as thorough checking +// for (very) basic syscall use. Generally not trying to do anything +// meaningful with the syscalls. + +#define GO(__NR_xxx, s) \ + fprintf(stderr, "-----------------------------------------------------\n" \ + "%3d:%20s %s\n" \ + "-----------------------------------------------------\n", \ + __NR_xxx, #__NR_xxx, s); + +#define SY res = syscall + +#define FAIL assert(-1 == res); +#define SUCC assert(-1 != res); +#define SUCC_OR_FAIL /* no test */ + +#define FAILx(E) \ + do { \ + int myerrno = errno; \ + if (-1 == res) { \ + if (E == myerrno) { \ + /* as expected */ \ + } else { \ + fprintf(stderr, "Expected error %s (%d), got %d\n", #E, E, myerrno); \ + exit(1); \ + } \ + } else { \ + fprintf(stderr, "Expected error %s (%d), got success\n", #E, E); \ + exit(1); \ + } \ + } while (0); + +#define SUCC_OR_FAILx(E) \ + do { \ + int myerrno = errno; \ + if (-1 == res) { \ + if (E == myerrno) { \ + /* as expected */ \ + } else { \ + fprintf(stderr, "Expected error %s (%d), got %d\n", #E, E, myerrno); \ + exit(1); \ + } \ + } \ + } while (0); diff --git a/memcheck/tests/loongarch64-linux/scalar.stderr.exp b/memcheck/tests/loongarch64-linux/scalar.stderr.exp new file mode 100644 index 0000000..a90b90a --- /dev/null +++ b/memcheck/tests/loongarch64-linux/scalar.stderr.exp @@ -0,0 +1,2716 @@ +----------------------------------------------------- +128:__NR_restart_syscall n/a +----------------------------------------------------- +----------------------------------------------------- + 93: __NR_exit below +----------------------------------------------------- +----------------------------------------------------- + 63: __NR_read 1+3s 1m +----------------------------------------------------- +Syscall param (syscallno) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:51) + +Syscall param read(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:51) + +Syscall param read(buf) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:51) + +Syscall param read(count) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:51) + +Syscall param read(buf) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:51) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 64: __NR_write 3s 1m +----------------------------------------------------- +Syscall param write(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:55) + +Syscall param write(buf) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:55) + +Syscall param write(count) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:55) + +Syscall param write(buf) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:55) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 57: __NR_close 1s 0m +----------------------------------------------------- +Syscall param close(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:69) + +----------------------------------------------------- +221: __NR_execve 3s 1m +----------------------------------------------------- +Syscall param execve(filename) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:89) + +Syscall param execve(argv) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:89) + +Syscall param execve(envp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:89) + +Syscall param execve(filename) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:89) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param execve(argv) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:89) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +221: __NR_execve 3s 1m +----------------------------------------------------- +Syscall param execve(filename) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:92) + +Syscall param execve(argv) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:92) + +Syscall param execve(envp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:92) + +Syscall param execve(filename) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:92) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param execve(argv) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:92) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +221: __NR_execve 4s 2m +----------------------------------------------------- +Syscall param execve(filename) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:96) + +Syscall param execve(argv) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:96) + +Syscall param execve(envp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:96) + +Syscall param execve(filename) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:96) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param execve(argv) points to uninitialised byte(s) + ... + by 0x........: main (scalar.c:96) + Address 0x........ is on thread 1's stack + in frame #1, created by main (scalar.c:28) + +Syscall param execve(argv[0]) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:96) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +221: __NR_execve 4s 2m +----------------------------------------------------- +Syscall param execve(filename) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:99) + +Syscall param execve(argv) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:99) + +Syscall param execve(envp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:99) + +Syscall param execve(filename) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:99) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param execve(envp) points to uninitialised byte(s) + ... + by 0x........: main (scalar.c:99) + Address 0x........ is on thread 1's stack + in frame #1, created by main (scalar.c:28) + +Syscall param execve(envp[i]) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:99) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 49: __NR_chdir 1s 1m +----------------------------------------------------- +Syscall param chdir(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:103) + +Syscall param chdir(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:103) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 62: __NR_lseek 3s 0m +----------------------------------------------------- +Syscall param lseek(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:131) + +Syscall param lseek(offset) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:131) + +Syscall param lseek(whence) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:131) + +----------------------------------------------------- +172: __NR_getpid 0s 0m +----------------------------------------------------- +----------------------------------------------------- + 40: __NR_mount 5s 3m +----------------------------------------------------- +Syscall param mount(source) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:139) + +Syscall param mount(target) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:139) + +Syscall param mount(type) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:139) + +Syscall param mount(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:139) + +Syscall param mount(data) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:139) + +Syscall param mount(target) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:139) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param mount(type) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:139) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +146: __NR_setuid 1s 0m +----------------------------------------------------- +Syscall param setuid(uid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:147) + +----------------------------------------------------- +174: __NR_getuid 0s 0m +----------------------------------------------------- +----------------------------------------------------- + 81: __NR_sync 0s 0m +----------------------------------------------------- +----------------------------------------------------- +129: __NR_kill 2s 0m +----------------------------------------------------- +Syscall param kill(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:204) + +Syscall param kill(signal) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:204) + +----------------------------------------------------- + 23: __NR_dup 1s 0m +----------------------------------------------------- +Syscall param dup(oldfd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:220) + +----------------------------------------------------- +153: __NR_times 1s 1m +----------------------------------------------------- +Syscall param times(buf) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:228) + +Syscall param times(buf) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:228) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +214: __NR_brk 1s 0m +----------------------------------------------------- +Syscall param brk(end_data_segment) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:236) + +----------------------------------------------------- +144: __NR_setgid 1s 0m +----------------------------------------------------- +Syscall param setgid(gid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:240) + +----------------------------------------------------- +176: __NR_getgid 0s 0m +----------------------------------------------------- +----------------------------------------------------- +175: __NR_geteuid 0s 0m +----------------------------------------------------- +----------------------------------------------------- +177: __NR_getegid 0s 0m +----------------------------------------------------- +----------------------------------------------------- + 89: __NR_acct 1s 1m +----------------------------------------------------- +Syscall param acct(filename) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:260) + +Syscall param acct(filename) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:260) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 39: __NR_umount2 2s 1m +----------------------------------------------------- +Syscall param umount2(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:264) + +Syscall param umount2(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:264) + +Syscall param umount2(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:264) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 29: __NR_ioctl 3s 1m +----------------------------------------------------- +Syscall param ioctl(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:273) + +Syscall param ioctl(request) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:273) + +Syscall param ioctl(arg) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:273) + +Syscall param ioctl(TCSET{S,SW,SF}) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:273) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 25: __NR_fcntl (GETFD) 2s 0m +----------------------------------------------------- +Syscall param fcntl(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:279) + +Syscall param fcntl(cmd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:279) + +----------------------------------------------------- + 25: __NR_fcntl (DUPFD) 1s 0m +----------------------------------------------------- +Syscall param fcntl(arg) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:285) + +----------------------------------------------------- + 25: __NR_fcntl (GETLK) 1s 5m +----------------------------------------------------- +Syscall param fcntl(lock) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:291) + +Syscall param fcntl(lock->l_type) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:291) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param fcntl(lock->l_whence) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:291) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param fcntl(lock->l_start) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:291) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param fcntl(lock->l_len) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:291) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param fcntl(lock->l_pid) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:291) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +154: __NR_setpgid 2s 0m +----------------------------------------------------- +Syscall param setpgid(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:299) + +Syscall param setpgid(pgid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:299) + +----------------------------------------------------- +166: __NR_umask 1s 0m +----------------------------------------------------- +Syscall param umask(mask) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:311) + +----------------------------------------------------- + 51: __NR_chroot 1s 1m +----------------------------------------------------- +Syscall param chroot(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:315) + +Syscall param chroot(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:315) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +173: __NR_getppid 0s 0m +----------------------------------------------------- +----------------------------------------------------- +157: __NR_setsid 0s 0m +----------------------------------------------------- +----------------------------------------------------- +145: __NR_setreuid 2s 0m +----------------------------------------------------- +Syscall param setreuid(ruid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:351) + +Syscall param setreuid(euid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:351) + +----------------------------------------------------- +143: __NR_setregid 2s 0m +----------------------------------------------------- +Syscall param setregid(rgid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:355) + +Syscall param setregid(egid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:355) + +----------------------------------------------------- +161: __NR_sethostname n/a +----------------------------------------------------- +----------------------------------------------------- +165: __NR_getrusage 2s 1m +----------------------------------------------------- +Syscall param getrusage(who) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:380) + +Syscall param getrusage(usage) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:380) + +Syscall param getrusage(usage) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:380) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +169: __NR_gettimeofday 2s 2m +----------------------------------------------------- +Syscall param gettimeofday(tv) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:384) + +Syscall param gettimeofday(tz) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:384) + +Syscall param gettimeofday(tv) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:384) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param gettimeofday(tz) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:384) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +170: __NR_settimeofday 2s 2m +----------------------------------------------------- +Syscall param settimeofday(tv) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:388) + +Syscall param settimeofday(tz) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:388) + +Syscall param settimeofday(tv) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:388) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param settimeofday(tz) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:388) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +158: __NR_getgroups 2s 1m +----------------------------------------------------- +Syscall param getgroups(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:392) + +Syscall param getgroups(list) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:392) + +Syscall param getgroups(list) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:392) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +159: __NR_setgroups 2s 1m +----------------------------------------------------- +Syscall param setgroups(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:396) + +Syscall param setgroups(list) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:396) + +Syscall param setgroups(list) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:396) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +224: __NR_swapon n/a +----------------------------------------------------- +----------------------------------------------------- +142: __NR_reboot n/a +----------------------------------------------------- +----------------------------------------------------- +222: __NR_mmap 1s 1m +----------------------------------------------------- +Syscall param mmap(addr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:437) + +----------------------------------------------------- +215: __NR_munmap 2s 0m +----------------------------------------------------- +Syscall param munmap(start) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:442) + +Syscall param munmap(length) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:442) + +----------------------------------------------------- + 45: __NR_truncate 2s 1m +----------------------------------------------------- +Syscall param truncate(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:446) + + +More than 100 errors detected. Subsequent errors +will still be recorded, but in less detail than before. +Syscall param truncate(length) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:446) + +Syscall param truncate(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:446) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 46: __NR_ftruncate 2s 0m +----------------------------------------------------- +Syscall param ftruncate(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:450) + +Syscall param ftruncate(length) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:450) + +----------------------------------------------------- + 52: __NR_fchmod 2s 0m +----------------------------------------------------- +Syscall param fchmod(fildes) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:454) + +Syscall param fchmod(mode) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:454) + +----------------------------------------------------- + 55: __NR_fchown 3s 0m +----------------------------------------------------- +Syscall param fchown(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:458) + +Syscall param fchown(owner) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:458) + +Syscall param fchown(group) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:458) + +----------------------------------------------------- +141: __NR_getpriority 2s 0m +----------------------------------------------------- +Syscall param getpriority(which) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:462) + +Syscall param getpriority(who) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:462) + +----------------------------------------------------- +140: __NR_setpriority 3s 0m +----------------------------------------------------- +Syscall param setpriority(which) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:466) + +Syscall param setpriority(who) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:466) + +Syscall param setpriority(prio) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:466) + +----------------------------------------------------- + 43: __NR_statfs 2s 2m +----------------------------------------------------- +Syscall param statfs(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:474) + +Syscall param statfs(buf) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:474) + +Syscall param statfs(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:474) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param statfs(buf) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:474) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 44: __NR_fstatfs 2s 1m +----------------------------------------------------- +Syscall param fstatfs(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:478) + +Syscall param fstatfs(buf) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:478) + +Syscall param fstatfs(buf) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:478) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +116: __NR_syslog 3s 1m +----------------------------------------------------- +Syscall param syslog(type) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:490) + +Syscall param syslog(bufp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:490) + +Syscall param syslog(len) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:490) + +Syscall param syslog(bufp) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:490) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +103: __NR_setitimer 3s 2m +----------------------------------------------------- +Syscall param setitimer(which) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:494) + +Syscall param setitimer(value) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:494) + +Syscall param setitimer(ovalue) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:494) + +Syscall param setitimer(&value->it_interval) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:494) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param setitimer(&value->it_value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:494) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param setitimer(&ovalue->it_interval) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:494) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param setitimer(&ovalue->it_value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:494) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +102: __NR_getitimer 2s 1m +----------------------------------------------------- +Syscall param getitimer(which) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:498) + +Syscall param getitimer(value) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:498) + +Syscall param getitimer(&value->it_interval) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:498) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param getitimer(&value->it_value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:498) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 58: __NR_vhangup 0s 0m +----------------------------------------------------- +----------------------------------------------------- +260: __NR_wait4 4s 2m +----------------------------------------------------- +Syscall param wait4(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:534) + +Syscall param wait4(status) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:534) + +Syscall param wait4(options) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:534) + +Syscall param wait4(rusage) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:534) + +Syscall param wait4(status) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:534) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param wait4(rusage) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:534) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +225: __NR_swapoff n/a +----------------------------------------------------- +----------------------------------------------------- +179: __NR_sysinfo 1s 1m +----------------------------------------------------- +Syscall param sysinfo(info) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:542) + +Syscall param sysinfo(info) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:542) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 82: __NR_fsync 1s 0m +----------------------------------------------------- +Syscall param fsync(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:553) + +----------------------------------------------------- +220: __NR_clone 5s 3m +----------------------------------------------------- +Syscall param clone(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:564) + +Syscall param clone(child_stack) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:564) + +Syscall param clone(parent_tidptr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:564) + +Syscall param clone(parent_tidptr) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:564) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param clone(tlsinfo) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:564) + +Syscall param clone(child_tidptr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:564) + +Syscall param clone(child_tidptr) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:564) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +162: __NR_setdomainname n/a +----------------------------------------------------- +----------------------------------------------------- +160: __NR_uname 1s 1m +----------------------------------------------------- +Syscall param uname(buf) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:575) + +Syscall param uname(buf) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:575) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +171: __NR_adjtimex XXX +----------------------------------------------------- +----------------------------------------------------- +226: __NR_mprotect 3s 0m +----------------------------------------------------- +Syscall param mprotect(addr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:588) + +Syscall param mprotect(len) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:588) + +Syscall param mprotect(prot) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:588) + +----------------------------------------------------- +105: __NR_init_module 3s 2m +----------------------------------------------------- +Syscall param init_module(umod) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:600) + +Syscall param init_module(len) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:600) + +Syscall param init_module(uargs) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:600) + +Syscall param init_module(umod) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:600) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param init_module(uargs) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:600) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +106: __NR_delete_module n/a +----------------------------------------------------- +----------------------------------------------------- + 60: __NR_quotactl 4s 1m +----------------------------------------------------- +Syscall param quotactl(cmd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:612) + +Syscall param quotactl(special) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:612) + +Syscall param quotactl(id) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:612) + +Syscall param quotactl(addr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:612) + +Syscall param quotactl(special) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:612) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +155: __NR_getpgid 1s 0m +----------------------------------------------------- +Syscall param getpgid(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:616) + +----------------------------------------------------- + 50: __NR_fchdir 1s 0m +----------------------------------------------------- +Syscall param fchdir(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:620) + +----------------------------------------------------- + 92: __NR_personality 1s 0m +----------------------------------------------------- +Syscall param personality(persona) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:632) + +----------------------------------------------------- +151: __NR_setfsuid 1s 0m +----------------------------------------------------- +Syscall param setfsuid(uid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:640) + +----------------------------------------------------- +152: __NR_setfsgid 1s 0m +----------------------------------------------------- +Syscall param setfsgid(gid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:644) + +----------------------------------------------------- + 32: __NR_flock 2s 0m +----------------------------------------------------- +Syscall param flock(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:660) + +Syscall param flock(operation) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:660) + +----------------------------------------------------- +227: __NR_msync 3s 1m +----------------------------------------------------- +Syscall param msync(start) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:664) + +Syscall param msync(length) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:664) + +Syscall param msync(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:664) + +Syscall param msync(start) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:664) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 65: __NR_readv 3s 1m +----------------------------------------------------- +Syscall param readv(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:668) + +Syscall param readv(vector) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:668) + +Syscall param readv(count) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:668) + +Syscall param readv(vector) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:668) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 66: __NR_writev 3s 1m +----------------------------------------------------- +Syscall param writev(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:672) + +Syscall param writev(vector) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:672) + +Syscall param writev(count) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:672) + +Syscall param writev(vector) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:672) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +156: __NR_getsid 1s 0m +----------------------------------------------------- +Syscall param getsid(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:676) + +----------------------------------------------------- + 83: __NR_fdatasync 1s 0m +----------------------------------------------------- +Syscall param fdatasync(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:680) + +----------------------------------------------------- +228: __NR_mlock 2s 0m +----------------------------------------------------- +Syscall param mlock(addr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:688) + +Syscall param mlock(len) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:688) + +----------------------------------------------------- +229: __NR_munlock 2s 0m +----------------------------------------------------- +Syscall param munlock(addr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:692) + +Syscall param munlock(len) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:692) + +----------------------------------------------------- +230: __NR_mlockall 1s 0m +----------------------------------------------------- +Syscall param mlockall(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:696) + +----------------------------------------------------- +231: __NR_munlockall 0s 0m +----------------------------------------------------- +----------------------------------------------------- +118: __NR_sched_setparam 2s 1m +----------------------------------------------------- +Syscall param sched_setparam(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:704) + +Syscall param sched_setparam(p) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:704) + +Syscall param sched_setparam(p) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:704) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +121: __NR_sched_getparam 2s 1m +----------------------------------------------------- +Syscall param sched_getparam(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:708) + +Syscall param sched_getparam(p) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:708) + +Syscall param sched_getparam(p) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:708) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +119:__NR_sched_setscheduler 3s 1m +----------------------------------------------------- +Syscall param sched_setscheduler(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:712) + +Syscall param sched_setscheduler(policy) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:712) + +Syscall param sched_setscheduler(p) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:712) + +Syscall param sched_setscheduler(p) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:712) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +120:__NR_sched_getscheduler 1s 0m +----------------------------------------------------- +Syscall param sched_getscheduler(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:716) + +----------------------------------------------------- +124: __NR_sched_yield 0s 0m +----------------------------------------------------- +----------------------------------------------------- +125:__NR_sched_get_priority_max 1s 0m +----------------------------------------------------- +Syscall param sched_get_priority_max(policy) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:724) + +----------------------------------------------------- +126:__NR_sched_get_priority_min 1s 0m +----------------------------------------------------- +Syscall param sched_get_priority_min(policy) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:728) + +----------------------------------------------------- +127:__NR_sched_rr_get_interval n/a +----------------------------------------------------- +----------------------------------------------------- +101: __NR_nanosleep 2s 2m +----------------------------------------------------- +Syscall param nanosleep(req) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:736) + +Syscall param nanosleep(rem) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:736) + +Syscall param nanosleep(req) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:736) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param nanosleep(rem) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:736) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +216: __NR_mremap 5s 0m +----------------------------------------------------- +Syscall param mremap(old_addr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:740) + +Syscall param mremap(old_size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:740) + +Syscall param mremap(new_size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:740) + +Syscall param mremap(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:740) + +Syscall param mremap(new_addr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:740) + +----------------------------------------------------- +147: __NR_setresuid 3s 0m +----------------------------------------------------- +Syscall param setresuid(ruid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:744) + +Syscall param setresuid(euid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:744) + +Syscall param setresuid(suid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:744) + +----------------------------------------------------- +148: __NR_getresuid 3s 3m +----------------------------------------------------- +Syscall param getresuid(ruid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:748) + +Syscall param getresuid(euid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:748) + +Syscall param getresuid(suid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:748) + +Syscall param getresuid(ruid) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:748) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param getresuid(euid) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:748) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param getresuid(suid) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:748) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 42: __NR_nfsservctl n/a +----------------------------------------------------- +----------------------------------------------------- +149: __NR_setresgid 3s 0m +----------------------------------------------------- +Syscall param setresgid(rgid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:768) + +Syscall param setresgid(egid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:768) + +Syscall param setresgid(sgid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:768) + +----------------------------------------------------- +150: __NR_getresgid 3s 3m +----------------------------------------------------- +Syscall param getresgid(rgid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:772) + +Syscall param getresgid(egid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:772) + +Syscall param getresgid(sgid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:772) + +Syscall param getresgid(rgid) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:772) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param getresgid(egid) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:772) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param getresgid(sgid) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:772) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +167: __NR_prctl 5s 0m +----------------------------------------------------- +Syscall param prctl(option) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:777) + +Syscall param prctl(arg2) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:777) + +Syscall param prctl(arg3) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:777) + +Syscall param prctl(arg4) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:777) + +Syscall param prctl(arg5) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:777) + +----------------------------------------------------- +167: __NR_prctl 2s 0m +----------------------------------------------------- +Syscall param prctl(option) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:782) + +Syscall param prctl(set-name) points to uninitialised byte(s) + ... + by 0x........: main (scalar.c:782) + Address 0x........ is on thread 1's stack + in frame #1, created by main (scalar.c:28) + +----------------------------------------------------- +167: __NR_prctl 1s 0m +----------------------------------------------------- +Syscall param prctl(option) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:787) + +----------------------------------------------------- +139: __NR_rt_sigreturn n/a +----------------------------------------------------- +----------------------------------------------------- +134: __NR_rt_sigaction 4s 4m +----------------------------------------------------- +Syscall param rt_sigaction(signum) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:795) + +Syscall param rt_sigaction(act) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:795) + +Syscall param rt_sigaction(oldact) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:795) + +Syscall param rt_sigaction(sigsetsize) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:795) + +Syscall param rt_sigaction(act->sa_handler) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:795) + Address 0x........ is 8 bytes after a block of size 8 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (scalar.c:30) + +Syscall param rt_sigaction(act->sa_mask) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:795) + Address 0x........ is 16 bytes after a block of size 16 in arena "client" + +Syscall param rt_sigaction(act->sa_flags) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:795) + Address 0x........ is 16 bytes after a block of size 8 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (scalar.c:30) + +Syscall param rt_sigaction(oldact) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:795) + Address 0x........ is 8 bytes after a block of size 8 alloc'd + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (scalar.c:30) + +----------------------------------------------------- +135: __NR_rt_sigprocmask 4s 2m +----------------------------------------------------- +Syscall param rt_sigprocmask(how) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:799) + +Syscall param rt_sigprocmask(set) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:799) + +Syscall param rt_sigprocmask(oldset) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:799) + +Syscall param rt_sigprocmask(sigsetsize) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:799) + +Syscall param rt_sigprocmask(set) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:799) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param rt_sigprocmask(oldset) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:799) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +136: __NR_rt_sigpending 2s 1m +----------------------------------------------------- +Syscall param rt_sigpending(set) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:803) + +Syscall param rt_sigpending(sigsetsize) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:803) + +Syscall param rt_sigpending(set) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:803) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +137:__NR_rt_sigtimedwait 4s 3m +----------------------------------------------------- +Syscall param rt_sigtimedwait(set) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:807) + +Syscall param rt_sigtimedwait(info) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:807) + +Syscall param rt_sigtimedwait(timeout) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:807) + +Syscall param rt_sigtimedwait(sigsetsize) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:807) + +Syscall param rt_sigtimedwait(set) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:807) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param rt_sigtimedwait(info) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:807) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param rt_sigtimedwait(timeout) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:807) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +138:__NR_rt_sigqueueinfo 3s 1m +----------------------------------------------------- +Syscall param rt_sigqueueinfo(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:811) + +Syscall param rt_sigqueueinfo(sig) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:811) + +Syscall param rt_sigqueueinfo(uinfo) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:811) + +Syscall param rt_sigqueueinfo(uinfo) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:811) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +133: __NR_rt_sigsuspend 2s 1m +----------------------------------------------------- +Syscall param rt_sigsuspend(mask) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:815) + +Syscall param rt_sigsuspend(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:815) + +Syscall param rt_sigsuspend(mask) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:815) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 67: __NR_pread64 5s 1m +----------------------------------------------------- +Syscall param pread64(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:819) + +Syscall param pread64(buf) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:819) + +Syscall param pread64(count) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:819) + +Syscall param pread64(offset) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:819) + +Syscall param pread64(buf) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:819) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 68: __NR_pwrite64 5s 1m +----------------------------------------------------- +Syscall param pwrite64(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:823) + +Syscall param pwrite64(buf) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:823) + +Syscall param pwrite64(count) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:823) + +Syscall param pwrite64(offset) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:823) + +Syscall param pwrite64(buf) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:823) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 17: __NR_getcwd 2s 1m +----------------------------------------------------- +Syscall param getcwd(buf) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:831) + +Syscall param getcwd(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:831) + +Syscall param getcwd(buf) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:831) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 90: __NR_capget 2s 2m +----------------------------------------------------- +Syscall param capget(header) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:835) + +Syscall param capget(data) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:835) + +Syscall param capget(header) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:835) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param capget(data) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:835) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 91: __NR_capset 2s 2m +----------------------------------------------------- +Syscall param capset(header) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:839) + +Syscall param capset(data) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:839) + +Syscall param capset(header) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:839) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param capset(data) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:839) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +132: __NR_sigaltstack 2s 2m +----------------------------------------------------- +Syscall param sigaltstack(ss) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:853) + +Syscall param sigaltstack(oss) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:853) + +Syscall param sigaltstack(ss) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:853) + Address 0x........ is on thread 1's stack + in frame #1, created by main (scalar.c:28) + +Syscall param sigaltstack(oss) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:853) + Address 0x........ is on thread 1's stack + in frame #1, created by main (scalar.c:28) + +----------------------------------------------------- + 71: __NR_sendfile 4s 1m +----------------------------------------------------- +Syscall param sendfile(out_fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:858) + +Syscall param sendfile(in_fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:858) + +Syscall param sendfile(offset) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:858) + +Syscall param sendfile(count) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:858) + +Syscall param sendfile(offset) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:858) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 41: __NR_pivot_root n/a +----------------------------------------------------- +----------------------------------------------------- +232: __NR_mincore 3s 1m +----------------------------------------------------- +Syscall param mincore(start) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:986) + +Syscall param mincore(length) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:986) + +Syscall param mincore(vec) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:986) + +Syscall param mincore(vec) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:986) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +233: __NR_madvise 3s 0m +----------------------------------------------------- +Syscall param madvise(start) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:990) + +Syscall param madvise(length) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:990) + +Syscall param madvise(advice) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:990) + +----------------------------------------------------- + 61: __NR_getdents64 3s 1m +----------------------------------------------------- +Syscall param getdents64(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:994) + +Syscall param getdents64(dirp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:994) + +Syscall param getdents64(count) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:994) + +Syscall param getdents64(dirp) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:994) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +222: 222 ni +----------------------------------------------------- +----------------------------------------------------- +223: 223 ni +----------------------------------------------------- +----------------------------------------------------- +178: __NR_gettid n/a +----------------------------------------------------- +----------------------------------------------------- +213: __NR_readahead n/a +----------------------------------------------------- +----------------------------------------------------- + 5: __NR_setxattr 5s 3m +----------------------------------------------------- +Syscall param setxattr(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1031) + +Syscall param setxattr(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1031) + +Syscall param setxattr(value) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1031) + +Syscall param setxattr(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1031) + +Syscall param setxattr(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1031) + +Syscall param setxattr(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1031) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param setxattr(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1031) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param setxattr(value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1031) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 6: __NR_lsetxattr 5s 3m +----------------------------------------------------- +Syscall param lsetxattr(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1035) + +Syscall param lsetxattr(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1035) + +Syscall param lsetxattr(value) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1035) + +Syscall param lsetxattr(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1035) + +Syscall param lsetxattr(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1035) + +Syscall param lsetxattr(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1035) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param lsetxattr(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1035) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param lsetxattr(value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1035) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 7: __NR_fsetxattr 5s 2m +----------------------------------------------------- +Syscall param fsetxattr(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1039) + +Syscall param fsetxattr(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1039) + +Syscall param fsetxattr(value) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1039) + +Syscall param fsetxattr(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1039) + +Syscall param fsetxattr(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1039) + +Syscall param fsetxattr(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1039) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param fsetxattr(value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1039) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 8: __NR_getxattr 4s 3m +----------------------------------------------------- +Syscall param getxattr(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1043) + +Syscall param getxattr(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1043) + +Syscall param getxattr(value) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1043) + +Syscall param getxattr(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1043) + +Syscall param getxattr(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1043) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param getxattr(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1043) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param getxattr(value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1043) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 9: __NR_lgetxattr 4s 3m +----------------------------------------------------- +Syscall param lgetxattr(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1047) + +Syscall param lgetxattr(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1047) + +Syscall param lgetxattr(value) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1047) + +Syscall param lgetxattr(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1047) + +Syscall param lgetxattr(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1047) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param lgetxattr(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1047) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param lgetxattr(value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1047) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 10: __NR_fgetxattr 4s 2m +----------------------------------------------------- +Syscall param fgetxattr(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1051) + +Syscall param fgetxattr(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1051) + +Syscall param fgetxattr(value) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1051) + +Syscall param fgetxattr(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1051) + +Syscall param fgetxattr(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1051) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param fgetxattr(value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1051) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 11: __NR_listxattr 3s 2m +----------------------------------------------------- +Syscall param listxattr(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1055) + +Syscall param listxattr(list) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1055) + +Syscall param listxattr(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1055) + +Syscall param listxattr(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1055) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param listxattr(list) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1055) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 12: __NR_llistxattr 3s 2m +----------------------------------------------------- +Syscall param llistxattr(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1059) + +Syscall param llistxattr(list) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1059) + +Syscall param llistxattr(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1059) + +Syscall param llistxattr(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1059) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param llistxattr(list) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1059) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 13: __NR_flistxattr 3s 1m +----------------------------------------------------- +Syscall param flistxattr(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1063) + +Syscall param flistxattr(list) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1063) + +Syscall param flistxattr(size) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1063) + +Syscall param flistxattr(list) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1063) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 14: __NR_removexattr 2s 2m +----------------------------------------------------- +Syscall param removexattr(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1067) + +Syscall param removexattr(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1067) + +Syscall param removexattr(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1067) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param removexattr(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1067) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 15: __NR_lremovexattr 2s 2m +----------------------------------------------------- +Syscall param lremovexattr(path) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1071) + +Syscall param lremovexattr(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1071) + +Syscall param lremovexattr(path) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1071) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param lremovexattr(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1071) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 16: __NR_fremovexattr 2s 1m +----------------------------------------------------- +Syscall param fremovexattr(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1075) + +Syscall param fremovexattr(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1075) + +Syscall param fremovexattr(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1075) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +130: __NR_tkill n/a +----------------------------------------------------- +----------------------------------------------------- + 98: __NR_futex 4s 2m +----------------------------------------------------- +Syscall param futex(futex) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1091) + +Syscall param futex(op) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1091) + +Syscall param futex(val) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1091) + +Syscall param futex(utime) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1091) + +Syscall param futex(futex) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1091) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param futex(timeout) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1091) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +122:__NR_sched_setaffinity 3s 1m +----------------------------------------------------- +Syscall param sched_setaffinity(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1095) + +Syscall param sched_setaffinity(len) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1095) + +Syscall param sched_setaffinity(mask) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1095) + +Syscall param sched_setaffinity(mask) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1095) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +123:__NR_sched_getaffinity 3s 1m +----------------------------------------------------- +Syscall param sched_getaffinity(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1099) + +Syscall param sched_getaffinity(len) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1099) + +Syscall param sched_getaffinity(mask) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1099) + +Syscall param sched_getaffinity(mask) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1099) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 0: __NR_io_setup 2s 1m +----------------------------------------------------- +Syscall param io_setup(nr_events) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1111) + +Syscall param io_setup(ctxp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1111) + +Syscall param io_setup(ctxp) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1111) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 1: __NR_io_destroy 1s 0m +----------------------------------------------------- +Syscall param io_destroy(ctx) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1124) + +----------------------------------------------------- + 4: __NR_io_getevents 5s 2m +----------------------------------------------------- +Syscall param io_getevents(ctx_id) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1129) + +Syscall param io_getevents(min_nr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1129) + +Syscall param io_getevents(nr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1129) + +Syscall param io_getevents(events) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1129) + +Syscall param io_getevents(timeout) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1129) + +Syscall param io_getevents(events) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1129) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param io_getevents(timeout) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1129) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 2: __NR_io_submit 3s 1m +----------------------------------------------------- +Syscall param io_submit(ctx_id) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1133) + +Syscall param io_submit(nr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1133) + +Syscall param io_submit(iocbpp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1133) + +Syscall param io_submit(iocbpp) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1133) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 3: __NR_io_cancel 3s 2m +----------------------------------------------------- +Syscall param io_cancel(ctx_id) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1137) + +Syscall param io_cancel(iocb) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1137) + +Syscall param io_cancel(result) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1137) + +Syscall param io_cancel(iocb) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1137) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param io_cancel(result) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1137) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +223: __NR_fadvise64 n/a +----------------------------------------------------- +----------------------------------------------------- +251: 251 ni +----------------------------------------------------- +WARNING: unhandled loongarch64-linux syscall: 251 +You may be able to write your own handler. +Read the file README_MISSING_SYSCALL_OR_IOCTL. +Nevertheless we consider this a bug. Please report +it at http://valgrind.org/support/bug_reports.html. +----------------------------------------------------- + 94: __NR_exit_group other +----------------------------------------------------- +----------------------------------------------------- + 18: __NR_lookup_dcookie 4s 1m +----------------------------------------------------- +Syscall param lookup_dcookie(cookie) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1153) + +Syscall param lookup_dcookie(buf) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1153) + +Syscall param lookup_dcookie(len) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1153) + +----------------------------------------------------- + 21: __NR_epoll_ctl 4s 1m +----------------------------------------------------- +Syscall param epoll_ctl(epfd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1161) + +Syscall param epoll_ctl(op) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1161) + +Syscall param epoll_ctl(fd) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1161) + +Syscall param epoll_ctl(event) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1161) + +Syscall param epoll_ctl(event) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1161) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +234:__NR_remap_file_pages n/a +----------------------------------------------------- +----------------------------------------------------- + 96:__NR_set_tid_address 1s 0m +----------------------------------------------------- +Syscall param set_tid_address(tidptr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1173) + +----------------------------------------------------- +107: __NR_timer_create 3s 2m +----------------------------------------------------- +Syscall param timer_create(clockid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1177) + +Syscall param timer_create(evp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1177) + +Syscall param timer_create(timerid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1177) + +Syscall param timer_create(evp.sigev_value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1177) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param timer_create(evp.sigev_signo) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1177) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param timer_create(evp.sigev_notify) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1177) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param timer_create(timerid) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1177) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +110: __NR_timer_settime 4s 2m +----------------------------------------------------- +Syscall param timer_settime(timerid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1181) + +Syscall param timer_settime(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1181) + +Syscall param timer_settime(value) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1181) + +Syscall param timer_settime(ovalue) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1181) + +Syscall param timer_settime(value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1181) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param timer_settime(ovalue) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1181) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +108: __NR_timer_gettime 2s 1m +----------------------------------------------------- +Syscall param timer_gettime(timerid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1185) + +Syscall param timer_gettime(value) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1185) + +Syscall param timer_gettime(value) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1185) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +109:__NR_timer_getoverrun 1s 0m +----------------------------------------------------- +Syscall param timer_getoverrun(timerid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1189) + +----------------------------------------------------- +111: __NR_timer_delete 1s 0m +----------------------------------------------------- +Syscall param timer_delete(timerid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1193) + +----------------------------------------------------- +112: __NR_clock_settime 2s 1m +----------------------------------------------------- +Syscall param clock_settime(clk_id) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1197) + +Syscall param clock_settime(tp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1197) + +Syscall param clock_settime(tp) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1197) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +113: __NR_clock_gettime 2s 1m +----------------------------------------------------- +Syscall param clock_gettime(clk_id) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1201) + +Syscall param clock_gettime(tp) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1201) + +Syscall param clock_gettime(tp) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1201) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +114: __NR_clock_getres 2s 1m +----------------------------------------------------- +Syscall param clock_getres(clk_id) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1205) + +Syscall param clock_getres(res) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1205) + +Syscall param clock_getres(res) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1205) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +115:__NR_clock_nanosleep n/a +----------------------------------------------------- +----------------------------------------------------- +131: __NR_tgkill n/a +----------------------------------------------------- +----------------------------------------------------- +235: __NR_mbind n/a +----------------------------------------------------- +----------------------------------------------------- +236: __NR_get_mempolicy n/a +----------------------------------------------------- +----------------------------------------------------- +237: __NR_set_mempolicy n/a +----------------------------------------------------- +----------------------------------------------------- +180: __NR_mq_open 4s 3m +----------------------------------------------------- +Syscall param mq_open(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1249) + +Syscall param mq_open(oflag) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1249) + +Syscall param mq_open(mode) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1249) + +Syscall param mq_open(attr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1249) + +Syscall param mq_open(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1249) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param mq_open(attr->mq_maxmsg) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1249) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param mq_open(attr->mq_msgsize) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1249) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +181: __NR_mq_unlink 1s 1m +----------------------------------------------------- +Syscall param mq_unlink(name) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1253) + +Syscall param mq_unlink(name) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1253) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +182: __NR_mq_timedsend 5s 2m +----------------------------------------------------- +Syscall param mq_timedsend(mqdes) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1257) + +Syscall param mq_timedsend(msg_ptr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1257) + +Syscall param mq_timedsend(msg_len) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1257) + +Syscall param mq_timedsend(msg_prio) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1257) + +Syscall param mq_timedsend(abs_timeout) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1257) + +Syscall param mq_timedsend(msg_ptr) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1257) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param mq_timedsend(abs_timeout) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1257) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +183:__NR_mq_timedreceive 5s 3m +----------------------------------------------------- +Syscall param mq_timedreceive(mqdes) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1261) + +Syscall param mq_timedreceive(msg_ptr) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1261) + +Syscall param mq_timedreceive(msg_len) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1261) + +Syscall param mq_timedreceive(msg_prio) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1261) + +Syscall param mq_timedreceive(abs_timeout) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1261) + +Syscall param mq_timedreceive(msg_ptr) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1261) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param mq_timedreceive(msg_prio) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1261) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param mq_timedreceive(abs_timeout) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1261) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +184: __NR_mq_notify 2s 1m +----------------------------------------------------- +Syscall param mq_notify(mqdes) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1265) + +Syscall param mq_notify(notification) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1265) + +Syscall param mq_notify(notification) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1265) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +185: __NR_mq_getsetattr 3s 2m +----------------------------------------------------- +Syscall param mq_getsetattr(mqdes) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1269) + +Syscall param mq_getsetattr(mqstat) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1269) + +Syscall param mq_getsetattr(omqstat) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1269) + +Syscall param mq_getsetattr(mqstat->mq_flags) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1269) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param mq_getsetattr(omqstat) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1269) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- + 20: __NR_epoll_create1 1s 0m +----------------------------------------------------- +Syscall param epoll_create1(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1277) + +----------------------------------------------------- +270:__NR_process_vm_readv 6s 2m +----------------------------------------------------- +Syscall param process_vm_readv(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1281) + +Syscall param process_vm_readv(lvec) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1281) + +Syscall param process_vm_readv(liovcnt) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1281) + +Syscall param process_vm_readv(rvec) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1281) + +Syscall param process_vm_readv(riovcnt) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1281) + +Syscall param process_vm_readv(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1281) + +Syscall param process_vm_readv(lvec) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1281) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param process_vm_readv(rvec) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1281) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +271:__NR_process_vm_writev 6s 2m +----------------------------------------------------- +Syscall param process_vm_writev(pid) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1285) + +Syscall param process_vm_writev(lvec) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1285) + +Syscall param process_vm_writev(liovcnt) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1285) + +Syscall param process_vm_writev(rvec) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1285) + +Syscall param process_vm_writev(riovcnt) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1285) + +Syscall param process_vm_writev(flags) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1285) + +Syscall param process_vm_writev(lvec) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1285) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param process_vm_writev(rvec) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:1285) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- +9999: 9999 1e +----------------------------------------------------- +WARNING: unhandled loongarch64-linux syscall: 9999 +You may be able to write your own handler. +Read the file README_MISSING_SYSCALL_OR_IOCTL. +Nevertheless we consider this a bug. Please report +it at http://valgrind.org/support/bug_reports.html. +----------------------------------------------------- + 93: __NR_exit 1s 0m +----------------------------------------------------- +Syscall param exit(status) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:1293) + diff --git a/memcheck/tests/loongarch64-linux/scalar.vgtest b/memcheck/tests/loongarch64-linux/scalar.vgtest new file mode 100644 index 0000000..53e87e8 --- /dev/null +++ b/memcheck/tests/loongarch64-linux/scalar.vgtest @@ -0,0 +1,5 @@ +prog: scalar +# Do not run under root +prereq: [ `id -u` -ne 0 ] +vgopts: -q --error-limit=no +args: < scalar.c diff --git a/memcheck/tests/mips32/Makefile.in b/memcheck/tests/mips32/Makefile.in index b20c604..01519ab 100644 --- a/memcheck/tests/mips32/Makefile.in +++ b/memcheck/tests/mips32/Makefile.in @@ -576,6 +576,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -623,6 +629,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/mips64/Makefile.in b/memcheck/tests/mips64/Makefile.in index c481d0e..138de75 100644 --- a/memcheck/tests/mips64/Makefile.in +++ b/memcheck/tests/mips64/Makefile.in @@ -576,6 +576,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -623,6 +629,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/ppc32/Makefile.in b/memcheck/tests/ppc32/Makefile.in index 615b1cd..92cd288 100644 --- a/memcheck/tests/ppc32/Makefile.in +++ b/memcheck/tests/ppc32/Makefile.in @@ -578,6 +578,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -625,6 +631,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/ppc64/Makefile.in b/memcheck/tests/ppc64/Makefile.in index 0d12344..84b272d 100644 --- a/memcheck/tests/ppc64/Makefile.in +++ b/memcheck/tests/ppc64/Makefile.in @@ -578,6 +578,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -625,6 +631,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/s390x/Makefile.in b/memcheck/tests/s390x/Makefile.in index 17cbd0c..af85cdb 100644 --- a/memcheck/tests/s390x/Makefile.in +++ b/memcheck/tests/s390x/Makefile.in @@ -610,6 +610,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -657,6 +663,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/solaris/Makefile.in b/memcheck/tests/solaris/Makefile.in index 52c57a1..34783f2 100644 --- a/memcheck/tests/solaris/Makefile.in +++ b/memcheck/tests/solaris/Makefile.in @@ -844,6 +844,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -891,6 +897,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/unit_libcbase.c b/memcheck/tests/unit_libcbase.c index 0ce65be..4803603 100644 --- a/memcheck/tests/unit_libcbase.c +++ b/memcheck/tests/unit_libcbase.c @@ -9,14 +9,14 @@ #include "pub_tool_vki.h" #include "m_libcbase.c" -/* On PPC, MIPS and ARM64 Linux VKI_PAGE_SIZE is a variable, not a macro. */ +/* On PPC, MIPS, ARM64 and LOONGARCH64 Linux VKI_PAGE_SIZE is a variable, not a macro. */ #if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ || defined(VGP_ppc64le_linux) unsigned long VKI_PAGE_SIZE = 1UL << 12; #elif defined(VGP_arm64_linux) unsigned long VKI_PAGE_SIZE = 1UL << 16; #elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ - || defined (VGP_nanomips_linux) + || defined (VGP_nanomips_linux) || defined(VGP_loongarch64_linux) #include unsigned long VKI_PAGE_SIZE; #endif diff --git a/memcheck/tests/vbit-test/Makefile.in b/memcheck/tests/vbit-test/Makefile.in index 5fef578..eeb4e09 100644 --- a/memcheck/tests/vbit-test/Makefile.in +++ b/memcheck/tests/vbit-test/Makefile.in @@ -627,6 +627,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -674,6 +680,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ EXTRA_DIST = vbit-test.vgtest vbit-test.stderr.exp \ diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c index 24f258b..89370f7 100644 --- a/memcheck/tests/vbit-test/irops.c +++ b/memcheck/tests/vbit-test/irops.c @@ -34,287 +34,297 @@ That is not necessary but helpful when supporting a new architecture. */ static irop_t irops[] = { - { DEFOP(Iop_Add8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Add16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Add32, UNDEF_INT_ADD), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Add64, UNDEF_INT_ADD), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_Sub8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Sub16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Sub32, UNDEF_INT_SUB), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Sub64, UNDEF_INT_SUB), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_Mul8, UNDEF_LEFT), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_Mul16, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_Mul32, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Mul64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_Or1, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Or8, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Or16, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Or32, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Or64, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_And1, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_And8, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_And16, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_And32, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_And64, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Xor8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Xor16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Xor32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Xor64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Shl8, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_Shl16, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_Shl32, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Shl64, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts - { DEFOP(Iop_Shr8, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert - { DEFOP(Iop_Shr16, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc32/64 assert - { DEFOP(Iop_Shr32, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Shr64, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts - { DEFOP(Iop_Sar8, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert - { DEFOP(Iop_Sar16, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc32/64 assert - { DEFOP(Iop_Sar32, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Sar64, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts - { DEFOP(Iop_CmpEQ8, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CmpEQ16, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_CmpEQ32, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_CmpEQ64, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_CmpNE8, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CmpNE16, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CmpNE32, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_CmpNE64, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_Not1, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Not8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Not16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Not32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Not64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CasCmpEQ8, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CasCmpEQ16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CasCmpEQ32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CasCmpEQ64, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_Add8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Add16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Add32, UNDEF_INT_ADD), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Add64, UNDEF_INT_ADD), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_Sub8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Sub16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Sub32, UNDEF_INT_SUB), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Sub64, UNDEF_INT_SUB), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32, mips assert + { DEFOP(Iop_Mul8, UNDEF_LEFT), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_Mul16, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_Mul32, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Mul64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 0 }, // ppc32, mips assert + { DEFOP(Iop_Or1, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Or8, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Or16, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Or32, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Or64, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_And1, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_And8, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_And16, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_And32, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_And64, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Xor8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Xor16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Xor32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Xor64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Shl8, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_Shl16, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_Shl32, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Shl64, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32 asserts + { DEFOP(Iop_Shr8, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // ppc32/64 assert + { DEFOP(Iop_Shr16, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, // ppc32/64 assert + { DEFOP(Iop_Shr32, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Shr64, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32 asserts + { DEFOP(Iop_Sar8, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // ppc32/64 assert + { DEFOP(Iop_Sar16, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, // ppc32/64 assert + { DEFOP(Iop_Sar32, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Sar64, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32 asserts + { DEFOP(Iop_CmpEQ8, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CmpEQ16, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_CmpEQ32, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_CmpEQ64, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32, mips assert + { DEFOP(Iop_CmpNE8, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CmpNE16, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CmpNE32, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_CmpNE64, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32, mips assert + { DEFOP(Iop_Not1, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Not8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Not16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_Not32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Not64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_CasCmpEQ8, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CasCmpEQ16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CasCmpEQ32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_CasCmpEQ64, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, - { DEFOP(Iop_CasCmpNE8, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CasCmpNE16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CasCmpNE32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CasCmpNE64, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_CasCmpNE8, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CasCmpNE16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CasCmpNE32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_CasCmpNE64, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, { DEFOP(Iop_ExpCmpNE8, UNDEF_UNKNOWN), }, // exact (expensive) equality { DEFOP(Iop_ExpCmpNE16, UNDEF_UNKNOWN), }, // exact (expensive) equality { DEFOP(Iop_ExpCmpNE32, UNDEF_UNKNOWN), }, // exact (expensive) equality { DEFOP(Iop_ExpCmpNE64, UNDEF_UNKNOWN), }, // exact (expensive) equality - { DEFOP(Iop_MullS8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_MullS16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_MullS32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts + { DEFOP(Iop_MullS8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_MullS16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_MullS32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts // s390 has signed multiplication of 64-bit values but the result // is 64-bit (not 128-bit). So we cannot test this op standalone. - { DEFOP(Iop_MullS64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_MullU8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, - { DEFOP(Iop_MullU16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, - { DEFOP(Iop_MullU32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_MullU64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32 asserts - { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, - { DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, - { DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, - { DEFOP(Iop_ClzNat64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts - { DEFOP(Iop_ClzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0 }, - { DEFOP(Iop_CtzNat64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, - { DEFOP(Iop_CtzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 1, .mips32 =0, .mips64 = 0 }, - { DEFOP(Iop_PopCount64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, - { DEFOP(Iop_PopCount32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0 }, - { DEFOP(Iop_CmpLT32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, - { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert - { DEFOP(Iop_CmpLE32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, - { DEFOP(Iop_CmpLE64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert - { DEFOP(Iop_CmpLT32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, - { DEFOP(Iop_CmpLT64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1}, // ppc32, mips assert - { DEFOP(Iop_CmpLE32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, - { DEFOP(Iop_CmpLE64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts + { DEFOP(Iop_MullS64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1, .loongarch64 = 1 }, // ppc32, mips assert + { DEFOP(Iop_MullU8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_MullU16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_MullU32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_MullU64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1, .loongarch64 = 1 }, // ppc32, mips assert + { DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1, .loongarch64 = 1 }, // ppc32 asserts + { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_ClzNat64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0, .loongarch64 = 0 }, // ppc32 asserts + { DEFOP(Iop_ClzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CtzNat64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CtzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 1, .mips32 =0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_PopCount64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_PopCount32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CmpLT32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1, .loongarch64 = 1 }, // ppc, mips assert + { DEFOP(Iop_CmpLE32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_CmpLE64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1, .loongarch64 = 1 }, // ppc, mips assert + { DEFOP(Iop_CmpLT32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_CmpLT64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1, .loongarch64 = 1 }, // ppc32, mips assert + { DEFOP(Iop_CmpLE32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_CmpLE64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0, .loongarch64 = 1 }, // ppc32 asserts { DEFOP(Iop_CmpNEZ8, UNDEF_ALL), }, // not supported by mc_translate { DEFOP(Iop_CmpNEZ16, UNDEF_ALL), }, // not supported by mc_translate { DEFOP(Iop_CmpNEZ32, UNDEF_ALL), }, // not supported by mc_translate { DEFOP(Iop_CmpNEZ64, UNDEF_ALL), }, // not supported by mc_translate - { DEFOP(Iop_CmpwNEZ32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_CmpwNEZ64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts + { DEFOP(Iop_CmpwNEZ32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_CmpwNEZ64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts { DEFOP(Iop_Left8, UNDEF_UNKNOWN), }, // not supported by mc_translate { DEFOP(Iop_Left16, UNDEF_UNKNOWN), }, // not supported by mc_translate { DEFOP(Iop_Left32, UNDEF_UNKNOWN), }, // not supported by mc_translate { DEFOP(Iop_Left64, UNDEF_UNKNOWN), }, // not supported by mc_translate { DEFOP(Iop_Max32U, UNDEF_UNKNOWN), }, // not supported by mc_translate - { DEFOP(Iop_CmpORD32U, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test - { DEFOP(Iop_CmpORD64U, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test - { DEFOP(Iop_CmpORD32S, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test - { DEFOP(Iop_CmpORD64S, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test - { DEFOP(Iop_DivU32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_DivS32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_DivU64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts - { DEFOP(Iop_DivS64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts - { DEFOP(Iop_DivU64E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts - { DEFOP(Iop_DivS64E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts - { DEFOP(Iop_DivU32E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_DivS32E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_CmpORD32U, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // support added in vbit-test + { DEFOP(Iop_CmpORD64U, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // support added in vbit-test + { DEFOP(Iop_CmpORD32S, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // support added in vbit-test + { DEFOP(Iop_CmpORD64S, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // support added in vbit-test + { DEFOP(Iop_DivU32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_DivS32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_DivU64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, // ppc32 asserts + { DEFOP(Iop_DivS64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, // ppc32 asserts + { DEFOP(Iop_DivU64E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // ppc32 asserts + { DEFOP(Iop_DivS64E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // ppc32 asserts + { DEFOP(Iop_DivU32E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_DivS32E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // On s390 the DivMod operations always appear in a certain context // So they cannot be tested in isolation on that platform. - { DEFOP(Iop_DivModU64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_DivModS64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_DivModU32to32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_DivModS32to32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_DivModU128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts - { DEFOP(Iop_DivModS128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts - { DEFOP(Iop_DivModS64to64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_DivModU64to64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_8Uto16, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_8Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_8Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert - { DEFOP(Iop_16Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_16Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert - { DEFOP(Iop_32Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_8Sto16, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_8Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_8Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_16Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_16Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_32Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_64to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_32to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_64to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_16to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_16HIto8, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_8HLto16, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc isel - { DEFOP(Iop_32to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_32HIto16, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_16HLto32, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc isel - { DEFOP(Iop_64to32, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_64HIto32, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_32HLto64, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_128to64, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_128HIto64, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_64HLto128, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_32to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_64to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_1Uto8, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_1Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_1Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert - { DEFOP(Iop_1Sto8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_DivModU64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_DivModS64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_DivModU32to32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_DivModS32to32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_DivModU128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // mips asserts + { DEFOP(Iop_DivModS128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // mips asserts + { DEFOP(Iop_DivModS64to64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_DivModU64to64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_8Uto16, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_8Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_8Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32 assert + { DEFOP(Iop_16Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_16Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32 assert + { DEFOP(Iop_32Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_8Sto16, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_8Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_8Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32, mips assert + { DEFOP(Iop_16Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_16Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32, mips assert + { DEFOP(Iop_32Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_64to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32, mips assert + { DEFOP(Iop_32to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_64to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 0 }, // ppc32, mips assert + { DEFOP(Iop_16to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_16HIto8, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_8HLto16, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, // ppc isel + { DEFOP(Iop_32to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_32HIto16, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_16HLto32, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, // ppc isel + { DEFOP(Iop_64to32, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_64HIto32, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_32HLto64, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_128to64, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_128HIto64, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_64HLto128, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_32to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_64to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 0 }, // ppc32, mips assert + { DEFOP(Iop_1Uto8, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_1Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_1Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // ppc32 assert + { DEFOP(Iop_1Sto8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 0 }, { DEFOP(Iop_1Sto16, UNDEF_ALL), }, // not handled by mc_translate - { DEFOP(Iop_1Sto32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_1Sto64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_AddF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_SubF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_MulF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_DivF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_AddF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_AddF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_SubF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_SubF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1,.ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_MulF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_DivF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_AddF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_SubF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_MulF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_DivF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_NegF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_AbsF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_NegF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_NegF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_AbsF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_AbsF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_SqrtF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_SqrtF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_SqrtF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_CmpF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts - { DEFOP(Iop_CmpF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CmpF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F64toI16S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_F64toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F64toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F64toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_I32StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_I64StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_I64UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, // mips asserts - { DEFOP(Iop_I64UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_I32UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_I32UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F32toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F32toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_F32toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F32toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_I32StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_I64StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_F32toF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_F64toF32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_ReinterpF64asI64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_ReinterpI64asF64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_ReinterpF32asI32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_1Sto32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_1Sto64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_AddF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_SubF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_MulF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_DivF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_ScaleBF64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_AddF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_AddF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_SubF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_SubF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1,.ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_MulF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_DivF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_ScaleBF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_AddF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_SubF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_MulF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_DivF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_NegF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_AbsF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_NegF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_NegF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_AbsF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_AbsF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_SqrtF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_RSqrtF64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_LogBF64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_SqrtF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_RSqrtF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_LogBF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_SqrtF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_CmpF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_CmpF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CmpF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F64toI16S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_F64toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_F64toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F64toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_I32StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_I64StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_I64UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, // mips asserts + { DEFOP(Iop_I64UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_I32UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_I32UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F32toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 1 }, + { DEFOP(Iop_F32toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_F32toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F32toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_I32StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_I64StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_F32toF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_F64toF32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_ReinterpF64asI64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_ReinterpI64asF64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, // mips asserts + { DEFOP(Iop_ReinterpF32asI32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, // ppc requires this op to show up in a specific context. So it cannot be // tested standalone on that platform. - { DEFOP(Iop_ReinterpI32asF32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_F64HLtoF128, UNDEF_CONCAT), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F128HItoF64, UNDEF_UPPER), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F128LOtoF64, UNDEF_TRUNC), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_AddF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_SubF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_MulF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_DivF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_MAddF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_MSubF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_NegMAddF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_NegMSubF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_NegF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_AbsF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_SqrtF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_I32StoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_I64StoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_I32UtoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_I64UtoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F32toF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F64toF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F128toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F128toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F128toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F128toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F128toI128S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F128toF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F128toF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_RndF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_TruncF128toI32S,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_TruncF128toI32U,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_TruncF128toI64U,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_TruncF128toI64S,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_AtanF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_Yl2xF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_Yl2xp1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_PRemF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_PRemC3210F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_PRem1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_PRem1C3210F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_ScaleF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_SinF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CosF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_TanF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_2xm1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_RoundF128toInt, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_RoundF64toInt, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_RoundF32toInt, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_MAddF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_MSubF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_MAddF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_MSubF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_MAddF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_MSubF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_RSqrtEst5GoodF64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_RoundF64toF64_NEAREST, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_RoundF64toF64_NegINF, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_RoundF64toF64_PosINF, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_RoundF64toF64_ZERO, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, - { DEFOP(Iop_TruncF64asF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_RoundF64toF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_ReinterpI32asF32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_F64HLtoF128, UNDEF_CONCAT), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F128HItoF64, UNDEF_UPPER), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F128LOtoF64, UNDEF_TRUNC), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_AddF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_SubF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_MulF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_DivF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_MAddF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_MSubF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_NegMAddF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_NegMSubF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_NegF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_AbsF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_SqrtF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_I32StoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_I64StoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_I32UtoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_I64UtoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F32toF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F64toF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F128toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F128toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F128toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F128toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F128toI128S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F128toF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_F128toF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_RndF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_TruncF128toI32S,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_TruncF128toI32U,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_TruncF128toI64U,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_TruncF128toI64S,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_AtanF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_Yl2xF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_Yl2xp1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_PRemF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_PRemC3210F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_PRem1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_PRem1C3210F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_ScaleF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_SinF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_CosF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_TanF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_2xm1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_RoundF128toInt, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_RoundF64toInt, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_RoundF32toInt, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_MAddF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_MSubF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_MAddF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_MSubF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 1 }, + { DEFOP(Iop_MAddF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_MSubF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_RSqrtEst5GoodF64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, + { DEFOP(Iop_RoundF64toF64_NEAREST, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_RoundF64toF64_NegINF, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_RoundF64toF64_PosINF, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_RoundF64toF64_ZERO, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 0 }, + { DEFOP(Iop_TruncF64asF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .loongarch64 = 0 }, // mips asserts + { DEFOP(Iop_RoundF64toF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .loongarch64 = 0 }, { DEFOP(Iop_RecpExpF64, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecpExpF32, UNDEF_UNKNOWN), }, /* --------- Possibly required by IEEE 754-2008. --------- */ - { DEFOP(Iop_MaxNumF64, UNDEF_ALL), .arm = 1 }, - { DEFOP(Iop_MinNumF64, UNDEF_ALL), .arm = 1 }, - { DEFOP(Iop_MaxNumF32, UNDEF_ALL), .arm = 1 }, - { DEFOP(Iop_MinNumF32, UNDEF_ALL), .arm = 1 }, + { DEFOP(Iop_MaxNumF64, UNDEF_ALL), .arm = 1, .loongarch64 = 1 }, + { DEFOP(Iop_MinNumF64, UNDEF_ALL), .arm = 1, .loongarch64 = 1 }, + { DEFOP(Iop_MaxNumAbsF64, UNDEF_ALL), .arm = 0, .loongarch64 = 1 }, + { DEFOP(Iop_MinNumAbsF64, UNDEF_ALL), .arm = 0, .loongarch64 = 1 }, + { DEFOP(Iop_MaxNumF32, UNDEF_ALL), .arm = 1, .loongarch64 = 1 }, + { DEFOP(Iop_MinNumF32, UNDEF_ALL), .arm = 1, .loongarch64 = 1 }, + { DEFOP(Iop_MaxNumAbsF32, UNDEF_ALL), .arm = 0, .loongarch64 = 1 }, + { DEFOP(Iop_MinNumAbsF32, UNDEF_ALL), .arm = 0, .loongarch64 = 1 }, /* ------------------ 16-bit scalar FP ------------------ */ { DEFOP(Iop_F16toF64, UNDEF_ALL), .arm64 = 1 }, @@ -1109,15 +1119,19 @@ static irop_t irops[] = { { DEFOP(Iop_Max8Sx32, UNDEF_UNKNOWN), }, { DEFOP(Iop_Max16Sx16, UNDEF_UNKNOWN), }, { DEFOP(Iop_Max32Sx8, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Max64Sx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Max8Ux32, UNDEF_UNKNOWN), }, { DEFOP(Iop_Max16Ux16, UNDEF_UNKNOWN), }, { DEFOP(Iop_Max32Ux8, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Max64Ux4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Min8Sx32, UNDEF_UNKNOWN), }, { DEFOP(Iop_Min16Sx16, UNDEF_UNKNOWN), }, { DEFOP(Iop_Min32Sx8, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Min64Sx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Min8Ux32, UNDEF_UNKNOWN), }, { DEFOP(Iop_Min16Ux16, UNDEF_UNKNOWN), }, { DEFOP(Iop_Min32Ux8, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Min64Ux4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Mul16x16, UNDEF_UNKNOWN), }, { DEFOP(Iop_Mul32x8, UNDEF_UNKNOWN), }, { DEFOP(Iop_MulHi16Ux16, UNDEF_UNKNOWN), }, diff --git a/memcheck/tests/vbit-test/vtest.h b/memcheck/tests/vbit-test/vtest.h index c724f41..fe17f67 100644 --- a/memcheck/tests/vbit-test/vtest.h +++ b/memcheck/tests/vbit-test/vtest.h @@ -179,15 +179,16 @@ typedef struct { unsigned immediate_type; // Indicate whether IROp can be tested on a particular architecture - unsigned s390x : 1; - unsigned amd64 : 1; - unsigned ppc32 : 1; - unsigned ppc64 : 1; - unsigned arm : 1; - unsigned arm64 : 1; - unsigned x86 : 1; - unsigned mips32 : 1; - unsigned mips64 : 1; + unsigned s390x : 1; + unsigned amd64 : 1; + unsigned ppc32 : 1; + unsigned ppc64 : 1; + unsigned arm : 1; + unsigned arm64 : 1; + unsigned x86 : 1; + unsigned mips32 : 1; + unsigned mips64 : 1; + unsigned loongarch64: 1; } irop_t; diff --git a/memcheck/tests/x86-freebsd/Makefile.in b/memcheck/tests/x86-freebsd/Makefile.in index 5bcbb87..9bcd33d 100644 --- a/memcheck/tests/x86-freebsd/Makefile.in +++ b/memcheck/tests/x86-freebsd/Makefile.in @@ -578,6 +578,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -625,6 +631,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/x86-linux/Makefile.in b/memcheck/tests/x86-linux/Makefile.in index 48dd441..168a21b 100644 --- a/memcheck/tests/x86-linux/Makefile.in +++ b/memcheck/tests/x86-linux/Makefile.in @@ -614,6 +614,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -661,6 +667,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/x86-solaris/Makefile.in b/memcheck/tests/x86-solaris/Makefile.in index 03dabc3..3762dd9 100644 --- a/memcheck/tests/x86-solaris/Makefile.in +++ b/memcheck/tests/x86-solaris/Makefile.in @@ -606,6 +606,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -653,6 +659,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/memcheck/tests/x86/Makefile.in b/memcheck/tests/x86/Makefile.in index 897ebd6..e4636dc 100644 --- a/memcheck/tests/x86/Makefile.in +++ b/memcheck/tests/x86/Makefile.in @@ -654,6 +654,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -701,6 +707,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/mpi/Makefile.in b/mpi/Makefile.in index 6d0024e..46bddc4 100644 --- a/mpi/Makefile.in +++ b/mpi/Makefile.in @@ -567,6 +567,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -614,6 +620,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ DEFAULT_INCLUDES = diff --git a/nightly/conf/loongarch64.conf b/nightly/conf/loongarch64.conf new file mode 100644 index 0000000..8603671 --- /dev/null +++ b/nightly/conf/loongarch64.conf @@ -0,0 +1,3 @@ +export ABT_DETAILS=`uname -mrs` +export ABT_JOBS=4 +export ABT_PERF="--vg=../valgrind-new --vg=../valgrind-old" diff --git a/nightly/conf/loongarch64.sendemail b/nightly/conf/loongarch64.sendemail new file mode 100644 index 0000000..d784da3 --- /dev/null +++ b/nightly/conf/loongarch64.sendemail @@ -0,0 +1,7 @@ +#!/bin/sh + +subject=$1 +body=$2 +file=$3 + +(cat "$body" "$file") | /usr/bin/mail -s "$subject" valgrind-testresults@lists.sourceforge.net -r "Feiyang Chen " diff --git a/none/Makefile.in b/none/Makefile.in index a8368f2..4d0c5c8 100644 --- a/none/Makefile.in +++ b/none/Makefile.in @@ -619,6 +619,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -666,6 +672,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ @@ -756,6 +763,10 @@ TOOL_LDFLAGS_MIPS64_LINUX = \ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ @FLAG_M64@ +TOOL_LDFLAGS_LOONGARCH64_LINUX = \ + -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \ + @FLAG_M64@ + TOOL_LDFLAGS_X86_SOLARIS = \ $(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ @@ -816,6 +827,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ LIBREPLACEMALLOC_MIPS64_LINUX = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a +LIBREPLACEMALLOC_LOONGARCH64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-loongarch64-linux.a + LIBREPLACEMALLOC_X86_SOLARIS = \ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a @@ -888,6 +902,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ $(LIBREPLACEMALLOC_MIPS64_LINUX) \ -Wl,--no-whole-archive +LIBREPLACEMALLOC_LDFLAGS_LOONGARCH64_LINUX = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_LOONGARCH64_LINUX) \ + -Wl,--no-whole-archive + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ -Wl,--whole-archive \ $(LIBREPLACEMALLOC_X86_SOLARIS) \ diff --git a/none/tests/Makefile.am b/none/tests/Makefile.am index 253d4a1..c5943a0 100644 --- a/none/tests/Makefile.am +++ b/none/tests/Makefile.am @@ -35,7 +35,9 @@ endif if VGCONF_ARCHS_INCLUDE_NANOMIPS SUBDIRS += nanomips endif - +if VGCONF_ARCHS_INCLUDE_LOONGARCH64 +SUBDIRS += loongarch64 +endif # OS-specific tests if VGCONF_OS_IS_LINUX @@ -75,8 +77,9 @@ SUBDIRS += x86-freebsd endif DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm arm64 s390x mips32 mips64 nanomips \ - linux darwin solaris freebsd amd64-linux x86-linux amd64-darwin \ - x86-darwin amd64-solaris x86-solaris x86-freebsd scripts . + loongarch64 linux darwin solaris freebsd amd64-linux x86-linux \ + amd64-darwin x86-darwin amd64-solaris x86-solaris x86-freebsd \ + scripts . dist_noinst_SCRIPTS = \ filter_cmdline0 \ diff --git a/none/tests/Makefile.in b/none/tests/Makefile.in index c86429e..f33c222 100644 --- a/none/tests/Makefile.in +++ b/none/tests/Makefile.in @@ -137,21 +137,22 @@ host_triplet = @host@ @VGCONF_ARCHS_INCLUDE_MIPS32_TRUE@am__append_19 = mips32 @VGCONF_ARCHS_INCLUDE_MIPS64_TRUE@am__append_20 = mips64 @VGCONF_ARCHS_INCLUDE_NANOMIPS_TRUE@am__append_21 = nanomips +@VGCONF_ARCHS_INCLUDE_LOONGARCH64_TRUE@am__append_22 = loongarch64 # OS-specific tests -@VGCONF_OS_IS_LINUX_TRUE@am__append_22 = linux -@VGCONF_OS_IS_DARWIN_TRUE@am__append_23 = darwin -@VGCONF_OS_IS_SOLARIS_TRUE@am__append_24 = solaris -@VGCONF_OS_IS_FREEBSD_TRUE@am__append_25 = freebsd +@VGCONF_OS_IS_LINUX_TRUE@am__append_23 = linux +@VGCONF_OS_IS_DARWIN_TRUE@am__append_24 = darwin +@VGCONF_OS_IS_SOLARIS_TRUE@am__append_25 = solaris +@VGCONF_OS_IS_FREEBSD_TRUE@am__append_26 = freebsd # Platform-specific tests -@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_26 = amd64-linux -@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_27 = x86-linux -@VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_TRUE@am__append_28 = amd64-darwin -@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_29 = x86-darwin -@VGCONF_PLATFORMS_INCLUDE_AMD64_SOLARIS_TRUE@am__append_30 = amd64-solaris -@VGCONF_PLATFORMS_INCLUDE_X86_SOLARIS_TRUE@am__append_31 = x86-solaris -@VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD_TRUE@am__append_32 = x86-freebsd +@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_27 = amd64-linux +@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_28 = x86-linux +@VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_TRUE@am__append_29 = amd64-darwin +@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_30 = x86-darwin +@VGCONF_PLATFORMS_INCLUDE_AMD64_SOLARIS_TRUE@am__append_31 = amd64-solaris +@VGCONF_PLATFORMS_INCLUDE_X86_SOLARIS_TRUE@am__append_32 = x86-solaris +@VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD_TRUE@am__append_33 = x86-freebsd check_PROGRAMS = args$(EXEEXT) async-sigs$(EXEEXT) bitfield1$(EXEEXT) \ bug129866$(EXEEXT) bug234814$(EXEEXT) closeall$(EXEEXT) \ coolo_strlen$(EXEEXT) discard$(EXEEXT) exec-sigmask$(EXEEXT) \ @@ -188,17 +189,17 @@ check_PROGRAMS = args$(EXEEXT) async-sigs$(EXEEXT) bitfield1$(EXEEXT) \ gxx304$(EXEEXT) process_vm_readv_writev$(EXEEXT) \ sigprocmask$(EXEEXT) $(am__EXEEXT_1) $(am__EXEEXT_2) \ $(am__EXEEXT_3) $(am__EXEEXT_4) $(am__EXEEXT_5) -@HAVE_NESTED_FUNCTIONS_TRUE@am__append_33 = nestedfns +@HAVE_NESTED_FUNCTIONS_TRUE@am__append_34 = nestedfns # This doesn't appear to be compilable on Darwin. -@VGCONF_OS_IS_DARWIN_OR_FREEBSD_FALSE@am__append_34 = rlimit64_nofile -@VGCONF_OS_IS_DARWIN_FALSE@am__append_35 = ppoll_alarm +@VGCONF_OS_IS_DARWIN_OR_FREEBSD_FALSE@am__append_35 = rlimit64_nofile +@VGCONF_OS_IS_DARWIN_FALSE@am__append_36 = ppoll_alarm # older (?) clang does not know -ansi -@HAVE_ANSI_TRUE@am__append_36 = ansi -@BUILD_IFUNC_TESTS_TRUE@am__append_37 = ifunc -@VGCONF_OS_IS_SOLARIS_TRUE@am__append_38 = -U_REENTRANT -@VGCONF_OS_IS_SOLARIS_TRUE@am__append_39 = -Du_int32_t=uint32_t +@HAVE_ANSI_TRUE@am__append_37 = ansi +@BUILD_IFUNC_TESTS_TRUE@am__append_38 = ifunc +@VGCONF_OS_IS_SOLARIS_TRUE@am__append_39 = -U_REENTRANT +@VGCONF_OS_IS_SOLARIS_TRUE@am__append_40 = -Du_int32_t=uint32_t subdir = none/tests ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac @@ -1109,6 +1110,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -1156,6 +1163,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ @@ -1184,10 +1192,12 @@ SUBDIRS = . scripts $(am__append_12) $(am__append_13) $(am__append_14) \ $(am__append_21) $(am__append_22) $(am__append_23) \ $(am__append_24) $(am__append_25) $(am__append_26) \ $(am__append_27) $(am__append_28) $(am__append_29) \ - $(am__append_30) $(am__append_31) $(am__append_32) + $(am__append_30) $(am__append_31) $(am__append_32) \ + $(am__append_33) DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm arm64 s390x mips32 mips64 nanomips \ - linux darwin solaris freebsd amd64-linux x86-linux amd64-darwin \ - x86-darwin amd64-solaris x86-solaris x86-freebsd scripts . + loongarch64 linux darwin solaris freebsd amd64-linux x86-linux \ + amd64-darwin x86-darwin amd64-solaris x86-solaris x86-freebsd \ + scripts . dist_noinst_SCRIPTS = \ filter_cmdline0 \ @@ -1386,9 +1396,9 @@ pth_term_signal_LDADD = -lpthread @VGCONF_OS_IS_FREEBSD_TRUE@res_search_LDADD = -lpthread @VGCONF_OS_IS_FREEBSD_FALSE@resolv_LDADD = -lresolv -lpthread @VGCONF_OS_IS_FREEBSD_TRUE@resolv_LDADD = -lpthread -resolv_CFLAGS = $(AM_CFLAGS) $(am__append_38) +resolv_CFLAGS = $(AM_CFLAGS) $(am__append_39) semlimit_LDADD = -lpthread -sha1_test_CFLAGS = $(AM_CFLAGS) $(am__append_39) +sha1_test_CFLAGS = $(AM_CFLAGS) $(am__append_40) sigsusp_LDADD = -lpthread thread_exits_LDADD = -lpthread threaded_fork_LDADD = -lpthread diff --git a/none/tests/allexec_prepare_prereq b/none/tests/allexec_prepare_prereq index a541f42..49c45c7 100755 --- a/none/tests/allexec_prepare_prereq +++ b/none/tests/allexec_prepare_prereq @@ -28,11 +28,12 @@ pair() } -pair x86 amd64 -pair ppc32 ppc64 -pair s390x_unexisting_in_32bits s390x -pair arm arm64 -pair mips32 mips64 -pair nanomips nanoMIPS_unexisting_in_64bits +pair x86 amd64 +pair ppc32 ppc64 +pair s390x_unexisting_in_32bits s390x +pair arm arm64 +pair mips32 mips64 +pair nanomips nanoMIPS_unexisting_in_64bits +pair loongarch_unexisting_in_32bits loongarch64 exit 0 diff --git a/none/tests/amd64-darwin/Makefile.in b/none/tests/amd64-darwin/Makefile.in index 053b4b0..06e8bda 100644 --- a/none/tests/amd64-darwin/Makefile.in +++ b/none/tests/amd64-darwin/Makefile.in @@ -570,6 +570,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -617,6 +623,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/amd64-linux/Makefile.in b/none/tests/amd64-linux/Makefile.in index 1bd04dc..ba1810a 100644 --- a/none/tests/amd64-linux/Makefile.in +++ b/none/tests/amd64-linux/Makefile.in @@ -578,6 +578,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -625,6 +631,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/amd64-solaris/Makefile.in b/none/tests/amd64-solaris/Makefile.in index 6d942c7..a86893a 100644 --- a/none/tests/amd64-solaris/Makefile.in +++ b/none/tests/amd64-solaris/Makefile.in @@ -583,6 +583,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -630,6 +636,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/amd64/Makefile.in b/none/tests/amd64/Makefile.in index 5f37f72..e1bcf12 100644 --- a/none/tests/amd64/Makefile.in +++ b/none/tests/amd64/Makefile.in @@ -913,6 +913,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -960,6 +966,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/arm/Makefile.in b/none/tests/arm/Makefile.in index ad8ba1a..f17f02f 100644 --- a/none/tests/arm/Makefile.in +++ b/none/tests/arm/Makefile.in @@ -680,6 +680,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -727,6 +733,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/arm64/Makefile.in b/none/tests/arm64/Makefile.in index 2ece958..652d21b 100644 --- a/none/tests/arm64/Makefile.in +++ b/none/tests/arm64/Makefile.in @@ -635,6 +635,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -682,6 +688,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/darwin/Makefile.in b/none/tests/darwin/Makefile.in index ed42225..9818e4b 100644 --- a/none/tests/darwin/Makefile.in +++ b/none/tests/darwin/Makefile.in @@ -583,6 +583,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -630,6 +636,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/freebsd/Makefile.in b/none/tests/freebsd/Makefile.in index 077b910..59d4d05 100644 --- a/none/tests/freebsd/Makefile.in +++ b/none/tests/freebsd/Makefile.in @@ -617,6 +617,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -664,6 +670,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/libvex_test.c b/none/tests/libvex_test.c index 5b57a4c..3080ce6 100644 --- a/none/tests/libvex_test.c +++ b/none/tests/libvex_test.c @@ -76,6 +76,8 @@ __attribute__((noinline)) static void get_guest_arch(VexArch *ga) *ga = VexArchMIPS64; #elif defined(VGA_nanomips) *ga = VexArchNANOMIPS; +#elif defined(VGA_loongarch64) + *ga = VexArchLOONGARCH64; #else missing arch; #endif @@ -113,6 +115,7 @@ static VexEndness arch_endness (VexArch va) { else return VexEndnessBE; } + case VexArchLOONGARCH64: return VexEndnessLE; default: failure_exit(); } } @@ -139,6 +142,7 @@ static UInt arch_hwcaps (VexArch va) { case VexArchMIPS64: return VEX_PRID_COMP_MIPS | VEX_MIPS_HOST_FR; #endif case VexArchNANOMIPS: return 0; + case VexArchLOONGARCH64: return VEX_HWCAPS_LOONGARCH_ISA_64BIT; default: failure_exit(); } } @@ -156,6 +160,7 @@ static Bool mode64 (VexArch va) { case VexArchMIPS32: return False; case VexArchMIPS64: return True; case VexArchNANOMIPS: return False; + case VexArchLOONGARCH64: return True; default: failure_exit(); } } @@ -275,7 +280,7 @@ int main(int argc, char **argv) // explicitly via command line arguments. if (multiarch) { VexArch va; - for (va = VexArchX86; va <= VexArchNANOMIPS; va++) { + for (va = VexArchX86; va <= VexArchLOONGARCH64; va++) { vta.arch_host = va; vta.archinfo_host.endness = arch_endness (vta.arch_host); vta.archinfo_host.hwcaps = arch_hwcaps (vta.arch_host); diff --git a/none/tests/linux/Makefile.in b/none/tests/linux/Makefile.in index 38d0563..8dd49c1 100644 --- a/none/tests/linux/Makefile.in +++ b/none/tests/linux/Makefile.in @@ -625,6 +625,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -672,6 +678,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/loongarch64/Makefile.am b/none/tests/loongarch64/Makefile.am new file mode 100644 index 0000000..01ec3e6 --- /dev/null +++ b/none/tests/loongarch64/Makefile.am @@ -0,0 +1,43 @@ + +include $(top_srcdir)/Makefile.tool-tests.am + +dist_noinst_SCRIPTS = filter_stderr + +EXTRA_DIST = \ + atomic.stdout.exp atomic.stderr.exp atomic.vgtest \ + branch.stdout.exp branch.stderr.exp branch.vgtest \ + cpucfg.stdout.exp cpucfg.stderr.exp cpucfg.vgtest \ + fault.stdout.exp fault.stderr.exp fault.vgtest \ + fault_fp.stdout.exp fault_fp.stderr.exp fault_fp.vgtest \ + float.stdout.exp float.stderr.exp float.vgtest \ + integer.stdout.exp integer.stderr.exp integer.vgtest \ + llsc.stdout.exp llsc.stderr.exp llsc.vgtest \ + memory.stdout.exp memory.stderr.exp memory.vgtest \ + move.stdout.exp move.stderr.exp move.vgtest \ + pc.stdout.exp pc.stderr.exp pc.vgtest \ + special.stdout.exp special.stderr.exp special.vgtest \ + vector128.stdout.exp vector128.stderr.exp vector128.vgtest \ + vector256.stdout.exp vector256.stderr.exp vector256.vgtest + +check_PROGRAMS = \ + allexec \ + atomic \ + branch \ + cpucfg \ + fault \ + fault_fp \ + float \ + integer \ + llsc \ + memory \ + move \ + pc \ + special \ + vector128 \ + vector256 + +AM_CFLAGS += @FLAG_M64@ +AM_CXXFLAGS += @FLAG_M64@ +AM_CCASFLAGS += @FLAG_M64@ + +allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ diff --git a/none/tests/loongarch64/allexec.c b/none/tests/loongarch64/allexec.c new file mode 100644 index 0000000..69e1208 --- /dev/null +++ b/none/tests/loongarch64/allexec.c @@ -0,0 +1,56 @@ +#include +#include +#include +#include +#include +#include + +extern char **environ; + +#define S(...) (fprintf(stdout, __VA_ARGS__),fflush(stdout)) +#define FORKEXECWAIT(exec_call) do { \ + int status;\ + pid_t child = fork(); \ + if (child == 0) {exec_call; perror ("exec failed");} \ + else if (child == -1) perror ("cannot fork\n"); \ + else if (child != wait (&status)) perror ("error waiting child"); \ + else S("child exited\n"); \ + } while (0) + +void test_allexec (char *exec) +{ + FORKEXECWAIT (execlp(exec, exec, (char *) NULL)); + FORKEXECWAIT (execlp(exec, exec, "constant_arg1", "constant_arg2", + (char *) NULL)); + { + /* Solaris requires that the argv parameter to execve() isn't NULL, so + set it. Note that this isn't necessary on Linux. */ + char *const argv[] = {exec, NULL}; + FORKEXECWAIT (execve(exec, argv, environ)); + } +} + + +/* If a single argument "exec" is given, will execute itself + (in bi-arch, a 32 bit and 64 bit variant) via various exec system calls. + Note that this test can only be run after the prerequisite have been + prepared by allexec_prepare_prereq, which will a.o. make links + for the allexec32 and allexec64 executables. On single arch build, + these links points to the same executable to ensure this test works + everywhere the same. + No arguments or more arguments means just print its args. */ +int main(int argc, char **argv, char **envp) +{ + if ( (argc == 2) && (strcmp (argv[1], "exec") == 0)) { + S("%s will exec ./allexec32\n", argv[0]); + test_allexec ("./allexec32"); + S("%s will exec ./allexec64\n", argv[0]); + test_allexec ("./allexec64"); + } else { + int i; + S("program exec-ed:"); + for (i = 0; i < argc; i++) S(" %s", argv[i]); + S("\n"); + } + return 0; +} diff --git a/none/tests/loongarch64/atomic.c b/none/tests/loongarch64/atomic.c new file mode 100644 index 0000000..916d5f7 --- /dev/null +++ b/none/tests/loongarch64/atomic.c @@ -0,0 +1,75 @@ +#include + +#define TESTINST_AM(insn, res, val, addr) \ + { \ + __asm__ __volatile__( \ + "move $t1, %1 \n\t" \ + "move $t2, %2 \n\t" \ + insn " $t0, $t1, $t2 \n\t" \ + "move %0, $t0 \n\t" \ + : "=r" (res) \ + : "r" (val), "r" (addr) \ + : "$t0", "$t1", "$t2", "memory"); \ + } + +#define TESTINST_AM_4(insn, v) \ + { \ + printf(#insn ".w ::\n"); \ + TESTINST_AM(#insn ".w", res_i, v, &val_i); \ + printf("old: %d new: %d\n", res_i, val_i); \ + \ + printf(#insn "_db.w ::\n"); \ + TESTINST_AM(#insn "_db.w", res_i, v, &val_i); \ + printf("old: %d new: %d\n", res_i, val_i); \ + \ + printf(#insn ".d ::\n"); \ + TESTINST_AM(#insn ".d", res_l, v, &val_l); \ + printf("old: %ld new: %ld\n", res_l, val_l); \ + \ + printf(#insn "_db.d ::\n"); \ + TESTINST_AM(#insn "_db.d", res_l, v, &val_l); \ + printf("old: %ld new: %ld\n", res_l, val_l); \ + } + +#define TESTINST_AM_U_4(insn, v) \ + { \ + printf(#insn ".wu ::\n"); \ + TESTINST_AM(#insn ".wu", res_i, v, &val_i); \ + printf("old: %u new: %u\n", res_i, val_i); \ + \ + printf(#insn "_db.wu ::\n"); \ + TESTINST_AM(#insn "_db.wu", res_i, v, &val_i); \ + printf("old: %u new: %u\n", res_i, val_i); \ + \ + printf(#insn ".du ::\n"); \ + TESTINST_AM(#insn ".du", res_l, v, &val_l); \ + printf("old: %lu new: %lu\n", res_l, val_l); \ + \ + printf(#insn "_db.du ::\n"); \ + TESTINST_AM(#insn "_db.du", res_l, v, &val_l); \ + printf("old: %lu new: %lu\n", res_l, val_l); \ + } + +void test(void) +{ + int res_i; + long res_l; + int val_i = 1; + long val_l = 1; + + TESTINST_AM_4(amswap, 2); + TESTINST_AM_4(amadd, 5); + TESTINST_AM_4(amand, 3); + TESTINST_AM_4(amor, 8); + TESTINST_AM_4(amxor, 4); + TESTINST_AM_4(ammax, 16); + TESTINST_AM_4(ammin, -1); + TESTINST_AM_U_4(ammax, 9); + TESTINST_AM_U_4(ammin, 6); +} + +int main(void) +{ + test(); + return 0; +} diff --git a/none/tests/loongarch64/atomic.stderr.exp b/none/tests/loongarch64/atomic.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/atomic.stdout.exp b/none/tests/loongarch64/atomic.stdout.exp new file mode 100644 index 0000000..7eab9eb --- /dev/null +++ b/none/tests/loongarch64/atomic.stdout.exp @@ -0,0 +1,72 @@ +amswap.w :: +old: 1 new: 2 +amswap_db.w :: +old: 2 new: 2 +amswap.d :: +old: 1 new: 2 +amswap_db.d :: +old: 2 new: 2 +amadd.w :: +old: 2 new: 7 +amadd_db.w :: +old: 7 new: 12 +amadd.d :: +old: 2 new: 7 +amadd_db.d :: +old: 7 new: 12 +amand.w :: +old: 12 new: 0 +amand_db.w :: +old: 0 new: 0 +amand.d :: +old: 12 new: 0 +amand_db.d :: +old: 0 new: 0 +amor.w :: +old: 0 new: 8 +amor_db.w :: +old: 8 new: 8 +amor.d :: +old: 0 new: 8 +amor_db.d :: +old: 8 new: 8 +amxor.w :: +old: 8 new: 12 +amxor_db.w :: +old: 12 new: 8 +amxor.d :: +old: 8 new: 12 +amxor_db.d :: +old: 12 new: 8 +ammax.w :: +old: 8 new: 16 +ammax_db.w :: +old: 16 new: 16 +ammax.d :: +old: 8 new: 16 +ammax_db.d :: +old: 16 new: 16 +ammin.w :: +old: 16 new: -1 +ammin_db.w :: +old: -1 new: -1 +ammin.d :: +old: 16 new: -1 +ammin_db.d :: +old: -1 new: -1 +ammax.wu :: +old: 4294967295 new: 4294967295 +ammax_db.wu :: +old: 4294967295 new: 4294967295 +ammax.du :: +old: 18446744073709551615 new: 18446744073709551615 +ammax_db.du :: +old: 18446744073709551615 new: 18446744073709551615 +ammin.wu :: +old: 4294967295 new: 6 +ammin_db.wu :: +old: 6 new: 6 +ammin.du :: +old: 18446744073709551615 new: 6 +ammin_db.du :: +old: 6 new: 6 diff --git a/none/tests/loongarch64/atomic.vgtest b/none/tests/loongarch64/atomic.vgtest new file mode 100644 index 0000000..8fe5ce5 --- /dev/null +++ b/none/tests/loongarch64/atomic.vgtest @@ -0,0 +1,3 @@ +prereq: ../../../tests/loongarch64_features lam +prog: atomic +vgopts: -q diff --git a/none/tests/loongarch64/branch.c b/none/tests/loongarch64/branch.c new file mode 100644 index 0000000..e702d3f --- /dev/null +++ b/none/tests/loongarch64/branch.c @@ -0,0 +1,148 @@ +#include + +#define TESTINST_B_RR(insn, val1, val2) \ + { \ + int res; \ + unsigned long v1 = (unsigned long)val1; \ + unsigned long v2 = (unsigned long)val2; \ + __asm__ __volatile__( \ + insn " %1, %2, 1f \n\t" \ + " move %0, $zero \n\t" \ + " b 2f \n\t" \ + "1: \n\t" \ + " addi.w %0, $zero, 1 \n\t" \ + "2: \n\t" \ + : "=r" (res) \ + : "r" (v1), "r" (v2) \ + : "memory"); \ + printf("%s::\n", insn); \ + printf("input: %#lx %#lx\n", v1, v2); \ + printf("output: %d\n", res); \ + } + +#define TESTINST_B_R(insn, val) \ + { \ + int res; \ + unsigned long v = (unsigned long)val; \ + __asm__ __volatile__( \ + insn " %1, 1f \n\t" \ + " move %0, $zero \n\t" \ + " b 2f \n\t" \ + "1: \n\t" \ + " addi.w %0, $zero, 1 \n\t" \ + "2: \n\t" \ + : "=r" (res) \ + : "r" (v) \ + : "memory"); \ + printf("%s::\n", insn); \ + printf("input: %#lx\n", v); \ + printf("output: %d\n", res); \ + } + +#define TESTINST_B_C(insn, val) \ + { \ + int res; \ + unsigned long v = (unsigned long)val; \ + __asm__ __volatile__( \ + " movgr2cf $fcc0, %1 \n\t" \ + insn " $fcc0, 1f \n\t" \ + " move %0, $zero \n\t" \ + " b 2f \n\t" \ + "1: \n\t" \ + " addi.w %0, $zero, 1 \n\t" \ + "2: \n\t" \ + : "=r" (res) \ + : "r" (v) \ + : "$fcc0", "memory"); \ + printf("%s::\n", insn); \ + printf("input: %#lx\n", v); \ + printf("output: %d\n", res); \ + } + +#define TESTINST_BL() \ + { \ + int res; \ + __asm__ __volatile__( \ + " move %0, $zero \n\t" \ + " bl 1f \n\t" \ + " addi.w %0, %0, 1 \n\t" \ + " b 2f \n\t" \ + "1: \n\t" \ + " addi.w %0, %0, 1 \n\t" \ + " jr $ra \n\t" \ + "2: \n\t" \ + : "=r" (res) \ + : \ + : "$ra", "memory"); \ + printf("bl::\n"); \ + printf("res: %d\n", res); \ + } + +#define TESTINST_JIRL(insn) \ + { \ + unsigned long addr1, addr2; \ + __asm__ __volatile__( \ + " pcaddi $t0, 2 \n\t" \ + " jirl %0, $t0, 0 \n\t" \ + " pcaddi %1, 0 \n\t" \ + : "=r" (addr1), "=r" (addr2) \ + : \ + : "$t0", "memory"); \ + printf("jirl::\n"); \ + printf("res: %d\n", addr1 == addr2); \ + } + +void test(void) +{ + /* ---------------- beq rj, rd, offs16 ---------------- */ + TESTINST_B_RR("beq", 1, 2); + TESTINST_B_RR("beq", 1, 1); + + /* ---------------- bne rj, rd, offs16 ---------------- */ + TESTINST_B_RR("bne", 1, 2); + TESTINST_B_RR("bne", 1, 1); + + /* ---------------- blt rj, rd, offs16 ---------------- */ + TESTINST_B_RR("blt", 1, 2); + TESTINST_B_RR("blt", 1, 0); + + /* ---------------- bge rj, rd, offs16 ---------------- */ + TESTINST_B_RR("bge", 1, 2); + TESTINST_B_RR("bge", 0, 0); + + /* ---------------- bltu rj, rd, offs16 ---------------- */ + TESTINST_B_RR("bltu", -1, 2); + TESTINST_B_RR("bltu", 0, 1); + + /* ---------------- bgeu rj, rd, offs16 ---------------- */ + TESTINST_B_RR("bgeu", -1, 2); + TESTINST_B_RR("bgeu", 0, 1); + + /* ---------------- beqz rj, offs21 ---------------- */ + TESTINST_B_R("beqz", 0); + TESTINST_B_R("beqz", -1); + + /* ---------------- bnez rj, offs21 ---------------- */ + TESTINST_B_R("bnez", 0); + TESTINST_B_R("bnez", -1); + + /* ---------------- bceqz cj, offs21 ---------------- */ + TESTINST_B_C("bceqz", 0); + TESTINST_B_C("bceqz", 1); + + /* ---------------- bcnez cj, offs21 ---------------- */ + TESTINST_B_C("bcnez", 0); + TESTINST_B_C("bcnez", 1); + + /* ---------------- bl offs26 ---------------- */ + TESTINST_BL(); + + /* ---------------- jirl rd, rj, offs16 ---------------- */ + TESTINST_JIRL(); +} + +int main(void) +{ + test(); + return 0; +} diff --git a/none/tests/loongarch64/branch.stderr.exp b/none/tests/loongarch64/branch.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/branch.stdout.exp b/none/tests/loongarch64/branch.stdout.exp new file mode 100644 index 0000000..0a32d6a --- /dev/null +++ b/none/tests/loongarch64/branch.stdout.exp @@ -0,0 +1,64 @@ +beq:: +input: 0x1 0x2 +output: 0 +beq:: +input: 0x1 0x1 +output: 1 +bne:: +input: 0x1 0x2 +output: 1 +bne:: +input: 0x1 0x1 +output: 0 +blt:: +input: 0x1 0x2 +output: 1 +blt:: +input: 0x1 0 +output: 0 +bge:: +input: 0x1 0x2 +output: 0 +bge:: +input: 0 0 +output: 1 +bltu:: +input: 0xffffffffffffffff 0x2 +output: 0 +bltu:: +input: 0 0x1 +output: 1 +bgeu:: +input: 0xffffffffffffffff 0x2 +output: 1 +bgeu:: +input: 0 0x1 +output: 0 +beqz:: +input: 0 +output: 1 +beqz:: +input: 0xffffffffffffffff +output: 0 +bnez:: +input: 0 +output: 0 +bnez:: +input: 0xffffffffffffffff +output: 1 +bceqz:: +input: 0 +output: 1 +bceqz:: +input: 0x1 +output: 0 +bcnez:: +input: 0 +output: 0 +bcnez:: +input: 0x1 +output: 1 +bl:: +res: 2 +jirl:: +res: 1 diff --git a/none/tests/loongarch64/branch.vgtest b/none/tests/loongarch64/branch.vgtest new file mode 100644 index 0000000..535c055 --- /dev/null +++ b/none/tests/loongarch64/branch.vgtest @@ -0,0 +1,2 @@ +prog: branch +vgopts: -q diff --git a/none/tests/loongarch64/cpucfg.c b/none/tests/loongarch64/cpucfg.c new file mode 100644 index 0000000..f5d0570 --- /dev/null +++ b/none/tests/loongarch64/cpucfg.c @@ -0,0 +1,24 @@ +#include + +void test(int reg) +{ + int res; + __asm__ __volatile__( + "cpucfg %0, %1 \n\t" + : "=r" (res) + : "r" (reg) + : "memory"); + printf("cpucfg ::\n"); + printf("input: %x\n", (unsigned)reg); + printf("output: %x\n", (unsigned)res); +} + +int main(void) +{ + int i; + + for (i = 0; i < 24; i++) + test(i); + + return 0; +} diff --git a/none/tests/loongarch64/cpucfg.stderr.exp b/none/tests/loongarch64/cpucfg.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/cpucfg.stdout.exp b/none/tests/loongarch64/cpucfg.stdout.exp new file mode 100644 index 0000000..49e0ba7 --- /dev/null +++ b/none/tests/loongarch64/cpucfg.stdout.exp @@ -0,0 +1,72 @@ +cpucfg :: +input: 0 +output: 14c010 +cpucfg :: +input: 1 +output: 3f2f2fe +cpucfg :: +input: 2 +output: 7ccfc7 +cpucfg :: +input: 3 +output: fcff +cpucfg :: +input: 4 +output: 5f5e100 +cpucfg :: +input: 5 +output: 10001 +cpucfg :: +input: 6 +output: 7f33 +cpucfg :: +input: 7 +output: 0 +cpucfg :: +input: 8 +output: 0 +cpucfg :: +input: 9 +output: 0 +cpucfg :: +input: a +output: 0 +cpucfg :: +input: b +output: 0 +cpucfg :: +input: c +output: 0 +cpucfg :: +input: d +output: 0 +cpucfg :: +input: e +output: 0 +cpucfg :: +input: f +output: 0 +cpucfg :: +input: 10 +output: 2c3d +cpucfg :: +input: 11 +output: 6080003 +cpucfg :: +input: 12 +output: 6080003 +cpucfg :: +input: 13 +output: 608000f +cpucfg :: +input: 14 +output: 60e000f +cpucfg :: +input: 15 +output: 0 +cpucfg :: +input: 16 +output: 0 +cpucfg :: +input: 17 +output: 0 diff --git a/none/tests/loongarch64/cpucfg.vgtest b/none/tests/loongarch64/cpucfg.vgtest new file mode 100644 index 0000000..fea9644 --- /dev/null +++ b/none/tests/loongarch64/cpucfg.vgtest @@ -0,0 +1,3 @@ +prereq: ../../../tests/loongarch64_features cpucfg +prog: cpucfg +vgopts: -q diff --git a/none/tests/loongarch64/fault.c b/none/tests/loongarch64/fault.c new file mode 100644 index 0000000..2941768 --- /dev/null +++ b/none/tests/loongarch64/fault.c @@ -0,0 +1,234 @@ +#include +#include +#include +#include +#include + +#define NUM 24 + +unsigned long mem[NUM] = { + 0x121f1e1f0000e680, 0x0000000000010700, 0x000000030000e7dc, + 0xffffffff0000b0d0, 0x232f2e2f2ab05fd0, 0x242c2b2b0000b6a0, + 0x252a2e2b0000be80, 0x262d2d2a0000de10, 0x3f343f3e0000df20, + 0x3e353d3c2ab05fe0, 0x363a3c3b0000dfd0, 0x3b373b3a00010300, + 0x0000e680121f1e1f, 0x0001070000000000, 0x0000e7dc00000003, + 0x0000b0d0ffffffff, 0x2ab05fd0232f2e2f, 0x0000b6a0242c2b2b, + 0x0000be80252a2e2b, 0x0000de10262d2d2a, 0x0000df203f343f3e, + 0x2ab05fe03e353d3c, 0x0000dfd0363a3c3b, 0x000103003b373b3a +}; + +long val1 = 0; +long val2 = 0xfdecba9087654321UL; +char *p = (char *)mem; + +#define TESTINST_LOAD_RRR(n, insn, addr1, addr2) \ + void test ## n (void) \ + { \ + printf("test %d\n", n); \ + printf("%s ::\n", insn); \ + __asm__ __volatile__( \ + insn " %0, %1, %2 \n\t" \ + : "=r" (val1) \ + : "r" (addr1), "r" (addr2) \ + : "memory"); \ + printf("output: %ld\n", val1); \ + } + +#define TESTINST_STORE_RRR(n, insn, addr1, addr2) \ + void test ## n (void) \ + { \ + printf("test %d\n", n); \ + printf("%s ::\n", insn); \ + printf("input: %ld\n", val2); \ + __asm__ __volatile__( \ + insn " %0, %1, %2 \n\t" \ + : \ + : "r" (val2), "r" (addr1), "r" (addr2) \ + : "memory"); \ + } + +#define TESTINST_RR(n, insn, v1, v2) \ + void test ## n (void) \ + { \ + printf("test %d\n", n); \ + printf("%s ::\n", insn); \ + printf("input: %ld %ld\n", (long)v1, (long)v2); \ + __asm__ __volatile__( \ + insn " %0, %1 \n\t" \ + : \ + : "r" (v1), "r" (v2) \ + : "memory"); \ + } + +#define TESTINST_I(n, insn, imm) \ + void test ## n (void) \ + { \ + printf("test %d\n", n); \ + printf("%s ::\n", insn); \ + printf("input: %d\n", imm); \ + __asm__ __volatile__( \ + insn " " #imm " \n\t" \ + : \ + : \ + : "memory"); \ + } + +static sigjmp_buf escape; + +static void handler(int sig, siginfo_t *si, void *uc) +{ + fprintf(stderr, "signal: %d\n", sig); + fprintf(stderr, "code: %d\n", si->si_code); + siglongjmp(escape, 1); +} + +static inline void show(void) +{ + int i; + printf("memory block:\n"); + for (i = 0; i < NUM; i++) + printf("0x%lx:\t%#018lx\n", i * sizeof(unsigned long), mem[i]); +} + +TESTINST_LOAD_RRR(1, "ldgt.b", &p[0], &p[64]); +TESTINST_LOAD_RRR(2, "ldgt.b", &p[1], &p[0] ); +TESTINST_LOAD_RRR(3, "ldgt.h", &p[1], &p[0] ); +TESTINST_LOAD_RRR(4, "ldgt.h", &p[2], &p[64]); +TESTINST_LOAD_RRR(5, "ldgt.h", &p[4], &p[0] ); +TESTINST_LOAD_RRR(6, "ldgt.w", &p[2], &p[0] ); +TESTINST_LOAD_RRR(7, "ldgt.w", &p[8], &p[64]); +TESTINST_LOAD_RRR(8, "ldgt.w", &p[12], &p[0] ); +TESTINST_LOAD_RRR(9, "ldgt.d", &p[4], &p[0] ); +TESTINST_LOAD_RRR(10, "ldgt.d", &p[16], &p[64]); +TESTINST_LOAD_RRR(11, "ldgt.d", &p[32], &p[0] ); + +TESTINST_LOAD_RRR(12, "ldle.b", &p[64], &p[0] ); +TESTINST_LOAD_RRR(13, "ldle.b", &p[65], &p[96]); +TESTINST_LOAD_RRR(14, "ldle.h", &p[65], &p[0] ); +TESTINST_LOAD_RRR(15, "ldle.h", &p[66], &p[0] ); +TESTINST_LOAD_RRR(16, "ldle.h", &p[68], &p[96]); +TESTINST_LOAD_RRR(17, "ldle.w", &p[66], &p[0] ); +TESTINST_LOAD_RRR(18, "ldle.w", &p[72], &p[0] ); +TESTINST_LOAD_RRR(19, "ldle.w", &p[76], &p[96]); +TESTINST_LOAD_RRR(20, "ldle.d", &p[68], &p[0] ); +TESTINST_LOAD_RRR(21, "ldle.d", &p[80], &p[0] ); +TESTINST_LOAD_RRR(22, "ldle.d", &p[88], &p[96]); + +TESTINST_STORE_RRR(23, "ldgt.b", &p[0], &p[64]); +TESTINST_STORE_RRR(24, "ldgt.b", &p[1], &p[0] ); +TESTINST_STORE_RRR(25, "ldgt.h", &p[1], &p[0] ); +TESTINST_STORE_RRR(26, "ldgt.h", &p[2], &p[64]); +TESTINST_STORE_RRR(27, "ldgt.h", &p[4], &p[0] ); +TESTINST_STORE_RRR(28, "ldgt.w", &p[2], &p[0] ); +TESTINST_STORE_RRR(29, "ldgt.w", &p[8], &p[64]); +TESTINST_STORE_RRR(30, "ldgt.w", &p[12], &p[0] ); +TESTINST_STORE_RRR(31, "ldgt.d", &p[4], &p[0] ); +TESTINST_STORE_RRR(32, "ldgt.d", &p[16], &p[64]); +TESTINST_STORE_RRR(33, "ldgt.d", &p[32], &p[0] ); + +TESTINST_STORE_RRR(34, "ldle.b", &p[64], &p[0] ); +TESTINST_STORE_RRR(35, "ldle.b", &p[65], &p[96]); +TESTINST_STORE_RRR(36, "ldle.h", &p[65], &p[0] ); +TESTINST_STORE_RRR(37, "ldle.h", &p[66], &p[0] ); +TESTINST_STORE_RRR(38, "ldle.h", &p[68], &p[96]); +TESTINST_STORE_RRR(39, "ldle.w", &p[66], &p[0] ); +TESTINST_STORE_RRR(40, "ldle.w", &p[72], &p[0] ); +TESTINST_STORE_RRR(41, "ldle.w", &p[76], &p[96]); +TESTINST_STORE_RRR(42, "ldle.d", &p[68], &p[0] ); +TESTINST_STORE_RRR(43, "ldle.d", &p[80], &p[0] ); +TESTINST_STORE_RRR(44, "ldle.d", &p[88], &p[96]); + +TESTINST_RR(45, "asrtle.d", 123, 456); +TESTINST_RR(46, "asrtle.d", 789, 0); +TESTINST_RR(47, "asrtgt.d", 123, 456); +TESTINST_RR(48, "asrtgt.d", 789, 0); + +TESTINST_I(49, "break", 0); +TESTINST_I(50, "break", 6); +TESTINST_I(51, "break", 7); +TESTINST_I(52, "break", 100); + +struct test { + void (*func)(void); + bool show; +} tests[] = { + { test1, false }, + { test2, false }, + { test3, false }, + { test4, false }, + { test5, false }, + { test6, false }, + { test7, false }, + { test8, false }, + { test9, false }, + { test10, false }, + { test11, true }, + { test12, false }, + { test13, false }, + { test14, false }, + { test15, false }, + { test16, false }, + { test17, false }, + { test18, false }, + { test19, false }, + { test20, false }, + { test21, false }, + { test22, true }, + { test23, false }, + { test24, false }, + { test25, false }, + { test26, false }, + { test27, false }, + { test28, false }, + { test29, false }, + { test30, false }, + { test31, false }, + { test32, false }, + { test33, true }, + { test34, false }, + { test35, false }, + { test36, false }, + { test37, false }, + { test38, false }, + { test39, false }, + { test40, false }, + { test41, false }, + { test42, false }, + { test43, false }, + { test44, true }, + { test45, false }, + { test46, false }, + { test47, false }, + { test48, false }, + { test49, false }, + { test50, false }, + { test51, false }, + { test52, false } +}; + +int main(void) +{ + int i; + struct sigaction sa; + int sigs[] = { SIGSYS, SIGBUS, SIGFPE, SIGTRAP }; + + sa.sa_sigaction = handler; + sa.sa_flags = SA_SIGINFO; + sigfillset(&sa.sa_mask); + + for(i = 0; i < sizeof(sigs) / sizeof(sigs[0]); i++) + sigaction(sigs[i], &sa, NULL); + + show(); + for(i = 0; i < sizeof(tests) / sizeof(tests[0]); i++) { + if (sigsetjmp(escape, 1) == 0) { + fprintf(stderr, "test %d\n", i + 1); + tests[i].func(); + if (tests[i].show) + show(); + fprintf(stderr, "no fault\n"); + } + } + + return 0; +} diff --git a/none/tests/loongarch64/fault.stderr.exp b/none/tests/loongarch64/fault.stderr.exp new file mode 100644 index 0000000..3f56668 --- /dev/null +++ b/none/tests/loongarch64/fault.stderr.exp @@ -0,0 +1,138 @@ +test 1 +signal: 31 +code: 128 +test 2 +no fault +test 3 +signal: 7 +code: 1 +test 4 +signal: 31 +code: 128 +test 5 +no fault +test 6 +signal: 7 +code: 1 +test 7 +signal: 31 +code: 128 +test 8 +no fault +test 9 +signal: 7 +code: 1 +test 10 +signal: 31 +code: 128 +test 11 +no fault +test 12 +signal: 31 +code: 128 +test 13 +no fault +test 14 +signal: 7 +code: 1 +test 15 +signal: 31 +code: 128 +test 16 +no fault +test 17 +signal: 7 +code: 1 +test 18 +signal: 31 +code: 128 +test 19 +no fault +test 20 +signal: 7 +code: 1 +test 21 +signal: 31 +code: 128 +test 22 +no fault +test 23 +signal: 31 +code: 128 +test 24 +no fault +test 25 +signal: 7 +code: 1 +test 26 +signal: 31 +code: 128 +test 27 +no fault +test 28 +signal: 7 +code: 1 +test 29 +signal: 31 +code: 128 +test 30 +no fault +test 31 +signal: 7 +code: 1 +test 32 +signal: 31 +code: 128 +test 33 +no fault +test 34 +signal: 31 +code: 128 +test 35 +no fault +test 36 +signal: 7 +code: 1 +test 37 +signal: 31 +code: 128 +test 38 +no fault +test 39 +signal: 7 +code: 1 +test 40 +signal: 31 +code: 128 +test 41 +no fault +test 42 +signal: 7 +code: 1 +test 43 +signal: 31 +code: 128 +test 44 +no fault +test 45 +no fault +test 46 +signal: 31 +code: 128 +test 47 +signal: 31 +code: 128 +test 48 +no fault +test 49 +signal: 5 +code: 1 +test 50 +signal: 8 +code: 2 +test 51 +signal: 8 +code: 1 +test 52 +signal: 5 +code: 1 diff --git a/none/tests/loongarch64/fault.stdout.exp b/none/tests/loongarch64/fault.stdout.exp new file mode 100644 index 0000000..d2e342d --- /dev/null +++ b/none/tests/loongarch64/fault.stdout.exp @@ -0,0 +1,267 @@ +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x0000000000010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0x232f2e2f2ab05fd0 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test 1 +ldgt.b :: +test 2 +ldgt.b :: +output: -26 +test 3 +ldgt.h :: +test 4 +ldgt.h :: +test 5 +ldgt.h :: +output: 7711 +test 6 +ldgt.w :: +test 7 +ldgt.w :: +test 8 +ldgt.w :: +output: 0 +test 9 +ldgt.d :: +test 10 +ldgt.d :: +test 11 +ldgt.d :: +output: 2535295895347421136 +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x0000000000010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0x232f2e2f2ab05fd0 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test 12 +ldle.b :: +test 13 +ldle.b :: +output: -33 +test 14 +ldle.h :: +test 15 +ldle.h :: +test 16 +ldle.h :: +output: 16190 +test 17 +ldle.w :: +test 18 +ldle.w :: +test 19 +ldle.w :: +output: 1043676476 +test 20 +ldle.d :: +test 21 +ldle.d :: +test 22 +ldle.d :: +output: 4266944292251042560 +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x0000000000010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0x232f2e2f2ab05fd0 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test 23 +ldgt.b :: +input: -149539557700451551 +test 24 +ldgt.b :: +input: -149539557700451551 +test 25 +ldgt.h :: +input: -149539557700451551 +test 26 +ldgt.h :: +input: -149539557700451551 +test 27 +ldgt.h :: +input: -149539557700451551 +test 28 +ldgt.w :: +input: -149539557700451551 +test 29 +ldgt.w :: +input: -149539557700451551 +test 30 +ldgt.w :: +input: -149539557700451551 +test 31 +ldgt.d :: +input: -149539557700451551 +test 32 +ldgt.d :: +input: -149539557700451551 +test 33 +ldgt.d :: +input: -149539557700451551 +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x0000000000010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0x232f2e2f2ab05fd0 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test 34 +ldle.b :: +input: -149539557700451551 +test 35 +ldle.b :: +input: -149539557700451551 +test 36 +ldle.h :: +input: -149539557700451551 +test 37 +ldle.h :: +input: -149539557700451551 +test 38 +ldle.h :: +input: -149539557700451551 +test 39 +ldle.w :: +input: -149539557700451551 +test 40 +ldle.w :: +input: -149539557700451551 +test 41 +ldle.w :: +input: -149539557700451551 +test 42 +ldle.d :: +input: -149539557700451551 +test 43 +ldle.d :: +input: -149539557700451551 +test 44 +ldle.d :: +input: -149539557700451551 +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x0000000000010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0x232f2e2f2ab05fd0 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test 45 +asrtle.d :: +input: 123 456 +test 46 +asrtle.d :: +input: 789 0 +test 47 +asrtgt.d :: +input: 123 456 +test 48 +asrtgt.d :: +input: 789 0 +test 49 +break :: +input: 0 +test 50 +break :: +input: 6 +test 51 +break :: +input: 7 +test 52 +break :: +input: 100 diff --git a/none/tests/loongarch64/fault.vgtest b/none/tests/loongarch64/fault.vgtest new file mode 100644 index 0000000..24bf21a --- /dev/null +++ b/none/tests/loongarch64/fault.vgtest @@ -0,0 +1,2 @@ +prog: fault +vgopts: -q diff --git a/none/tests/loongarch64/fault_fp.c b/none/tests/loongarch64/fault_fp.c new file mode 100644 index 0000000..0d5862d --- /dev/null +++ b/none/tests/loongarch64/fault_fp.c @@ -0,0 +1,163 @@ +#include +#include +#include +#include +#include + +#define NUM 24 + +unsigned long mem[NUM] = { + 0x121f1e1f0000e680, 0x0000000000010700, 0x000000030000e7dc, + 0xffffffff0000b0d0, 0x232f2e2f2ab05fd0, 0x242c2b2b0000b6a0, + 0x252a2e2b0000be80, 0x262d2d2a0000de10, 0x3f343f3e0000df20, + 0x3e353d3c2ab05fe0, 0x363a3c3b0000dfd0, 0x3b373b3a00010300, + 0x0000e680121f1e1f, 0x0001070000000000, 0x0000e7dc00000003, + 0x0000b0d0ffffffff, 0x2ab05fd0232f2e2f, 0x0000b6a0242c2b2b, + 0x0000be80252a2e2b, 0x0000de10262d2d2a, 0x0000df203f343f3e, + 0x2ab05fe03e353d3c, 0x0000dfd0363a3c3b, 0x000103003b373b3a +}; + +long val1 = 0; +long val2 = 0xfdecba9087654321UL; +char *p = (char *)mem; + +#define TESTINST_LOAD_FRR_S(n, insn, addr1, addr2) \ + void test ## n (void) \ + { \ + printf("test %d\n", n); \ + printf("%s ::\n", insn); \ + __asm__ __volatile__( \ + insn " %0, %1, %2 \n\t" \ + : "=f" (val1) \ + : "r" (addr1), "r" (addr2) \ + : "memory"); \ + printf("output: %d\n", (int)val1); \ + } + +#define TESTINST_LOAD_FRR_D(n, insn, addr1, addr2) \ + void test ## n (void) \ + { \ + printf("test %d\n", n); \ + printf("%s ::\n", insn); \ + __asm__ __volatile__( \ + insn " %0, %1, %2 \n\t" \ + : "=f" (val1) \ + : "r" (addr1), "r" (addr2) \ + : "memory"); \ + printf("output: %ld\n", val1); \ + } + +#define TESTINST_STORE_FRR(n, insn, addr1, addr2) \ + void test ## n (void) \ + { \ + printf("test %d\n", n); \ + printf("%s ::\n", insn); \ + printf("input: %ld\n", val2); \ + __asm__ __volatile__( \ + insn " %0, %1, %2 \n\t" \ + : \ + : "f" (val2), "r" (addr1), "r" (addr2) \ + : "memory"); \ + } + +static sigjmp_buf escape; + +static void handler(int sig, siginfo_t *si, void *uc) +{ + fprintf(stderr, "signal: %d\n", sig); + fprintf(stderr, "code: %d\n", si->si_code); + siglongjmp(escape, 1); +} + +static inline void show(void) +{ + int i; + printf("memory block:\n"); + for (i = 0; i < NUM; i++) + printf("0x%lx:\t%#018lx\n", i * sizeof(unsigned long), mem[i]); +} + +TESTINST_LOAD_FRR_S(1, "fldgt.s", &p[2], &p[0] ); +TESTINST_LOAD_FRR_S(2, "fldgt.s", &p[8], &p[64]); +TESTINST_LOAD_FRR_S(3, "fldgt.s", &p[12], &p[0] ); +TESTINST_LOAD_FRR_D(4, "fldgt.d", &p[4], &p[0] ); +TESTINST_LOAD_FRR_D(5, "fldgt.d", &p[16], &p[64]); +TESTINST_LOAD_FRR_D(6, "fldgt.d", &p[32], &p[0] ); + +TESTINST_LOAD_FRR_S(7, "fldle.s", &p[66], &p[0] ); +TESTINST_LOAD_FRR_S(8, "fldle.s", &p[72], &p[0] ); +TESTINST_LOAD_FRR_S(9, "fldle.s", &p[76], &p[96]); +TESTINST_LOAD_FRR_D(10, "fldle.d", &p[68], &p[0] ); +TESTINST_LOAD_FRR_D(11, "fldle.d", &p[80], &p[0] ); +TESTINST_LOAD_FRR_D(12, "fldle.d", &p[88], &p[96]); + +TESTINST_STORE_FRR(13, "fstgt.s", &p[2], &p[0] ); +TESTINST_STORE_FRR(14, "fstgt.s", &p[8], &p[64]); +TESTINST_STORE_FRR(15, "fstgt.s", &p[12], &p[0] ); +TESTINST_STORE_FRR(16, "fstgt.d", &p[4], &p[0] ); +TESTINST_STORE_FRR(17, "fstgt.d", &p[16], &p[64]); +TESTINST_STORE_FRR(18, "fstgt.d", &p[32], &p[0] ); + +TESTINST_STORE_FRR(19, "fstle.s", &p[66], &p[0] ); +TESTINST_STORE_FRR(20, "fstle.s", &p[72], &p[0] ); +TESTINST_STORE_FRR(21, "fstle.s", &p[76], &p[96]); +TESTINST_STORE_FRR(22, "fstle.d", &p[68], &p[0] ); +TESTINST_STORE_FRR(23, "fstle.d", &p[80], &p[0] ); +TESTINST_STORE_FRR(24, "fstle.d", &p[88], &p[96]); + +struct test { + void (*func)(void); + bool show; +} tests[] = { + { test1, false }, + { test2, false }, + { test3, false }, + { test4, false }, + { test5, false }, + { test6, true }, + { test7, false }, + { test8, false }, + { test9, false }, + { test10, false }, + { test11, false }, + { test12, true }, + { test13, false }, + { test14, false }, + { test15, false }, + { test16, false }, + { test17, false }, + { test18, true }, + { test19, false }, + { test20, false }, + { test21, false }, + { test22, false }, + { test23, false }, + { test24, true } +}; + +int main(void) +{ + int i; + struct sigaction sa; + int sigs[] = { SIGSYS, SIGBUS }; + + sa.sa_sigaction = handler; + sa.sa_flags = SA_SIGINFO; + sigfillset(&sa.sa_mask); + + for(i = 0; i < sizeof(sigs) / sizeof(sigs[0]); i++) + sigaction(sigs[i], &sa, NULL); + + show(); + for(i = 0; i < sizeof(tests) / sizeof(tests[0]); i++) { + if (sigsetjmp(escape, 1) == 0) { + fprintf(stderr, "test %d\n", i + 1); + tests[i].func(); + if (tests[i].show) + show(); + fprintf(stderr, "no fault\n"); + } + } + + return 0; +} diff --git a/none/tests/loongarch64/fault_fp.stderr.exp b/none/tests/loongarch64/fault_fp.stderr.exp new file mode 100644 index 0000000..a983dea --- /dev/null +++ b/none/tests/loongarch64/fault_fp.stderr.exp @@ -0,0 +1,64 @@ +test 1 +signal: 7 +code: 1 +test 2 +signal: 31 +code: 128 +test 3 +no fault +test 4 +signal: 7 +code: 1 +test 5 +signal: 31 +code: 128 +test 6 +no fault +test 7 +signal: 7 +code: 1 +test 8 +signal: 31 +code: 128 +test 9 +no fault +test 10 +signal: 7 +code: 1 +test 11 +signal: 31 +code: 128 +test 12 +no fault +test 13 +signal: 7 +code: 1 +test 14 +signal: 31 +code: 128 +test 15 +no fault +test 16 +signal: 7 +code: 1 +test 17 +signal: 31 +code: 128 +test 18 +no fault +test 19 +signal: 7 +code: 1 +test 20 +signal: 31 +code: 128 +test 21 +no fault +test 22 +signal: 7 +code: 1 +test 23 +signal: 31 +code: 128 +test 24 +no fault diff --git a/none/tests/loongarch64/fault_fp.stdout.exp b/none/tests/loongarch64/fault_fp.stdout.exp new file mode 100644 index 0000000..254a123 --- /dev/null +++ b/none/tests/loongarch64/fault_fp.stdout.exp @@ -0,0 +1,189 @@ +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x0000000000010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0x232f2e2f2ab05fd0 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test 1 +fldgt.s :: +test 2 +fldgt.s :: +test 3 +fldgt.s :: +output: 0 +test 4 +fldgt.d :: +test 5 +fldgt.d :: +test 6 +fldgt.d :: +output: 2535295895347421136 +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x0000000000010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0x232f2e2f2ab05fd0 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test 7 +fldle.s :: +test 8 +fldle.s :: +test 9 +fldle.s :: +output: 1043676476 +test 10 +fldle.d :: +test 11 +fldle.d :: +test 12 +fldle.d :: +output: 4266944292251042560 +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x0000000000010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0x232f2e2f2ab05fd0 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test 13 +fstgt.s :: +input: -149539557700451551 +test 14 +fstgt.s :: +input: -149539557700451551 +test 15 +fstgt.s :: +input: -149539557700451551 +test 16 +fstgt.d :: +input: -149539557700451551 +test 17 +fstgt.d :: +input: -149539557700451551 +test 18 +fstgt.d :: +input: -149539557700451551 +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x8765432100010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0xfdecba9087654321 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test 19 +fstle.s :: +input: -149539557700451551 +test 20 +fstle.s :: +input: -149539557700451551 +test 21 +fstle.s :: +input: -149539557700451551 +test 22 +fstle.d :: +input: -149539557700451551 +test 23 +fstle.d :: +input: -149539557700451551 +test 24 +fstle.d :: +input: -149539557700451551 +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x8765432100010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0xfdecba9087654321 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x876543212ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0xfdecba9087654321 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a diff --git a/none/tests/loongarch64/fault_fp.vgtest b/none/tests/loongarch64/fault_fp.vgtest new file mode 100644 index 0000000..b750af8 --- /dev/null +++ b/none/tests/loongarch64/fault_fp.vgtest @@ -0,0 +1,3 @@ +prereq: ../../../tests/loongarch64_features fpu +prog: fault_fp +vgopts: -q diff --git a/none/tests/loongarch64/filter_stderr b/none/tests/loongarch64/filter_stderr new file mode 100755 index 0000000..0ae9313 --- /dev/null +++ b/none/tests/loongarch64/filter_stderr @@ -0,0 +1,3 @@ +#! /bin/sh + +../filter_stderr diff --git a/none/tests/loongarch64/float.c b/none/tests/loongarch64/float.c new file mode 100644 index 0000000..7aa1b6c --- /dev/null +++ b/none/tests/loongarch64/float.c @@ -0,0 +1,804 @@ +#include +#include + +#define NUM 24 + +const float fj_s[NUM] = { + 0, 456.25, 3, -1, + 1384.5, -7.25, 1000000000, -5786.5, + 1752, 0.015625, 0.03125, -248562.75, + -45786.5, 456, 34.03125, 45786.75, + 1752065, 107, -45667.25, -7, + -347856.5, 356047.5, -1.0, 23.0625 +}; + +const double fj_d[NUM] = { + 0, 456.25, 3, -1, + 1384.5, -7.25, 1000000000, -5786.5, + 1752, 0.015625, 0.03125, -248562.75, + -45786.5, 456, 34.03125, 45786.75, + 1752065, 107, -45667.25, -7, + -347856.5, 356047.5, -1.0, 23.0625 +}; + +const float fk_s[NUM] = { + -4578.5, 456.25, 34.03125, 4578.75, + 175, 107, -456.25, -7.25, + -3478.5, 356.5, -1.0, 23.0625, + 0, 456.25, 3, -1, + 1384.5, -7, 100, -5786.5, + 1752, 0.015625, 0.03125, -248562.75 +}; + +const double fk_d[NUM] = { + -45786.5, 456.25, 34.03125, 45786.75, + 1752065, 107, -45667.25, -7.25, + -347856.5, 356047.5, -1.0, 23.0625, + 0, 456.25, 3, -1, + 1384.5, -7, 1000000000, -5786.5, + 1752, 0.015625, 0.03125, -248562.75 +}; + +const float fa_s[NUM] = { + -347856.5, 356047.5, -1.0, 23.0625, + 1752, 0.015625, 0.03125, -248562.75, + 1384.5, -7.25, 1000000000, -5786.5, + -347856.75, 356047.75, -1.0, 23.03125, + 0, 456.25, 3, -1, + -45786.5, 456, 34.03125, 45786.03125 +}; + +const double fa_d[NUM] = { + -347856.5, 356047.5, -1.0, 23.0625, + 1752, 0.015625, 0.03125, -248562.75, + 1384.5, -7.25, 1000000000, -5786.5, + -347856.75, 356047.75, -1.0, 23.03125, + 0, 456.25, 3, -1, + -45786.5, 456, 34.03125, 45786.03125 +}; + +const int fj_w[NUM] = { + 0, 456, 3, -1, + 0xffffffff, 356, 1000000000, -5786, + 1752, 24575, 10, -248562, + -45786, 456, 34, 45786, + 1752065, 107, -45667, -7, + -347856, 0x80000000, 0xfffffff, 23 +}; + +const long fj_l[NUM] = { + 18, 25, 3, -1, + 0xffffffff, 356, 1000000, -5786, + -1, 24575, 10, -125458, + -486, 456, 34, 45786, + 0, 1700000, -45667, -7, + -347856, 0x80000000, 0xfffffff, 23 +}; + +const int cf[NUM] = { + 0, 1, 0, 1, + 1, 0, 1, 0, + 0, 0, 1, 1, + 1, 1, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1 +}; + +typedef enum { + TO_NEAREST = 0, + TO_ZERO, + TO_PLUS_INFINITY, + TO_MINUS_INFINITY +} round_mode_t; + +typedef enum { + FADD_S, FADD_D, FSUB_S, FSUB_D, + FMUL_S, FMUL_D, FDIV_S, FDIV_D, + FMADD_S, FMADD_D, FMSUB_S, FMSUB_D, + FNMADD_S, FNMADD_D, FNMSUB_S, FNMSUB_D, + FMAX_S, FMAX_D, FMIN_S, FMIN_D, + FMAXA_S, FMAXA_D, FMINA_S, FMINA_D, + FABS_S, FABS_D, FNEG_S, FNEG_D, + FSQRT_S, FSQRT_D, + FRECIP_S, FRECIP_D, + FRSQRT_S, FRSQRT_D, + FSCALEB_S, FSCALEB_D, + FLOGB_S, FLOGB_D, + FCVT_S_D, FCVT_D_S, + FTINTRM_W_S, FTINTRM_W_D, FTINTRM_L_S, FTINTRM_L_D, + FTINTRP_W_S, FTINTRP_W_D, FTINTRP_L_S, FTINTRP_L_D, + FTINTRZ_W_S, FTINTRZ_W_D, FTINTRZ_L_S, FTINTRZ_L_D, + FTINTRNE_W_S, FTINTRNE_W_D, FTINTRNE_L_S, FTINTRNE_L_D, + FTINT_W_S, FTINT_W_D, FTINT_L_S, FTINT_L_D, + FFINT_S_W, FFINT_S_L, FFINT_D_W, FFINT_D_L, + FRINT_S, FRINT_D, + FCMP_CAF_S, FCMP_CAF_D, FCMP_SAF_S, FCMP_SAF_D, + FCMP_CLT_S, FCMP_CLT_D, FCMP_SLT_S, FCMP_SLT_D, + FCMP_CEQ_S, FCMP_CEQ_D, FCMP_SEQ_S, FCMP_SEQ_D, + FCMP_CLE_S, FCMP_CLE_D, FCMP_SLE_S, FCMP_SLE_D, + FCMP_CUN_S, FCMP_CUN_D, FCMP_SUN_S, FCMP_SUN_D, + FCMP_CULT_S, FCMP_CULT_D, FCMP_SULT_S, FCMP_SULT_D, + FCMP_CUEQ_S, FCMP_CUEQ_D, FCMP_SUEQ_S, FCMP_SUEQ_D, + FCMP_CULE_S, FCMP_CULE_D, FCMP_SULE_S, FCMP_SULE_D, + FCMP_CNE_S, FCMP_CNE_D, FCMP_SNE_S, FCMP_SNE_D, + FCMP_COR_S, FCMP_COR_D, FCMP_SOR_S, FCMP_SOR_D, + FCMP_CUNE_S, FCMP_CUNE_D, FCMP_SUNE_S, FCMP_SUNE_D, + FSEL, FMOV_S, FMOV_D +} op_t; + +static inline void set_fcsr(round_mode_t mode) +{ + __asm__ __volatile__("movgr2fcsr $r0, %0" : : "r" (mode << 8)); + + const char *round_mode_name[] = { "near", "zero", "+inf", "-inf" }; + printf("roundig mode: %s\n", round_mode_name[mode]); +} + +#define TESTINST_FF_S(insn, v1) \ + { \ + unsigned int fcsr; \ + float fd_s; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_s), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.6f\n", v1); \ + printf("output: %.6f\n", fd_s); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FF_D(insn, v1) \ + { \ + unsigned int fcsr; \ + double fd_d; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_d), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.15f\n", v1); \ + printf("output: %.15f\n", fd_d); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FFF_S(insn, v1, v2) \ + { \ + unsigned int fcsr; \ + float fd_s; \ + __asm__ __volatile__( \ + insn " %0, %2, %3 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_s), "=r" (fcsr) \ + : "f" (v1), "f" (v2) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.6f %.6f\n", v1, v2); \ + printf("output: %.6f\n", fd_s); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FFF_D(insn, v1, v2) \ + { \ + unsigned int fcsr; \ + double fd_s; \ + __asm__ __volatile__( \ + insn " %0, %2, %3 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_s), "=r" (fcsr) \ + : "f" (v1), "f" (v2) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.15f %.15f\n", v1, v2); \ + printf("output: %.15f\n", fd_s); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FFFF_S(insn, v1, v2, v3) \ + { \ + unsigned int fcsr; \ + float fd_s; \ + __asm__ __volatile__( \ + insn " %0, %2, %3, %4 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_s), "=r" (fcsr) \ + : "f" (v1), "f" (v2), "f" (v3) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.6f %.6f %.6f\n", v1, v2, v3); \ + printf("output: %.6f\n", fd_s); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FFFF_D(insn, v1, v2, v3) \ + { \ + unsigned int fcsr; \ + double fd_s; \ + __asm__ __volatile__( \ + insn " %0, %2, %3, %4 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_s), "=r" (fcsr) \ + : "f" (v1), "f" (v2), "f" (v3) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.15f %.15f %.15f\n", v1, v2, v3); \ + printf("output: %.15f\n", fd_s); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FF_S_D(insn, v1) \ + { \ + unsigned int fcsr; \ + float fd_s; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_s), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.15f\n", v1); \ + printf("output: %.6f\n", fd_s); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FF_D_S(insn, v1) \ + { \ + unsigned int fcsr; \ + double fd_d; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_d), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.6f\n", v1); \ + printf("output: %.15f\n", fd_d); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FF_W_S(insn, v1) \ + { \ + unsigned int fcsr; \ + int fd_w; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_w), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.6f\n", v1); \ + printf("output: %d\n", fd_w); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FF_W_D(insn, v1) \ + { \ + unsigned int fcsr; \ + int fd_w; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_w), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.15f\n", v1); \ + printf("output: %d\n", fd_w); \ + printf("fcsr: %#x\n", fcsr); \ + } +#define TESTINST_FF_L_S(insn, v1) \ + { \ + unsigned int fcsr; \ + long fd_l; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_l), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.6f\n", v1); \ + printf("output: %ld\n", fd_l); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FF_L_D(insn, v1) \ + { \ + unsigned int fcsr; \ + long fd_l; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_l), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.15f\n", v1); \ + printf("output: %ld\n", fd_l); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FF_S_W(insn, v1) \ + { \ + unsigned int fcsr; \ + float fd_s; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_s), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %d\n", v1); \ + printf("output: %.6f\n", fd_s); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FF_S_L(insn, v1) \ + { \ + unsigned int fcsr; \ + float fd_s; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_s), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %ld\n", v1); \ + printf("output: %.6f\n", fd_s); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FF_D_W(insn, v1) \ + { \ + unsigned int fcsr; \ + double fd_d; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_d), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %d\n", v1); \ + printf("output: %.15f\n", fd_d); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FF_D_L(insn, v1) \ + { \ + unsigned int fcsr; \ + double fd_d; \ + __asm__ __volatile__( \ + insn " %0, %2 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_d), "=r" (fcsr) \ + : "f" (v1) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %ld\n", v1); \ + printf("output: %.15f\n", fd_d); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FFC_S(insn, v1, v2) \ + { \ + unsigned int fcsr; \ + int fcc; \ + __asm__ __volatile__( \ + insn " $fcc0, %2, %3 \n\t" \ + "movcf2gr %0, $fcc0 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=r" (fcc), "=r" (fcsr) \ + : "f" (v1), "f" (v2) \ + : "$fcc0", "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.6f %.6f\n", v1, v2); \ + printf("output: %d\n", fcc); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FFC_D(insn, v1, v2) \ + { \ + unsigned int fcsr; \ + int fcc; \ + __asm__ __volatile__( \ + insn " $fcc0, %2, %3 \n\t" \ + "movcf2gr %0, $fcc0 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=r" (fcc), "=r" (fcsr) \ + : "f" (v1), "f" (v2) \ + : "$fcc0", "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.15f %.15f\n", v1, v2); \ + printf("output: %d\n", fcc); \ + printf("fcsr: %#x\n", fcsr); \ + } + +#define TESTINST_FFFC(insn, v1, v2, v3) \ + { \ + unsigned int fcsr; \ + double fd_s; \ + __asm__ __volatile__( \ + "movgr2cf $fcc0, %4 \n\t" \ + insn " %0, %2, %3, $fcc0 \n\t" \ + "movfcsr2gr %1, $r0 \n\t" \ + : "=f" (fd_s), "=r" (fcsr) \ + : "f" (v1), "f" (v2), "r" (v3) \ + : "memory"); \ + printf("%s ::\n", insn); \ + printf("input: %.15f %.15f %d\n", v1, v2, v3); \ + printf("output: %.15f\n", fd_s); \ + printf("fcsr: %#x\n", fcsr); \ + } + +void test(op_t op) +{ + int i; + round_mode_t mode; + for (mode = TO_NEAREST; mode <= TO_MINUS_INFINITY; mode++) { + for (i = 0; i < NUM; i++) { + set_fcsr(mode); + switch (op) { + case FADD_S: + TESTINST_FFF_S("fadd.s", fj_s[i], fk_s[i]); + break; + case FADD_D: + TESTINST_FFF_D("fadd.d", fj_d[i], fk_d[i]); + break; + case FSUB_S: + TESTINST_FFF_S("fsub.s", fj_s[i], fk_s[i]); + break; + case FSUB_D: + TESTINST_FFF_D("fsub.d", fj_d[i], fk_d[i]); + break; + case FMUL_S: + TESTINST_FFF_S("fmul.s", fj_s[i], fk_s[i]); + break; + case FMUL_D: + TESTINST_FFF_D("fmul.d", fj_d[i], fk_d[i]); + break; + case FDIV_S: + TESTINST_FFF_S("fdiv.s", fj_s[i], fk_s[i]); + break; + case FDIV_D: + TESTINST_FFF_D("fdiv.d", fj_d[i], fk_d[i]); + break; + case FMADD_S: + TESTINST_FFFF_S("fmadd.s", fj_s[i], fk_s[i], fa_s[i]); + break; + case FMADD_D: + TESTINST_FFFF_D("fmadd.d", fj_d[i], fk_d[i], fa_d[i]); + break; + case FMSUB_S: + TESTINST_FFFF_S("fmsub.s", fj_s[i], fk_s[i], fa_s[i]); + break; + case FMSUB_D: + TESTINST_FFFF_D("fmsub.d", fj_d[i], fk_d[i], fa_d[i]); + break; + case FNMADD_S: + TESTINST_FFFF_S("fnmadd.s", fj_s[i], fk_s[i], fa_s[i]); + break; + case FNMADD_D: + TESTINST_FFFF_D("fnmadd.d", fj_d[i], fk_d[i], fa_d[i]); + break; + case FNMSUB_S: + TESTINST_FFFF_S("fnmsub.s", fj_s[i], fk_s[i], fa_s[i]); + break; + case FNMSUB_D: + TESTINST_FFFF_D("fnmsub.d", fj_d[i], fk_d[i], fa_d[i]); + break; + case FMAX_S: + TESTINST_FFF_S("fmax.s", fj_s[i], fk_s[i]); + break; + case FMAX_D: + TESTINST_FFF_D("fmax.d", fj_d[i], fk_d[i]); + break; + case FMIN_S: + TESTINST_FFF_S("fmin.s", fj_s[i], fk_s[i]); + break; + case FMIN_D: + TESTINST_FFF_D("fmin.d", fj_d[i], fk_d[i]); + break; + case FMAXA_S: + TESTINST_FFF_S("fmaxa.s", fj_s[i], fk_s[i]); + break; + case FMAXA_D: + TESTINST_FFF_D("fmaxa.d", fj_d[i], fk_d[i]); + break; + case FMINA_S: + TESTINST_FFF_S("fmina.s", fj_s[i], fk_s[i]); + break; + case FMINA_D: + TESTINST_FFF_D("fmina.d", fj_d[i], fk_d[i]); + break; + case FABS_S: + TESTINST_FF_S("fabs.s", fj_s[i]); + break; + case FABS_D: + TESTINST_FF_D("fabs.d", fj_d[i]); + break; + case FNEG_S: + TESTINST_FF_S("fneg.s", fj_s[i]); + break; + case FNEG_D: + TESTINST_FF_D("fneg.d", fj_d[i]); + break; + case FSQRT_S: + TESTINST_FF_S("fsqrt.s", fj_s[i]); + break; + case FSQRT_D: + TESTINST_FF_D("fsqrt.d", fj_d[i]); + break; + case FRECIP_S: + TESTINST_FF_S("frecip.s", fj_s[i]); + break; + case FRECIP_D: + TESTINST_FF_D("frecip.d", fj_d[i]); + break; + case FRSQRT_S: + TESTINST_FF_S("frsqrt.s", fj_s[i]); + break; + case FRSQRT_D: + TESTINST_FF_D("frsqrt.d", fj_d[i]); + break; + case FSCALEB_S: + TESTINST_FFF_S("fscaleb.s", fj_s[i], fk_s[i]); + break; + case FSCALEB_D: + TESTINST_FFF_D("fscaleb.d", fj_d[i], fk_d[i]); + break; + case FLOGB_S: + TESTINST_FF_S("flogb.s", fj_s[i]); + break; + case FLOGB_D: + TESTINST_FF_D("flogb.d", fj_d[i]); + break; + case FCVT_S_D: + TESTINST_FF_S_D("fcvt.s.d", fj_d[i]); + break; + case FCVT_D_S: + TESTINST_FF_D_S("fcvt.d.s", fj_s[i]); + break; + case FTINTRM_W_S: + TESTINST_FF_W_S("ftintrm.w.s", fj_s[i]); + break; + case FTINTRM_W_D: + TESTINST_FF_W_D("ftintrm.w.d", fj_d[i]); + break; + case FTINTRM_L_S: + TESTINST_FF_L_S("ftintrm.l.s", fj_s[i]); + break; + case FTINTRM_L_D: + TESTINST_FF_L_D("ftintrm.l.d", fj_d[i]); + break; + case FTINTRP_W_S: + TESTINST_FF_W_S("ftintrp.w.s", fj_s[i]); + break; + case FTINTRP_W_D: + TESTINST_FF_W_D("ftintrp.w.d", fj_d[i]); + break; + case FTINTRP_L_S: + TESTINST_FF_L_S("ftintrp.l.s", fj_s[i]); + break; + case FTINTRP_L_D: + TESTINST_FF_L_D("ftintrp.l.d", fj_d[i]); + break; + case FTINTRZ_W_S: + TESTINST_FF_W_S("ftintrz.w.s", fj_s[i]); + break; + case FTINTRZ_W_D: + TESTINST_FF_W_D("ftintrz.w.d", fj_d[i]); + break; + case FTINTRZ_L_S: + TESTINST_FF_L_S("ftintrz.l.s", fj_s[i]); + break; + case FTINTRZ_L_D: + TESTINST_FF_L_D("ftintrz.l.d", fj_d[i]); + break; + case FTINTRNE_W_S: + TESTINST_FF_W_S("ftintrne.w.s", fj_s[i]); + break; + case FTINTRNE_W_D: + TESTINST_FF_W_D("ftintrne.w.d", fj_d[i]); + break; + case FTINTRNE_L_S: + TESTINST_FF_L_S("ftintrne.l.s", fj_s[i]); + break; + case FTINTRNE_L_D: + TESTINST_FF_L_D("ftintrne.l.d", fj_d[i]); + break; + case FTINT_W_S: + TESTINST_FF_W_S("ftint.w.s", fj_s[i]); + break; + case FTINT_W_D: + TESTINST_FF_W_D("ftint.w.d", fj_d[i]); + break; + case FTINT_L_S: + TESTINST_FF_L_S("ftint.l.s", fj_s[i]); + break; + case FTINT_L_D: + TESTINST_FF_L_D("ftint.l.d", fj_d[i]); + break; + case FFINT_S_W: + TESTINST_FF_S_W("ffint.s.w", fj_w[i]); + break; + case FFINT_S_L: + TESTINST_FF_S_L("ffint.s.l", fj_l[i]); + break; + case FFINT_D_W: + TESTINST_FF_D_W("ffint.d.w", fj_w[i]); + break; + case FFINT_D_L: + TESTINST_FF_D_L("ffint.d.l", fj_l[i]); + break; + case FRINT_S: + TESTINST_FF_S("frint.s", fj_s[i]); + break; + case FRINT_D: + TESTINST_FF_D("frint.d", fj_d[i]); + break; + case FCMP_CAF_S: + TESTINST_FFC_S("fcmp.caf.s", fj_s[i], fk_s[i]); + break; + case FCMP_CAF_D: + TESTINST_FFC_D("fcmp.caf.d", fj_d[i], fk_d[i]); + break; + case FCMP_SAF_S: + TESTINST_FFC_S("fcmp.saf.s", fj_s[i], fk_s[i]); + break; + case FCMP_SAF_D: + TESTINST_FFC_D("fcmp.saf.d", fj_d[i], fk_d[i]); + break; + case FCMP_CLT_S: + TESTINST_FFC_S("fcmp.clt.s", fj_s[i], fk_s[i]); + break; + case FCMP_CLT_D: + TESTINST_FFC_D("fcmp.clt.d", fj_d[i], fk_d[i]); + break; + case FCMP_SLT_S: + TESTINST_FFC_S("fcmp.slt.s", fj_s[i], fk_s[i]); + break; + case FCMP_SLT_D: + TESTINST_FFC_D("fcmp.slt.d", fj_d[i], fk_d[i]); + break; + case FCMP_CEQ_S: + TESTINST_FFC_S("fcmp.ceq.s", fj_s[i], fk_s[i]); + break; + case FCMP_CEQ_D: + TESTINST_FFC_D("fcmp.ceq.d", fj_d[i], fk_d[i]); + break; + case FCMP_SEQ_S: + TESTINST_FFC_S("fcmp.seq.s", fj_s[i], fk_s[i]); + break; + case FCMP_SEQ_D: + TESTINST_FFC_D("fcmp.seq.d", fj_d[i], fk_d[i]); + break; + case FCMP_CLE_S: + TESTINST_FFC_S("fcmp.cle.s", fj_s[i], fk_s[i]); + break; + case FCMP_CLE_D: + TESTINST_FFC_D("fcmp.cle.d", fj_d[i], fk_d[i]); + break; + case FCMP_SLE_S: + TESTINST_FFC_S("fcmp.sle.s", fj_s[i], fk_s[i]); + break; + case FCMP_SLE_D: + TESTINST_FFC_D("fcmp.sle.d", fj_d[i], fk_d[i]); + break; + case FCMP_CUN_S: + TESTINST_FFC_S("fcmp.cun.s", fj_s[i], fk_s[i]); + break; + case FCMP_CUN_D: + TESTINST_FFC_D("fcmp.cun.d", fj_d[i], fk_d[i]); + break; + case FCMP_SUN_S: + TESTINST_FFC_S("fcmp.sun.s", fj_s[i], fk_s[i]); + break; + case FCMP_SUN_D: + TESTINST_FFC_D("fcmp.sun.d", fj_d[i], fk_d[i]); + break; + case FCMP_CULT_S: + TESTINST_FFC_S("fcmp.cult.s", fj_s[i], fk_s[i]); + break; + case FCMP_CULT_D: + TESTINST_FFC_D("fcmp.cult.d", fj_d[i], fk_d[i]); + break; + case FCMP_SULT_S: + TESTINST_FFC_S("fcmp.sult.s", fj_s[i], fk_s[i]); + break; + case FCMP_SULT_D: + TESTINST_FFC_D("fcmp.sult.d", fj_d[i], fk_d[i]); + break; + case FCMP_CUEQ_S: + TESTINST_FFC_S("fcmp.cueq.s", fj_s[i], fk_s[i]); + break; + case FCMP_CUEQ_D: + TESTINST_FFC_D("fcmp.cueq.d", fj_d[i], fk_d[i]); + break; + case FCMP_SUEQ_S: + TESTINST_FFC_S("fcmp.sueq.s", fj_s[i], fk_s[i]); + break; + case FCMP_SUEQ_D: + TESTINST_FFC_D("fcmp.sueq.d", fj_d[i], fk_d[i]); + break; + case FCMP_CULE_S: + TESTINST_FFC_S("fcmp.cule.s", fj_s[i], fk_s[i]); + break; + case FCMP_CULE_D: + TESTINST_FFC_D("fcmp.cule.d", fj_d[i], fk_d[i]); + break; + case FCMP_SULE_S: + TESTINST_FFC_S("fcmp.sule.s", fj_s[i], fk_s[i]); + break; + case FCMP_SULE_D: + TESTINST_FFC_D("fcmp.sule.d", fj_d[i], fk_d[i]); + break; + case FCMP_CNE_S: + TESTINST_FFC_S("fcmp.cne.s", fj_s[i], fk_s[i]); + break; + case FCMP_CNE_D: + TESTINST_FFC_D("fcmp.cne.d", fj_d[i], fk_d[i]); + break; + case FCMP_SNE_S: + TESTINST_FFC_S("fcmp.sne.s", fj_s[i], fk_s[i]); + break; + case FCMP_SNE_D: + TESTINST_FFC_D("fcmp.sne.d", fj_d[i], fk_d[i]); + break; + case FCMP_COR_S: + TESTINST_FFC_S("fcmp.cor.s", fj_s[i], fk_s[i]); + break; + case FCMP_COR_D: + TESTINST_FFC_D("fcmp.cor.d", fj_d[i], fk_d[i]); + break; + case FCMP_SOR_S: + TESTINST_FFC_S("fcmp.sor.s", fj_s[i], fk_s[i]); + break; + case FCMP_SOR_D: + TESTINST_FFC_D("fcmp.sor.d", fj_d[i], fk_d[i]); + break; + case FCMP_CUNE_S: + TESTINST_FFC_S("fcmp.cune.s", fj_s[i], fk_s[i]); + break; + case FCMP_CUNE_D: + TESTINST_FFC_D("fcmp.cune.d", fj_d[i], fk_d[i]); + break; + case FCMP_SUNE_S: + TESTINST_FFC_S("fcmp.sune.s", fj_s[i], fk_s[i]); + break; + case FCMP_SUNE_D: + TESTINST_FFC_D("fcmp.sune.d", fj_d[i], fk_d[i]); + break; + case FSEL: + TESTINST_FFFC("fsel", fj_d[i], fk_d[i], cf[i]); + break; + case FMOV_S: + TESTINST_FF_S("fmov.s", fj_s[i]); + break; + case FMOV_D: + TESTINST_FF_D("fmov.d", fj_d[i]); + break; + default: + assert(0); + break; + } + } + } +} + +int main(void) +{ + op_t op; + for (op = FADD_S; op <= FMOV_D; op++) + test(op); + return 0; +} diff --git a/none/tests/loongarch64/float.stderr.exp b/none/tests/loongarch64/float.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/float.stdout.exp b/none/tests/loongarch64/float.stdout.exp new file mode 100644 index 0000000..f4914ff --- /dev/null +++ b/none/tests/loongarch64/float.stdout.exp @@ -0,0 +1,54240 @@ +roundig mode: near +fadd.s :: +input: 0.000000 -4578.500000 +output: -4578.500000 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 456.250000 456.250000 +output: 912.500000 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 3.000000 34.031250 +output: 37.031250 +fcsr: 0 +roundig mode: near +fadd.s :: +input: -1.000000 4578.750000 +output: 4577.750000 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 1384.500000 175.000000 +output: 1559.500000 +fcsr: 0 +roundig mode: near +fadd.s :: +input: -7.250000 107.000000 +output: 99.750000 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 1000000000.000000 -456.250000 +output: 999999552.000000 +fcsr: 0x1010000 +roundig mode: near +fadd.s :: +input: -5786.500000 -7.250000 +output: -5793.750000 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 1752.000000 -3478.500000 +output: -1726.500000 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 0.015625 356.500000 +output: 356.515625 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 0.031250 -1.000000 +output: -0.968750 +fcsr: 0 +roundig mode: near +fadd.s :: +input: -248562.750000 23.062500 +output: -248539.687500 +fcsr: 0 +roundig mode: near +fadd.s :: +input: -45786.500000 0.000000 +output: -45786.500000 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 456.000000 456.250000 +output: 912.250000 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 34.031250 3.000000 +output: 37.031250 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 45786.750000 -1.000000 +output: 45785.750000 +fcsr: 0 +roundig mode: near +fadd.s :: +input: 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45786.750000000000000 +fcsr: 0x300 +roundig mode: -inf +fmov.d :: +input: 1752065.000000000000000 +output: 1752065.000000000000000 +fcsr: 0x300 +roundig mode: -inf +fmov.d :: +input: 107.000000000000000 +output: 107.000000000000000 +fcsr: 0x300 +roundig mode: -inf +fmov.d :: +input: -45667.250000000000000 +output: -45667.250000000000000 +fcsr: 0x300 +roundig mode: -inf +fmov.d :: +input: -7.000000000000000 +output: -7.000000000000000 +fcsr: 0x300 +roundig mode: -inf +fmov.d :: +input: -347856.500000000000000 +output: -347856.500000000000000 +fcsr: 0x300 +roundig mode: -inf +fmov.d :: +input: 356047.500000000000000 +output: 356047.500000000000000 +fcsr: 0x300 +roundig mode: -inf +fmov.d :: +input: -1.000000000000000 +output: -1.000000000000000 +fcsr: 0x300 +roundig mode: -inf +fmov.d :: +input: 23.062500000000000 +output: 23.062500000000000 +fcsr: 0x300 diff --git a/none/tests/loongarch64/float.vgtest b/none/tests/loongarch64/float.vgtest new file mode 100644 index 0000000..e65d969 --- /dev/null +++ b/none/tests/loongarch64/float.vgtest @@ -0,0 +1,3 @@ +prereq: ../../../tests/loongarch64_features fpu +prog: float +vgopts: -q diff --git a/none/tests/loongarch64/integer.c b/none/tests/loongarch64/integer.c new file mode 100644 index 0000000..369d628 --- /dev/null +++ b/none/tests/loongarch64/integer.c @@ -0,0 +1,1311 @@ +#include +#include + +typedef enum { + SA2, SA2_1 /* for alsl */, SA3, + MSBW, LSBW, MSBD, LSBD, + UI5, UI6, UI12, + SI12, SI14, SI16, SI20 +} imm_t; + +static inline void showImm (unsigned int i, imm_t ty) +{ + switch (ty) { + case SA2: + assert(i < (1 << 2)); + break; + case SA2_1: + assert(i < (1 << 3)); + break; + case SA3: + assert(i < (1 << 3)); + break; + case MSBW: + assert(i < (1 << 5)); + break; + case LSBW: + assert(i < (1 << 5)); + break; + case MSBD: + assert(i < (1 << 6)); + break; + case LSBD: + assert(i < (1 << 6)); + break; + case UI5: + assert(i < (1 << 5)); + break; + case UI6: + assert(i < (1 << 6)); + break; + case UI12: + assert(i < (1 << 12)); + break; + case SI12: + assert(i < (1 << 12) || (i >> 12) == 0xfffff); + break; + case SI14: + assert(i < (1 << 14) || (i >> 14) == 0x3ffff); + break; + case SI16: + assert(i < (1 << 16) || (i >> 16) == 0xffff); + break; + case SI20: + assert(i < (1 << 20) || (i >> 20) == 0xfff); + break; + default: + assert(0); + break; + } + printf("%d", i); +} + +#define TESTINST_RR(insn, rd, rj, v1, v2) \ + { \ + unsigned long res1, res2; \ + unsigned long val1 = (unsigned long)v1; \ + unsigned long val2 = (unsigned long)v2; \ + __asm__ __volatile__( \ + "move " rd ", %2 \n\t" \ + "move " rj ", %3 \n\t" \ + insn " " rd ", " rj " \n\t" \ + "move %0, " rd " \n\t" \ + "move %1, " rj " \n\t" \ + : "=r" (res1), "=r" (res2) \ + : "r" (val1), "r" (val2) \ + : rd, rj, "memory"); \ + printf("%s %s, %s ::\n", insn, rd, rj); \ + printf("before: %s=%#018lx, %s=%#018lx\n", \ + rd, val1, rj, val2); \ + printf("after: %s=%#018lx, %s=%#018lx\n", \ + rd, res1, rj, res2); \ + } + +#define TESTINST_RI(insn, rd, type, v1, imm) \ + { \ + unsigned long res1; \ + unsigned long val1 = (unsigned long)v1; \ + __asm__ __volatile__( \ + "move " rd ", %1 \n\t" \ + insn " " rd ", " #imm "\n\t" \ + "move %0, " rd " \n\t" \ + : "=r" (res1) \ + : "r" (val1) \ + : rd, "memory"); \ + printf("%s %s, ", insn, rd); \ + showImm(imm, type); \ + printf(" ::\n"); \ + printf("before: %s=%#018lx\n", rd, val1); \ + printf("after: %s=%#018lx\n", rd, res1); \ + } + +#define TESTINST_RRRI(insn, rd, rj, rk, type, v1, v2, v3, imm) \ + { \ + unsigned long res1, res2, res3; \ + unsigned long val1 = (unsigned long)v1; \ + unsigned long val2 = (unsigned long)v2; \ + unsigned long val3 = (unsigned long)v3; \ + __asm__ __volatile__( \ + "move " rd ", %3 \n\t" \ + "move " rj ", %4 \n\t" \ + "move " rk ", %5 \n\t" \ + insn " " rd ", " rj ", " rk ", " #imm "\n\t" \ + "move %0, " rd " \n\t" \ + "move %1, " rj " \n\t" \ + "move %2, " rk " \n\t" \ + : "=r" (res1), "=r" (res2), "=r" (res3) \ + : "r" (val1), "r" (val2), "r" (val3) \ + : rd, rj, rk, "memory"); \ + printf("%s %s, %s, %s, ", insn, rd, rj, rk); \ + showImm(imm, type); \ + printf(" ::\n"); \ + printf("before: %s=%#018lx, %s=%#018lx, %s=%#018lx\n", \ + rd, val1, rj, val2, rk, val3); \ + printf("after: %s=%#018lx, %s=%#018lx, %s=%#018lx\n", \ + rd, res1, rj, res2, rk, res3); \ + } + +#define TESTINST_RRR(insn, rd, rj, rk, v1, v2, v3) \ + { \ + unsigned long res1, res2, res3; \ + unsigned long val1 = (unsigned long)v1; \ + unsigned long val2 = (unsigned long)v2; \ + unsigned long val3 = (unsigned long)v3; \ + __asm__ __volatile__( \ + "move " rd ", %3 \n\t" \ + "move " rj ", %4 \n\t" \ + "move " rk ", %5 \n\t" \ + insn " " rd ", " rj ", " rk "\n\t" \ + "move %0, " rd " \n\t" \ + "move %1, " rj " \n\t" \ + "move %2, " rk " \n\t" \ + : "=r" (res1), "=r" (res2), "=r" (res3) \ + : "r" (val1), "r" (val2), "r" (val3) \ + : rd, rj, rk, "memory"); \ + printf("%s %s, %s, %s ::\n", insn, rd, rj, rk); \ + printf("before: %s=%#018lx, %s=%#018lx, %s=%#018lx\n", \ + rd, val1, rj, val2, rk, val3); \ + printf("after: %s=%#018lx, %s=%#018lx, %s=%#018lx\n", \ + rd, res1, rj, res2, rk, res3); \ + } + +#define TESTINST_RRI(insn, rd, rj, type, v1, v2, imm) \ + { \ + unsigned long res1, res2; \ + unsigned long val1 = (unsigned long)v1; \ + unsigned long val2 = (unsigned long)v2; \ + __asm__ __volatile__( \ + "move " rd ", %2 \n\t" \ + "move " rj ", %3 \n\t" \ + insn " " rd ", " rj ", " #imm "\n\t" \ + "move %0, " rd " \n\t" \ + "move %1, " rj " \n\t" \ + : "=r" (res1), "=r" (res2) \ + : "r" (val1), "r" (val2) \ + : rd, rj, "memory"); \ + printf("%s %s, %s, ", insn, rd, rj); \ + showImm(imm, type); \ + printf(" ::\n"); \ + printf("before: %s=%#018lx, %s=%#018lx\n", \ + rd, val1, rj, val2); \ + printf("after: %s=%#018lx, %s=%#018lx\n", \ + rd, res1, rj, res2); \ + } + +#define TESTINST_RRII(insn, rd, rj, type1, type2, v1, v2, imm1, imm2) \ + { \ + unsigned long res1, res2; \ + unsigned long val1 = (unsigned long)v1; \ + unsigned long val2 = (unsigned long)v2; \ + __asm__ __volatile__( \ + "move " rd ", %2 \n\t" \ + "move " rj ", %3 \n\t" \ + insn " " rd ", " rj ", " #imm1 ", " #imm2 "\n\t" \ + "move %0, " rd " \n\t" \ + "move %1, " rj " \n\t" \ + : "=r" (res1), "=r" (res2) \ + : "r" (val1), "r" (val2) \ + : rd, rj, "memory"); \ + printf("%s %s, %s, ", insn, rd, rj); \ + showImm(imm1, type1); \ + printf(", "); \ + showImm(imm2, type2); \ + printf(" ::\n"); \ + printf("before: %s=%#018lx, %s=%#018lx\n", \ + rd, val1, rj, val2); \ + printf("after: %s=%#018lx, %s=%#018lx\n", \ + rd, res1, rj, res2); \ + } + +void test(void) +{ + /* ---------------- add.w rd, rj, rk ---------------- */ + TESTINST_RRR("add.w", "$r19", "$r20", "$r25", 0xf7f01ffbc9696094UL, 0xb664b1ce21c8c7fcUL, 0xd0a02b79ace85cfUL); + TESTINST_RRR("add.w", "$r29", "$r9", "$r12", 0x5418cd6f6b640953UL, 0x6465907ca2dac58cUL, 0xefea76d0d526df3aUL); + TESTINST_RRR("add.w", "$r23", "$r15", "$r28", 0x6ae34fbc6f2f7a9aUL, 0xbf21c48ab5c2edccUL, 0x24824ebd458ed20eUL); + TESTINST_RRR("add.w", "$r27", "$r14", "$r26", 0x9f33e38db05616ccUL, 0xf12ee0c276c52c78UL, 0xc3054d65ecec3fe6UL); + TESTINST_RRR("add.w", "$r14", "$r23", "$r27", 0x17eaa07c4607901fUL, 0xa5fa9d0c8472848eUL, 0xa34301227bb57f76UL); + TESTINST_RRR("add.w", "$r19", "$r19", "$r4", 0xd2e0644d9532b5eaUL, 0x2957c6f0638238bcUL, 0xf01566d0031ee917UL); + TESTINST_RRR("add.w", "$r19", "$r26", "$r13", 0x7b39b3f2ccbdaf79UL, 0xee877221beef9d45UL, 0x4a743034eefe075dUL); + TESTINST_RRR("add.w", "$r29", "$r18", "$r14", 0x95214c4de7e6d3baUL, 0x26502eb481799cd1UL, 0x34d57b775083fb91UL); + TESTINST_RRR("add.w", "$r16", "$r26", "$r8", 0xb66b18865bbb3036UL, 0x8881ccbe1e31aa8dUL, 0xffe0d2dde8325edcUL); + TESTINST_RRR("add.w", "$r26", "$r5", "$r8", 0xc367af71c905540cUL, 0xcdcbe4860d983fe3UL, 0x6687aa19ee1fc503UL); + + /* ---------------- add.d rd, rj, rk ---------------- */ + TESTINST_RRR("add.d", "$r16", "$r18", "$r8", 0xbe5505b409ce995cUL, 0x561a85fd57e87226UL, 0x923f3293987edab0UL); + TESTINST_RRR("add.d", "$r12", "$r7", "$r29", 0xff2682151edc3476UL, 0x90beb037eacfe3dbUL, 0xa4017082880f1151UL); + TESTINST_RRR("add.d", "$r31", "$r31", "$r5", 0x81e38385e39d9f16UL, 0xedb2ffa50c0c8b5fUL, 0x8776f30d75fc97c2UL); + TESTINST_RRR("add.d", "$r31", "$r6", "$r26", 0x64ff385d97b60dc2UL, 0x80f903f206f08f60UL, 0x4f5b589532e85398UL); + TESTINST_RRR("add.d", "$r25", "$r10", "$r20", 0xdd8973d6b99634caUL, 0x34c0fe5a72dd43d9UL, 0x2494af03cf5878e7UL); + TESTINST_RRR("add.d", "$r5", "$r10", "$r4", 0x94b272b05ffe39c8UL, 0x152d15efbbc54c04UL, 0x25afc06cf151ab29UL); + TESTINST_RRR("add.d", "$r19", "$r30", "$r18", 0xa6e14d42459cadf6UL, 0x558620ff616141b1UL, 0x1978905697120747UL); + TESTINST_RRR("add.d", "$r7", "$r8", "$r20", 0x2ea6f88031a29aeUL, 0x6a08c12301e00d49UL, 0xdd533acf17f59142UL); + TESTINST_RRR("add.d", "$r24", "$r14", "$r26", 0xb88df6b8315eb7a6UL, 0x137d04f7f6fe285UL, 0x2ccb253ff7ea93d6UL); + TESTINST_RRR("add.d", "$r7", "$r19", "$r23", 0xad464722c0967f28UL, 0x30295c1fd85ae029UL, 0x2c69edb227e01d94UL); + + /* ---------------- sub.w rd, rj, rk ---------------- */ + TESTINST_RRR("sub.w", "$r16", "$r28", "$r17", 0x8b0ba4ef20207fddUL, 0x90493cb39ff734a2UL, 0x519842bab5cc1208UL); + TESTINST_RRR("sub.w", "$r6", "$r13", "$r15", 0x13af983aafc53691UL, 0x27bc6a037865e47fUL, 0xe20df003930575d5UL); + TESTINST_RRR("sub.w", "$r8", "$r19", "$r23", 0x4177aec74585d42dUL, 0xba89b6aa9b7728acUL, 0xe6a089b8eaf43feUL); + TESTINST_RRR("sub.w", "$r7", "$r10", "$r23", 0xca1b83a7ab88912UL, 0xd5e2759ea82c2c80UL, 0x76e9d6f88c2624ffUL); + TESTINST_RRR("sub.w", "$r19", "$r24", "$r24", 0x99d63505ea0474b3UL, 0x1b53c4c34957af8eUL, 0x6146da47b731d3edUL); + TESTINST_RRR("sub.w", "$r26", "$r31", "$r7", 0x8eca560d8234ff55UL, 0x5beb18985c3f451eUL, 0x9c9634dfaa7b9313UL); + TESTINST_RRR("sub.w", "$r29", "$r16", "$r6", 0x229544d2cb1d5a64UL, 0xd23751d515597128UL, 0xa09dd29330aa8d15UL); + TESTINST_RRR("sub.w", "$r12", "$r16", "$r4", 0x229f5aefe9fb7fb7UL, 0x740ed49b5e95faeUL, 0xbc6304a0df442807UL); + TESTINST_RRR("sub.w", "$r30", "$r29", "$r26", 0x94f3a67d188df281UL, 0x48e066cdad20ac2UL, 0x1e032e60568554a7UL); + TESTINST_RRR("sub.w", "$r18", "$r23", "$r25", 0xedb4f44fb338ba4fUL, 0xf06e698cd08c8e7bUL, 0xa22b91e88b77d4d8UL); + + /* ---------------- sub.d rd, rj, rk ---------------- */ + TESTINST_RRR("sub.d", "$r18", "$r10", "$r27", 0x68647aa06a23c8f9UL, 0xd001cb46cb78fc4fUL, 0x460cc8702b1761f9UL); + TESTINST_RRR("sub.d", "$r7", "$r24", "$r18", 0x8d18e952fb747f43UL, 0x1e7d1a019fb96490UL, 0xb466fb9891e8c151UL); + TESTINST_RRR("sub.d", "$r4", "$r16", "$r27", 0x5f6647277ca4c99dUL, 0xa1156b863ec98e1dUL, 0xc15612f3ce819d64UL); + TESTINST_RRR("sub.d", "$r4", "$r25", "$r9", 0xe67b33778df480b4UL, 0xc24b2711be7e4ef1UL, 0xd940ca25b956100fUL); + TESTINST_RRR("sub.d", "$r5", "$r12", "$r18", 0x258ae461ef798ce7UL, 0x3f4984ea3f5692deUL, 0x99fa673f30e69019UL); + TESTINST_RRR("sub.d", "$r13", "$r10", "$r9", 0xdafb48debea5211eUL, 0xeac1d3b25f6bf8dbUL, 0x297d671b1c96e48fUL); + TESTINST_RRR("sub.d", "$r7", "$r15", "$r23", 0xc6b03274ff37baf6UL, 0x5b37ffc2c84aec9UL, 0x74d62a52cbaaec15UL); + TESTINST_RRR("sub.d", "$r26", "$r18", "$r26", 0x35c71e0956ffcd43UL, 0xad703a4e8078070bUL, 0x634924e8a9fdbb9eUL); + TESTINST_RRR("sub.d", "$r16", "$r29", "$r5", 0x18bf961cba922928UL, 0x54ed9198405f8983UL, 0x977f5b65e5f86b4aUL); + TESTINST_RRR("sub.d", "$r31", "$r28", "$r14", 0xa38a1e8cb3c7ba00UL, 0xd220d1ef3cf8f3f7UL, 0xc972df2ace170d61UL); + + /* ---------------- slt rd, rj, rk ---------------- */ + TESTINST_RRR("slt", "$r12", "$r17", "$r18", 0xd7a0e65c279e1082UL, 0x819edf00a849ba44UL, 0x41a0b2fe37d44db2UL); + TESTINST_RRR("slt", "$r31", "$r13", "$r18", 0x2ef00a5cfd100f71UL, 0x4792cd9f9abf36d3UL, 0x2c117902110ef9a8UL); + TESTINST_RRR("slt", "$r4", "$r30", "$r29", 0x6d8be2fb73e2c006UL, 0xf76ce97d7658995eUL, 0x3856e09bfe39df6eUL); + TESTINST_RRR("slt", "$r4", "$r18", "$r10", 0xeddcb9dcf092c3f5UL, 0xe57b7c25d13dea8UL, 0x761d86b48cb5ce21UL); + TESTINST_RRR("slt", "$r16", "$r18", "$r16", 0xcddd92e2340cd593UL, 0xc9a30f4707743f80UL, 0x3ff7d36f17396d3aUL); + TESTINST_RRR("slt", "$r6", "$r14", "$r10", 0xa9e71c6376093499UL, 0x26bb3955b588461fUL, 0xfae7e7a950447826UL); + TESTINST_RRR("slt", "$r19", "$r4", "$r17", 0x35bb27f64ebd7d62UL, 0x4a7d3941ebf88bc1UL, 0xcda32e4b1c1d5c4UL); + TESTINST_RRR("slt", "$r19", "$r28", "$r15", 0x29419b8261e40b99UL, 0xe7e9b059033afa7dUL, 0x1ea916293b1cc3ddUL); + TESTINST_RRR("slt", "$r31", "$r16", "$r16", 0xe0fb75047bc62c9aUL, 0xa634f6174dcced7dUL, 0xcca5a9d25b670e70UL); + TESTINST_RRR("slt", "$r4", "$r4", "$r10", 0x724ee03fb3fcdec8UL, 0xae2587f097065e2cUL, 0x65c69548f83dd0dfUL); + + /* ---------------- sltu rd, rj, rk ---------------- */ + TESTINST_RRR("sltu", "$r14", "$r10", "$r13", 0x1956e5498db3fb6eUL, 0x2d909abfec4490bdUL, 0xa7d554ebe591d5ccUL); + TESTINST_RRR("sltu", "$r6", "$r5", "$r18", 0xc34214447a064eb8UL, 0xad4413e45f0a226aUL, 0x4b09aab500b04bffUL); + TESTINST_RRR("sltu", "$r31", "$r17", "$r17", 0x86e16a1618a639c4UL, 0x87917b281cef8df0UL, 0xd543115a56dee48UL); + TESTINST_RRR("sltu", "$r20", "$r6", "$r25", 0x164fff47b8b23752UL, 0x9ad830d46b1660f6UL, 0xc5d72c146f4aba72UL); + TESTINST_RRR("sltu", "$r6", "$r26", "$r7", 0x1428360430b7c9b5UL, 0xc2052dc6eea5a53cUL, 0xda1a8e35dd060adfUL); + TESTINST_RRR("sltu", "$r19", "$r15", "$r26", 0xdfc9984966167604UL, 0xa9ea12b5a37dd492UL, 0x7a24be9fcf349afcUL); + TESTINST_RRR("sltu", "$r29", "$r26", "$r29", 0x5a3822db2cc26fc5UL, 0x5985f02e77511d80UL, 0x370f15cc98f2a6c1UL); + TESTINST_RRR("sltu", "$r7", "$r28", "$r16", 0xe4594ee2cc8c6d7UL, 0x177ac0014f5dd20UL, 0xde1724c7590a4908UL); + TESTINST_RRR("sltu", "$r8", "$r12", "$r4", 0x1df979e50aa0ed18UL, 0x5b410cd0985fce18UL, 0x9d3c39d61e29025dUL); + TESTINST_RRR("sltu", "$r30", "$r23", "$r25", 0x1cba022788d49d13UL, 0xd2b40941478ee865UL, 0xa503a74e41535830UL); + + /* ---------------- slti rd, rj, si12 ---------------- */ + TESTINST_RRI("slti", "$r15", "$r27", SI12, 0xe24c4ca567d1d5f4UL, 0xfef05a88adf4b892UL, 1913); + TESTINST_RRI("slti", "$r8", "$r31", SI12, 0xfba7284a8ab83b2dUL, 0xff63b80173f1e368UL, -738); + TESTINST_RRI("slti", "$r31", "$r31", SI12, 0xb4599a9fa734365aUL, 0x4327139de75dde1eUL, -1544); + TESTINST_RRI("slti", "$r5", "$r4", SI12, 0xa5572272e0c04a20UL, 0x87657c1b1699936bUL, 1529); + TESTINST_RRI("slti", "$r10", "$r28", SI12, 0x1260731618214410UL, 0xd0de0dfbafb7960aUL, 557); + TESTINST_RRI("slti", "$r5", "$r12", SI12, 0x4c6317772a4b06b0UL, 0x7a1d4eeb507d649bUL, -222); + TESTINST_RRI("slti", "$r4", "$r31", SI12, 0x23b4d62a21994afbUL, 0x85304cc393f6506bUL, 717); + TESTINST_RRI("slti", "$r18", "$r26", SI12, 0x67b6f5dbf6a0c55dUL, 0x451013f9a2337f9fUL, 730); + TESTINST_RRI("slti", "$r25", "$r8", SI12, 0xdb278cca57f1ad7bUL, 0x7371a60f5af6334bUL, 1193); + TESTINST_RRI("slti", "$r17", "$r24", SI12, 0xffa3ed31f9ea3a29UL, 0x1138e06e1a45c4f3UL, 329); + + /* ---------------- sltui rd, rj, si12 ---------------- */ + TESTINST_RRI("sltui", "$r13", "$r26", SI12, 0x62677116040aebffUL, 0xeedd6ccd0e5e2771UL, -462); + TESTINST_RRI("sltui", "$r24", "$r28", SI12, 0xef9500b68a87984aUL, 0xaf5922683f40599dUL, 1890); + TESTINST_RRI("sltui", "$r9", "$r6", SI12, 0x9996aa21d2b51922UL, 0xd5214fb275e738dcUL, -1538); + TESTINST_RRI("sltui", "$r19", "$r26", SI12, 0x3eb2777655f0f1c5UL, 0x98ed915860f0eb26UL, -215); + TESTINST_RRI("sltui", "$r8", "$r19", SI12, 0x5c44b5807c43724cUL, 0x63a068026b529b03UL, -780); + TESTINST_RRI("sltui", "$r19", "$r17", SI12, 0xf6926016cdbfacc1UL, 0xec04a9bcc8d1192aUL, -1041); + TESTINST_RRI("sltui", "$r26", "$r14", SI12, 0x542f05c795aa07c2UL, 0xb634bf537df4c4ceUL, 1653); + TESTINST_RRI("sltui", "$r8", "$r5", SI12, 0x371daf74e330ee8bUL, 0xedb0321c888ae22eUL, 441); + TESTINST_RRI("sltui", "$r25", "$r4", SI12, 0xba813c7acc8f5621UL, 0x8d5ce4750fe7603bUL, 678); + TESTINST_RRI("sltui", "$r17", "$r15", SI12, 0x199b641cefe0a0e2UL, 0x7ea0508a3fed3453UL, 2019); + + /* ---------------- nor rd, rj, rk ---------------- */ + TESTINST_RRR("nor", "$r14", "$r28", "$r9", 0xccf23cf02a48844dUL, 0x2608ea0069c4e9ddUL, 0x1c7a04255a2d13f8UL); + TESTINST_RRR("nor", "$r6", "$r30", "$r4", 0xbfcc3de6da2483beUL, 0xd24e9abca28d6cb5UL, 0xbb01b508523673c6UL); + TESTINST_RRR("nor", "$r6", "$r28", "$r13", 0x28dacd828d5736d7UL, 0xb365ff31474f736cUL, 0x593621c0f82b445cUL); + TESTINST_RRR("nor", "$r24", "$r16", "$r31", 0x5898010a4c6cf1bbUL, 0xecac6e093ba6146aUL, 0x50e6093f19b1194UL); + TESTINST_RRR("nor", "$r15", "$r7", "$r20", 0x2ddb1dea334fd92aUL, 0x401d7a663be0b31aUL, 0xb6c008973a85f779UL); + TESTINST_RRR("nor", "$r18", "$r31", "$r29", 0xc987982e1d91684UL, 0x181f20f581ed38f4UL, 0xefaa786e00a2e5b9UL); + TESTINST_RRR("nor", "$r19", "$r31", "$r13", 0x39e476d555cd20bcUL, 0xfb8fab5d35576d50UL, 0x71a92a8377c0f729UL); + TESTINST_RRR("nor", "$r25", "$r7", "$r5", 0x7f36d0c6d173e8c8UL, 0x181763a9f9350680UL, 0x5ec5099605d7d418UL); + TESTINST_RRR("nor", "$r30", "$r23", "$r23", 0x688e1d04976ac8dbUL, 0xd37b6d6a1c510287UL, 0x8670301ee2a715dfUL); + TESTINST_RRR("nor", "$r5", "$r23", "$r14", 0x71c4a211dd9262f4UL, 0xcb8a4aebc2c6c4f2UL, 0x84d79a5254447c9UL); + + /* ---------------- and rd, rj, rk ---------------- */ + TESTINST_RRR("and", "$r8", "$r14", "$r31", 0xbddf22c4109e20b5UL, 0xb2d25973efd1a8ffUL, 0x28b78b59dfe641e9UL); + TESTINST_RRR("and", "$r19", "$r23", "$r17", 0xb25e185c549f6661UL, 0xb6ccc215c2f17718UL, 0xf20669c51aee8ffeUL); + TESTINST_RRR("and", "$r30", "$r27", "$r23", 0xa7f4ad796393e12bUL, 0xefbcf405df3e7affUL, 0x548a0141e9fe1700UL); + TESTINST_RRR("and", "$r18", "$r31", "$r29", 0xa399c7f46c61d974UL, 0xe0fe8cca1cbab773UL, 0x49e680ddee7f666bUL); + TESTINST_RRR("and", "$r5", "$r26", "$r25", 0x1682ca17c11f90acUL, 0x4e9706cb2c885742UL, 0x250ff6304dd87d57UL); + TESTINST_RRR("and", "$r28", "$r14", "$r8", 0xcacf15e6ffad256fUL, 0x99527f4fa2aa8fb1UL, 0xcff546a883b63cfbUL); + TESTINST_RRR("and", "$r28", "$r9", "$r28", 0xc60423b9cf70d112UL, 0x2fb0db47f1d8f166UL, 0x1e9cec9d13e85210UL); + TESTINST_RRR("and", "$r18", "$r28", "$r5", 0x5059c37ee38d2f25UL, 0x74bf57d85d90af3aUL, 0x35479df0ebec9209UL); + TESTINST_RRR("and", "$r23", "$r25", "$r12", 0x18742ef4c73416beUL, 0x8b93e775860ef52bUL, 0xa909915f60a546d2UL); + TESTINST_RRR("and", "$r18", "$r17", "$r24", 0xadb2cc6aec909946UL, 0x3068f8b21d583e4cUL, 0xcf8aae1918f3a88eUL); + + /* ---------------- or rd, rj, rk ---------------- */ + TESTINST_RRR("or", "$r19", "$r28", "$r25", 0x46819825f87044c2UL, 0x65cb2cc7e5f5a720UL, 0x1fc0130146f13f76UL); + TESTINST_RRR("or", "$r8", "$r25", "$r4", 0x45083dd59c60e6feUL, 0x936ecfaeb4d51c95UL, 0xdc37c27c69024f6eUL); + TESTINST_RRR("or", "$r15", "$r16", "$r8", 0x516659e51cf19b26UL, 0x7589da0802d59510UL, 0x6b713c60390f3fbfUL); + TESTINST_RRR("or", "$r9", "$r15", "$r6", 0x1646568625c40022UL, 0xa68db9141a88850cUL, 0x756d912fbefef973UL); + TESTINST_RRR("or", "$r24", "$r9", "$r25", 0xda34c24d14fce443UL, 0x6ad9bf24481630b0UL, 0x2aefcdfa652395bUL); + TESTINST_RRR("or", "$r13", "$r9", "$r14", 0x900358ad1e848728UL, 0xa0e361b5b891a62eUL, 0xddfa0c1377ce01acUL); + TESTINST_RRR("or", "$r23", "$r16", "$r15", 0x27a55515d39aded9UL, 0xd0daf17f9cb0bf5aUL, 0xf44c4372982c4d74UL); + TESTINST_RRR("or", "$r20", "$r16", "$r16", 0x7045887bb8325d6fUL, 0xbac771cbb78dae04UL, 0x23f4928023125a5cUL); + TESTINST_RRR("or", "$r30", "$r5", "$r7", 0xcf609aa2057d1b98UL, 0x379641544fd1cd48UL, 0x5275ef34f265f01aUL); + TESTINST_RRR("or", "$r23", "$r4", "$r30", 0xc43fc1c750887406UL, 0x44a3229c33d1cd65UL, 0xceaa00084fc04912UL); + + /* ---------------- xor rd, rj, rk ---------------- */ + TESTINST_RRR("xor", "$r6", "$r19", "$r31", 0x18522418b59bf8aUL, 0x270a2ec823f26e39UL, 0x99ef76e6d4495ae3UL); + TESTINST_RRR("xor", "$r28", "$r20", "$r27", 0x57de83cac9dade15UL, 0xd39fdecdfd4ccb08UL, 0xc97b854adacdb4UL); + TESTINST_RRR("xor", "$r4", "$r29", "$r5", 0x9f7356fff2445f77UL, 0xc3c3a34d2c226b5aUL, 0x51abdd266816b94fUL); + TESTINST_RRR("xor", "$r14", "$r6", "$r28", 0xdd5ca0b5c6c45804UL, 0xa0ba047990ec0798UL, 0x89e6efd43651c28UL); + TESTINST_RRR("xor", "$r8", "$r19", "$r23", 0xc3e35cd44af166faUL, 0x6affcfe12104ccc7UL, 0x4adbb3601a07a1d9UL); + TESTINST_RRR("xor", "$r16", "$r5", "$r18", 0x685cdc5ca969c8e1UL, 0xd88d0e2a9900b8ebUL, 0xdd4dfbba723cde28UL); + TESTINST_RRR("xor", "$r20", "$r18", "$r24", 0x2362838018fa39beUL, 0xbbc8d438b24c037aUL, 0xe020a8456a45b667UL); + TESTINST_RRR("xor", "$r19", "$r23", "$r19", 0x637cae50fc0a1c95UL, 0x514b81a7227dd07eUL, 0x59a27a7f9c8481c3UL); + TESTINST_RRR("xor", "$r20", "$r16", "$r18", 0xb728dd7a443bcc8fUL, 0xe2de9bf67cdbdc0cUL, 0x26687435fbe4dbf6UL); + TESTINST_RRR("xor", "$r23", "$r14", "$r6", 0x744915919b52e27eUL, 0x16863c1d3e1cded7UL, 0x40ce8607349c380UL); + + /* ---------------- orn rd, rj, rk ---------------- */ + TESTINST_RRR("orn", "$r24", "$r9", "$r15", 0x39320ce9aa25fb73UL, 0xaaec06dc1b47cf43UL, 0x5fa36a558c884a69UL); + TESTINST_RRR("orn", "$r12", "$r4", "$r26", 0xa9c2abcbc14e3f3cUL, 0x7c87d633528d97b0UL, 0xe383c14e72ab8677UL); + TESTINST_RRR("orn", "$r20", "$r24", "$r28", 0xb117d8b0280738a2UL, 0x318fd949c3ba430fUL, 0xc9edab5116dc1582UL); + TESTINST_RRR("orn", "$r8", "$r25", "$r25", 0xb140441a36f8ededUL, 0xa26782a5e34d7addUL, 0x61bdd5b78d019958UL); + TESTINST_RRR("orn", "$r16", "$r18", "$r25", 0xcda0e2c1bce1eeecUL, 0xa4486eefd2c444d9UL, 0xbd007605c829cadcUL); + TESTINST_RRR("orn", "$r5", "$r28", "$r19", 0x8196fca50795a2aaUL, 0xec7f689a0d676560UL, 0xb4450418c4e1b333UL); + TESTINST_RRR("orn", "$r15", "$r14", "$r8", 0xaf1e2a9fe35ba4edUL, 0xd2207f86d89b890aUL, 0xfb31b9e37313a94dUL); + TESTINST_RRR("orn", "$r27", "$r14", "$r14", 0x1f24566bfa353160UL, 0xc4e17319c4766becUL, 0x29a3bbaaf6b49218UL); + TESTINST_RRR("orn", "$r17", "$r12", "$r31", 0xf5195a72c175fed7UL, 0x7aa8d4840359cbf6UL, 0xa1a42af83c82215bUL); + TESTINST_RRR("orn", "$r16", "$r20", "$r20", 0x76bb09b5b50705e2UL, 0x613fdcbd8c1eba2aUL, 0xfb1e04641f5da4ffUL); + + /* ---------------- andn rd, rj, rk ---------------- */ + TESTINST_RRR("andn", "$r19", "$r31", "$r17", 0xbcc81a9b2e349626UL, 0x5a38a8ef9c7e30e4UL, 0xcb490976d0652986UL); + TESTINST_RRR("andn", "$r10", "$r4", "$r10", 0x9acfa0cd6ea107fdUL, 0x1d9b572e8f6bedb7UL, 0x768fe778d2a543eaUL); + TESTINST_RRR("andn", "$r6", "$r12", "$r26", 0x949e36cff3b5decbUL, 0x56723f7285834fc9UL, 0xf6fa544d6cd57fa8UL); + TESTINST_RRR("andn", "$r16", "$r6", "$r4", 0x44a39d85132d6513UL, 0x3ca7f972b865b7ceUL, 0xf18819e4740308bcUL); + TESTINST_RRR("andn", "$r19", "$r26", "$r15", 0x856d1e3162c8fa2dUL, 0xc1ef79456be3885UL, 0x3c089064e60da1dUL); + TESTINST_RRR("andn", "$r17", "$r28", "$r9", 0x512a518c554f4b0aUL, 0x43454425b8b7755UL, 0xdc5dca386b49bdd7UL); + TESTINST_RRR("andn", "$r16", "$r16", "$r14", 0xa9c14796fec54f89UL, 0xe31928f90d2723a4UL, 0xcf2deaf4af11410aUL); + TESTINST_RRR("andn", "$r9", "$r4", "$r20", 0x51d79964a699ec8dUL, 0xe82135537ca93e7fUL, 0xcbadcb1dc4dd0ed0UL); + TESTINST_RRR("andn", "$r18", "$r25", "$r25", 0xeb546ce75bcba3f5UL, 0x953d86e2bd6b136dUL, 0x4914dbeee506d8adUL); + TESTINST_RRR("andn", "$r27", "$r15", "$r14", 0xc8b599a43b0b4683UL, 0x509638630676b88UL, 0x3d278ed22a112a89UL); + + /* ---------------- mul.w rd, rj, rk ---------------- */ + TESTINST_RRR("mul.w", "$r28", "$r12", "$r10", 0xf6fcce3e1c5b1598UL, 0xef2747013f911fe8UL, 0x14a216fd69537967UL); + TESTINST_RRR("mul.w", "$r13", "$r18", "$r24", 0x5e8a32c1e1e12aa4UL, 0x30e007bb8dd185faUL, 0x1a74dd893af9fb5aUL); + TESTINST_RRR("mul.w", "$r10", "$r20", "$r4", 0xf06f4af61b0e0c24UL, 0x1b3624a77f26275fUL, 0x653052ae3a1347dfUL); + TESTINST_RRR("mul.w", "$r23", "$r19", "$r10", 0xccb5485ae4605cddUL, 0x67c67c647eaf9e6cUL, 0xfb9b6c7b49ec10cfUL); + TESTINST_RRR("mul.w", "$r12", "$r30", "$r7", 0xc1f45aaf98ffcb39UL, 0x906f0c08c0bae02eUL, 0xdf6cf5c05b5f2d34UL); + TESTINST_RRR("mul.w", "$r27", "$r12", "$r12", 0x9545c6d9f812c0d9UL, 0xacd016cb69e028b3UL, 0x2b68e3a280d9c0b6UL); + TESTINST_RRR("mul.w", "$r28", "$r7", "$r19", 0x4cf68a9590da3da5UL, 0x70ed8b9b03a6325dUL, 0x1125383d12dad118UL); + TESTINST_RRR("mul.w", "$r20", "$r12", "$r20", 0x10683d31408fb4c5UL, 0x9ef4ea79672ce58dUL, 0x960a13776923d3e4UL); + TESTINST_RRR("mul.w", "$r26", "$r19", "$r28", 0xbf8a20b69fa4357bUL, 0xf3e9b53a654e3cbfUL, 0x20afdeb5a4b4e1c9UL); + TESTINST_RRR("mul.w", "$r13", "$r26", "$r25", 0x78f637d350c666bfUL, 0xff742d96dc73e9e9UL, 0x94a3289b55744707UL); + + /* ---------------- mulh.w rd, rj, rk ---------------- */ + TESTINST_RRR("mulh.w", "$r18", "$r25", "$r14", 0xa988161162710d96UL, 0x37443c6f5d0625eaUL, 0x94da379219de8576UL); + TESTINST_RRR("mulh.w", "$r13", "$r16", "$r18", 0x246298a54a25030aUL, 0x33643ceed35cff64UL, 0xc25702631b42c849UL); + TESTINST_RRR("mulh.w", "$r20", "$r5", "$r15", 0x3b606ea986dcf13eUL, 0x269dcd16567786d2UL, 0x96c0983df45d5c03UL); + TESTINST_RRR("mulh.w", "$r19", "$r19", "$r25", 0xab8fc1c922ba3e7aUL, 0xdec5bddca513d198UL, 0xf05e814d67d43f5aUL); + TESTINST_RRR("mulh.w", "$r15", "$r28", "$r16", 0x82fcfa24449231baUL, 0xf37548fee13133f3UL, 0x256188ef96bb3d23UL); + TESTINST_RRR("mulh.w", "$r24", "$r9", "$r27", 0x858ddeb68e948058UL, 0xffb64d62e202462UL, 0xe07a6dae07f46c11UL); + TESTINST_RRR("mulh.w", "$r23", "$r20", "$r14", 0x7713930e419350ffUL, 0xd5d72e6efb86e428UL, 0x49f87e78ddcc8400UL); + TESTINST_RRR("mulh.w", "$r28", "$r20", "$r25", 0x552a9b7f3fa0c48aUL, 0xd616afd20f193287UL, 0xbcd2ae680b131cd2UL); + TESTINST_RRR("mulh.w", "$r16", "$r19", "$r12", 0x94b154fc890497c3UL, 0xd8217f47e4257a7cUL, 0xb47bb0e4cff83cbfUL); + TESTINST_RRR("mulh.w", "$r23", "$r23", "$r6", 0xafb7fddb344318fUL, 0xaafee418c4267e18UL, 0x1763f686cd41d46eUL); + + /* ---------------- mulh.wu rd, rj, rk ---------------- */ + TESTINST_RRR("mulh.wu", "$r18", "$r17", "$r8", 0xa92fa2817b19786cUL, 0xaf23e3d2092f080cUL, 0x771c36ac19259f2aUL); + TESTINST_RRR("mulh.wu", "$r16", "$r13", "$r8", 0xf4a7b7abe5f3831aUL, 0xe8beff7f8f4330cdUL, 0x38cebbe3d1af354dUL); + TESTINST_RRR("mulh.wu", "$r8", "$r23", "$r29", 0x6ca8c7d8ec316750UL, 0xc3a59754c752c3a5UL, 0x4b77e251de7f45f1UL); + TESTINST_RRR("mulh.wu", "$r20", "$r25", "$r30", 0x6faa5d1372250132UL, 0x68734123142c820aUL, 0xf7b4bdf342e2017UL); + TESTINST_RRR("mulh.wu", "$r31", "$r18", "$r19", 0x8cfa67422c1c5d5UL, 0xb48ac9531206cef2UL, 0x9f9f5d925c5cf738UL); + TESTINST_RRR("mulh.wu", "$r25", "$r7", "$r27", 0x85aa17ff1b3699baUL, 0x9a7aeabb800edb53UL, 0x4eb1ec754c7cdb59UL); + TESTINST_RRR("mulh.wu", "$r19", "$r4", "$r28", 0x821038d7fb43149cUL, 0x44cd20261f5ae87eUL, 0xf9d8916e8eb4ecb1UL); + TESTINST_RRR("mulh.wu", "$r30", "$r23", "$r28", 0xef34433557594fb3UL, 0x2f9401c8064c8ca0UL, 0x5de6287c2a56e507UL); + TESTINST_RRR("mulh.wu", "$r13", "$r6", "$r17", 0xd6b38c427ad5f669UL, 0xbe04ea8987b20188UL, 0x52cee1d144e3c134UL); + TESTINST_RRR("mulh.wu", "$r26", "$r19", "$r17", 0x2ea15eee9429b8a0UL, 0x43598be92000d9f7UL, 0x6364cfeb707aba6cUL); + + /* ---------------- mul.d rd, rj, rk ---------------- */ + TESTINST_RRR("mul.d", "$r19", "$r4", "$r10", 0xf0235819cf1bab1fUL, 0xdc7a0086353cfddfUL, 0x6f18aec465b5af87UL); + TESTINST_RRR("mul.d", "$r19", "$r31", "$r20", 0x24d7526c5e4669e3UL, 0xaab7dd46e5af2493UL, 0xd5df6eea42205e25UL); + TESTINST_RRR("mul.d", "$r15", "$r20", "$r4", 0x3740ba48d64cc478UL, 0xcfeffb7c35a98382UL, 0xeab050fc9bdb3c52UL); + TESTINST_RRR("mul.d", "$r29", "$r7", "$r25", 0xe8858552c0e8eac8UL, 0xb65ed231c27efb70UL, 0xbb753de59e4ca3d1UL); + TESTINST_RRR("mul.d", "$r5", "$r30", "$r4", 0xc4f17df5c983317dUL, 0xb2af9e86d443d8ceUL, 0xf9e3c6d18372d0d3UL); + TESTINST_RRR("mul.d", "$r25", "$r17", "$r29", 0xa09d11d50056b350UL, 0x6609b14ca65f9affUL, 0x692def5a14a3278cUL); + TESTINST_RRR("mul.d", "$r13", "$r15", "$r26", 0xd528ed047af75775UL, 0x896658fe826a0817UL, 0xa456f53d5f2760b1UL); + TESTINST_RRR("mul.d", "$r23", "$r9", "$r7", 0x5d33f63ce8637a69UL, 0xad38922264c721ffUL, 0xe0514fea4ee52acaUL); + TESTINST_RRR("mul.d", "$r25", "$r23", "$r30", 0x5d74125f059662f3UL, 0xa708100731e88710UL, 0x739e4de71fec92e0UL); + TESTINST_RRR("mul.d", "$r26", "$r18", "$r30", 0x110a94ffa2e12f32UL, 0x1b770d6c423d4f8UL, 0x38bf04d66f91531aUL); + + /* ---------------- mulh.d rd, rj, rk ---------------- */ + TESTINST_RRR("mulh.d", "$r5", "$r15", "$r12", 0xd72f46d42ca4db6bUL, 0xe1771af0e69e49a6UL, 0xd796f52fbd01a4bbUL); + TESTINST_RRR("mulh.d", "$r28", "$r18", "$r14", 0x904e699bcbe32b08UL, 0x9b5b69b4d817779cUL, 0xa02ca97cc4e37f13UL); + TESTINST_RRR("mulh.d", "$r6", "$r12", "$r7", 0xc75e1065b8dbcd34UL, 0xec7d8ae6a65f2fd3UL, 0xb7e32b52f40bc8efUL); + TESTINST_RRR("mulh.d", "$r5", "$r25", "$r19", 0x7b2e04c0c2f95e4fUL, 0x9a5037ff200e982aUL, 0xf862c0c6425ff2bcUL); + TESTINST_RRR("mulh.d", "$r14", "$r8", "$r23", 0x5fd7ae31ad151daaUL, 0x444243172f499ec0UL, 0x9003c8aeabc39884UL); + TESTINST_RRR("mulh.d", "$r7", "$r23", "$r13", 0xbc21ca397041a2bUL, 0xe886455c8737b2caUL, 0xd5ccec2f631a1d60UL); + TESTINST_RRR("mulh.d", "$r26", "$r16", "$r13", 0xd3894783f187ee9cUL, 0xa7a6c4abeda9a22cUL, 0x4375f7e49ed91384UL); + TESTINST_RRR("mulh.d", "$r17", "$r31", "$r16", 0xa93bd0cf9137745eUL, 0x3a1b2b922b7645f1UL, 0x7e33f64c19972ae3UL); + TESTINST_RRR("mulh.d", "$r20", "$r19", "$r8", 0xda9224c9ab488939UL, 0xb7f5978bf509641dUL, 0xf6fcd615333c30c0UL); + TESTINST_RRR("mulh.d", "$r12", "$r17", "$r20", 0xcdbd51e35d5c1df3UL, 0x254bd8eaadc946feUL, 0x9de163435088598bUL); + + /* ---------------- mulh.du rd, rj, rk ---------------- */ + TESTINST_RRR("mulh.du", "$r25", "$r28", "$r29", 0xf7ef0dbf1bf7938aUL, 0xd267d11ae422f604UL, 0x89d6fd68226e13dUL); + TESTINST_RRR("mulh.du", "$r7", "$r28", "$r24", 0xe568cf4a6d6bc199UL, 0x6efedad6fbe95f2aUL, 0xdf55853ed22d024eUL); + TESTINST_RRR("mulh.du", "$r25", "$r8", "$r9", 0xbf7c0226b0c2072UL, 0x794fd44a65c65ebbUL, 0xa0391c3fa3cf1e5cUL); + TESTINST_RRR("mulh.du", "$r30", "$r16", "$r7", 0x3df3f3b3ff17f61aUL, 0xcadd1f7e7150ad7bUL, 0xbdc63d3f762cf02dUL); + TESTINST_RRR("mulh.du", "$r6", "$r10", "$r19", 0x6601e05fc5f801cbUL, 0xbc10a70104969251UL, 0x2f50a00036fb7821UL); + TESTINST_RRR("mulh.du", "$r17", "$r9", "$r5", 0xffabc0cbdc8aa7b0UL, 0x5288bc60da558afbUL, 0x2795644a58b2668fUL); + TESTINST_RRR("mulh.du", "$r26", "$r8", "$r15", 0x68b64c997f561b59UL, 0xe2ed2375e64b1bf3UL, 0xe1033e583092ad96UL); + TESTINST_RRR("mulh.du", "$r10", "$r13", "$r30", 0x6450ec488eb4753bUL, 0x4287b82860366cf8UL, 0x1c15ed3f051fe8cUL); + TESTINST_RRR("mulh.du", "$r24", "$r13", "$r15", 0x1169fa9dd6f8273dUL, 0x6fd2cdb39e5d1fa3UL, 0xff0526e206880684UL); + TESTINST_RRR("mulh.du", "$r8", "$r9", "$r10", 0xe9cb6416a1492fbfUL, 0xaf89960e18913df0UL, 0x76b4251409ff9830UL); + + /* ---------------- mulw.d.w rd, rj, rk ---------------- */ + TESTINST_RRR("mulw.d.w", "$r6", "$r31", "$r7", 0x50ce021eb3b3f3a4UL, 0xb859e7514e4c4d7cUL, 0x372cb1e2b3200f36UL); + TESTINST_RRR("mulw.d.w", "$r31", "$r7", "$r28", 0x925642fa7e2de9abUL, 0x61404b6550238cebUL, 0x75ed502242ed0430UL); + TESTINST_RRR("mulw.d.w", "$r19", "$r16", "$r10", 0xef82de697f7239fUL, 0xdf1c56dfe5c0e48dUL, 0xbc7e740fe1b1dc25UL); + TESTINST_RRR("mulw.d.w", "$r29", "$r12", "$r27", 0xc104a400fa0d1dbfUL, 0x2aa34e8a5fad6c6fUL, 0x7f8e4d23644b0d4dUL); + TESTINST_RRR("mulw.d.w", "$r25", "$r16", "$r25", 0x5b8ff9172c849fb9UL, 0x843f90380af6f2afUL, 0x12f7f8780cb8bfe0UL); + TESTINST_RRR("mulw.d.w", "$r13", "$r13", "$r7", 0x6bba79a88056d891UL, 0x6757a43d403285abUL, 0x2d2ea385888c2664UL); + TESTINST_RRR("mulw.d.w", "$r12", "$r8", "$r23", 0x5c96927dcf1fb14eUL, 0x2b3767b9e9029d4bUL, 0x252bbcc66b5d834bUL); + TESTINST_RRR("mulw.d.w", "$r6", "$r13", "$r10", 0x5fa5a8b36e8ec3e0UL, 0xcbca4b4d518b9466UL, 0xabdf2ec674f70c5bUL); + TESTINST_RRR("mulw.d.w", "$r16", "$r15", "$r23", 0x5b94eeb9c3c9fa01UL, 0x5c4ebef486f83b43UL, 0x73f3781c3a1e9216UL); + TESTINST_RRR("mulw.d.w", "$r6", "$r31", "$r7", 0xbc263312a123caedUL, 0xe9aa8545d3a99a97UL, 0x71b5dbacf4f7f2b8UL); + + /* ---------------- mulw.d.wu rd, rj, rk ---------------- */ + TESTINST_RRR("mulw.d.wu", "$r14", "$r17", "$r30", 0x94452e0d7eb407b7UL, 0x629b1902a484a77dUL, 0x474359ca7f7165edUL); + TESTINST_RRR("mulw.d.wu", "$r26", "$r7", "$r5", 0xae9771f0d59319b3UL, 0x1bcb563dea8f3a3fUL, 0x759334cc2d543103UL); + TESTINST_RRR("mulw.d.wu", "$r25", "$r28", "$r27", 0x27ca0bf2d6cd2699UL, 0x5a015da9b52ffc64UL, 0x482a4fa5b5625914UL); + TESTINST_RRR("mulw.d.wu", "$r8", "$r4", "$r16", 0x22f61239dad7bc92UL, 0xe8c9964b31b0e199UL, 0x99fdef421aa22322UL); + TESTINST_RRR("mulw.d.wu", "$r29", "$r17", "$r15", 0xcc5eec6e4f2b5fdbUL, 0x2d08ada074c2ac37UL, 0x8967ce1cd4c2362eUL); + TESTINST_RRR("mulw.d.wu", "$r27", "$r23", "$r16", 0x2d057e2ead214d6cUL, 0x987e7a10a0f3ee5dUL, 0xd515e2a2f06be633UL); + TESTINST_RRR("mulw.d.wu", "$r15", "$r19", "$r12", 0xce24943d6fe20263UL, 0xd6bbdcb20d76de15UL, 0xcc277905bc41da62UL); + TESTINST_RRR("mulw.d.wu", "$r4", "$r4", "$r19", 0xe37942a26dc0e882UL, 0x6a30fb04c3b5431fUL, 0x4c937bed67cb6c73UL); + TESTINST_RRR("mulw.d.wu", "$r7", "$r12", "$r9", 0xbdebe7a7b19b7dc0UL, 0x3f6e790fb24d19f1UL, 0x7a19c4fdd0d29f3eUL); + TESTINST_RRR("mulw.d.wu", "$r31", "$r30", "$r28", 0x690687056e169108UL, 0xa8abab5bf1d42538UL, 0x636a31884ca1e99UL); + + /* ---------------- div.w rd, rj, rk ---------------- */ + TESTINST_RRR("div.w", "$r13", "$r28", "$r23", 0x16546290UL, 0x627aa138UL, 0x534168cUL); + TESTINST_RRR("div.w", "$r28", "$r19", "$r9", 0xffffffffbe03930dUL, 0x223d0ec7UL, 0xffffffff8404aa67UL); + TESTINST_RRR("div.w", "$r18", "$r19", "$r30", 0xffffffffac214649UL, 0xffffffff8019c3b7UL, 0xffffffff871cbf90UL); + TESTINST_RRR("div.w", "$r24", "$r25", "$r7", 0xffffffffa144ed80UL, 0x1c4370c7UL, 0x4695aa29UL); + TESTINST_RRR("div.w", "$r9", "$r27", "$r4", 0x3ae8b7c7UL, 0xfffffffff3a6ebb2UL, 0x181d816aUL); + TESTINST_RRR("div.w", "$r28", "$r15", "$r7", 0xffffffff956a7de4UL, 0xffffffff9aab217bUL, 0x3b061b78UL); + TESTINST_RRR("div.w", "$r25", "$r24", "$r12", 0x3c6167d4UL, 0x2673145eUL, 0x1d5e391UL); + TESTINST_RRR("div.w", "$r23", "$r15", "$r4", 0x3e0820eeUL, 0x42793c51UL, 0x286cdb51UL); + TESTINST_RRR("div.w", "$r28", "$r16", "$r30", 0xffffffffcf8fd242UL, 0x2a76141eUL, 0x2429a52UL); + TESTINST_RRR("div.w", "$r29", "$r8", "$r18", 0x74991388UL, 0xffffffffd594ef43UL, 0x6d3f9603UL); + + /* ---------------- mod.w rd, rj, rk ---------------- */ + TESTINST_RRR("mod.w", "$r8", "$r13", "$r14", 0x5cc9e6dbUL, 0xfffffffff7327c6dUL, 0x23eef833UL); + TESTINST_RRR("mod.w", "$r25", "$r24", "$r25", 0x539195e4UL, 0xffffffffd94f10c8UL, 0x2c5786d9UL); + TESTINST_RRR("mod.w", "$r10", "$r16", "$r23", 0xffffffff9b15f725UL, 0x448a831dUL, 0xffffffffd5d7d92bUL); + TESTINST_RRR("mod.w", "$r6", "$r5", "$r29", 0x1794d969UL, 0x2fba86b0UL, 0x40e6ab6bUL); + TESTINST_RRR("mod.w", "$r16", "$r14", "$r29", 0x6a503328UL, 0xffffffffdf0b2ad2UL, 0xffffffff90dc29c6UL); + TESTINST_RRR("mod.w", "$r30", "$r14", "$r18", 0xffffffffc7670acdUL, 0x53f3b34fUL, 0xffffffff84b62159UL); + TESTINST_RRR("mod.w", "$r31", "$r6", "$r18", 0xffffffff98334c95UL, 0xfffffffff241ffd8UL, 0xffffffffa73314aaUL); + TESTINST_RRR("mod.w", "$r12", "$r8", "$r4", 0xffffffffd9f19db4UL, 0xffffffffc89f9796UL, 0xffffffffaa8e2a3bUL); + TESTINST_RRR("mod.w", "$r23", "$r12", "$r4", 0xffffffff94e93220UL, 0xfffffffffea1587aUL, 0xffffffffb88b2b87UL); + TESTINST_RRR("mod.w", "$r13", "$r9", "$r18", 0xf718c0UL, 0xffffffffe264a3a5UL, 0x2f29ef3UL); + + /* ---------------- div.wu rd, rj, rk ---------------- */ + TESTINST_RRR("div.wu", "$r24", "$r5", "$r16", 0xddf57c5UL, 0x6b1a808cUL, 0x576fe70UL); + TESTINST_RRR("div.wu", "$r26", "$r7", "$r9", 0x665e82ffUL, 0x344d887fUL, 0x7fd6d6d8UL); + TESTINST_RRR("div.wu", "$r13", "$r18", "$r15", 0xffffffffe82e2cf8UL, 0x7c66b628UL, 0x305c899UL); + TESTINST_RRR("div.wu", "$r15", "$r14", "$r7", 0xb06b1fUL, 0x56016282UL, 0x95a8701UL); + TESTINST_RRR("div.wu", "$r19", "$r12", "$r31", 0xffffffffb3a487d1UL, 0xffffffffbe2fe16eUL, 0xffffffff8dc0ff7fUL); + TESTINST_RRR("div.wu", "$r6", "$r10", "$r20", 0x1bb491e9UL, 0x64e382eUL, 0x5977f9f1UL); + TESTINST_RRR("div.wu", "$r9", "$r29", "$r28", 0x498c3349UL, 0x14cbb257UL, 0xffffffff95165a4aUL); + TESTINST_RRR("div.wu", "$r10", "$r29", "$r15", 0xffffffffbb3f9c5dUL, 0x2755057dUL, 0x14039cc4UL); + TESTINST_RRR("div.wu", "$r24", "$r31", "$r7", 0xffffffffe5a9a3cdUL, 0xffffffffa1f84b49UL, 0xffffffffe45bd3b9UL); + TESTINST_RRR("div.wu", "$r23", "$r18", "$r6", 0x54e07e9fUL, 0xffffffffaccbdd8cUL, 0xfffffffff3729b57UL); + + /* ---------------- mod.wu rd, rj, rk ---------------- */ + TESTINST_RRR("mod.wu", "$r5", "$r20", "$r18", 0xffffffffa1ce2e4eUL, 0xffffffffdbeb0e2dUL, 0x70157135UL); + TESTINST_RRR("mod.wu", "$r14", "$r30", "$r17", 0x10e75d07UL, 0x39c3080UL, 0x1658d87bUL); + TESTINST_RRR("mod.wu", "$r28", "$r7", "$r4", 0x6df194dbUL, 0x55fae7c9UL, 0xffffffff9a87c1efUL); + TESTINST_RRR("mod.wu", "$r6", "$r14", "$r10", 0xffffffff8feb78ccUL, 0xffffffffe5032316UL, 0x18ab441eUL); + TESTINST_RRR("mod.wu", "$r13", "$r15", "$r9", 0xffffffffbb28952cUL, 0x2d43f57dUL, 0x2dfbf584UL); + TESTINST_RRR("mod.wu", "$r7", "$r30", "$r5", 0x9bfb2cfUL, 0x6595d7b3UL, 0xfffffffffffd1025UL); + TESTINST_RRR("mod.wu", "$r10", "$r9", "$r16", 0x342671c6UL, 0xfffffffff1ff8be3UL, 0xfffffffffaea052bUL); + TESTINST_RRR("mod.wu", "$r16", "$r16", "$r23", 0xffffffffc0356055UL, 0x2ac1f414UL, 0x4a75c890UL); + TESTINST_RRR("mod.wu", "$r19", "$r8", "$r7", 0xfffffffff8ed6580UL, 0x5fef460eUL, 0x68eedef2UL); + TESTINST_RRR("mod.wu", "$r29", "$r25", "$r25", 0xffffffff9ea76eb0UL, 0xffffffff818904b9UL, 0xffffffffe92f4f30UL); + + /* ---------------- div.d rd, rj, rk ---------------- */ + TESTINST_RRR("div.d", "$r7", "$r17", "$r7", 0xc8f25fb958f2d668UL, 0x74a14cbaa00fdeaUL, 0xcf95f3de82ceb015UL); + TESTINST_RRR("div.d", "$r10", "$r19", "$r12", 0x9ead8a6f6ea63534UL, 0xaf80d344d48e6cd5UL, 0xe1f40f759cbfe0e7UL); + TESTINST_RRR("div.d", "$r23", "$r28", "$r28", 0x35481a5285093e04UL, 0xfd79e3c19b697fa8UL, 0x6ffab603b9e1b7fbUL); + TESTINST_RRR("div.d", "$r30", "$r25", "$r4", 0x3eacf1d695a34b95UL, 0xfbff957ab051d494UL, 0x670724b8930d53fUL); + TESTINST_RRR("div.d", "$r31", "$r29", "$r6", 0xce8d3df48871d655UL, 0xf351f7f35927e83dUL, 0x93a3085686f4101fUL); + TESTINST_RRR("div.d", "$r17", "$r23", "$r8", 0xfc913f8b14dda5a5UL, 0x1f938af81988deUL, 0x9d021a9f06b46953UL); + TESTINST_RRR("div.d", "$r7", "$r29", "$r15", 0x4593da2923f2ac5bUL, 0x11fc5a958b182a55UL, 0x2edafaf2857c6697UL); + TESTINST_RRR("div.d", "$r13", "$r31", "$r27", 0x97236145608dd8c3UL, 0x1f0ee96afd23910bUL, 0xe35e4d5efd2204d3UL); + TESTINST_RRR("div.d", "$r13", "$r26", "$r14", 0x2c057bd222f216dfUL, 0x1e006853720971c3UL, 0x81e35a993e6a15b5UL); + TESTINST_RRR("div.d", "$r5", "$r9", "$r4", 0x93c0d85c66f2c5abUL, 0x774fbe894b2ed067UL, 0x2c46387d55732742UL); + + /* ---------------- mod.d rd, rj, rk ---------------- */ + TESTINST_RRR("mod.d", "$r19", "$r26", "$r16", 0x63304d2181f4a4daUL, 0x9ed948849ddee475UL, 0x18a360d3ab980398UL); + TESTINST_RRR("mod.d", "$r27", "$r23", "$r13", 0xf7156e74db7a8d92UL, 0x324e7001287ce2a8UL, 0x3cc7524686bed31cUL); + TESTINST_RRR("mod.d", "$r8", "$r26", "$r19", 0x7bda37a222135803UL, 0x1daf8fd66ff987edUL, 0x334631279104fc3bUL); + TESTINST_RRR("mod.d", "$r25", "$r15", "$r7", 0xd1a0f45d5b463d53UL, 0x9c4cd7bef3bf0712UL, 0x420a5c702006f3ccUL); + TESTINST_RRR("mod.d", "$r25", "$r18", "$r7", 0x93487a905cb08a75UL, 0x8c79cafa8bebf0a8UL, 0x1478409d192c144bUL); + TESTINST_RRR("mod.d", "$r8", "$r27", "$r27", 0x8756a1690dd7896dUL, 0x35273279ea76319fUL, 0xc5292f2331abc6ddUL); + TESTINST_RRR("mod.d", "$r15", "$r10", "$r24", 0xf8c476adbc930802UL, 0x8b5832bcd0f6c87eUL, 0x6cba54a72da38702UL); + TESTINST_RRR("mod.d", "$r27", "$r7", "$r6", 0x2387015bddb2c076UL, 0x231e30de7a72ad90UL, 0x81f1285973e8dc11UL); + TESTINST_RRR("mod.d", "$r16", "$r9", "$r12", 0x3388d23c07feb1daUL, 0xe8c01f744b310474UL, 0xa29071d702959009UL); + TESTINST_RRR("mod.d", "$r13", "$r10", "$r20", 0xbd45a261f8de4fe4UL, 0x6fb0a8c9a2681a8eUL, 0x2f1b7055cf2409ecUL); + + /* ---------------- div.du rd, rj, rk ---------------- */ + TESTINST_RRR("div.du", "$r17", "$r10", "$r24", 0x4d363fd48a626fdaUL, 0x7ccdeeaa6c24885fUL, 0xfcc68e72f59750aeUL); + TESTINST_RRR("div.du", "$r20", "$r20", "$r10", 0x808fa5cb6a75fd6fUL, 0xf3f712970031005UL, 0x1709a8adab2fa578UL); + TESTINST_RRR("div.du", "$r15", "$r14", "$r19", 0xcd3107423486c8feUL, 0xf6bc56277282cd14UL, 0x961ac833f00f3e3UL); + TESTINST_RRR("div.du", "$r4", "$r29", "$r18", 0xa0bfc2fc5b35fa79UL, 0x2b28c09aa5f12845UL, 0xed44da2fdf5dce00UL); + TESTINST_RRR("div.du", "$r4", "$r6", "$r25", 0x1fc6e23fd0f09ed0UL, 0xeaa71d9fb42223caUL, 0x45689545e60381cUL); + TESTINST_RRR("div.du", "$r10", "$r8", "$r12", 0xa3710c512d4c006cUL, 0xc011778733c50a6eUL, 0xb44475ee048d8167UL); + TESTINST_RRR("div.du", "$r29", "$r4", "$r29", 0x46d27abff0da1972UL, 0x17a4e863a182dcd0UL, 0x59a7b82980ac6a6dUL); + TESTINST_RRR("div.du", "$r15", "$r8", "$r30", 0x68120919dbbd9b19UL, 0x4c296c89a6f7a6dfUL, 0x9d9166c1cd0eecfaUL); + TESTINST_RRR("div.du", "$r7", "$r18", "$r17", 0xd2389cb7af92be89UL, 0x9a1f65b2c59cfda3UL, 0xe316cf92f8f0574fUL); + TESTINST_RRR("div.du", "$r15", "$r25", "$r17", 0x49651d72d87da955UL, 0xd22c499c27908743UL, 0x8d824b01058ecb8UL); + + /* ---------------- mod.du rd, rj, rk ---------------- */ + TESTINST_RRR("mod.du", "$r26", "$r8", "$r23", 0xb0bd66f10c34fe23UL, 0x5eb9b775d83b4893UL, 0x8867d4b638f2622UL); + TESTINST_RRR("mod.du", "$r8", "$r10", "$r25", 0xe236349cd47eeb11UL, 0x119102fd7b236a81UL, 0x8fd72a09e4fb45fUL); + TESTINST_RRR("mod.du", "$r25", "$r4", "$r5", 0x1b669725a0c3a970UL, 0x175359099c87b83UL, 0xcad295c79f1d835aUL); + TESTINST_RRR("mod.du", "$r7", "$r28", "$r20", 0x7117e70798869df4UL, 0xe35b93aa0c37fe97UL, 0x741084dead7970d0UL); + TESTINST_RRR("mod.du", "$r30", "$r24", "$r9", 0xc4d432a8ce91f693UL, 0x77c03aceb2ea6b45UL, 0xb8cd7773fb72b7caUL); + TESTINST_RRR("mod.du", "$r23", "$r9", "$r28", 0x13f1f3e1891b6b73UL, 0x9811699becce53a9UL, 0xed15e264f0c39b88UL); + TESTINST_RRR("mod.du", "$r13", "$r12", "$r14", 0xb8b22bcb0cb970e8UL, 0x16cdecd7c0091cd2UL, 0x4fcab819ebadbdfdUL); + TESTINST_RRR("mod.du", "$r30", "$r17", "$r12", 0xbf96226d2de1240dUL, 0x9fe4b2c7557d6b9aUL, 0x3668e581a5de6efdUL); + TESTINST_RRR("mod.du", "$r14", "$r4", "$r6", 0x9bc8f8a69a7f55c2UL, 0x530a9c5a21769babUL, 0x2805bef72d33cbd5UL); + TESTINST_RRR("mod.du", "$r23", "$r28", "$r12", 0x82a854f86e642cbaUL, 0xdd0fd63485d6c3dUL, 0x56b21f15cb9d2bf2UL); + + /* ---------------- alsl.w rd, rj, rk, sa2 ---------------- */ + TESTINST_RRRI("alsl.w", "$r18", "$r10", "$r15", SA2_1, 0xafb40df16156827bUL, 0x9b0b86116a0d89cbUL, 0x80086c066ea6842bUL, 2); + TESTINST_RRRI("alsl.w", "$r24", "$r5", "$r4", SA2_1, 0xb8b63b8205a919dfUL, 0x7319260322fa2d6dUL, 0x1efce6644a51ebf9UL, 2); + TESTINST_RRRI("alsl.w", "$r24", "$r5", "$r27", SA2_1, 0xb4f0fd355869e078UL, 0x26abeea20b7d1ac1UL, 0x4108f7f27e321c8fUL, 2); + TESTINST_RRRI("alsl.w", "$r24", "$r29", "$r10", SA2_1, 0x4b948e9a0b82df22UL, 0x11893c9dd43d0112UL, 0x51a030165671a055UL, 1); + TESTINST_RRRI("alsl.w", "$r5", "$r10", "$r18", SA2_1, 0xfc253ac9e2b55590UL, 0x2682507563a85b07UL, 0xa467083f66457d1dUL, 1); + TESTINST_RRRI("alsl.w", "$r20", "$r13", "$r10", SA2_1, 0x76e8c346a721cdabUL, 0x548f2762bfb1bc01UL, 0xa6e0d27e62dcc594UL, 3); + TESTINST_RRRI("alsl.w", "$r16", "$r6", "$r24", SA2_1, 0x39f77b88fc3b663UL, 0x281818bf4a36a7e5UL, 0x86cd2a06ef475a61UL, 3); + TESTINST_RRRI("alsl.w", "$r14", "$r18", "$r9", SA2_1, 0x8a58ea94346ff16UL, 0x4ff191f91397adeaUL, 0x4cda359b03c97a53UL, 4); + TESTINST_RRRI("alsl.w", "$r8", "$r6", "$r29", SA2_1, 0xae0bfa182556c725UL, 0xda179bc2f41d03d3UL, 0x1d23e4da08af7978UL, 1); + TESTINST_RRRI("alsl.w", "$r31", "$r26", "$r30", SA2_1, 0xd6af9fcd7ffd8e75UL, 0x3e88bb77d6665633UL, 0x23a0414c69b804c1UL, 1); + + /* ---------------- alsl.wu rd, rj, rk, sa2 ---------------- */ + TESTINST_RRRI("alsl.wu", "$r20", "$r24", "$r18", SA2_1, 0xc714872ff3c39370UL, 0xcaea31ddabb275f9UL, 0xedbfc2cedca8eb7aUL, 2); + TESTINST_RRRI("alsl.wu", "$r13", "$r26", "$r15", SA2_1, 0xe1a0ba1adcb75aa4UL, 0x8adbed432acf321aUL, 0xeae447eaa60bb142UL, 3); + TESTINST_RRRI("alsl.wu", "$r4", "$r17", "$r27", SA2_1, 0xb153f9ecea23068cUL, 0xd2066b089c9499a3UL, 0x36ed3c96ac4751aaUL, 3); + TESTINST_RRRI("alsl.wu", "$r20", "$r10", "$r4", SA2_1, 0x8fb2705357e98d66UL, 0xd353329585fc71ddUL, 0x739237ed6a677f00UL, 4); + TESTINST_RRRI("alsl.wu", "$r31", "$r12", "$r23", SA2_1, 0x6caac60acd9bc6f4UL, 0xc87131b9171530dfUL, 0x39c8e321a6e131c0UL, 2); + TESTINST_RRRI("alsl.wu", "$r13", "$r14", "$r19", SA2_1, 0xd2c7072036f54e45UL, 0x35ea1627556f8f98UL, 0x97054728433042d3UL, 2); + TESTINST_RRRI("alsl.wu", "$r7", "$r14", "$r5", SA2_1, 0x5a0f1fae80105d64UL, 0xd300b74879e33a53UL, 0x3a1e7389d0669d4cUL, 1); + TESTINST_RRRI("alsl.wu", "$r28", "$r4", "$r9", SA2_1, 0xcd7fd8389b4f4062UL, 0xad1830d644c205e7UL, 0xced1c031d73f9087UL, 1); + TESTINST_RRRI("alsl.wu", "$r13", "$r9", "$r29", SA2_1, 0x81601560f53b081UL, 0xd3ee3c45f08cd218UL, 0xa7d5a43a1df2aa1dUL, 4); + TESTINST_RRRI("alsl.wu", "$r30", "$r29", "$r31", SA2_1, 0xf383bd5bfae7e46dUL, 0x67862a0151c65567UL, 0x9cdcbf604f46c48aUL, 2); + + /* ---------------- alsl.d rd, rj, rk, sa2 ---------------- */ + TESTINST_RRRI("alsl.d", "$r18", "$r28", "$r16", SA2_1, 0x53e533e973dfa49cUL, 0x6665a9d32abaaf55UL, 0xf70490874fb75e6eUL, 4); + TESTINST_RRRI("alsl.d", "$r10", "$r30", "$r18", SA2_1, 0xfb14c3e6acd722c3UL, 0xcae19862ab088fccUL, 0x87c434d85259d923UL, 2); + TESTINST_RRRI("alsl.d", "$r17", "$r25", "$r26", SA2_1, 0x95e79a567c313ec7UL, 0x83a0e706c2c4c534UL, 0x2f49f1e9d5b91fc9UL, 1); + TESTINST_RRRI("alsl.d", "$r7", "$r24", "$r24", SA2_1, 0x35b966d0db9f681cUL, 0xc0bc97593f1054fcUL, 0x7e564928b0a53ac6UL, 2); + TESTINST_RRRI("alsl.d", "$r6", "$r30", "$r24", SA2_1, 0x38ad1fb21e071421UL, 0xb959c439b0436d6dUL, 0x647c742c9ce02fc5UL, 3); + TESTINST_RRRI("alsl.d", "$r18", "$r28", "$r10", SA2_1, 0x1bde2962dc5bb68bUL, 0x67c403d00c9389bdUL, 0x8fc18921f225d05aUL, 2); + TESTINST_RRRI("alsl.d", "$r8", "$r27", "$r15", SA2_1, 0x5b8de9d8b393fa06UL, 0x393ec1c28e89e9d8UL, 0x1a59f9d852c3f8baUL, 3); + TESTINST_RRRI("alsl.d", "$r27", "$r24", "$r6", SA2_1, 0x72195c1ca51cc4dbUL, 0x4ee5b51e1e161ab2UL, 0x8a10acb4b625fefUL, 4); + TESTINST_RRRI("alsl.d", "$r29", "$r4", "$r18", SA2_1, 0xf3ed9e39d83d3decUL, 0xa3816509b9a6c23dUL, 0x6949e8e534450dd5UL, 2); + TESTINST_RRRI("alsl.d", "$r16", "$r13", "$r8", SA2_1, 0x588f388f25a342dfUL, 0xde33a74109c7be30UL, 0x8b02cf06997a065aUL, 1); + + /* ---------------- lu12i.w rd, si20 ---------------- */ + TESTINST_RI("lu12i.w", "$r9", SI20, 0xdf45bd002ccf48e1UL, 94146); + TESTINST_RI("lu12i.w", "$r10", SI20, 0xa5138a37d09ada8aUL, 129014); + TESTINST_RI("lu12i.w", "$r18", SI20, 0xefe46a52b8b3e5eUL, -130138); + TESTINST_RI("lu12i.w", "$r7", SI20, 0x29084adf6d033a88UL, -467080); + TESTINST_RI("lu12i.w", "$r10", SI20, 0xe9072e7fec2a5d1cUL, 360675); + TESTINST_RI("lu12i.w", "$r28", SI20, 0x2f7d41c7bd959cd5UL, 205272); + TESTINST_RI("lu12i.w", "$r16", SI20, 0xcb48200d89b48566UL, -266298); + TESTINST_RI("lu12i.w", "$r12", SI20, 0xd605223c244f4a50UL, -186346); + TESTINST_RI("lu12i.w", "$r15", SI20, 0x22c035c8c90016beUL, 247864); + TESTINST_RI("lu12i.w", "$r20", SI20, 0x6b2fd1aa0b603fecUL, -511005); + + /* ---------------- lu32i.d rd, si20 ---------------- */ + TESTINST_RI("lu32i.d", "$r8", SI20, 0xb331616751ed8877UL, -310956); + TESTINST_RI("lu32i.d", "$r17", SI20, 0xe49bab8d80e1dd7UL, 35590); + TESTINST_RI("lu32i.d", "$r4", SI20, 0x842cdc9ac0a0adf6UL, 500474); + TESTINST_RI("lu32i.d", "$r23", SI20, 0xc9ca69b8e5ab079eUL, -447277); + TESTINST_RI("lu32i.d", "$r12", SI20, 0x27d83e1c77dec50aUL, -503028); + TESTINST_RI("lu32i.d", "$r26", SI20, 0xc00dcc918a89f350UL, -355708); + TESTINST_RI("lu32i.d", "$r16", SI20, 0xd180188cdc073491UL, -231989); + TESTINST_RI("lu32i.d", "$r26", SI20, 0x4efae034432bbb3bUL, 250642); + TESTINST_RI("lu32i.d", "$r15", SI20, 0x7bf2141e673e336fUL, 237105); + TESTINST_RI("lu32i.d", "$r4", SI20, 0x187c50bfc5eb8f32UL, -312071); + + /* ---------------- lu52i.d rd, rj, si12 ---------------- */ + TESTINST_RRI("lu52i.d", "$r8", "$r25", SI12, 0x1da74dfcb33d471aUL, 0x453ae9f1200f4d41UL, 1920); + TESTINST_RRI("lu52i.d", "$r14", "$r25", SI12, 0x5e954055ebaec78fUL, 0xb7637f9119e12e31UL, -2008); + TESTINST_RRI("lu52i.d", "$r26", "$r24", SI12, 0xead69e40b96b23bfUL, 0x779862b03d1ab575UL, -1803); + TESTINST_RRI("lu52i.d", "$r5", "$r25", SI12, 0x452236306da7c667UL, 0x9f16a6e48cca3a7bUL, -1406); + TESTINST_RRI("lu52i.d", "$r26", "$r23", SI12, 0x5604b9744291e45aUL, 0x70eecb3116b1795cUL, -667); + TESTINST_RRI("lu52i.d", "$r14", "$r27", SI12, 0x6d9a8cfe459c1c48UL, 0x85452bdd40205e0dUL, -1221); + TESTINST_RRI("lu52i.d", "$r25", "$r8", SI12, 0x1a8d72e42f68a33dUL, 0x7089b6fe4c1f7a70UL, 423); + TESTINST_RRI("lu52i.d", "$r30", "$r10", SI12, 0x7c4fe646acac7ac0UL, 0xe7d222ba1fd5cae2UL, -177); + TESTINST_RRI("lu52i.d", "$r6", "$r13", SI12, 0xdb3d6a615a9e492fUL, 0xaa9303648ff489f2UL, -1438); + TESTINST_RRI("lu52i.d", "$r25", "$r4", SI12, 0x8b41b813d85b8ee8UL, 0xe4d31961e42e713cUL, -634); + + /* ---------------- addi.w rd, rj, si12 ---------------- */ + TESTINST_RRI("addi.w", "$r6", "$r27", SI12, 0x12845f036198fa6fUL, 0xda77c63c764655daUL, 1727); + TESTINST_RRI("addi.w", "$r9", "$r8", SI12, 0x21a7e3cfa2649a4fUL, 0xc64c73b3bd4c1dcbUL, -381); + TESTINST_RRI("addi.w", "$r16", "$r6", SI12, 0x6c47b02ef52a3502UL, 0x24ca1a646dac5cc3UL, -186); + TESTINST_RRI("addi.w", "$r20", "$r31", SI12, 0xb6144d8f9513c78eUL, 0xc4b808764e894e6cUL, 1503); + TESTINST_RRI("addi.w", "$r19", "$r17", SI12, 0xcf97c9215c961121UL, 0x9b714c4cb899399bUL, -1918); + TESTINST_RRI("addi.w", "$r14", "$r8", SI12, 0xe1abf22f6c3c82ecUL, 0x4110e9c1b5f59ef6UL, -1781); + TESTINST_RRI("addi.w", "$r29", "$r18", SI12, 0x4b64427195dda12dUL, 0xadf5af70b7b3f37bUL, 2047); + TESTINST_RRI("addi.w", "$r4", "$r30", SI12, 0xfc785d46f5bbdff4UL, 0x1e061e9d51362d9cUL, 244); + TESTINST_RRI("addi.w", "$r7", "$r23", SI12, 0xe037576d82c12e8dUL, 0xa77c8da72af708f1UL, -376); + TESTINST_RRI("addi.w", "$r23", "$r17", SI12, 0xa10df57c4103efUL, 0x26d2628746ad0a3eUL, 1924); + + /* ---------------- addi.d rd, rj, si12 ---------------- */ + TESTINST_RRI("addi.d", "$r14", "$r14", SI12, 0x61b497fb58a816d9UL, 0x29eb218dd65d9d6cUL, 152); + TESTINST_RRI("addi.d", "$r20", "$r13", SI12, 0xd80db8387a8cdd93UL, 0x5e23e4b01f2bbd6dUL, -640); + TESTINST_RRI("addi.d", "$r13", "$r25", SI12, 0x5dfea060c6e8f587UL, 0x95f49b783954f9f9UL, -743); + TESTINST_RRI("addi.d", "$r4", "$r30", SI12, 0xd72f370f6ce7bc4cUL, 0x148550b0f97ce601UL, 676); + TESTINST_RRI("addi.d", "$r26", "$r8", SI12, 0xa4120a67f8d6df1aUL, 0xa83f4bbcaf5bc52eUL, 1630); + TESTINST_RRI("addi.d", "$r20", "$r29", SI12, 0xa8f9c82780ac16d5UL, 0x7ab169a5751642bcUL, -1971); + TESTINST_RRI("addi.d", "$r8", "$r8", SI12, 0x6f22bdb480c14540UL, 0x94e1253c331b17f2UL, 1160); + TESTINST_RRI("addi.d", "$r15", "$r27", SI12, 0x312473547bcfe03UL, 0x7a786cbc8149d818UL, 844); + TESTINST_RRI("addi.d", "$r8", "$r26", SI12, 0xee2b1be852671bc3UL, 0x6a36d61dfee3a6fbUL, -1185); + TESTINST_RRI("addi.d", "$r17", "$r27", SI12, 0x70e068b54ed72e20UL, 0x922681ab8837027bUL, -2046); + + /* ---------------- addu16i.d rd, rj, si16 ---------------- */ + TESTINST_RRI("addu16i.d", "$r20", "$r29", SI16, 0x8232770e3472bdc3UL, 0x4d28c5567787c26eUL, -14564); + TESTINST_RRI("addu16i.d", "$r29", "$r4", SI16, 0x9076403ed2f0fdf4UL, 0x471cafb4183a389fUL, -3511); + TESTINST_RRI("addu16i.d", "$r26", "$r15", SI16, 0xdec118b1eb13234UL, 0x6ff5ce56111b301UL, 25897); + TESTINST_RRI("addu16i.d", "$r9", "$r5", SI16, 0x73209239d98fb81aUL, 0x1dc8f0ba4710eba3UL, -21829); + TESTINST_RRI("addu16i.d", "$r28", "$r25", SI16, 0xa39ba8429a9c13a6UL, 0x4fffb32851c13ff2UL, -23832); + TESTINST_RRI("addu16i.d", "$r23", "$r30", SI16, 0x8abd919f5ea43b1UL, 0x40078826f7336f0eUL, -32189); + TESTINST_RRI("addu16i.d", "$r28", "$r24", SI16, 0x695e543e25e7d3e4UL, 0x30279db606efa8ecUL, 16372); + TESTINST_RRI("addu16i.d", "$r4", "$r18", SI16, 0xa125cadb71209757UL, 0xff287b5e7fb2a2baUL, -28041); + TESTINST_RRI("addu16i.d", "$r5", "$r17", SI16, 0xd5d3e6da7c594ca9UL, 0x2bc9be0ef252584cUL, -11268); + TESTINST_RRI("addu16i.d", "$r29", "$r28", SI16, 0xee0391151007613UL, 0xae616c39d87c4b6eUL, -15645); + + /* ---------------- andi rd, rj, ui12 ---------------- */ + TESTINST_RRI("andi", "$r28", "$r18", UI12, 0xd62f833fbbd483b3UL, 0xa2f268cdcf18dd00UL, 1288); + TESTINST_RRI("andi", "$r12", "$r13", UI12, 0xc40efc9a74a3a13bUL, 0xfd609200795f877cUL, 153); + TESTINST_RRI("andi", "$r6", "$r18", UI12, 0x79ee7ee7a7865b79UL, 0x644bec92dca1ad7fUL, 3633); + TESTINST_RRI("andi", "$r5", "$r31", UI12, 0x2d64be0e5c2ec0f6UL, 0x87253b6589f182c7UL, 3299); + TESTINST_RRI("andi", "$r28", "$r5", UI12, 0xf2e4ed85d98a1860UL, 0x9f58e4edd98b60d1UL, 3189); + TESTINST_RRI("andi", "$r18", "$r29", UI12, 0x3c067920d48cf0d2UL, 0x2bf35e68c503ecfeUL, 4031); + TESTINST_RRI("andi", "$r20", "$r24", UI12, 0xe1d95be05fd57a64UL, 0xd33e771521b24bd3UL, 3252); + TESTINST_RRI("andi", "$r6", "$r23", UI12, 0x23341b2d86d02365UL, 0x16de10f2b4a45064UL, 1665); + TESTINST_RRI("andi", "$r27", "$r14", UI12, 0xd7db9d77aea4dcf5UL, 0x142272b737435eb7UL, 325); + TESTINST_RRI("andi", "$r23", "$r16", UI12, 0x57fee53581b09718UL, 0x2ace25d9e2ddbaaUL, 1056); + + /* ---------------- ori rd, rj, ui12 ---------------- */ + TESTINST_RRI("ori", "$r26", "$r13", UI12, 0x6d47cf7e5bb5c13eUL, 0x93aed4996805ba3bUL, 3251); + TESTINST_RRI("ori", "$r10", "$r25", UI12, 0x42f0332098f938afUL, 0xd7916fe8d569567bUL, 568); + TESTINST_RRI("ori", "$r12", "$r17", UI12, 0xc507d4150a742b76UL, 0x2b9a102a5b5b15f7UL, 1798); + TESTINST_RRI("ori", "$r15", "$r15", UI12, 0xa54ad5ecc0e72adbUL, 0x37c18ad4ec6e678cUL, 1781); + TESTINST_RRI("ori", "$r5", "$r4", UI12, 0x1f388b2a2b18004dUL, 0xb5fa23fbb02eeedbUL, 682); + TESTINST_RRI("ori", "$r27", "$r24", UI12, 0x73b086f8a8b4d7b5UL, 0xd23e30ab1e45470aUL, 1931); + TESTINST_RRI("ori", "$r28", "$r6", UI12, 0x972967beac695928UL, 0x2c701d0bc28816c5UL, 3593); + TESTINST_RRI("ori", "$r27", "$r4", UI12, 0x54fecbbf0a06e5a6UL, 0xf0b6d846464a3331UL, 3679); + TESTINST_RRI("ori", "$r9", "$r16", UI12, 0x71f3cd001c729062UL, 0xc5720758095e4592UL, 905); + TESTINST_RRI("ori", "$r26", "$r7", UI12, 0xd7ce86800c3c0f4bUL, 0xc4a58f787cdf5bb2UL, 3473); + + /* ---------------- xori rd, rj, ui12 ---------------- */ + TESTINST_RRI("xori", "$r27", "$r31", UI12, 0xe6d49c2dc629fbc7UL, 0x91832665d1a898e2UL, 2690); + TESTINST_RRI("xori", "$r15", "$r5", UI12, 0xada49c0d48beffc5UL, 0xe3cf426f1be4766UL, 697); + TESTINST_RRI("xori", "$r9", "$r20", UI12, 0x174a71d6d3757e3eUL, 0x25ed4678037622beUL, 2268); + TESTINST_RRI("xori", "$r31", "$r15", UI12, 0x1fac1694b40fbf2eUL, 0x4fe4fb2e0b660ca2UL, 3817); + TESTINST_RRI("xori", "$r17", "$r14", UI12, 0x2dc443400df4e153UL, 0x1db25e602ef8ece5UL, 3929); + TESTINST_RRI("xori", "$r4", "$r28", UI12, 0x5fb5ad5a84e97835UL, 0xc52da11293641639UL, 2735); + TESTINST_RRI("xori", "$r5", "$r13", UI12, 0x5c5fc4ba45da005fUL, 0xe46f853b7d602b84UL, 1153); + TESTINST_RRI("xori", "$r30", "$r26", UI12, 0x1419915b6f92678bUL, 0xa984612f1266da94UL, 3867); + TESTINST_RRI("xori", "$r13", "$r13", UI12, 0xc2b8fd036ba6314bUL, 0x4cf49604f644713cUL, 3426); + TESTINST_RRI("xori", "$r25", "$r23", UI12, 0xde46e3673c9a75dcUL, 0xfa1177a89f08c81eUL, 2669); + + /* ---------------- sll.w rd, rj, rk ---------------- */ + TESTINST_RRR("sll.w", "$r13", "$r8", "$r12", 0x26131fa72f4b76f1UL, 0xf34f7108538078d0UL, 0x10bbd12a8e087501UL); + TESTINST_RRR("sll.w", "$r29", "$r8", "$r15", 0xb6f529da4017d0d9UL, 0x49fbfb11ef643171UL, 0x9d0425e747d11bdeUL); + TESTINST_RRR("sll.w", "$r30", "$r31", "$r12", 0xcfc5236f5c070644UL, 0xba8301a1087b3a96UL, 0xff7589561824e1beUL); + TESTINST_RRR("sll.w", "$r28", "$r10", "$r7", 0x37fa51674df87149UL, 0x39212605c5d0cf7dUL, 0x18a8e323326ce5aaUL); + TESTINST_RRR("sll.w", "$r8", "$r9", "$r14", 0x707a9e0ece8abe40UL, 0x94b7b20a80c16c7bUL, 0x6887c46efb4cc181UL); + TESTINST_RRR("sll.w", "$r8", "$r4", "$r24", 0xd718a01b03a53964UL, 0x8ebd8bfeec304e2aUL, 0x6b4a83a6838b5d1UL); + TESTINST_RRR("sll.w", "$r23", "$r31", "$r27", 0xf50cab824a06d30eUL, 0xa8ee12cbd8dec935UL, 0x118002b3f0cecbabUL); + TESTINST_RRR("sll.w", "$r8", "$r25", "$r26", 0x8163368243faadeeUL, 0x3a04f47bf19a4cc8UL, 0x6a58cd3a57b4eeb4UL); + TESTINST_RRR("sll.w", "$r25", "$r13", "$r12", 0x3d6831e1afab1b1aUL, 0x9ee672580cb39777UL, 0x9084acd2bc7404caUL); + TESTINST_RRR("sll.w", "$r20", "$r5", "$r29", 0x90f7ee3ff75817a6UL, 0xe4ae07989d6148d7UL, 0x3e208bfcf046fffdUL); + + /* ---------------- srl.w rd, rj, rk ---------------- */ + TESTINST_RRR("srl.w", "$r20", "$r29", "$r30", 0xff3f6b79b5e2b56dUL, 0x1195aa09fa92d26bUL, 0xa93a8fd11ad5ae99UL); + TESTINST_RRR("srl.w", "$r8", "$r15", "$r4", 0x5d2fb7cd04ecd00cUL, 0x47bf914b6eca2852UL, 0x1bc63138cc45a75cUL); + TESTINST_RRR("srl.w", "$r20", "$r12", "$r18", 0x61fa22abda7c7b02UL, 0x9341cf09aa2e106eUL, 0x2dea831e9e121355UL); + TESTINST_RRR("srl.w", "$r30", "$r20", "$r26", 0x43e0249584da52dbUL, 0x482a209e436cda53UL, 0xb323a7f463f80660UL); + TESTINST_RRR("srl.w", "$r31", "$r16", "$r28", 0x4b10d05d93bf7288UL, 0x6d0330e88122d7c1UL, 0xc531cf8c92d53d03UL); + TESTINST_RRR("srl.w", "$r31", "$r15", "$r31", 0xd4654233c7648c3aUL, 0x12e6fc2a04cbf809UL, 0xcfe1c1b558a94808UL); + TESTINST_RRR("srl.w", "$r10", "$r30", "$r19", 0x602dee9c45a3b99bUL, 0x3ce0a6ac2acf19faUL, 0xdb5fab4bc2f82e7aUL); + TESTINST_RRR("srl.w", "$r17", "$r9", "$r23", 0x45106f11d4a57641UL, 0x5354795b675edacUL, 0xc67578c28ed7b6c7UL); + TESTINST_RRR("srl.w", "$r25", "$r26", "$r29", 0x1dc3b8477fba650cUL, 0x814377a71768e75UL, 0x60276c0e316db833UL); + TESTINST_RRR("srl.w", "$r31", "$r7", "$r30", 0x360fc92a085c2e14UL, 0x1b44ec96def89449UL, 0x56d6c5d85a81ed1fUL); + + /* ---------------- sra.w rd, rj, rk ---------------- */ + TESTINST_RRR("sra.w", "$r10", "$r17", "$r19", 0x576f2bfc771641b8UL, 0xfb1fb20b98a54405UL, 0xb20e9dae5a212078UL); + TESTINST_RRR("sra.w", "$r12", "$r16", "$r31", 0xbfdbb9a90ccc08a0UL, 0xb5d3c7f3b1a800a6UL, 0x57c3ff79f3b4198bUL); + TESTINST_RRR("sra.w", "$r18", "$r16", "$r5", 0xadcb6c153538b6b1UL, 0x99e245813e90b5e9UL, 0x7adff58363d5ebd2UL); + TESTINST_RRR("sra.w", "$r17", "$r28", "$r25", 0x7faea6a29686caf9UL, 0x801d40ea40b19beeUL, 0xf5174f678600d3fUL); + TESTINST_RRR("sra.w", "$r8", "$r27", "$r13", 0x86e5534832150e05UL, 0x47bb53d1cdc3560fUL, 0x917e2b49633a0f44UL); + TESTINST_RRR("sra.w", "$r26", "$r18", "$r20", 0xbfb83a0d762c171aUL, 0xbf67ed78d934d37cUL, 0x9f377995293fcc6bUL); + TESTINST_RRR("sra.w", "$r5", "$r25", "$r19", 0x266703af59334b0fUL, 0x4ed92cdab9f641c9UL, 0x5da1d0b8846d1a3dUL); + TESTINST_RRR("sra.w", "$r19", "$r27", "$r24", 0x72557561b3b40007UL, 0xd5db278ea099b3b5UL, 0x50b4a888b898610fUL); + TESTINST_RRR("sra.w", "$r16", "$r10", "$r4", 0xb349f888f1809ba3UL, 0x23d60a1fc100d89eUL, 0xc2846cc882dbc8e2UL); + TESTINST_RRR("sra.w", "$r23", "$r10", "$r31", 0xd7bdeddd344bb5afUL, 0xa015a07c13ff2234UL, 0x7c0fe410ce063a85UL); + + /* ---------------- sll.d rd, rj, rk ---------------- */ + TESTINST_RRR("sll.d", "$r28", "$r17", "$r10", 0x167adf26efd66416UL, 0xb861ba6e0aadf304UL, 0xa19e21ba0f406c33UL); + TESTINST_RRR("sll.d", "$r18", "$r29", "$r13", 0x3e8ea4dc3a9d9b44UL, 0x28ccf5dfa9cdc3b2UL, 0x33ef837a5a476bdcUL); + TESTINST_RRR("sll.d", "$r23", "$r27", "$r29", 0x23e29c76deed70caUL, 0x9e2265d8422e78dUL, 0xe9cc62bfd8a7c913UL); + TESTINST_RRR("sll.d", "$r16", "$r17", "$r17", 0xf5e858c7445fceddUL, 0x6735e4cf2fcb78fbUL, 0x726dd10e13b62663UL); + TESTINST_RRR("sll.d", "$r17", "$r15", "$r29", 0xfc1dbfc0551f8813UL, 0xec45100b21a74025UL, 0x186d3b737cbfd39aUL); + TESTINST_RRR("sll.d", "$r19", "$r15", "$r9", 0xbb01afe39a1e17b6UL, 0x3e66dd1100acc44aUL, 0xa9c74257f6e39cdfUL); + TESTINST_RRR("sll.d", "$r23", "$r9", "$r31", 0x945b101751c38d12UL, 0x262d14baae546199UL, 0x7ccdd8a7840948dfUL); + TESTINST_RRR("sll.d", "$r5", "$r31", "$r28", 0xa88eaecc1405995bUL, 0xd96ed500aff4596bUL, 0x6994841a196c562eUL); + TESTINST_RRR("sll.d", "$r27", "$r10", "$r25", 0x1e9540fa8237a849UL, 0x9aad6101b2470a60UL, 0x90c95628696f752fUL); + TESTINST_RRR("sll.d", "$r4", "$r26", "$r18", 0xb4dc3cdeab2e8454UL, 0xd27a92db3b2906cUL, 0x2bc7647c40c0b375UL); + + /* ---------------- srl.d rd, rj, rk ---------------- */ + TESTINST_RRR("srl.d", "$r6", "$r27", "$r13", 0x66ebeca9a7fad574UL, 0xdc837ce646ea6b51UL, 0xa57259e1758c564bUL); + TESTINST_RRR("srl.d", "$r6", "$r20", "$r5", 0x91794316e6c5e65UL, 0xdc7c47d39d64a16UL, 0x35f029b9942e11c8UL); + TESTINST_RRR("srl.d", "$r15", "$r5", "$r4", 0xbc963842b3ebc906UL, 0x42ea773b0bd19807UL, 0xd05cd2c4b01ea630UL); + TESTINST_RRR("srl.d", "$r18", "$r25", "$r28", 0x30d908baaa31230eUL, 0x779272ae228746a5UL, 0xf7b665809a3f303bUL); + TESTINST_RRR("srl.d", "$r5", "$r28", "$r27", 0x1f1d414f1d0f1feUL, 0x647277d3759d74bfUL, 0xa5c5fce39b4a1810UL); + TESTINST_RRR("srl.d", "$r24", "$r9", "$r26", 0x5fa44419162fc2c8UL, 0x9d2a589e6f6b3440UL, 0x810a615115238d8dUL); + TESTINST_RRR("srl.d", "$r31", "$r23", "$r30", 0xfa1a7ad64758b758UL, 0xe3d69d99e87b4297UL, 0x87fd8dc0a78e86bbUL); + TESTINST_RRR("srl.d", "$r26", "$r10", "$r24", 0x540888639a787231UL, 0x168791cefeb1660aUL, 0xd02b158115db9cdfUL); + TESTINST_RRR("srl.d", "$r23", "$r15", "$r12", 0xff3e950565409999UL, 0xe15a01fa0e34ea3bUL, 0x237aba34fe552f8eUL); + TESTINST_RRR("srl.d", "$r8", "$r16", "$r4", 0x825bafd36cc0d32eUL, 0x321677304d1b1406UL, 0xca68c6c83dfa5837UL); + + /* ---------------- sra.d rd, rj, rk ---------------- */ + TESTINST_RRR("sra.d", "$r23", "$r19", "$r16", 0x4cab63abd8f64774UL, 0x2c007c3ac68d7c80UL, 0xd8f4ac963a8b2c01UL); + TESTINST_RRR("sra.d", "$r18", "$r30", "$r25", 0x531de73fca30361aUL, 0x2857ba730cd281ffUL, 0xacab0fe400e4c113UL); + TESTINST_RRR("sra.d", "$r31", "$r13", "$r10", 0x3184416bc93a5e26UL, 0xad5864bc4022de96UL, 0xf7007bdbf1f728abUL); + TESTINST_RRR("sra.d", "$r6", "$r25", "$r23", 0x9184d2df291f3402UL, 0x7c0b117dcad80c03UL, 0x35b29b0dde1a94bdUL); + TESTINST_RRR("sra.d", "$r16", "$r6", "$r29", 0x2849e543d35dff5fUL, 0x9f13f36a632a3fUL, 0xf31f881e12072fe2UL); + TESTINST_RRR("sra.d", "$r7", "$r29", "$r10", 0x25c763f8366139ddUL, 0xfd77fd6e69e371c6UL, 0xcaa2ec6ad4f3b996UL); + TESTINST_RRR("sra.d", "$r24", "$r25", "$r26", 0x472602300b4f04c9UL, 0x54ceea832a5677e9UL, 0x5f63e9d9d6eb4af0UL); + TESTINST_RRR("sra.d", "$r23", "$r4", "$r27", 0xe8b449325a0ed51eUL, 0xd96928476f8441a5UL, 0x7e1ae8fd9c849dceUL); + TESTINST_RRR("sra.d", "$r15", "$r9", "$r12", 0x71601a1a2b155f51UL, 0xbcbb1d162563240UL, 0x5a906ad2f4abb4c7UL); + TESTINST_RRR("sra.d", "$r16", "$r29", "$r23", 0x1686886f27d397fbUL, 0x851328b2655e5689UL, 0x1634457590cd4033UL); + + /* ---------------- rotr.w rd, rj, rk ---------------- */ + TESTINST_RRR("rotr.w", "$r8", "$r5", "$r18", 0xc4394aae4c13908bUL, 0xa0c5728d1211b595UL, 0x3d562746b3943f3bUL); + TESTINST_RRR("rotr.w", "$r19", "$r18", "$r10", 0x284b501639de116bUL, 0x4248ad6cc0107902UL, 0xb41907b756bf8004UL); + TESTINST_RRR("rotr.w", "$r29", "$r8", "$r4", 0x2656b50c7d689f19UL, 0x7b5d21fdce9bcb73UL, 0x5b212fbe9e6b8522UL); + TESTINST_RRR("rotr.w", "$r25", "$r6", "$r30", 0x4c79ed7a1695fc25UL, 0x6bac1698a978f50fUL, 0xf1d58570dfb10203UL); + TESTINST_RRR("rotr.w", "$r14", "$r18", "$r6", 0xe894476b4ebbff23UL, 0x1398b65ae1e91c98UL, 0xebb6c3f5f689d2d8UL); + TESTINST_RRR("rotr.w", "$r19", "$r29", "$r26", 0x2595423cc93ecd7cUL, 0x6c462c2d29d8f908UL, 0x19142efd8e0b48b8UL); + TESTINST_RRR("rotr.w", "$r23", "$r10", "$r25", 0x68b4d913b267a3a2UL, 0x69afb673907e4506UL, 0xbd09ff2ed890862dUL); + TESTINST_RRR("rotr.w", "$r9", "$r14", "$r27", 0x17a45b8cbdebd6efUL, 0x33effef864846356UL, 0x3f52e437f2d5da62UL); + TESTINST_RRR("rotr.w", "$r5", "$r12", "$r23", 0x2d191b1a9707cf26UL, 0x86fa75433dac3d39UL, 0x21136a02424e5da4UL); + TESTINST_RRR("rotr.w", "$r29", "$r18", "$r27", 0x7d989f74f9944f8dUL, 0x50fe5829a153e6UL, 0x926776f9140b06fcUL); + + /* ---------------- rotr.d rd, rj, rk ---------------- */ + TESTINST_RRR("rotr.d", "$r29", "$r19", "$r13", 0x1e02c0c28ec3f9b1UL, 0xf2e79e6ff240b188UL, 0x60f500663eddf444UL); + TESTINST_RRR("rotr.d", "$r30", "$r4", "$r14", 0x97f6be8229e2e822UL, 0xf79aaeb2c03a2113UL, 0xbbdb2cb642605ed7UL); + TESTINST_RRR("rotr.d", "$r6", "$r19", "$r7", 0x1611806010ce99d8UL, 0xcb64270e0fc5b4c7UL, 0xeda6972c46af03cUL); + TESTINST_RRR("rotr.d", "$r4", "$r15", "$r30", 0xe63084e97bd0efb3UL, 0x6e1aa322e38e9b66UL, 0xa7df0f1d92106e2dUL); + TESTINST_RRR("rotr.d", "$r16", "$r27", "$r10", 0x1ff92fbb0f10ff9aUL, 0x15c2eb91c9ae124UL, 0x8b4c97ee7f9bc2faUL); + TESTINST_RRR("rotr.d", "$r28", "$r7", "$r25", 0xbd766a63bbead21cUL, 0xd97b509610db5e7UL, 0x3151203010315af5UL); + TESTINST_RRR("rotr.d", "$r9", "$r20", "$r23", 0x8a2bb5eacea50d68UL, 0x947ec1930151adb9UL, 0xc2f39e045d278b7bUL); + TESTINST_RRR("rotr.d", "$r25", "$r13", "$r23", 0xcaddb8ea7bd492c7UL, 0x416a1b790dbf45cbUL, 0x44c59965e1c6af25UL); + TESTINST_RRR("rotr.d", "$r14", "$r7", "$r31", 0x8ca18b58047c8b5aUL, 0x93a6cdc3585b5446UL, 0x70cd84ec07e33cefUL); + TESTINST_RRR("rotr.d", "$r14", "$r9", "$r4", 0x48bd5c133004f490UL, 0xad095be0915fe20bUL, 0xc1fff6ff603a47b3UL); + + /* ---------------- slli.w rd, rj, ui5 ---------------- */ + TESTINST_RRI("slli.w", "$r18", "$r8", UI5, 0xe7f8823a2989c395UL, 0xf0ccc85519ad1e0aUL, 10); + TESTINST_RRI("slli.w", "$r27", "$r17", UI5, 0x2e66b550a3bb071dUL, 0x20943aa3eaa4024eUL, 30); + TESTINST_RRI("slli.w", "$r27", "$r23", UI5, 0x70daa2bee8209243UL, 0x2e9160afd2e28a64UL, 31); + TESTINST_RRI("slli.w", "$r10", "$r13", UI5, 0x701c424632b5dc29UL, 0x591054db6afe1725UL, 12); + TESTINST_RRI("slli.w", "$r7", "$r15", UI5, 0xdd1d7fe3ae579499UL, 0x2e077f689088c0c7UL, 19); + TESTINST_RRI("slli.w", "$r6", "$r8", UI5, 0xff732113ddaab79bUL, 0x9cacf8e6d9e37f97UL, 12); + TESTINST_RRI("slli.w", "$r5", "$r19", UI5, 0xcef75ddd2adc5853UL, 0xcc24ed9167fd06eaUL, 22); + TESTINST_RRI("slli.w", "$r17", "$r8", UI5, 0x3c8788fed3e8a049UL, 0xccf9b2d2c2e80251UL, 7); + TESTINST_RRI("slli.w", "$r14", "$r29", UI5, 0xe1b0b077db4f08eUL, 0x76aea4b9ae43cdfbUL, 10); + TESTINST_RRI("slli.w", "$r23", "$r30", UI5, 0x13d8514aeb0dc12bUL, 0x9c8352804e7e8ccbUL, 26); + + /* ---------------- slli.d rd, rj, ui6 ---------------- */ + TESTINST_RRI("slli.d", "$r27", "$r28", UI6, 0x689a2c4141835926UL, 0x1b6ff38e611d1e4dUL, 5); + TESTINST_RRI("slli.d", "$r5", "$r20", UI6, 0xff3391c2323defa6UL, 0xe99a134a0c1a2574UL, 1); + TESTINST_RRI("slli.d", "$r27", "$r7", UI6, 0xc32d8fb319ba47e6UL, 0xc6530e0e601d3631UL, 61); + TESTINST_RRI("slli.d", "$r5", "$r26", UI6, 0x979553ff112cdf52UL, 0x931e420364fdcacaUL, 45); + TESTINST_RRI("slli.d", "$r27", "$r5", UI6, 0xa7f70b048a4087b0UL, 0xc1b829210c3cd5a9UL, 60); + TESTINST_RRI("slli.d", "$r23", "$r10", UI6, 0xcd547af78ac66ca7UL, 0xa2c0802de6c82645UL, 59); + TESTINST_RRI("slli.d", "$r13", "$r30", UI6, 0x410b8f25e1234eeUL, 0xdbaacfe884cda24dUL, 56); + TESTINST_RRI("slli.d", "$r16", "$r4", UI6, 0x44a2ff35045ec37cUL, 0xee2240010629a8eeUL, 20); + TESTINST_RRI("slli.d", "$r19", "$r20", UI6, 0x8617d88408d75cacUL, 0xba15483820d66ae7UL, 25); + TESTINST_RRI("slli.d", "$r24", "$r27", UI6, 0x669e0e9b99d5b604UL, 0xf5d1ffc374e53c7dUL, 13); + + /* ---------------- srli.w rd, rj, ui5 ---------------- */ + TESTINST_RRI("srli.w", "$r20", "$r16", UI5, 0x7f5310ac5eaa9924UL, 0xea8b69613d183eeUL, 10); + TESTINST_RRI("srli.w", "$r13", "$r15", UI5, 0x5f4d9313f9224389UL, 0xd544272206f4e814UL, 0); + TESTINST_RRI("srli.w", "$r17", "$r18", UI5, 0xd9b2c942f996cc8aUL, 0x704cd1d89de5c2b4UL, 7); + TESTINST_RRI("srli.w", "$r27", "$r28", UI5, 0xa3eef8efc97e0d4fUL, 0x8c449e6236daa7a2UL, 18); + TESTINST_RRI("srli.w", "$r9", "$r10", UI5, 0x6c044927152e5fc9UL, 0x592a1607944e0109UL, 29); + TESTINST_RRI("srli.w", "$r8", "$r24", UI5, 0xcaa01b37d49db675UL, 0x5e35848bbc958164UL, 31); + TESTINST_RRI("srli.w", "$r6", "$r16", UI5, 0xe2fbe1accb343769UL, 0x85f5e17c7d785222UL, 18); + TESTINST_RRI("srli.w", "$r18", "$r25", UI5, 0x4653c07e0627825fUL, 0x44fffa524ffd0417UL, 31); + TESTINST_RRI("srli.w", "$r5", "$r26", UI5, 0x817ebd7154c8ed46UL, 0xc7399a9899fc5958UL, 22); + TESTINST_RRI("srli.w", "$r27", "$r4", UI5, 0x3e4b17b34f2b08d0UL, 0x5bedb97aefd697f4UL, 27); + + /* ---------------- srli.d rd, rj, ui6 ---------------- */ + TESTINST_RRI("srli.d", "$r31", "$r9", UI6, 0x8fc21da189af52edUL, 0x235bf33e3e612a15UL, 51); + TESTINST_RRI("srli.d", "$r26", "$r7", UI6, 0xcd1eaac4df2531ddUL, 0xe87216fce9c75788UL, 36); + TESTINST_RRI("srli.d", "$r6", "$r31", UI6, 0xc0282beeb7dc6618UL, 0x8b58604d6be3e8e0UL, 29); + TESTINST_RRI("srli.d", "$r20", "$r6", UI6, 0x1546fdd9fc133e39UL, 0x74067840bb05a992UL, 18); + TESTINST_RRI("srli.d", "$r28", "$r20", UI6, 0xaa1f88b09e13e4c6UL, 0x6e153faa5221e893UL, 28); + TESTINST_RRI("srli.d", "$r26", "$r4", UI6, 0x2ba2151c80dbea7aUL, 0x21246f3c7063edf9UL, 55); + TESTINST_RRI("srli.d", "$r28", "$r29", UI6, 0xcd72eff1b5aa0877UL, 0x5d9488c1d61a1544UL, 34); + TESTINST_RRI("srli.d", "$r13", "$r7", UI6, 0x5953b78fbd8109a9UL, 0x862731652b653859UL, 62); + TESTINST_RRI("srli.d", "$r29", "$r18", UI6, 0xab821449d149a976UL, 0xcb73553146cc4bdcUL, 25); + TESTINST_RRI("srli.d", "$r28", "$r7", UI6, 0x31272fa88123357dUL, 0xe9359f7a9f92ec5UL, 2); + + /* ---------------- srai.w rd, rj, ui5 ---------------- */ + TESTINST_RRI("srai.w", "$r26", "$r23", UI5, 0xe73a55c2b7005c01UL, 0xfcd659254f4b3fe7UL, 2); + TESTINST_RRI("srai.w", "$r31", "$r10", UI5, 0x2e0c4330fae0890aUL, 0xa76ca364a204c82bUL, 0); + TESTINST_RRI("srai.w", "$r31", "$r8", UI5, 0x64790bb6e8674f68UL, 0xce5594f964c4a026UL, 0); + TESTINST_RRI("srai.w", "$r15", "$r31", UI5, 0xccfb53c708026acdUL, 0xce185873627515b5UL, 27); + TESTINST_RRI("srai.w", "$r16", "$r28", UI5, 0x994c4d22e90185a2UL, 0x49995d51019e1050UL, 1); + TESTINST_RRI("srai.w", "$r13", "$r16", UI5, 0x484408b57b3ab89UL, 0x437401347e23c399UL, 16); + TESTINST_RRI("srai.w", "$r4", "$r9", UI5, 0xd1d936105b7cca3UL, 0xd49c3c65e292b942UL, 7); + TESTINST_RRI("srai.w", "$r24", "$r15", UI5, 0xaa9377005232ec93UL, 0xde29d0172b40f03dUL, 10); + TESTINST_RRI("srai.w", "$r19", "$r14", UI5, 0xa49c65a4c2cde36dUL, 0x782e0d4b8a7a28d0UL, 24); + TESTINST_RRI("srai.w", "$r24", "$r27", UI5, 0x404f816ff696bbc8UL, 0x1b6900e15f252315UL, 24); + + /* ---------------- srai.d rd, rj, ui6 ---------------- */ + TESTINST_RRI("srai.d", "$r24", "$r4", UI6, 0x96250384fede78c7UL, 0x6c501d9ec5e9e731UL, 22); + TESTINST_RRI("srai.d", "$r30", "$r19", UI6, 0xcfc52d7caaf7bf47UL, 0x82499a30d50f8b83UL, 17); + TESTINST_RRI("srai.d", "$r12", "$r12", UI6, 0x628a1a46bbe30c16UL, 0xaba392c50d63ea53UL, 5); + TESTINST_RRI("srai.d", "$r24", "$r9", UI6, 0x21c1bb01f0253d8UL, 0xb35e31d92548a2feUL, 2); + TESTINST_RRI("srai.d", "$r28", "$r7", UI6, 0x2a5ac0a983332ec3UL, 0x2297ae499a473c6dUL, 62); + TESTINST_RRI("srai.d", "$r8", "$r17", UI6, 0xa27cf36651750e09UL, 0x1984e046b042d0cfUL, 31); + TESTINST_RRI("srai.d", "$r25", "$r16", UI6, 0x7df3822fb20b8dedUL, 0xb4e464563029fac8UL, 37); + TESTINST_RRI("srai.d", "$r14", "$r5", UI6, 0xe8c1939c13a2e6caUL, 0x6a22077c63497a9aUL, 57); + TESTINST_RRI("srai.d", "$r25", "$r15", UI6, 0xf2df68e25cccf72eUL, 0xe0af648201f919fcUL, 10); + TESTINST_RRI("srai.d", "$r6", "$r15", UI6, 0xa24591b35142aa9cUL, 0x12b20ac67de77b8dUL, 49); + + /* ---------------- rotri.w rd, rj, ui5 ---------------- */ + TESTINST_RRI("rotri.w", "$r18", "$r6", UI5, 0xf0c65b137926ba00UL, 0x95e0f5f057a212c5UL, 20); + TESTINST_RRI("rotri.w", "$r9", "$r16", UI5, 0xe36356471d2a7e18UL, 0xb8af3071021bd869UL, 27); + TESTINST_RRI("rotri.w", "$r5", "$r31", UI5, 0x5992fc9cfce2ebe9UL, 0x6c427c821603d01aUL, 1); + TESTINST_RRI("rotri.w", "$r27", "$r13", UI5, 0x239c57dca2ab060UL, 0xed54e28825b25471UL, 23); + TESTINST_RRI("rotri.w", "$r18", "$r18", UI5, 0xb84df2305a710936UL, 0x8aae5248c6d4973cUL, 7); + TESTINST_RRI("rotri.w", "$r4", "$r27", UI5, 0x730e1701570ac9fcUL, 0xd55b9d54232536e7UL, 29); + TESTINST_RRI("rotri.w", "$r19", "$r18", UI5, 0x36dbceffa501d8dcUL, 0x8415238fa1dd314fUL, 0); + TESTINST_RRI("rotri.w", "$r13", "$r24", UI5, 0xc1ac428ddf5193UL, 0x3b588028fcfbb0a8UL, 21); + TESTINST_RRI("rotri.w", "$r14", "$r25", UI5, 0x733414543ca8145eUL, 0xded24831de35be08UL, 29); + TESTINST_RRI("rotri.w", "$r27", "$r5", UI5, 0x60afaebb36d22ba0UL, 0xfd31a16f03582b5UL, 8); + + /* ---------------- rotri.d rd, rj, ui6 ---------------- */ + TESTINST_RRI("rotri.d", "$r20", "$r7", UI6, 0xe112a6d47c0444c1UL, 0xbd9bbb91bdc381c5UL, 53); + TESTINST_RRI("rotri.d", "$r27", "$r16", UI6, 0xf254a827c1ef7351UL, 0x3de084650f757cebUL, 62); + TESTINST_RRI("rotri.d", "$r30", "$r17", UI6, 0x31c36a8c83999eb2UL, 0x107098a9863e85d5UL, 10); + TESTINST_RRI("rotri.d", "$r29", "$r8", UI6, 0xf2e7a25c121af3c3UL, 0xb177c110c3dd3225UL, 46); + TESTINST_RRI("rotri.d", "$r4", "$r26", UI6, 0xdd94ff60f2e1abffUL, 0xb76d3e4a0af02e4dUL, 45); + TESTINST_RRI("rotri.d", "$r10", "$r9", UI6, 0x6064d48d901beca7UL, 0xea20b33360134ab2UL, 42); + TESTINST_RRI("rotri.d", "$r4", "$r26", UI6, 0x27f1e63c8f7f71cfUL, 0xf4c5c8a69f37a1bdUL, 27); + TESTINST_RRI("rotri.d", "$r9", "$r16", UI6, 0x7d4cb07a3ab72944UL, 0xd5ee210421c6080eUL, 20); + TESTINST_RRI("rotri.d", "$r24", "$r26", UI6, 0x1ce66a79f3e45e6fUL, 0x6e1767144ffa6e2dUL, 4); + TESTINST_RRI("rotri.d", "$r4", "$r18", UI6, 0x4173f8102b03399UL, 0xde7066568917d899UL, 46); + + /* ---------------- ext.w.h rd, rj ---------------- */ + TESTINST_RR("ext.w.h", "$r17", "$r14", 0x58af862c6fc4208dUL, 0x6235b0cfe4eed6edUL); + TESTINST_RR("ext.w.h", "$r31", "$r20", 0x425af3dcd83fa9fdUL, 0x6e59403101a538f1UL); + TESTINST_RR("ext.w.h", "$r18", "$r27", 0xcb140226bf788367UL, 0x58a5430ee4e1616eUL); + TESTINST_RR("ext.w.h", "$r15", "$r10", 0xd3debaf05f7d909fUL, 0x6f7083340247fb12UL); + TESTINST_RR("ext.w.h", "$r12", "$r15", 0x5dc6f7191af80bcfUL, 0xb1f1c8f4b11c03d9UL); + TESTINST_RR("ext.w.h", "$r7", "$r15", 0x5ffe304a5c9dc9d2UL, 0x102fb4fa33193103UL); + TESTINST_RR("ext.w.h", "$r16", "$r16", 0x533616e37505799fUL, 0xf988c7255086f4f5UL); + TESTINST_RR("ext.w.h", "$r13", "$r25", 0x805a406557ed3facUL, 0xdc6ce0f2993b219bUL); + TESTINST_RR("ext.w.h", "$r19", "$r20", 0xcc49c20125c4755dUL, 0xde7b765222a9703aUL); + TESTINST_RR("ext.w.h", "$r18", "$r7", 0xe0dd9155cbe168c6UL, 0xc1063421eae07663UL); + + /* ---------------- ext.w.b rd, rj ---------------- */ + TESTINST_RR("ext.w.b", "$r16", "$r23", 0x21666e814555aa02UL, 0x926b8d68b5c40592UL); + TESTINST_RR("ext.w.b", "$r8", "$r20", 0xf68ae0a0ac497dedUL, 0xbfb5d489716d0c5UL); + TESTINST_RR("ext.w.b", "$r24", "$r15", 0xbc84e54c82fd6e51UL, 0x7d814b11e5eb07f6UL); + TESTINST_RR("ext.w.b", "$r31", "$r17", 0x14e575a8dda1f0d3UL, 0x6a111e663a52244cUL); + TESTINST_RR("ext.w.b", "$r16", "$r8", 0x911acc218fcf640bUL, 0xac1405ad05b23e43UL); + TESTINST_RR("ext.w.b", "$r28", "$r8", 0x77fb13eaa8995607UL, 0x5c97a81f12da7d3UL); + TESTINST_RR("ext.w.b", "$r9", "$r23", 0xb88cfdb98683e15eUL, 0x74893b34973e16cbUL); + TESTINST_RR("ext.w.b", "$r31", "$r4", 0xc7168cb4f7d079e4UL, 0xf4fc215bc2c5273eUL); + TESTINST_RR("ext.w.b", "$r4", "$r18", 0xe2e5dca4727b373UL, 0xa1b97136f32e452bUL); + TESTINST_RR("ext.w.b", "$r8", "$r29", 0x625eb5236f483daaUL, 0x3ceca34ee347e7c8UL); + + /* ---------------- clo.w rd, rj ---------------- */ + TESTINST_RR("clo.w", "$r4", "$r13", 0xbcca747f77aca28UL, 0x8df71972c1a17096UL); + TESTINST_RR("clo.w", "$r27", "$r5", 0x98a9e6d99d8e84cbUL, 0xdc59d3c8fc1540e4UL); + TESTINST_RR("clo.w", "$r9", "$r14", 0xe8e78b162c95ed66UL, 0xdfad6854bbf442e6UL); + TESTINST_RR("clo.w", "$r13", "$r26", 0xa3db2cf80f9112cdUL, 0x7676463dd6f13f80UL); + TESTINST_RR("clo.w", "$r7", "$r16", 0xb5213ab31b574031UL, 0x478c19ebdeaa74c0UL); + TESTINST_RR("clo.w", "$r13", "$r12", 0xd68d9661284fb9d7UL, 0x702bf24fddd8bfe0UL); + TESTINST_RR("clo.w", "$r18", "$r20", 0x510cd4002aff4c6cUL, 0x4fc898e8b83669eeUL); + TESTINST_RR("clo.w", "$r5", "$r9", 0x53c0de96f709208dUL, 0xe56d87b898438b5UL); + TESTINST_RR("clo.w", "$r20", "$r5", 0x96187854fcce4fd1UL, 0xf1248bea6ed8be30UL); + TESTINST_RR("clo.w", "$r20", "$r31", 0xb1abb4795d411683UL, 0x1025f914a9225e6UL); + + /* ---------------- clz.w rd, rj ---------------- */ + TESTINST_RR("clz.w", "$r19", "$r8", 0x374348642747a8dcUL, 0xd8ec1d547d95ada5UL); + TESTINST_RR("clz.w", "$r26", "$r4", 0x741ab4d14b9ee1f8UL, 0x99e2ef840817cfffUL); + TESTINST_RR("clz.w", "$r17", "$r4", 0x45c9ce7217f501b3UL, 0xa387a194cd03bcf1UL); + TESTINST_RR("clz.w", "$r13", "$r26", 0x69707656f354d758UL, 0xd4a8f8ab02b876b0UL); + TESTINST_RR("clz.w", "$r25", "$r13", 0x103ce6ee41e094c3UL, 0xd7a85bf4006e655aUL); + TESTINST_RR("clz.w", "$r5", "$r13", 0x3910578929e7cd4aUL, 0x93c87b02b7b1b603UL); + TESTINST_RR("clz.w", "$r18", "$r29", 0x10639f8979feefe5UL, 0x9d8b4b8f8493f844UL); + TESTINST_RR("clz.w", "$r25", "$r16", 0x7b35b3e995b3b44dUL, 0xad953d0ae0b3e870UL); + TESTINST_RR("clz.w", "$r6", "$r25", 0xda6cbd19f10ef86fUL, 0x1d6665db1162cfb4UL); + TESTINST_RR("clz.w", "$r5", "$r12", 0x8a6f4d6ec8d7c00dUL, 0x19b40cb8dd8d1679UL); + + /* ---------------- cto.w rd, rj ---------------- */ + TESTINST_RR("cto.w", "$r7", "$r15", 0x7285e9c364562d11UL, 0x963655c7f58de520UL); + TESTINST_RR("cto.w", "$r4", "$r15", 0x105dceebc6d7e641UL, 0xfc01c17baaca9c46UL); + TESTINST_RR("cto.w", "$r31", "$r28", 0xdeff9742b93f0591UL, 0x2cf98074b0151f33UL); + TESTINST_RR("cto.w", "$r13", "$r8", 0xeee665743cd218ffUL, 0xbdd700b2535aa3b7UL); + TESTINST_RR("cto.w", "$r23", "$r13", 0x1cc22cfd7c0c869cUL, 0x5b848b64decbee8fUL); + TESTINST_RR("cto.w", "$r12", "$r18", 0x5c32b3db803e5988UL, 0x2d5d1ebf93b79dd0UL); + TESTINST_RR("cto.w", "$r17", "$r9", 0xc11d806786501f0eUL, 0xd175fe2ca41bda38UL); + TESTINST_RR("cto.w", "$r24", "$r16", 0x504f9b43af62e2adUL, 0xfce545d98e2361daUL); + TESTINST_RR("cto.w", "$r24", "$r8", 0xc13ac5668538f5a4UL, 0x3096912e575d64dbUL); + TESTINST_RR("cto.w", "$r27", "$r17", 0xd27f68629dd8d4fbUL, 0x15ac43632e175a8bUL); + + /* ---------------- ctz.w rd, rj ---------------- */ + TESTINST_RR("ctz.w", "$r8", "$r12", 0xfc9bd3736a3c08bdUL, 0xaebba33c2e268daaUL); + TESTINST_RR("ctz.w", "$r5", "$r27", 0x5dc8af7bac7db01aUL, 0xabce2f0e113597aaUL); + TESTINST_RR("ctz.w", "$r18", "$r6", 0xe4ac5b59d8442dfeUL, 0x935d1b694e96bd04UL); + TESTINST_RR("ctz.w", "$r9", "$r15", 0x9b760f465efbb52eUL, 0x834c9974dba65d99UL); + TESTINST_RR("ctz.w", "$r13", "$r7", 0x95b5748f5f8bfb38UL, 0x75dd7a9890cdf2d9UL); + TESTINST_RR("ctz.w", "$r29", "$r17", 0xa25119fd892d1b20UL, 0x38c12e795dc52acfUL); + TESTINST_RR("ctz.w", "$r15", "$r12", 0x95c2ce0f0446807cUL, 0x623a5915ac8164b2UL); + TESTINST_RR("ctz.w", "$r6", "$r17", 0xd9034892a300dca8UL, 0x5911fea4e6ce1df3UL); + TESTINST_RR("ctz.w", "$r10", "$r25", 0xda1e0d0eb34884abUL, 0x8d70d49a10ba8968UL); + TESTINST_RR("ctz.w", "$r14", "$r13", 0x207d275c076e5247UL, 0xd243debc9b557922UL); + + /* ---------------- clo.d rd, rj ---------------- */ + TESTINST_RR("clo.d", "$r7", "$r16", 0x9432ccd773e86812UL, 0x9f921ea959c97c2bUL); + TESTINST_RR("clo.d", "$r7", "$r12", 0xaf19ef0b422b09bfUL, 0x8773ec5c72444fe2UL); + TESTINST_RR("clo.d", "$r5", "$r10", 0xa2912bc0ca36fa58UL, 0x2c93a7506a8979b7UL); + TESTINST_RR("clo.d", "$r7", "$r28", 0x69dd3f71121c7380UL, 0x1784b7c2c7558b4aUL); + TESTINST_RR("clo.d", "$r15", "$r9", 0x95b40b42f113ceccUL, 0xf0cdb7b9c17bb9e1UL); + TESTINST_RR("clo.d", "$r9", "$r27", 0x1961ee1499945d08UL, 0x23c7a2252c1cbc78UL); + TESTINST_RR("clo.d", "$r30", "$r19", 0xda0aa8b04f719a51UL, 0x8f93c7a1b3cc9f12UL); + TESTINST_RR("clo.d", "$r26", "$r20", 0xdd4f62bfe1237a28UL, 0xd61c7bfe05165d04UL); + TESTINST_RR("clo.d", "$r26", "$r6", 0x44a1378e22d6ec81UL, 0x1b21543ee9abd103UL); + TESTINST_RR("clo.d", "$r24", "$r16", 0x51efcf6ef8eb9917UL, 0x602cbdf020ee6da8UL); + + /* ---------------- clz.d rd, rj ---------------- */ + TESTINST_RR("clz.d", "$r27", "$r7", 0x91df318f7b476077UL, 0x6ca0b9cf9bb84c4aUL); + TESTINST_RR("clz.d", "$r19", "$r30", 0x435d7fb412d9c12cUL, 0xc926e58bdb46104eUL); + TESTINST_RR("clz.d", "$r12", "$r30", 0x906b06441b2ef62bUL, 0x4b9b91966077ef0UL); + TESTINST_RR("clz.d", "$r28", "$r6", 0x28bb3e3324f33e14UL, 0x7628cd8752be6223UL); + TESTINST_RR("clz.d", "$r14", "$r15", 0xb7a5ae04bf2e60c0UL, 0x41a328a79afda305UL); + TESTINST_RR("clz.d", "$r4", "$r23", 0x5fd8327a265b1a3bUL, 0x66b92d8b5b842d4aUL); + TESTINST_RR("clz.d", "$r18", "$r29", 0x73df6808e38c72adUL, 0x6b91b11261dd26b6UL); + TESTINST_RR("clz.d", "$r13", "$r8", 0xd8d2dbd71d1783adUL, 0xdc50b7586ccab6a1UL); + TESTINST_RR("clz.d", "$r17", "$r10", 0xee6f842bb7686b8dUL, 0xdf52e003cd95f02fUL); + TESTINST_RR("clz.d", "$r13", "$r8", 0x91e717aef96cc046UL, 0x5dd0743ed560ba78UL); + + /* ---------------- cto.d rd, rj ---------------- */ + TESTINST_RR("cto.d", "$r31", "$r5", 0xf361d5d1fb232769UL, 0x1530b67240d804cfUL); + TESTINST_RR("cto.d", "$r5", "$r26", 0xbedb393d17f69d40UL, 0xcef56269ef7aecdaUL); + TESTINST_RR("cto.d", "$r5", "$r31", 0xadd75db878cdbf84UL, 0x8e08acc65c97f0b2UL); + TESTINST_RR("cto.d", "$r31", "$r31", 0x6a8a89827e4929f9UL, 0x7df0f59d97924bb3UL); + TESTINST_RR("cto.d", "$r14", "$r30", 0xefb0874ef3600b6dUL, 0x97a4b45ab971a548UL); + TESTINST_RR("cto.d", "$r5", "$r17", 0x144271fb49c8d2d8UL, 0x787e6dbb4fec4d21UL); + TESTINST_RR("cto.d", "$r28", "$r20", 0xd6d0953d2a12c998UL, 0xafd578caad0dfa09UL); + TESTINST_RR("cto.d", "$r16", "$r18", 0xde650be54a7990cUL, 0x3ea8f45e10441829UL); + TESTINST_RR("cto.d", "$r15", "$r16", 0xbbd328743f49a86UL, 0x5cafc638b6b509beUL); + TESTINST_RR("cto.d", "$r6", "$r20", 0x598ee27859cf8d0eUL, 0x4bce530e537ad762UL); + + /* ---------------- ctz.d rd, rj ---------------- */ + TESTINST_RR("ctz.d", "$r14", "$r28", 0xf2e4d886a8fd3fe3UL, 0xdafbabdfefac692UL); + TESTINST_RR("ctz.d", "$r6", "$r27", 0xe005a6a20d44fbcaUL, 0xe000ac4f4cfb2ce2UL); + TESTINST_RR("ctz.d", "$r15", "$r26", 0x871c2ccd50ec0784UL, 0xa82b0d96dd72f11cUL); + TESTINST_RR("ctz.d", "$r17", "$r20", 0xebe7d9f4ec5055d5UL, 0x65575957936d1d6eUL); + TESTINST_RR("ctz.d", "$r19", "$r8", 0x394effa243e5f14cUL, 0xf6852349a7b00561UL); + TESTINST_RR("ctz.d", "$r5", "$r9", 0x3c67392fc408e9dbUL, 0xeff4bf8e886d7cc3UL); + TESTINST_RR("ctz.d", "$r31", "$r15", 0xbf5435775bd0435bUL, 0x19760246c8d1d680UL); + TESTINST_RR("ctz.d", "$r9", "$r5", 0xccde230362ce06aUL, 0x7590c6e73077c2bcUL); + TESTINST_RR("ctz.d", "$r28", "$r25", 0x2518777b06d608a0UL, 0xb87647dad481ba32UL); + TESTINST_RR("ctz.d", "$r23", "$r19", 0xbe232a9fe2090e75UL, 0x2dceda5cdc990d2eUL); + + /* ---------------- revb.2h rd, rj ---------------- */ + TESTINST_RR("revb.2h", "$r29", "$r30", 0x75397084990a0745UL, 0xd4c83f5966c1c17UL); + TESTINST_RR("revb.2h", "$r17", "$r23", 0xecfbee2a69bbe344UL, 0x5a42dc5dc5705f68UL); + TESTINST_RR("revb.2h", "$r6", "$r14", 0xbfeffdbd68845522UL, 0x3490af5b50fd56bfUL); + TESTINST_RR("revb.2h", "$r13", "$r6", 0x58e1821d319a1598UL, 0x4c6711d021a72be6UL); + TESTINST_RR("revb.2h", "$r18", "$r8", 0x6e14994d4e16ff86UL, 0x9fda01513ab5ceb8UL); + TESTINST_RR("revb.2h", "$r7", "$r30", 0x9979d3a3fcfc9323UL, 0x504c708535bc136fUL); + TESTINST_RR("revb.2h", "$r28", "$r19", 0x9daf4aa3a33eec5fUL, 0xaa376fc54f4be6f5UL); + TESTINST_RR("revb.2h", "$r30", "$r8", 0x2e0bba43ec83e59eUL, 0xaee8b8acd436f6daUL); + TESTINST_RR("revb.2h", "$r14", "$r7", 0x9634787c9be10863UL, 0xe9da521d42716c0aUL); + TESTINST_RR("revb.2h", "$r23", "$r14", 0x687b89225667081aUL, 0x9089e36a4f12f9c6UL); + + /* ---------------- revb.4h rd, rj ---------------- */ + TESTINST_RR("revb.4h", "$r4", "$r25", 0xc42859bd06b669d2UL, 0x782e4ae6ab812191UL); + TESTINST_RR("revb.4h", "$r18", "$r19", 0x45ca4499d789fe5bUL, 0x6e558c98b95d346dUL); + TESTINST_RR("revb.4h", "$r24", "$r10", 0x2d04871fd753c43fUL, 0xbeab033e2b5a979eUL); + TESTINST_RR("revb.4h", "$r24", "$r8", 0xbc4deb39fb2ffe2eUL, 0x5e3e50b8025e77f3UL); + TESTINST_RR("revb.4h", "$r7", "$r14", 0xf44a6ea6f42e0918UL, 0x9f617a848e4ad8f2UL); + TESTINST_RR("revb.4h", "$r13", "$r12", 0xda815ff8648e92b9UL, 0xa401e74c4dd88e12UL); + TESTINST_RR("revb.4h", "$r31", "$r19", 0x7964d861d2ecb8d5UL, 0xe402e87f73fb4c68UL); + TESTINST_RR("revb.4h", "$r29", "$r25", 0x6beff3fa6167cdccUL, 0x11e350b71aee0229UL); + TESTINST_RR("revb.4h", "$r4", "$r8", 0x357a56e8ae275376UL, 0xdf8ebc175f4be7e3UL); + TESTINST_RR("revb.4h", "$r15", "$r27", 0xeb11b29acfe397d6UL, 0x42d231083cd97aa0UL); + + /* ---------------- revb.2w rd, rj ---------------- */ + TESTINST_RR("revb.2w", "$r27", "$r31", 0x978f867dd7f0cb8UL, 0x19eec2d357cd6a06UL); + TESTINST_RR("revb.2w", "$r10", "$r10", 0x7897a40c4fda96d5UL, 0xcb849783a18de892UL); + TESTINST_RR("revb.2w", "$r23", "$r14", 0x18338c734be53a1UL, 0x6258664ec1bb96b8UL); + TESTINST_RR("revb.2w", "$r12", "$r19", 0x7417ec4fef3451ccUL, 0x216ad32ee149542bUL); + TESTINST_RR("revb.2w", "$r31", "$r30", 0x8132835b9905b650UL, 0x6fac007fbefdecf2UL); + TESTINST_RR("revb.2w", "$r25", "$r10", 0x7336ebe375c83bedUL, 0x643f76ac3010a6bbUL); + TESTINST_RR("revb.2w", "$r31", "$r29", 0x5d99f79f18e805b8UL, 0xe65e70ca4cf299faUL); + TESTINST_RR("revb.2w", "$r30", "$r19", 0xec10dd6d7249c5faUL, 0x3f6bb22d66caf299UL); + TESTINST_RR("revb.2w", "$r6", "$r30", 0x2c394783817c0870UL, 0xd823cff07efd78dbUL); + TESTINST_RR("revb.2w", "$r4", "$r15", 0xc5acf61f075cd4e4UL, 0xc154dd7479b90c6cUL); + + /* ---------------- revb.d rd, rj ---------------- */ + TESTINST_RR("revb.d", "$r6", "$r23", 0xe6e05a0dafda37ceUL, 0x2ac7d047f197f6fbUL); + TESTINST_RR("revb.d", "$r19", "$r4", 0xc07a757bea6011ffUL, 0xcef6cef3e0f941ffUL); + TESTINST_RR("revb.d", "$r6", "$r15", 0x711bb31e18fcb2f3UL, 0x522068042cf5be1aUL); + TESTINST_RR("revb.d", "$r9", "$r7", 0xf9654c655c67392eUL, 0xa1b065742110e3f4UL); + TESTINST_RR("revb.d", "$r29", "$r4", 0x70c0dcad23609060UL, 0x5d04b7b2ece6f6bbUL); + TESTINST_RR("revb.d", "$r15", "$r4", 0x809930516f3136ebUL, 0xda33327a8d42ef55UL); + TESTINST_RR("revb.d", "$r10", "$r4", 0x1a7ee04b354f6af5UL, 0xcda6c6943e46fed7UL); + TESTINST_RR("revb.d", "$r20", "$r4", 0x315f95452d748459UL, 0xa001e934745758e0UL); + TESTINST_RR("revb.d", "$r6", "$r8", 0xabbd06000374627aUL, 0x85441006689de89bUL); + TESTINST_RR("revb.d", "$r27", "$r24", 0x2d404e69f54afa48UL, 0x46f47b822772f3cdUL); + + /* ---------------- revh.2w rd, rj ---------------- */ + TESTINST_RR("revh.2w", "$r6", "$r15", 0x5b764c7bfb1999ebUL, 0x86603fc3f96843edUL); + TESTINST_RR("revh.2w", "$r19", "$r10", 0xf39f8e6b43dd63ceUL, 0x141d294d06276941UL); + TESTINST_RR("revh.2w", "$r5", "$r20", 0x3ff54e5c35d83e69UL, 0xd677d6a21384278aUL); + TESTINST_RR("revh.2w", "$r4", "$r31", 0xce463b02a2f840ccUL, 0x6f87c9636f9cfca6UL); + TESTINST_RR("revh.2w", "$r19", "$r26", 0x34abc96ddde64e27UL, 0x723ec7ce92720502UL); + TESTINST_RR("revh.2w", "$r8", "$r18", 0x1454a1ee8739c235UL, 0xd890efa373a6dfb0UL); + TESTINST_RR("revh.2w", "$r12", "$r31", 0xf0c8b856751cae70UL, 0xb675dff2568e6ebfUL); + TESTINST_RR("revh.2w", "$r24", "$r9", 0xb36984e3a7a3eaeaUL, 0xa169cfa9f35f6a8aUL); + TESTINST_RR("revh.2w", "$r25", "$r27", 0x640b3e6b41180473UL, 0x9bc307f0a2ef368fUL); + TESTINST_RR("revh.2w", "$r7", "$r9", 0x897e1406a0eb2dc9UL, 0x1921bcf657fecdccUL); + + /* ---------------- revh.d rd, rj ---------------- */ + TESTINST_RR("revh.d", "$r14", "$r25", 0xec3573411ea025e5UL, 0x6976d4371b08f1abUL); + TESTINST_RR("revh.d", "$r24", "$r31", 0x9ef9e5cb1375d42aUL, 0x9ce130c8a579e11dUL); + TESTINST_RR("revh.d", "$r9", "$r28", 0x3c8cd0055a5e7031UL, 0xf05f9381753ded16UL); + TESTINST_RR("revh.d", "$r24", "$r26", 0x6a4e5797f19041f6UL, 0xd26a5ae65e21041cUL); + TESTINST_RR("revh.d", "$r14", "$r24", 0xe2cb9a83aee22d97UL, 0x6405d71e0bb63321UL); + TESTINST_RR("revh.d", "$r19", "$r23", 0x91cdf3bcd9afe76dUL, 0x171953826107396aUL); + TESTINST_RR("revh.d", "$r23", "$r14", 0x93ed49255d084e12UL, 0x374bd76990198b43UL); + TESTINST_RR("revh.d", "$r31", "$r12", 0x8e54a908f04882bUL, 0xf7e8756491b9d346UL); + TESTINST_RR("revh.d", "$r31", "$r20", 0xbb7cd34502fdf01fUL, 0x906b7289a6957d3fUL); + TESTINST_RR("revh.d", "$r27", "$r30", 0xacbca1aacdd9dd3fUL, 0x3072d9c69004d4b5UL); + + /* ---------------- bitrev.4b rd, rj ---------------- */ + TESTINST_RR("bitrev.4b", "$r23", "$r19", 0xb422f2854b491d92UL, 0x7649084cec69098aUL); + TESTINST_RR("bitrev.4b", "$r27", "$r16", 0xd14736328d74b448UL, 0x1abee3a271c71db9UL); + TESTINST_RR("bitrev.4b", "$r15", "$r23", 0xf17c0f0ccfbb2c38UL, 0x490107ff4155bd17UL); + TESTINST_RR("bitrev.4b", "$r5", "$r18", 0x8408d6a30523619dUL, 0x625d5aedf0add9fbUL); + TESTINST_RR("bitrev.4b", "$r8", "$r15", 0xc41a2fdb60ba75a6UL, 0xe2562eab3b333a00UL); + TESTINST_RR("bitrev.4b", "$r17", "$r18", 0x6a409394f364c02aUL, 0xea970d90edb343ccUL); + TESTINST_RR("bitrev.4b", "$r25", "$r29", 0xd8d1c9b8dcff266dUL, 0xacca47ac7597ca65UL); + TESTINST_RR("bitrev.4b", "$r26", "$r24", 0xe2a0d11df8c5055bUL, 0xc57559d03e3e216dUL); + TESTINST_RR("bitrev.4b", "$r8", "$r27", 0xb6a5815170d657f0UL, 0x9f60901eefa1347aUL); + TESTINST_RR("bitrev.4b", "$r20", "$r16", 0x432a2fbf2b073732UL, 0x604b8d7ecb5e86dcUL); + + /* ---------------- bitrev.8b rd, rj ---------------- */ + TESTINST_RR("bitrev.8b", "$r25", "$r7", 0x22b2e6007f742fd1UL, 0xe8c23886def1bbc9UL); + TESTINST_RR("bitrev.8b", "$r28", "$r30", 0xf985d7779c5ca157UL, 0x285cbdc0f47395d1UL); + TESTINST_RR("bitrev.8b", "$r29", "$r13", 0xd9b8364a793bc50cUL, 0xded35d7c7ba73d29UL); + TESTINST_RR("bitrev.8b", "$r12", "$r28", 0x18d7769bc1147dc5UL, 0xfb6cda8c7f12313aUL); + TESTINST_RR("bitrev.8b", "$r23", "$r6", 0xeff84dc134b3acbeUL, 0xee7c4e89e333eda8UL); + TESTINST_RR("bitrev.8b", "$r24", "$r20", 0xad65748f0bc46e9fUL, 0xd0d88137a6284eacUL); + TESTINST_RR("bitrev.8b", "$r10", "$r5", 0xe0e1c1e262352e89UL, 0x9c43ebc4f7c65dc1UL); + TESTINST_RR("bitrev.8b", "$r27", "$r13", 0x444a53aa65d317dcUL, 0x473eea7ea5691da7UL); + TESTINST_RR("bitrev.8b", "$r13", "$r9", 0xfc48d0fdf4c7a6e5UL, 0x5dcad407df3401a5UL); + TESTINST_RR("bitrev.8b", "$r12", "$r5", 0xebef32fcbd91e9aUL, 0xe1eeea527816355eUL); + + /* ---------------- bitrev.w rd, rj ---------------- */ + TESTINST_RR("bitrev.w", "$r18", "$r15", 0x2028b0c8691a767UL, 0x5822df2950c9c2d3UL); + TESTINST_RR("bitrev.w", "$r30", "$r27", 0x2a2d48209d9f377bUL, 0xde9d59b836df41fcUL); + TESTINST_RR("bitrev.w", "$r17", "$r4", 0xe6fb8b07c90464e6UL, 0x65976cb5c6c6a5b0UL); + TESTINST_RR("bitrev.w", "$r9", "$r31", 0x1b95159ec5c37644UL, 0x62c549b741c2adadUL); + TESTINST_RR("bitrev.w", "$r17", "$r14", 0x8b414dfa7156f0ceUL, 0x9642d0186f420e7cUL); + TESTINST_RR("bitrev.w", "$r15", "$r8", 0x2722ecb374b4d5e3UL, 0xeaf151a286bbc4cfUL); + TESTINST_RR("bitrev.w", "$r27", "$r19", 0x58ec913c63634a5UL, 0xe723c39df96a4fd2UL); + TESTINST_RR("bitrev.w", "$r7", "$r26", 0xa245e7dd80a324a2UL, 0xe7d6c2b2683291eUL); + TESTINST_RR("bitrev.w", "$r31", "$r6", 0x114292ed02ba1255UL, 0x13cd62afac5ac3d4UL); + TESTINST_RR("bitrev.w", "$r7", "$r25", 0xbd46d88fc8d2933bUL, 0x69ce9ccb487dadd1UL); + + /* ---------------- bitrev.d rd, rj ---------------- */ + TESTINST_RR("bitrev.d", "$r4", "$r29", 0xeaacaeb60b227eabUL, 0x799f36da44887e2cUL); + TESTINST_RR("bitrev.d", "$r29", "$r6", 0xcfbb055ab1ebf7faUL, 0x2924f63fec744b02UL); + TESTINST_RR("bitrev.d", "$r28", "$r31", 0xaac74a398d76900dUL, 0xf6c75e45e33b4cb7UL); + TESTINST_RR("bitrev.d", "$r24", "$r12", 0xfc8bc33fb4a8d023UL, 0xcccd98e9d53aa26aUL); + TESTINST_RR("bitrev.d", "$r8", "$r7", 0x7502cd68289f4c3aUL, 0x746ddfd3c3a512b1UL); + TESTINST_RR("bitrev.d", "$r6", "$r16", 0xe8b94bfe615774aeUL, 0x518770bbee53d619UL); + TESTINST_RR("bitrev.d", "$r24", "$r4", 0x6318c17dbae816c3UL, 0x9ab684e129b57f07UL); + TESTINST_RR("bitrev.d", "$r27", "$r23", 0x8a22909b005a86b8UL, 0x69337e8c3b1fc2bbUL); + TESTINST_RR("bitrev.d", "$r20", "$r9", 0x9f43885d40caf0UL, 0x193cbf609dbc33d4UL); + TESTINST_RR("bitrev.d", "$r30", "$r19", 0x30fa02e0fc390ac9UL, 0x21686c931c6260daUL); + + /* ---------------- bytepick.w rd, rj, rk, sa2 ---------------- */ + TESTINST_RRRI("bytepick.w", "$r26", "$r15", "$r19", SA2, 0x1b0b980dd3271273UL, 0x8737ca6c8106ceeeUL, 0x2807e0dcb47d6efUL, 1); + TESTINST_RRRI("bytepick.w", "$r15", "$r17", "$r7", SA2, 0x3d2e3fbcbd032001UL, 0x5eced8cf3da8b205UL, 0xb8155b41321e09c0UL, 0); + TESTINST_RRRI("bytepick.w", "$r12", "$r15", "$r17", SA2, 0x2670c80f12a87520UL, 0x29ab42125e3ea5c8UL, 0x32a39ac435460f2fUL, 3); + TESTINST_RRRI("bytepick.w", "$r4", "$r20", "$r18", SA2, 0x5a64271926277c04UL, 0xcbde225cc736e5d5UL, 0x18abacc874db47e9UL, 3); + TESTINST_RRRI("bytepick.w", "$r8", "$r5", "$r24", SA2, 0xdb41606ce3f9df94UL, 0xc3f6ce370d754a3fUL, 0x34ad5a423a5c42e3UL, 3); + TESTINST_RRRI("bytepick.w", "$r5", "$r30", "$r14", SA2, 0xedb3aad221050d0bUL, 0x46f5823389f2581aUL, 0xf766f1e75349809eUL, 2); + TESTINST_RRRI("bytepick.w", "$r4", "$r19", "$r18", SA2, 0xf92ed0231f25c991UL, 0xba59df0352ed6b3eUL, 0x58d6fbce4e4325e8UL, 0); + TESTINST_RRRI("bytepick.w", "$r18", "$r28", "$r24", SA2, 0x177dcaf8fcd30180UL, 0xbdc04b3b8f707462UL, 0x6102168606deb3edUL, 3); + TESTINST_RRRI("bytepick.w", "$r13", "$r27", "$r29", SA2, 0x383d82c5d717259bUL, 0x495e30e5e680d7fcUL, 0x1c17f315ebb3bec3UL, 2); + TESTINST_RRRI("bytepick.w", "$r5", "$r29", "$r4", SA2, 0x26a0fb212ab80a3aUL, 0x78b167aecd81f869UL, 0x6daab499f228fef4UL, 1); + + /* ---------------- bytepick.d rd, rj, rk, sa3 ---------------- */ + TESTINST_RRRI("bytepick.d", "$r28", "$r4", "$r28", SA3, 0x794fa22d52f7e834UL, 0x2f084db071d3bcceUL, 0xa0cf51d7020f10c1UL, 7); + TESTINST_RRRI("bytepick.d", "$r10", "$r18", "$r4", SA3, 0x9fd7a6b378604833UL, 0x37da15f8a7154cabUL, 0xaedd64328d27a0a8UL, 2); + TESTINST_RRRI("bytepick.d", "$r7", "$r6", "$r24", SA3, 0xdee49920d429d3c2UL, 0x15e3f61f2f82a2d1UL, 0xdeba03c7761e4678UL, 3); + TESTINST_RRRI("bytepick.d", "$r19", "$r16", "$r5", SA3, 0x53bda4d18e61fc44UL, 0xc79bd94439006673UL, 0xa8024ab452a2bd52UL, 4); + TESTINST_RRRI("bytepick.d", "$r26", "$r19", "$r25", SA3, 0xc8aae5136d925592UL, 0xea109dd2837d3acfUL, 0x30e93a75e695666aUL, 7); + TESTINST_RRRI("bytepick.d", "$r8", "$r14", "$r8", SA3, 0xa03db273c845b37fUL, 0xa7fd0053a136769fUL, 0x6ab932903229b035UL, 2); + TESTINST_RRRI("bytepick.d", "$r9", "$r14", "$r23", SA3, 0x2f160a0d147b300fUL, 0xdae9d5d15bb8f5b5UL, 0xc4fdfbb29d49dfe4UL, 2); + TESTINST_RRRI("bytepick.d", "$r20", "$r18", "$r15", SA3, 0x30cefdebc30b841aUL, 0xbfd016fb0312277cUL, 0x44269b95d496912fUL, 5); + TESTINST_RRRI("bytepick.d", "$r12", "$r17", "$r5", SA3, 0xde32bc5d3471eed2UL, 0xdb807610c6e762e4UL, 0xb2148e34e649d1b8UL, 2); + TESTINST_RRRI("bytepick.d", "$r5", "$r24", "$r28", SA3, 0x9ab1be6a0faa61a8UL, 0x97d4a12579967739UL, 0xaa592ef1fd606badUL, 3); + + /* ---------------- maskeqz rd, rj, rk ---------------- */ + TESTINST_RRR("maskeqz", "$r14", "$r28", "$r25", 0xc263b6b8f3404c8dUL, 0x90ef733c88c88866UL, 0xd256888d94e8d21aUL); + TESTINST_RRR("maskeqz", "$r13", "$r9", "$r15", 0x5bdd86b962c61db4UL, 0x8a78f7b88a728d92UL, 0x69e707acb2c26a83UL); + TESTINST_RRR("maskeqz", "$r7", "$r7", "$r13", 0xea86abdbdea660cbUL, 0xfb778deef0a5b893UL, 0xad10e23c971d1a9fUL); + TESTINST_RRR("maskeqz", "$r8", "$r7", "$r19", 0xf64df33b6146939fUL, 0xe7376d3da44f4dfdUL, 0x7987e122af2505abUL); + TESTINST_RRR("maskeqz", "$r10", "$r27", "$r29", 0x404a261c069b488bUL, 0x81886c523ec2658cUL, 0x3236dc83d0a27cc1UL); + TESTINST_RRR("maskeqz", "$r23", "$r16", "$r25", 0x8671050519b7bda0UL, 0x26fa2567b106d73aUL, 0xd884011e0d767feUL); + TESTINST_RRR("maskeqz", "$r5", "$r19", "$r18", 0xbd8d4cef53122132UL, 0x4976c047c57ec148UL, 0x602312f372049a5eUL); + TESTINST_RRR("maskeqz", "$r29", "$r24", "$r23", 0x7f390b695d8b12eUL, 0x70043e7666a24a34UL, 0xfee8f8f90ab3ac9bUL); + TESTINST_RRR("maskeqz", "$r25", "$r4", "$r18", 0x7eaffcb6dac1b5bUL, 0x4b12f8c6738216a2UL, 0x409acb80b7391511UL); + TESTINST_RRR("maskeqz", "$r30", "$r6", "$r24", 0x14d829636b628dc9UL, 0xdb88a366a2271c2cUL, 0xea0d5998835940aUL); + + /* ---------------- masknez rd, rj, rk ---------------- */ + TESTINST_RRR("masknez", "$r14", "$r24", "$r5", 0x46b15bbb9507bd79UL, 0xc92af628c880a454UL, 0x846a586db0af0965UL); + TESTINST_RRR("masknez", "$r30", "$r8", "$r8", 0x43cd20b5234db4e8UL, 0x7aeee6ab6b10561fUL, 0x45ab4fdb4ca8b325UL); + TESTINST_RRR("masknez", "$r24", "$r19", "$r15", 0xd3d50bbb34b528e2UL, 0xdd71746b0beedae3UL, 0xa34d82fc50174094UL); + TESTINST_RRR("masknez", "$r29", "$r26", "$r26", 0x576cb2da15b1462dUL, 0x6c669f0195b50b7aUL, 0xec1609ef36aa938fUL); + TESTINST_RRR("masknez", "$r4", "$r29", "$r10", 0xaa220f67a02617dbUL, 0xffcd18e3016e10fUL, 0x4cf9bdd8dca7f88fUL); + TESTINST_RRR("masknez", "$r23", "$r9", "$r29", 0x774e1c840428fbdeUL, 0x391268694388d2a7UL, 0xf06192a4e5780c53UL); + TESTINST_RRR("masknez", "$r7", "$r25", "$r28", 0x7b75099f16135faaUL, 0xf95af681c18bf31cUL, 0x2f6122581dfdef74UL); + TESTINST_RRR("masknez", "$r26", "$r10", "$r16", 0xe6006c9bd6bae204UL, 0x7e84e5db1181249dUL, 0x6ab2371059cdc875UL); + TESTINST_RRR("masknez", "$r26", "$r15", "$r28", 0xb4c9c784ef74245fUL, 0x20cc1c4c169ca02cUL, 0x606eeb8ce6278d16UL); + TESTINST_RRR("masknez", "$r19", "$r16", "$r16", 0x75a721553f7c7054UL, 0x7b63b7b7b3f5bd5fUL, 0xf8c7933e92e155eeUL); + + /* ---------------- bstrins.w rd, rj, msbw, lsbw ---------------- */ + TESTINST_RRII("bstrins.w", "$r27", "$r16", MSBW, LSBW, 0x431055863e78b187UL, 0xe18dda9620a50e9dUL, 31, 8); + TESTINST_RRII("bstrins.w", "$r26", "$r27", MSBW, LSBW, 0x19f800eab7e1ab51UL, 0x61e7d86005d21d29UL, 30, 27); + TESTINST_RRII("bstrins.w", "$r15", "$r4", MSBW, LSBW, 0xb141d462e777528dUL, 0xb7aebff9bcca1643UL, 17, 14); + TESTINST_RRII("bstrins.w", "$r30", "$r17", MSBW, LSBW, 0xfac48083375844feUL, 0x6d3283ba14cc27ebUL, 24, 6); + TESTINST_RRII("bstrins.w", "$r12", "$r12", MSBW, LSBW, 0x9b7629774f19f64aUL, 0x84ee8d65b2842686UL, 30, 25); + TESTINST_RRII("bstrins.w", "$r15", "$r10", MSBW, LSBW, 0x290172844863090fUL, 0x85ea298976069fcdUL, 26, 1); + TESTINST_RRII("bstrins.w", "$r10", "$r13", MSBW, LSBW, 0x66942ba1c15e85aaUL, 0xddb2dfa7474a4370UL, 23, 8); + TESTINST_RRII("bstrins.w", "$r5", "$r20", MSBW, LSBW, 0x3dcfecca80bf0d79UL, 0x5044b246f2d3f890UL, 18, 16); + TESTINST_RRII("bstrins.w", "$r23", "$r5", MSBW, LSBW, 0xa11723142f1472a7UL, 0xcbaaa9a23d119663UL, 25, 21); + TESTINST_RRII("bstrins.w", "$r20", "$r31", MSBW, LSBW, 0x6a1110240ba884b8UL, 0x45cadf0ffe08cc25UL, 13, 12); + + /* ---------------- bstrpick.w rd, rj, msbw, lsbw ---------------- */ + TESTINST_RRII("bstrpick.w", "$r5", "$r23", MSBW, LSBW, 0x6885eaa89f691954UL, 0x94f8458597294f2eUL, 23, 11); + TESTINST_RRII("bstrpick.w", "$r25", "$r8", MSBW, LSBW, 0x11be9b9923ebee96UL, 0x23deda120a49df15UL, 18, 11); + TESTINST_RRII("bstrpick.w", "$r6", "$r6", MSBW, LSBW, 0x3546d655181289bcUL, 0x7ee84a41c952b690UL, 10, 3); + TESTINST_RRII("bstrpick.w", "$r25", "$r5", MSBW, LSBW, 0xb2eec884ea77f548UL, 0x23992bc40919416fUL, 15, 9); + TESTINST_RRII("bstrpick.w", "$r26", "$r14", MSBW, LSBW, 0x8e591161730ac582UL, 0xf45f4435cc1cb138UL, 21, 8); + TESTINST_RRII("bstrpick.w", "$r9", "$r14", MSBW, LSBW, 0x1ac92d930e8361f9UL, 0xcc11dd56e96c6256UL, 7, 3); + TESTINST_RRII("bstrpick.w", "$r19", "$r9", MSBW, LSBW, 0xd15fd80fafe60a58UL, 0xb1426a8c680d628cUL, 8, 8); + TESTINST_RRII("bstrpick.w", "$r17", "$r13", MSBW, LSBW, 0xfa48c3cd091d2b5eUL, 0x3a2827a58a014a72UL, 30, 12); + TESTINST_RRII("bstrpick.w", "$r6", "$r31", MSBW, LSBW, 0xca10a858ebfa78a1UL, 0x202a38722f270884UL, 16, 7); + TESTINST_RRII("bstrpick.w", "$r20", "$r10", MSBW, LSBW, 0xc010deb269ae6ba2UL, 0x98f1d297734f9f4cUL, 31, 15); + + /* ---------------- bstrins.d rd, rj, msbd, lsbd ---------------- */ + TESTINST_RRII("bstrins.d", "$r29", "$r17", MSBD, LSBD, 0x7cf4a9ec79307e59UL, 0xb1b5afc00eef90a3UL, 60, 25); + TESTINST_RRII("bstrins.d", "$r10", "$r27", MSBD, LSBD, 0xc708602dee32579fUL, 0x199d90a711e94375UL, 31, 22); + TESTINST_RRII("bstrins.d", "$r4", "$r24", MSBD, LSBD, 0x4e5ce98e217a4b59UL, 0xaf25b5661daefdeaUL, 58, 58); + TESTINST_RRII("bstrins.d", "$r12", "$r30", MSBD, LSBD, 0x9505d862c56b1708UL, 0x7f3f0c983ce27863UL, 16, 6); + TESTINST_RRII("bstrins.d", "$r29", "$r5", MSBD, LSBD, 0x248f295ef3afe5aaUL, 0x9469277db61227b7UL, 43, 0); + TESTINST_RRII("bstrins.d", "$r31", "$r31", MSBD, LSBD, 0xbc5f0c47c3a63a94UL, 0x4aacc1c77ad0c09aUL, 49, 23); + TESTINST_RRII("bstrins.d", "$r6", "$r24", MSBD, LSBD, 0x79110235b8c34188UL, 0x75e3e311aef2bef9UL, 12, 2); + TESTINST_RRII("bstrins.d", "$r6", "$r16", MSBD, LSBD, 0xaa6e63ffd80b76c5UL, 0xb1ea7dcb3af0881dUL, 43, 13); + TESTINST_RRII("bstrins.d", "$r15", "$r25", MSBD, LSBD, 0x5b68a802f26a1804UL, 0xb4f651115b84591bUL, 53, 29); + TESTINST_RRII("bstrins.d", "$r9", "$r9", MSBD, LSBD, 0x3394218c965d5f1aUL, 0xf3d30b5d4d4089b4UL, 61, 40); + + /* ---------------- bstrpick.d rd, rj, msbd, lsbd ---------------- */ + TESTINST_RRII("bstrpick.d", "$r27", "$r27", MSBD, LSBD, 0x503c8fae2d6d7b58UL, 0x9fd9869ca812de0cUL, 63, 33); + TESTINST_RRII("bstrpick.d", "$r14", "$r5", MSBD, LSBD, 0x65f05eaa5e13856aUL, 0xd52c72fbeccc39f5UL, 52, 40); + TESTINST_RRII("bstrpick.d", "$r13", "$r20", MSBD, LSBD, 0x9cea777df4d2eae0UL, 0x6326727a36499800UL, 48, 14); + TESTINST_RRII("bstrpick.d", "$r10", "$r17", MSBD, LSBD, 0xf30a073a4a56604bUL, 0xc12d112f6a0c8f1UL, 43, 20); + TESTINST_RRII("bstrpick.d", "$r13", "$r25", MSBD, LSBD, 0xe559d975e0d9ac85UL, 0xcf41f30cc4a46713UL, 55, 37); + TESTINST_RRII("bstrpick.d", "$r29", "$r4", MSBD, LSBD, 0x41843db6c2a206cbUL, 0x343f795d45fcff8cUL, 34, 20); + TESTINST_RRII("bstrpick.d", "$r27", "$r28", MSBD, LSBD, 0xb359821297377feeUL, 0x4fc51c5773e64f69UL, 27, 10); + TESTINST_RRII("bstrpick.d", "$r24", "$r24", MSBD, LSBD, 0xed3cb5d1e8f0e55eUL, 0x9cdbb70a8b8d3945UL, 63, 20); + TESTINST_RRII("bstrpick.d", "$r7", "$r30", MSBD, LSBD, 0x11b7344343be1ccfUL, 0xa3422c671803480fUL, 34, 30); + TESTINST_RRII("bstrpick.d", "$r15", "$r4", MSBD, LSBD, 0x3670c6b869f28085UL, 0x2caa9d9c1351e402UL, 55, 4); + + /* ---------------- crc.w.b.w rd, rj, rk ---------------- */ + TESTINST_RRR("crc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4b154113f7d32514UL, 0xcce230caafbf9cc9UL); + TESTINST_RRR("crc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x33d5d595721d4f13UL, 0xf4509311f443a7ceUL); + TESTINST_RRR("crc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4a3c6de6954cbc17UL, 0x111b21e39fbd7254UL); + TESTINST_RRR("crc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xfbb5c64ed1b044c6UL, 0x33ca4c4fb3960326UL); + TESTINST_RRR("crc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x2b7c5939d7c0f528UL, 0xb73870a5a6630162UL); + TESTINST_RRR("crc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x02fe41918ac5cdbaUL, 0x48e0815289728f05UL); + TESTINST_RRR("crc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xb60a8f381f187baeUL, 0x008c208cc413ff72UL); + + /* ---------------- crc.w.h.w rd, rj, rk ---------------- */ + TESTINST_RRR("crc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4b154113f7d32514UL, 0xcce230caafbf9cc9UL); + TESTINST_RRR("crc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x33d5d595721d4f13UL, 0xf4509311f443a7ceUL); + TESTINST_RRR("crc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4a3c6de6954cbc17UL, 0x111b21e39fbd7254UL); + TESTINST_RRR("crc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xfbb5c64ed1b044c6UL, 0x33ca4c4fb3960326UL); + TESTINST_RRR("crc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x2b7c5939d7c0f528UL, 0xb73870a5a6630162UL); + TESTINST_RRR("crc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x02fe41918ac5cdbaUL, 0x48e0815289728f05UL); + TESTINST_RRR("crc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xb60a8f381f187baeUL, 0x008c208cc413ff72UL); + + /* ---------------- crc.w.w.w rd, rj, rk ---------------- */ + TESTINST_RRR("crc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4b154113f7d32514UL, 0xcce230caafbf9cc9UL); + TESTINST_RRR("crc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x33d5d595721d4f13UL, 0xf4509311f443a7ceUL); + TESTINST_RRR("crc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4a3c6de6954cbc17UL, 0x111b21e39fbd7254UL); + TESTINST_RRR("crc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xfbb5c64ed1b044c6UL, 0x33ca4c4fb3960326UL); + TESTINST_RRR("crc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x2b7c5939d7c0f528UL, 0xb73870a5a6630162UL); + TESTINST_RRR("crc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x02fe41918ac5cdbaUL, 0x48e0815289728f05UL); + TESTINST_RRR("crc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xb60a8f381f187baeUL, 0x008c208cc413ff72UL); + + /* ---------------- crc.w.d.w rd, rj, rk ---------------- */ + TESTINST_RRR("crc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4b154113f7d32514UL, 0xcce230caafbf9cc9UL); + TESTINST_RRR("crc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x33d5d595721d4f13UL, 0xf4509311f443a7ceUL); + TESTINST_RRR("crc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4a3c6de6954cbc17UL, 0x111b21e39fbd7254UL); + TESTINST_RRR("crc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xfbb5c64ed1b044c6UL, 0x33ca4c4fb3960326UL); + TESTINST_RRR("crc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x2b7c5939d7c0f528UL, 0xb73870a5a6630162UL); + TESTINST_RRR("crc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x02fe41918ac5cdbaUL, 0x48e0815289728f05UL); + TESTINST_RRR("crc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xb60a8f381f187baeUL, 0x008c208cc413ff72UL); + + /* ---------------- crcc.w.b.w rd, rj, rk ---------------- */ + TESTINST_RRR("crcc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4b154113f7d32514UL, 0xcce230caafbf9cc9UL); + TESTINST_RRR("crcc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x33d5d595721d4f13UL, 0xf4509311f443a7ceUL); + TESTINST_RRR("crcc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4a3c6de6954cbc17UL, 0x111b21e39fbd7254UL); + TESTINST_RRR("crcc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xfbb5c64ed1b044c6UL, 0x33ca4c4fb3960326UL); + TESTINST_RRR("crcc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x2b7c5939d7c0f528UL, 0xb73870a5a6630162UL); + TESTINST_RRR("crcc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x02fe41918ac5cdbaUL, 0x48e0815289728f05UL); + TESTINST_RRR("crcc.w.b.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xb60a8f381f187baeUL, 0x008c208cc413ff72UL); + + /* ---------------- crcc.w.h.w rd, rj, rk ---------------- */ + TESTINST_RRR("crcc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4b154113f7d32514UL, 0xcce230caafbf9cc9UL); + TESTINST_RRR("crcc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x33d5d595721d4f13UL, 0xf4509311f443a7ceUL); + TESTINST_RRR("crcc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4a3c6de6954cbc17UL, 0x111b21e39fbd7254UL); + TESTINST_RRR("crcc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xfbb5c64ed1b044c6UL, 0x33ca4c4fb3960326UL); + TESTINST_RRR("crcc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x2b7c5939d7c0f528UL, 0xb73870a5a6630162UL); + TESTINST_RRR("crcc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x02fe41918ac5cdbaUL, 0x48e0815289728f05UL); + TESTINST_RRR("crcc.w.h.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xb60a8f381f187baeUL, 0x008c208cc413ff72UL); + + /* ---------------- crcc.w.w.w rd, rj, rk ---------------- */ + TESTINST_RRR("crcc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4b154113f7d32514UL, 0xcce230caafbf9cc9UL); + TESTINST_RRR("crcc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x33d5d595721d4f13UL, 0xf4509311f443a7ceUL); + TESTINST_RRR("crcc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4a3c6de6954cbc17UL, 0x111b21e39fbd7254UL); + TESTINST_RRR("crcc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xfbb5c64ed1b044c6UL, 0x33ca4c4fb3960326UL); + TESTINST_RRR("crcc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x2b7c5939d7c0f528UL, 0xb73870a5a6630162UL); + TESTINST_RRR("crcc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x02fe41918ac5cdbaUL, 0x48e0815289728f05UL); + TESTINST_RRR("crcc.w.w.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xb60a8f381f187baeUL, 0x008c208cc413ff72UL); + + /* ---------------- crcc.w.d.w rd, rj, rk ---------------- */ + TESTINST_RRR("crcc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4b154113f7d32514UL, 0xcce230caafbf9cc9UL); + TESTINST_RRR("crcc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x33d5d595721d4f13UL, 0xf4509311f443a7ceUL); + TESTINST_RRR("crcc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x4a3c6de6954cbc17UL, 0x111b21e39fbd7254UL); + TESTINST_RRR("crcc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xfbb5c64ed1b044c6UL, 0x33ca4c4fb3960326UL); + TESTINST_RRR("crcc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x2b7c5939d7c0f528UL, 0xb73870a5a6630162UL); + TESTINST_RRR("crcc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0x02fe41918ac5cdbaUL, 0x48e0815289728f05UL); + TESTINST_RRR("crcc.w.d.w", "$r12", "$r13", "$r14", 0x123456789abcdefUL, 0xb60a8f381f187baeUL, 0x008c208cc413ff72UL); +} + +int main(void) +{ + test(); + return 0; +} diff --git a/none/tests/loongarch64/integer.stderr.exp b/none/tests/loongarch64/integer.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/integer.stdout.exp b/none/tests/loongarch64/integer.stdout.exp new file mode 100644 index 0000000..a4592b7 --- /dev/null +++ b/none/tests/loongarch64/integer.stdout.exp @@ -0,0 +1,2748 @@ +add.w $r19, $r20, $r25 :: +before: $r19=0xf7f01ffbc9696094, $r20=0xb664b1ce21c8c7fc, $r25=0x0d0a02b79ace85cf +after: $r19=0xffffffffbc974dcb, $r20=0xb664b1ce21c8c7fc, $r25=0x0d0a02b79ace85cf +add.w $r29, $r9, $r12 :: +before: $r29=0x5418cd6f6b640953, $r9=0x6465907ca2dac58c, $r12=0xefea76d0d526df3a +after: $r29=0x000000007801a4c6, $r9=0x6465907ca2dac58c, $r12=0xefea76d0d526df3a +add.w $r23, $r15, $r28 :: +before: $r23=0x6ae34fbc6f2f7a9a, $r15=0xbf21c48ab5c2edcc, $r28=0x24824ebd458ed20e +after: $r23=0xfffffffffb51bfda, $r15=0xbf21c48ab5c2edcc, $r28=0x24824ebd458ed20e +add.w $r27, $r14, $r26 :: +before: $r27=0x9f33e38db05616cc, $r14=0xf12ee0c276c52c78, $r26=0xc3054d65ecec3fe6 +after: $r27=0x0000000063b16c5e, $r14=0xf12ee0c276c52c78, $r26=0xc3054d65ecec3fe6 +add.w $r14, $r23, $r27 :: +before: $r14=0x17eaa07c4607901f, $r23=0xa5fa9d0c8472848e, $r27=0xa34301227bb57f76 +after: $r14=0x0000000000280404, $r23=0xa5fa9d0c8472848e, $r27=0xa34301227bb57f76 +add.w $r19, $r19, $r4 :: +before: $r19=0xd2e0644d9532b5ea, $r19=0x2957c6f0638238bc, $r4=0xf01566d0031ee917 +after: $r19=0x0000000066a121d3, $r19=0x0000000066a121d3, $r4=0xf01566d0031ee917 +add.w $r19, $r26, $r13 :: +before: $r19=0x7b39b3f2ccbdaf79, $r26=0xee877221beef9d45, $r13=0x4a743034eefe075d +after: $r19=0xffffffffadeda4a2, $r26=0xee877221beef9d45, $r13=0x4a743034eefe075d +add.w $r29, $r18, $r14 :: +before: $r29=0x95214c4de7e6d3ba, $r18=0x26502eb481799cd1, $r14=0x34d57b775083fb91 +after: $r29=0xffffffffd1fd9862, $r18=0x26502eb481799cd1, $r14=0x34d57b775083fb91 +add.w $r16, $r26, $r8 :: +before: $r16=0xb66b18865bbb3036, $r26=0x8881ccbe1e31aa8d, $r8=0xffe0d2dde8325edc +after: $r16=0x0000000006640969, $r26=0x8881ccbe1e31aa8d, $r8=0xffe0d2dde8325edc +add.w $r26, $r5, $r8 :: +before: $r26=0xc367af71c905540c, $r5=0xcdcbe4860d983fe3, $r8=0x6687aa19ee1fc503 +after: $r26=0xfffffffffbb804e6, $r5=0xcdcbe4860d983fe3, $r8=0x6687aa19ee1fc503 +add.d $r16, $r18, $r8 :: +before: $r16=0xbe5505b409ce995c, $r18=0x561a85fd57e87226, $r8=0x923f3293987edab0 +after: $r16=0xe859b890f0674cd6, $r18=0x561a85fd57e87226, $r8=0x923f3293987edab0 +add.d $r12, $r7, $r29 :: +before: $r12=0xff2682151edc3476, $r7=0x90beb037eacfe3db, $r29=0xa4017082880f1151 +after: $r12=0x34c020ba72def52c, $r7=0x90beb037eacfe3db, $r29=0xa4017082880f1151 +add.d $r31, $r31, $r5 :: +before: $r31=0x81e38385e39d9f16, $r31=0xedb2ffa50c0c8b5f, $r5=0x8776f30d75fc97c2 +after: $r31=0x7529f2b282092321, $r31=0x7529f2b282092321, $r5=0x8776f30d75fc97c2 +add.d $r31, $r6, $r26 :: +before: $r31=0x64ff385d97b60dc2, $r6=0x80f903f206f08f60, $r26=0x4f5b589532e85398 +after: $r31=0xd0545c8739d8e2f8, $r6=0x80f903f206f08f60, $r26=0x4f5b589532e85398 +add.d $r25, $r10, $r20 :: +before: $r25=0xdd8973d6b99634ca, $r10=0x34c0fe5a72dd43d9, $r20=0x2494af03cf5878e7 +after: $r25=0x5955ad5e4235bcc0, $r10=0x34c0fe5a72dd43d9, $r20=0x2494af03cf5878e7 +add.d $r5, $r10, $r4 :: +before: $r5=0x94b272b05ffe39c8, $r10=0x152d15efbbc54c04, $r4=0x25afc06cf151ab29 +after: $r5=0x3adcd65cad16f72d, $r10=0x152d15efbbc54c04, $r4=0x25afc06cf151ab29 +add.d $r19, $r30, $r18 :: +before: $r19=0xa6e14d42459cadf6, $r30=0x558620ff616141b1, $r18=0x1978905697120747 +after: $r19=0x6efeb155f87348f8, $r30=0x558620ff616141b1, $r18=0x1978905697120747 +add.d $r7, $r8, $r20 :: +before: $r7=0x02ea6f88031a29ae, $r8=0x6a08c12301e00d49, $r20=0xdd533acf17f59142 +after: $r7=0x475bfbf219d59e8b, $r8=0x6a08c12301e00d49, $r20=0xdd533acf17f59142 +add.d $r24, $r14, $r26 :: +before: $r24=0xb88df6b8315eb7a6, $r14=0x0137d04f7f6fe285, $r26=0x2ccb253ff7ea93d6 +after: $r24=0x2e02f58f775a765b, $r14=0x0137d04f7f6fe285, $r26=0x2ccb253ff7ea93d6 +add.d $r7, $r19, $r23 :: +before: $r7=0xad464722c0967f28, $r19=0x30295c1fd85ae029, $r23=0x2c69edb227e01d94 +after: $r7=0x5c9349d2003afdbd, $r19=0x30295c1fd85ae029, $r23=0x2c69edb227e01d94 +sub.w $r16, $r28, $r17 :: +before: $r16=0x8b0ba4ef20207fdd, $r28=0x90493cb39ff734a2, $r17=0x519842bab5cc1208 +after: $r16=0xffffffffea2b229a, $r28=0x90493cb39ff734a2, $r17=0x519842bab5cc1208 +sub.w $r6, $r13, $r15 :: +before: $r6=0x13af983aafc53691, $r13=0x27bc6a037865e47f, $r15=0xe20df003930575d5 +after: $r6=0xffffffffe5606eaa, $r13=0x27bc6a037865e47f, $r15=0xe20df003930575d5 +sub.w $r8, $r19, $r23 :: +before: $r8=0x4177aec74585d42d, $r19=0xba89b6aa9b7728ac, $r23=0x0e6a089b8eaf43fe +after: $r8=0x000000000cc7e4ae, $r19=0xba89b6aa9b7728ac, $r23=0x0e6a089b8eaf43fe +sub.w $r7, $r10, $r23 :: +before: $r7=0x0ca1b83a7ab88912, $r10=0xd5e2759ea82c2c80, $r23=0x76e9d6f88c2624ff +after: $r7=0x000000001c060781, $r10=0xd5e2759ea82c2c80, $r23=0x76e9d6f88c2624ff +sub.w $r19, $r24, $r24 :: +before: $r19=0x99d63505ea0474b3, $r24=0x1b53c4c34957af8e, $r24=0x6146da47b731d3ed +after: $r19=000000000000000000, $r24=0x6146da47b731d3ed, $r24=0x6146da47b731d3ed +sub.w $r26, $r31, $r7 :: +before: $r26=0x8eca560d8234ff55, $r31=0x5beb18985c3f451e, $r7=0x9c9634dfaa7b9313 +after: $r26=0xffffffffb1c3b20b, $r31=0x5beb18985c3f451e, $r7=0x9c9634dfaa7b9313 +sub.w $r29, $r16, $r6 :: +before: $r29=0x229544d2cb1d5a64, $r16=0xd23751d515597128, $r6=0xa09dd29330aa8d15 +after: $r29=0xffffffffe4aee413, $r16=0xd23751d515597128, $r6=0xa09dd29330aa8d15 +sub.w $r12, $r16, $r4 :: +before: $r12=0x229f5aefe9fb7fb7, $r16=0x0740ed49b5e95fae, $r4=0xbc6304a0df442807 +after: $r12=0xffffffffd6a537a7, $r16=0x0740ed49b5e95fae, $r4=0xbc6304a0df442807 +sub.w $r30, $r29, $r26 :: +before: $r30=0x94f3a67d188df281, $r29=0x048e066cdad20ac2, $r26=0x1e032e60568554a7 +after: $r30=0xffffffff844cb61b, $r29=0x048e066cdad20ac2, $r26=0x1e032e60568554a7 +sub.w $r18, $r23, $r25 :: +before: $r18=0xedb4f44fb338ba4f, $r23=0xf06e698cd08c8e7b, $r25=0xa22b91e88b77d4d8 +after: $r18=0x000000004514b9a3, $r23=0xf06e698cd08c8e7b, $r25=0xa22b91e88b77d4d8 +sub.d $r18, $r10, $r27 :: +before: $r18=0x68647aa06a23c8f9, $r10=0xd001cb46cb78fc4f, $r27=0x460cc8702b1761f9 +after: $r18=0x89f502d6a0619a56, $r10=0xd001cb46cb78fc4f, $r27=0x460cc8702b1761f9 +sub.d $r7, $r24, $r18 :: +before: $r7=0x8d18e952fb747f43, $r24=0x1e7d1a019fb96490, $r18=0xb466fb9891e8c151 +after: $r7=0x6a161e690dd0a33f, $r24=0x1e7d1a019fb96490, $r18=0xb466fb9891e8c151 +sub.d $r4, $r16, $r27 :: +before: $r4=0x5f6647277ca4c99d, $r16=0xa1156b863ec98e1d, $r27=0xc15612f3ce819d64 +after: $r4=0xdfbf58927047f0b9, $r16=0xa1156b863ec98e1d, $r27=0xc15612f3ce819d64 +sub.d $r4, $r25, $r9 :: +before: $r4=0xe67b33778df480b4, $r25=0xc24b2711be7e4ef1, $r9=0xd940ca25b956100f +after: $r4=0xe90a5cec05283ee2, $r25=0xc24b2711be7e4ef1, $r9=0xd940ca25b956100f +sub.d $r5, $r12, $r18 :: +before: $r5=0x258ae461ef798ce7, $r12=0x3f4984ea3f5692de, $r18=0x99fa673f30e69019 +after: $r5=0xa54f1dab0e7002c5, $r12=0x3f4984ea3f5692de, $r18=0x99fa673f30e69019 +sub.d $r13, $r10, $r9 :: +before: $r13=0xdafb48debea5211e, $r10=0xeac1d3b25f6bf8db, $r9=0x297d671b1c96e48f +after: $r13=0xc1446c9742d5144c, $r10=0xeac1d3b25f6bf8db, $r9=0x297d671b1c96e48f +sub.d $r7, $r15, $r23 :: +before: $r7=0xc6b03274ff37baf6, $r15=0x05b37ffc2c84aec9, $r23=0x74d62a52cbaaec15 +after: $r7=0x90dd55a960d9c2b4, $r15=0x05b37ffc2c84aec9, $r23=0x74d62a52cbaaec15 +sub.d $r26, $r18, $r26 :: +before: $r26=0x35c71e0956ffcd43, $r18=0xad703a4e8078070b, $r26=0x634924e8a9fdbb9e +after: $r26=0x4a271565d67a4b6d, $r18=0xad703a4e8078070b, $r26=0x4a271565d67a4b6d +sub.d $r16, $r29, $r5 :: +before: $r16=0x18bf961cba922928, $r29=0x54ed9198405f8983, $r5=0x977f5b65e5f86b4a +after: $r16=0xbd6e36325a671e39, $r29=0x54ed9198405f8983, $r5=0x977f5b65e5f86b4a +sub.d $r31, $r28, $r14 :: +before: $r31=0xa38a1e8cb3c7ba00, $r28=0xd220d1ef3cf8f3f7, $r14=0xc972df2ace170d61 +after: $r31=0x08adf2c46ee1e696, $r28=0xd220d1ef3cf8f3f7, $r14=0xc972df2ace170d61 +slt $r12, $r17, $r18 :: +before: $r12=0xd7a0e65c279e1082, $r17=0x819edf00a849ba44, $r18=0x41a0b2fe37d44db2 +after: $r12=0x0000000000000001, $r17=0x819edf00a849ba44, $r18=0x41a0b2fe37d44db2 +slt $r31, $r13, $r18 :: +before: $r31=0x2ef00a5cfd100f71, $r13=0x4792cd9f9abf36d3, $r18=0x2c117902110ef9a8 +after: $r31=000000000000000000, $r13=0x4792cd9f9abf36d3, $r18=0x2c117902110ef9a8 +slt $r4, $r30, $r29 :: +before: $r4=0x6d8be2fb73e2c006, $r30=0xf76ce97d7658995e, $r29=0x3856e09bfe39df6e +after: $r4=0x0000000000000001, $r30=0xf76ce97d7658995e, $r29=0x3856e09bfe39df6e +slt $r4, $r18, $r10 :: +before: $r4=0xeddcb9dcf092c3f5, $r18=0x0e57b7c25d13dea8, $r10=0x761d86b48cb5ce21 +after: $r4=0x0000000000000001, $r18=0x0e57b7c25d13dea8, $r10=0x761d86b48cb5ce21 +slt $r16, $r18, $r16 :: +before: $r16=0xcddd92e2340cd593, $r18=0xc9a30f4707743f80, $r16=0x3ff7d36f17396d3a +after: $r16=0x0000000000000001, $r18=0xc9a30f4707743f80, $r16=0x0000000000000001 +slt $r6, $r14, $r10 :: +before: $r6=0xa9e71c6376093499, $r14=0x26bb3955b588461f, $r10=0xfae7e7a950447826 +after: $r6=000000000000000000, $r14=0x26bb3955b588461f, $r10=0xfae7e7a950447826 +slt $r19, $r4, $r17 :: +before: $r19=0x35bb27f64ebd7d62, $r4=0x4a7d3941ebf88bc1, $r17=0x0cda32e4b1c1d5c4 +after: $r19=000000000000000000, $r4=0x4a7d3941ebf88bc1, $r17=0x0cda32e4b1c1d5c4 +slt $r19, $r28, $r15 :: +before: $r19=0x29419b8261e40b99, $r28=0xe7e9b059033afa7d, $r15=0x1ea916293b1cc3dd +after: $r19=0x0000000000000001, $r28=0xe7e9b059033afa7d, $r15=0x1ea916293b1cc3dd +slt $r31, $r16, $r16 :: +before: $r31=0xe0fb75047bc62c9a, $r16=0xa634f6174dcced7d, $r16=0xcca5a9d25b670e70 +after: $r31=000000000000000000, $r16=0xcca5a9d25b670e70, $r16=0xcca5a9d25b670e70 +slt $r4, $r4, $r10 :: +before: $r4=0x724ee03fb3fcdec8, $r4=0xae2587f097065e2c, $r10=0x65c69548f83dd0df +after: $r4=0x0000000000000001, $r4=0x0000000000000001, $r10=0x65c69548f83dd0df +sltu $r14, $r10, $r13 :: +before: $r14=0x1956e5498db3fb6e, $r10=0x2d909abfec4490bd, $r13=0xa7d554ebe591d5cc +after: $r14=0x0000000000000001, $r10=0x2d909abfec4490bd, $r13=0xa7d554ebe591d5cc +sltu $r6, $r5, $r18 :: +before: $r6=0xc34214447a064eb8, $r5=0xad4413e45f0a226a, $r18=0x4b09aab500b04bff +after: $r6=000000000000000000, $r5=0xad4413e45f0a226a, $r18=0x4b09aab500b04bff +sltu $r31, $r17, $r17 :: +before: $r31=0x86e16a1618a639c4, $r17=0x87917b281cef8df0, $r17=0x0d543115a56dee48 +after: $r31=000000000000000000, $r17=0x0d543115a56dee48, $r17=0x0d543115a56dee48 +sltu $r20, $r6, $r25 :: +before: $r20=0x164fff47b8b23752, $r6=0x9ad830d46b1660f6, $r25=0xc5d72c146f4aba72 +after: $r20=0x0000000000000001, $r6=0x9ad830d46b1660f6, $r25=0xc5d72c146f4aba72 +sltu $r6, $r26, $r7 :: +before: $r6=0x1428360430b7c9b5, $r26=0xc2052dc6eea5a53c, $r7=0xda1a8e35dd060adf +after: $r6=0x0000000000000001, $r26=0xc2052dc6eea5a53c, $r7=0xda1a8e35dd060adf +sltu $r19, $r15, $r26 :: +before: $r19=0xdfc9984966167604, $r15=0xa9ea12b5a37dd492, $r26=0x7a24be9fcf349afc +after: $r19=000000000000000000, $r15=0xa9ea12b5a37dd492, $r26=0x7a24be9fcf349afc +sltu $r29, $r26, $r29 :: +before: $r29=0x5a3822db2cc26fc5, $r26=0x5985f02e77511d80, $r29=0x370f15cc98f2a6c1 +after: $r29=000000000000000000, $r26=0x5985f02e77511d80, $r29=000000000000000000 +sltu $r7, $r28, $r16 :: +before: $r7=0x0e4594ee2cc8c6d7, $r28=0x0177ac0014f5dd20, $r16=0xde1724c7590a4908 +after: $r7=0x0000000000000001, $r28=0x0177ac0014f5dd20, $r16=0xde1724c7590a4908 +sltu $r8, $r12, $r4 :: +before: $r8=0x1df979e50aa0ed18, $r12=0x5b410cd0985fce18, $r4=0x9d3c39d61e29025d +after: $r8=0x0000000000000001, $r12=0x5b410cd0985fce18, $r4=0x9d3c39d61e29025d +sltu $r30, $r23, $r25 :: +before: $r30=0x1cba022788d49d13, $r23=0xd2b40941478ee865, $r25=0xa503a74e41535830 +after: $r30=000000000000000000, $r23=0xd2b40941478ee865, $r25=0xa503a74e41535830 +slti $r15, $r27, 1913 :: +before: $r15=0xe24c4ca567d1d5f4, $r27=0xfef05a88adf4b892 +after: $r15=0x0000000000000001, $r27=0xfef05a88adf4b892 +slti $r8, $r31, -738 :: +before: $r8=0xfba7284a8ab83b2d, $r31=0xff63b80173f1e368 +after: $r8=0x0000000000000001, $r31=0xff63b80173f1e368 +slti $r31, $r31, -1544 :: +before: $r31=0xb4599a9fa734365a, $r31=0x4327139de75dde1e +after: $r31=000000000000000000, $r31=000000000000000000 +slti $r5, $r4, 1529 :: +before: $r5=0xa5572272e0c04a20, $r4=0x87657c1b1699936b +after: $r5=0x0000000000000001, $r4=0x87657c1b1699936b +slti $r10, $r28, 557 :: +before: $r10=0x1260731618214410, $r28=0xd0de0dfbafb7960a +after: $r10=0x0000000000000001, $r28=0xd0de0dfbafb7960a +slti $r5, $r12, -222 :: +before: $r5=0x4c6317772a4b06b0, $r12=0x7a1d4eeb507d649b +after: $r5=000000000000000000, $r12=0x7a1d4eeb507d649b +slti $r4, $r31, 717 :: +before: $r4=0x23b4d62a21994afb, $r31=0x85304cc393f6506b +after: $r4=0x0000000000000001, $r31=0x85304cc393f6506b +slti $r18, $r26, 730 :: +before: $r18=0x67b6f5dbf6a0c55d, $r26=0x451013f9a2337f9f +after: $r18=000000000000000000, $r26=0x451013f9a2337f9f +slti $r25, $r8, 1193 :: +before: $r25=0xdb278cca57f1ad7b, $r8=0x7371a60f5af6334b +after: $r25=000000000000000000, $r8=0x7371a60f5af6334b +slti $r17, $r24, 329 :: +before: $r17=0xffa3ed31f9ea3a29, $r24=0x1138e06e1a45c4f3 +after: $r17=000000000000000000, $r24=0x1138e06e1a45c4f3 +sltui $r13, $r26, -462 :: +before: $r13=0x62677116040aebff, $r26=0xeedd6ccd0e5e2771 +after: $r13=0x0000000000000001, $r26=0xeedd6ccd0e5e2771 +sltui $r24, $r28, 1890 :: +before: $r24=0xef9500b68a87984a, $r28=0xaf5922683f40599d +after: $r24=000000000000000000, $r28=0xaf5922683f40599d +sltui $r9, $r6, -1538 :: +before: $r9=0x9996aa21d2b51922, $r6=0xd5214fb275e738dc +after: $r9=0x0000000000000001, $r6=0xd5214fb275e738dc +sltui $r19, $r26, -215 :: +before: $r19=0x3eb2777655f0f1c5, $r26=0x98ed915860f0eb26 +after: $r19=0x0000000000000001, $r26=0x98ed915860f0eb26 +sltui $r8, $r19, -780 :: +before: $r8=0x5c44b5807c43724c, $r19=0x63a068026b529b03 +after: $r8=0x0000000000000001, $r19=0x63a068026b529b03 +sltui $r19, $r17, -1041 :: +before: $r19=0xf6926016cdbfacc1, $r17=0xec04a9bcc8d1192a +after: $r19=0x0000000000000001, $r17=0xec04a9bcc8d1192a +sltui $r26, $r14, 1653 :: +before: $r26=0x542f05c795aa07c2, $r14=0xb634bf537df4c4ce +after: $r26=000000000000000000, $r14=0xb634bf537df4c4ce +sltui $r8, $r5, 441 :: +before: $r8=0x371daf74e330ee8b, $r5=0xedb0321c888ae22e +after: $r8=000000000000000000, $r5=0xedb0321c888ae22e +sltui $r25, $r4, 678 :: +before: $r25=0xba813c7acc8f5621, $r4=0x8d5ce4750fe7603b +after: $r25=000000000000000000, $r4=0x8d5ce4750fe7603b +sltui $r17, $r15, 2019 :: +before: $r17=0x199b641cefe0a0e2, $r15=0x7ea0508a3fed3453 +after: $r17=000000000000000000, $r15=0x7ea0508a3fed3453 +nor $r14, $r28, $r9 :: +before: $r14=0xccf23cf02a48844d, $r28=0x2608ea0069c4e9dd, $r9=0x1c7a04255a2d13f8 +after: $r14=0xc18511da84120402, $r28=0x2608ea0069c4e9dd, $r9=0x1c7a04255a2d13f8 +nor $r6, $r30, $r4 :: +before: $r6=0xbfcc3de6da2483be, $r30=0xd24e9abca28d6cb5, $r4=0xbb01b508523673c6 +after: $r6=0x04b040430d408008, $r30=0xd24e9abca28d6cb5, $r4=0xbb01b508523673c6 +nor $r6, $r28, $r13 :: +before: $r6=0x28dacd828d5736d7, $r28=0xb365ff31474f736c, $r13=0x593621c0f82b445c +after: $r6=0x0488000e00908883, $r28=0xb365ff31474f736c, $r13=0x593621c0f82b445c +nor $r24, $r16, $r31 :: +before: $r24=0x5898010a4c6cf1bb, $r16=0xecac6e093ba6146a, $r31=0x050e6093f19b1194 +after: $r24=0x125191640440ea01, $r16=0xecac6e093ba6146a, $r31=0x050e6093f19b1194 +nor $r15, $r7, $r20 :: +before: $r15=0x2ddb1dea334fd92a, $r7=0x401d7a663be0b31a, $r20=0xb6c008973a85f779 +after: $r15=0x09228508c41a0884, $r7=0x401d7a663be0b31a, $r20=0xb6c008973a85f779 +nor $r18, $r31, $r29 :: +before: $r18=0x0c987982e1d91684, $r31=0x181f20f581ed38f4, $r29=0xefaa786e00a2e5b9 +after: $r18=0x004087007e100202, $r31=0x181f20f581ed38f4, $r29=0xefaa786e00a2e5b9 +nor $r19, $r31, $r13 :: +before: $r19=0x39e476d555cd20bc, $r31=0xfb8fab5d35576d50, $r13=0x71a92a8377c0f729 +after: $r19=0x0450542088280086, $r31=0xfb8fab5d35576d50, $r13=0x71a92a8377c0f729 +nor $r25, $r7, $r5 :: +before: $r25=0x7f36d0c6d173e8c8, $r7=0x181763a9f9350680, $r5=0x5ec5099605d7d418 +after: $r25=0xa128944002082967, $r7=0x181763a9f9350680, $r5=0x5ec5099605d7d418 +nor $r30, $r23, $r23 :: +before: $r30=0x688e1d04976ac8db, $r23=0xd37b6d6a1c510287, $r23=0x8670301ee2a715df +after: $r30=0x798fcfe11d58ea20, $r23=0x8670301ee2a715df, $r23=0x8670301ee2a715df +nor $r5, $r23, $r14 :: +before: $r5=0x71c4a211dd9262f4, $r23=0xcb8a4aebc2c6c4f2, $r14=0x084d79a5254447c9 +after: $r5=0x3430841018393804, $r23=0xcb8a4aebc2c6c4f2, $r14=0x084d79a5254447c9 +and $r8, $r14, $r31 :: +before: $r8=0xbddf22c4109e20b5, $r14=0xb2d25973efd1a8ff, $r31=0x28b78b59dfe641e9 +after: $r8=0x20920951cfc000e9, $r14=0xb2d25973efd1a8ff, $r31=0x28b78b59dfe641e9 +and $r19, $r23, $r17 :: +before: $r19=0xb25e185c549f6661, $r23=0xb6ccc215c2f17718, $r17=0xf20669c51aee8ffe +after: $r19=0xb204400502e00718, $r23=0xb6ccc215c2f17718, $r17=0xf20669c51aee8ffe +and $r30, $r27, $r23 :: +before: $r30=0xa7f4ad796393e12b, $r27=0xefbcf405df3e7aff, $r23=0x548a0141e9fe1700 +after: $r30=0x44880001c93e1200, $r27=0xefbcf405df3e7aff, $r23=0x548a0141e9fe1700 +and $r18, $r31, $r29 :: +before: $r18=0xa399c7f46c61d974, $r31=0xe0fe8cca1cbab773, $r29=0x49e680ddee7f666b +after: $r18=0x40e680c80c3a2663, $r31=0xe0fe8cca1cbab773, $r29=0x49e680ddee7f666b +and $r5, $r26, $r25 :: +before: $r5=0x1682ca17c11f90ac, $r26=0x4e9706cb2c885742, $r25=0x250ff6304dd87d57 +after: $r5=0x040706000c885542, $r26=0x4e9706cb2c885742, $r25=0x250ff6304dd87d57 +and $r28, $r14, $r8 :: +before: $r28=0xcacf15e6ffad256f, $r14=0x99527f4fa2aa8fb1, $r8=0xcff546a883b63cfb +after: $r28=0x8950460882a20cb1, $r14=0x99527f4fa2aa8fb1, $r8=0xcff546a883b63cfb +and $r28, $r9, $r28 :: +before: $r28=0xc60423b9cf70d112, $r9=0x2fb0db47f1d8f166, $r28=0x1e9cec9d13e85210 +after: $r28=0x0e90c80511c85000, $r9=0x2fb0db47f1d8f166, $r28=0x0e90c80511c85000 +and $r18, $r28, $r5 :: +before: $r18=0x5059c37ee38d2f25, $r28=0x74bf57d85d90af3a, $r5=0x35479df0ebec9209 +after: $r18=0x340715d049808208, $r28=0x74bf57d85d90af3a, $r5=0x35479df0ebec9209 +and $r23, $r25, $r12 :: +before: $r23=0x18742ef4c73416be, $r25=0x8b93e775860ef52b, $r12=0xa909915f60a546d2 +after: $r23=0x8901815500044402, $r25=0x8b93e775860ef52b, $r12=0xa909915f60a546d2 +and $r18, $r17, $r24 :: +before: $r18=0xadb2cc6aec909946, $r17=0x3068f8b21d583e4c, $r24=0xcf8aae1918f3a88e +after: $r18=0x0008a8101850280c, $r17=0x3068f8b21d583e4c, $r24=0xcf8aae1918f3a88e +or $r19, $r28, $r25 :: +before: $r19=0x46819825f87044c2, $r28=0x65cb2cc7e5f5a720, $r25=0x1fc0130146f13f76 +after: $r19=0x7fcb3fc7e7f5bf76, $r28=0x65cb2cc7e5f5a720, $r25=0x1fc0130146f13f76 +or $r8, $r25, $r4 :: +before: $r8=0x45083dd59c60e6fe, $r25=0x936ecfaeb4d51c95, $r4=0xdc37c27c69024f6e +after: $r8=0xdf7fcffefdd75fff, $r25=0x936ecfaeb4d51c95, $r4=0xdc37c27c69024f6e +or $r15, $r16, $r8 :: +before: $r15=0x516659e51cf19b26, $r16=0x7589da0802d59510, $r8=0x6b713c60390f3fbf +after: $r15=0x7ff9fe683bdfbfbf, $r16=0x7589da0802d59510, $r8=0x6b713c60390f3fbf +or $r9, $r15, $r6 :: +before: $r9=0x1646568625c40022, $r15=0xa68db9141a88850c, $r6=0x756d912fbefef973 +after: $r9=0xf7edb93fbefefd7f, $r15=0xa68db9141a88850c, $r6=0x756d912fbefef973 +or $r24, $r9, $r25 :: +before: $r24=0xda34c24d14fce443, $r9=0x6ad9bf24481630b0, $r25=0x02aefcdfa652395b +after: $r24=0x6affffffee5639fb, $r9=0x6ad9bf24481630b0, $r25=0x02aefcdfa652395b +or $r13, $r9, $r14 :: +before: $r13=0x900358ad1e848728, $r9=0xa0e361b5b891a62e, $r14=0xddfa0c1377ce01ac +after: $r13=0xfdfb6db7ffdfa7ae, $r9=0xa0e361b5b891a62e, $r14=0xddfa0c1377ce01ac +or $r23, $r16, $r15 :: +before: $r23=0x27a55515d39aded9, $r16=0xd0daf17f9cb0bf5a, $r15=0xf44c4372982c4d74 +after: $r23=0xf4def37f9cbcff7e, $r16=0xd0daf17f9cb0bf5a, $r15=0xf44c4372982c4d74 +or $r20, $r16, $r16 :: +before: $r20=0x7045887bb8325d6f, $r16=0xbac771cbb78dae04, $r16=0x23f4928023125a5c +after: $r20=0x23f4928023125a5c, $r16=0x23f4928023125a5c, $r16=0x23f4928023125a5c +or $r30, $r5, $r7 :: +before: $r30=0xcf609aa2057d1b98, $r5=0x379641544fd1cd48, $r7=0x5275ef34f265f01a +after: $r30=0x77f7ef74fff5fd5a, $r5=0x379641544fd1cd48, $r7=0x5275ef34f265f01a +or $r23, $r4, $r30 :: +before: $r23=0xc43fc1c750887406, $r4=0x44a3229c33d1cd65, $r30=0xceaa00084fc04912 +after: $r23=0xceab229c7fd1cd77, $r4=0x44a3229c33d1cd65, $r30=0xceaa00084fc04912 +xor $r6, $r19, $r31 :: +before: $r6=0x018522418b59bf8a, $r19=0x270a2ec823f26e39, $r31=0x99ef76e6d4495ae3 +after: $r6=0xbee5582ef7bb34da, $r19=0x270a2ec823f26e39, $r31=0x99ef76e6d4495ae3 +xor $r28, $r20, $r27 :: +before: $r28=0x57de83cac9dade15, $r20=0xd39fdecdfd4ccb08, $r27=0x00c97b854adacdb4 +after: $r28=0xd356a548b79606bc, $r20=0xd39fdecdfd4ccb08, $r27=0x00c97b854adacdb4 +xor $r4, $r29, $r5 :: +before: $r4=0x9f7356fff2445f77, $r29=0xc3c3a34d2c226b5a, $r5=0x51abdd266816b94f +after: $r4=0x92687e6b4434d215, $r29=0xc3c3a34d2c226b5a, $r5=0x51abdd266816b94f +xor $r14, $r6, $r28 :: +before: $r14=0xdd5ca0b5c6c45804, $r6=0xa0ba047990ec0798, $r28=0x089e6efd43651c28 +after: $r14=0xa8246a84d3891bb0, $r6=0xa0ba047990ec0798, $r28=0x089e6efd43651c28 +xor $r8, $r19, $r23 :: +before: $r8=0xc3e35cd44af166fa, $r19=0x6affcfe12104ccc7, $r23=0x4adbb3601a07a1d9 +after: $r8=0x20247c813b036d1e, $r19=0x6affcfe12104ccc7, $r23=0x4adbb3601a07a1d9 +xor $r16, $r5, $r18 :: +before: $r16=0x685cdc5ca969c8e1, $r5=0xd88d0e2a9900b8eb, $r18=0xdd4dfbba723cde28 +after: $r16=0x05c0f590eb3c66c3, $r5=0xd88d0e2a9900b8eb, $r18=0xdd4dfbba723cde28 +xor $r20, $r18, $r24 :: +before: $r20=0x2362838018fa39be, $r18=0xbbc8d438b24c037a, $r24=0xe020a8456a45b667 +after: $r20=0x5be87c7dd809b51d, $r18=0xbbc8d438b24c037a, $r24=0xe020a8456a45b667 +xor $r19, $r23, $r19 :: +before: $r19=0x637cae50fc0a1c95, $r23=0x514b81a7227dd07e, $r19=0x59a27a7f9c8481c3 +after: $r19=0x08e9fbd8bef951bd, $r23=0x514b81a7227dd07e, $r19=0x08e9fbd8bef951bd +xor $r20, $r16, $r18 :: +before: $r20=0xb728dd7a443bcc8f, $r16=0xe2de9bf67cdbdc0c, $r18=0x26687435fbe4dbf6 +after: $r20=0xc4b6efc3873f07fa, $r16=0xe2de9bf67cdbdc0c, $r18=0x26687435fbe4dbf6 +xor $r23, $r14, $r6 :: +before: $r23=0x744915919b52e27e, $r14=0x16863c1d3e1cded7, $r6=0x040ce8607349c380 +after: $r23=0x128ad47d4d551d57, $r14=0x16863c1d3e1cded7, $r6=0x040ce8607349c380 +orn $r24, $r9, $r15 :: +before: $r24=0x39320ce9aa25fb73, $r9=0xaaec06dc1b47cf43, $r15=0x5fa36a558c884a69 +after: $r24=0xaafc97fe7b77ffd7, $r9=0xaaec06dc1b47cf43, $r15=0x5fa36a558c884a69 +orn $r12, $r4, $r26 :: +before: $r12=0xa9c2abcbc14e3f3c, $r4=0x7c87d633528d97b0, $r26=0xe383c14e72ab8677 +after: $r12=0x7cfffeb3dfddffb8, $r4=0x7c87d633528d97b0, $r26=0xe383c14e72ab8677 +orn $r20, $r24, $r28 :: +before: $r20=0xb117d8b0280738a2, $r24=0x318fd949c3ba430f, $r28=0xc9edab5116dc1582 +after: $r20=0x379fddefebbbeb7f, $r24=0x318fd949c3ba430f, $r28=0xc9edab5116dc1582 +orn $r8, $r25, $r25 :: +before: $r8=0xb140441a36f8eded, $r25=0xa26782a5e34d7add, $r25=0x61bdd5b78d019958 +after: $r8=0xffffffffffffffff, $r25=0x61bdd5b78d019958, $r25=0x61bdd5b78d019958 +orn $r16, $r18, $r25 :: +before: $r16=0xcda0e2c1bce1eeec, $r18=0xa4486eefd2c444d9, $r25=0xbd007605c829cadc +after: $r16=0xe6ffeffff7d675fb, $r18=0xa4486eefd2c444d9, $r25=0xbd007605c829cadc +orn $r5, $r28, $r19 :: +before: $r5=0x8196fca50795a2aa, $r28=0xec7f689a0d676560, $r19=0xb4450418c4e1b333 +after: $r5=0xeffffbff3f7f6dec, $r28=0xec7f689a0d676560, $r19=0xb4450418c4e1b333 +orn $r15, $r14, $r8 :: +before: $r15=0xaf1e2a9fe35ba4ed, $r14=0xd2207f86d89b890a, $r8=0xfb31b9e37313a94d +after: $r15=0xd6ee7f9edcffdfba, $r14=0xd2207f86d89b890a, $r8=0xfb31b9e37313a94d +orn $r27, $r14, $r14 :: +before: $r27=0x1f24566bfa353160, $r14=0xc4e17319c4766bec, $r14=0x29a3bbaaf6b49218 +after: $r27=0xffffffffffffffff, $r14=0x29a3bbaaf6b49218, $r14=0x29a3bbaaf6b49218 +orn $r17, $r12, $r31 :: +before: $r17=0xf5195a72c175fed7, $r12=0x7aa8d4840359cbf6, $r31=0xa1a42af83c82215b +after: $r17=0x7efbd587c37ddff6, $r12=0x7aa8d4840359cbf6, $r31=0xa1a42af83c82215b +orn $r16, $r20, $r20 :: +before: $r16=0x76bb09b5b50705e2, $r20=0x613fdcbd8c1eba2a, $r20=0xfb1e04641f5da4ff +after: $r16=0xffffffffffffffff, $r20=0xfb1e04641f5da4ff, $r20=0xfb1e04641f5da4ff +andn $r19, $r31, $r17 :: +before: $r19=0xbcc81a9b2e349626, $r31=0x5a38a8ef9c7e30e4, $r17=0xcb490976d0652986 +after: $r19=0x1030a0890c1a1060, $r31=0x5a38a8ef9c7e30e4, $r17=0xcb490976d0652986 +andn $r10, $r4, $r10 :: +before: $r10=0x9acfa0cd6ea107fd, $r4=0x1d9b572e8f6bedb7, $r10=0x768fe778d2a543ea +after: $r10=0x091010060d4aac15, $r4=0x1d9b572e8f6bedb7, $r10=0x091010060d4aac15 +andn $r6, $r12, $r26 :: +before: $r6=0x949e36cff3b5decb, $r12=0x56723f7285834fc9, $r26=0xf6fa544d6cd57fa8 +after: $r6=0x00002b3281020041, $r12=0x56723f7285834fc9, $r26=0xf6fa544d6cd57fa8 +andn $r16, $r6, $r4 :: +before: $r16=0x44a39d85132d6513, $r6=0x3ca7f972b865b7ce, $r4=0xf18819e4740308bc +after: $r16=0x0c27e0128864b742, $r6=0x3ca7f972b865b7ce, $r4=0xf18819e4740308bc +andn $r19, $r26, $r15 :: +before: $r19=0x856d1e3162c8fa2d, $r26=0x0c1ef79456be3885, $r15=0x03c089064e60da1d +after: $r19=0x0c1e7690109e2080, $r26=0x0c1ef79456be3885, $r15=0x03c089064e60da1d +andn $r17, $r28, $r9 :: +before: $r17=0x512a518c554f4b0a, $r28=0x043454425b8b7755, $r9=0xdc5dca386b49bdd7 +after: $r17=0x0020144210824200, $r28=0x043454425b8b7755, $r9=0xdc5dca386b49bdd7 +andn $r16, $r16, $r14 :: +before: $r16=0xa9c14796fec54f89, $r16=0xe31928f90d2723a4, $r14=0xcf2deaf4af11410a +after: $r16=0x20100009002622a4, $r16=0x20100009002622a4, $r14=0xcf2deaf4af11410a +andn $r9, $r4, $r20 :: +before: $r9=0x51d79964a699ec8d, $r4=0xe82135537ca93e7f, $r20=0xcbadcb1dc4dd0ed0 +after: $r9=0x200034423820302f, $r4=0xe82135537ca93e7f, $r20=0xcbadcb1dc4dd0ed0 +andn $r18, $r25, $r25 :: +before: $r18=0xeb546ce75bcba3f5, $r25=0x953d86e2bd6b136d, $r25=0x4914dbeee506d8ad +after: $r18=000000000000000000, $r25=0x4914dbeee506d8ad, $r25=0x4914dbeee506d8ad +andn $r27, $r15, $r14 :: +before: $r27=0xc8b599a43b0b4683, $r15=0x0509638630676b88, $r14=0x3d278ed22a112a89 +after: $r27=0x0008610410664100, $r15=0x0509638630676b88, $r14=0x3d278ed22a112a89 +mul.w $r28, $r12, $r10 :: +before: $r28=0xf6fcce3e1c5b1598, $r12=0xef2747013f911fe8, $r10=0x14a216fd69537967 +after: $r28=0xffffffffabb07e58, $r12=0xef2747013f911fe8, $r10=0x14a216fd69537967 +mul.w $r13, $r18, $r24 :: +before: $r13=0x5e8a32c1e1e12aa4, $r18=0x30e007bb8dd185fa, $r24=0x1a74dd893af9fb5a +after: $r13=0x000000003e2f37e4, $r18=0x30e007bb8dd185fa, $r24=0x1a74dd893af9fb5a +mul.w $r10, $r20, $r4 :: +before: $r10=0xf06f4af61b0e0c24, $r20=0x1b3624a77f26275f, $r4=0x653052ae3a1347df +after: $r10=0xffffffffc934a4c1, $r20=0x1b3624a77f26275f, $r4=0x653052ae3a1347df +mul.w $r23, $r19, $r10 :: +before: $r23=0xccb5485ae4605cdd, $r19=0x67c67c647eaf9e6c, $r10=0xfb9b6c7b49ec10cf +after: $r23=0x000000004177d954, $r19=0x67c67c647eaf9e6c, $r10=0xfb9b6c7b49ec10cf +mul.w $r12, $r30, $r7 :: +before: $r12=0xc1f45aaf98ffcb39, $r30=0x906f0c08c0bae02e, $r7=0xdf6cf5c05b5f2d34 +after: $r12=0xffffffff8a6f9f58, $r30=0x906f0c08c0bae02e, $r7=0xdf6cf5c05b5f2d34 +mul.w $r27, $r12, $r12 :: +before: $r27=0x9545c6d9f812c0d9, $r12=0xacd016cb69e028b3, $r12=0x2b68e3a280d9c0b6 +after: $r27=0x00000000459d8164, $r12=0x2b68e3a280d9c0b6, $r12=0x2b68e3a280d9c0b6 +mul.w $r28, $r7, $r19 :: +before: $r28=0x4cf68a9590da3da5, $r7=0x70ed8b9b03a6325d, $r19=0x1125383d12dad118 +after: $r28=0x0000000073e4a5b8, $r7=0x70ed8b9b03a6325d, $r19=0x1125383d12dad118 +mul.w $r20, $r12, $r20 :: +before: $r20=0x10683d31408fb4c5, $r12=0x9ef4ea79672ce58d, $r20=0x960a13776923d3e4 +after: $r20=0x000000001c76a894, $r12=0x9ef4ea79672ce58d, $r20=0x000000001c76a894 +mul.w $r26, $r19, $r28 :: +before: $r26=0xbf8a20b69fa4357b, $r19=0xf3e9b53a654e3cbf, $r28=0x20afdeb5a4b4e1c9 +after: $r26=0x00000000601d90f7, $r19=0xf3e9b53a654e3cbf, $r28=0x20afdeb5a4b4e1c9 +mul.w $r13, $r26, $r25 :: +before: $r13=0x78f637d350c666bf, $r26=0xff742d96dc73e9e9, $r25=0x94a3289b55744707 +after: $r13=0xffffffff879f045f, $r26=0xff742d96dc73e9e9, $r25=0x94a3289b55744707 +mulh.w $r18, $r25, $r14 :: +before: $r18=0xa988161162710d96, $r25=0x37443c6f5d0625ea, $r14=0x94da379219de8576 +after: $r18=0x0000000009667587, $r25=0x37443c6f5d0625ea, $r14=0x94da379219de8576 +mulh.w $r13, $r16, $r18 :: +before: $r13=0x246298a54a25030a, $r16=0x33643ceed35cff64, $r18=0xc25702631b42c849 +after: $r13=0xfffffffffb3f29fd, $r16=0x33643ceed35cff64, $r18=0xc25702631b42c849 +mulh.w $r20, $r5, $r15 :: +before: $r20=0x3b606ea986dcf13e, $r5=0x269dcd16567786d2, $r15=0x96c0983df45d5c03 +after: $r20=0xfffffffffc11ee2e, $r5=0x269dcd16567786d2, $r15=0x96c0983df45d5c03 +mulh.w $r19, $r19, $r25 :: +before: $r19=0xab8fc1c922ba3e7a, $r19=0xdec5bddca513d198, $r25=0xf05e814d67d43f5a +after: $r19=0xffffffffdb1f973d, $r19=0xffffffffdb1f973d, $r25=0xf05e814d67d43f5a +mulh.w $r15, $r28, $r16 :: +before: $r15=0x82fcfa24449231ba, $r28=0xf37548fee13133f3, $r16=0x256188ef96bb3d23 +after: $r15=0x000000000cab1812, $r28=0xf37548fee13133f3, $r16=0x256188ef96bb3d23 +mulh.w $r24, $r9, $r27 :: +before: $r24=0x858ddeb68e948058, $r9=0x0ffb64d62e202462, $r27=0xe07a6dae07f46c11 +after: $r24=0x00000000016eeb19, $r9=0x0ffb64d62e202462, $r27=0xe07a6dae07f46c11 +mulh.w $r23, $r20, $r14 :: +before: $r23=0x7713930e419350ff, $r20=0xd5d72e6efb86e428, $r14=0x49f87e78ddcc8400 +after: $r23=0x000000000098fbfd, $r20=0xd5d72e6efb86e428, $r14=0x49f87e78ddcc8400 +mulh.w $r28, $r20, $r25 :: +before: $r28=0x552a9b7f3fa0c48a, $r20=0xd616afd20f193287, $r25=0xbcd2ae680b131cd2 +after: $r28=0x0000000000a735bd, $r20=0xd616afd20f193287, $r25=0xbcd2ae680b131cd2 +mulh.w $r16, $r19, $r12 :: +before: $r16=0x94b154fc890497c3, $r19=0xd8217f47e4257a7c, $r12=0xb47bb0e4cff83cbf +after: $r16=0x000000000539d140, $r19=0xd8217f47e4257a7c, $r12=0xb47bb0e4cff83cbf +mulh.w $r23, $r23, $r6 :: +before: $r23=0x0afb7fddb344318f, $r23=0xaafee418c4267e18, $r6=0x1763f686cd41d46e +after: $r23=0x000000000bdcf0fd, $r23=0x000000000bdcf0fd, $r6=0x1763f686cd41d46e +mulh.wu $r18, $r17, $r8 :: +before: $r18=0xa92fa2817b19786c, $r17=0xaf23e3d2092f080c, $r8=0x771c36ac19259f2a +after: $r18=0x0000000000e6f14b, $r17=0xaf23e3d2092f080c, $r8=0x771c36ac19259f2a +mulh.wu $r16, $r13, $r8 :: +before: $r16=0xf4a7b7abe5f3831a, $r13=0xe8beff7f8f4330cd, $r8=0x38cebbe3d1af354d +after: $r16=0x000000007557e799, $r13=0xe8beff7f8f4330cd, $r8=0x38cebbe3d1af354d +mulh.wu $r8, $r23, $r29 :: +before: $r8=0x6ca8c7d8ec316750, $r23=0xc3a59754c752c3a5, $r29=0x4b77e251de7f45f1 +after: $r8=0xffffffffad3cde2d, $r23=0xc3a59754c752c3a5, $r29=0x4b77e251de7f45f1 +mulh.wu $r20, $r25, $r30 :: +before: $r20=0x6faa5d1372250132, $r25=0x68734123142c820a, $r30=0x0f7b4bdf342e2017 +after: $r20=0x00000000041cacf0, $r25=0x68734123142c820a, $r30=0x0f7b4bdf342e2017 +mulh.wu $r31, $r18, $r19 :: +before: $r31=0x08cfa67422c1c5d5, $r18=0xb48ac9531206cef2, $r19=0x9f9f5d925c5cf738 +after: $r31=0x000000000680fe39, $r18=0xb48ac9531206cef2, $r19=0x9f9f5d925c5cf738 +mulh.wu $r25, $r7, $r27 :: +before: $r25=0x85aa17ff1b3699ba, $r7=0x9a7aeabb800edb53, $r27=0x4eb1ec754c7cdb59 +after: $r25=0x000000002642de08, $r7=0x9a7aeabb800edb53, $r27=0x4eb1ec754c7cdb59 +mulh.wu $r19, $r4, $r28 :: +before: $r19=0x821038d7fb43149c, $r4=0x44cd20261f5ae87e, $r28=0xf9d8916e8eb4ecb1 +after: $r19=0x00000000117a95de, $r4=0x44cd20261f5ae87e, $r28=0xf9d8916e8eb4ecb1 +mulh.wu $r30, $r23, $r28 :: +before: $r30=0xef34433557594fb3, $r23=0x2f9401c8064c8ca0, $r28=0x5de6287c2a56e507 +after: $r30=0x00000000010ab26c, $r23=0x2f9401c8064c8ca0, $r28=0x5de6287c2a56e507 +mulh.wu $r13, $r6, $r17 :: +before: $r13=0xd6b38c427ad5f669, $r6=0xbe04ea8987b20188, $r17=0x52cee1d144e3c134 +after: $r13=0x00000000248401a8, $r6=0xbe04ea8987b20188, $r17=0x52cee1d144e3c134 +mulh.wu $r26, $r19, $r17 :: +before: $r26=0x2ea15eee9429b8a0, $r19=0x43598be92000d9f7, $r17=0x6364cfeb707aba6c +after: $r26=0x000000000e0fb712, $r19=0x43598be92000d9f7, $r17=0x6364cfeb707aba6c +mul.d $r19, $r4, $r10 :: +before: $r19=0xf0235819cf1bab1f, $r4=0xdc7a0086353cfddf, $r10=0x6f18aec465b5af87 +after: $r19=0xb1beaa2f3e605199, $r4=0xdc7a0086353cfddf, $r10=0x6f18aec465b5af87 +mul.d $r19, $r31, $r20 :: +before: $r19=0x24d7526c5e4669e3, $r31=0xaab7dd46e5af2493, $r20=0xd5df6eea42205e25 +after: $r19=0x7ec27945fa1e433f, $r31=0xaab7dd46e5af2493, $r20=0xd5df6eea42205e25 +mul.d $r15, $r20, $r4 :: +before: $r15=0x3740ba48d64cc478, $r20=0xcfeffb7c35a98382, $r4=0xeab050fc9bdb3c52 +after: $r15=0x3ae548f8215497a4, $r20=0xcfeffb7c35a98382, $r4=0xeab050fc9bdb3c52 +mul.d $r29, $r7, $r25 :: +before: $r29=0xe8858552c0e8eac8, $r7=0xb65ed231c27efb70, $r25=0xbb753de59e4ca3d1 +after: $r29=0x57c0018869039670, $r7=0xb65ed231c27efb70, $r25=0xbb753de59e4ca3d1 +mul.d $r5, $r30, $r4 :: +before: $r5=0xc4f17df5c983317d, $r30=0xb2af9e86d443d8ce, $r4=0xf9e3c6d18372d0d3 +after: $r5=0xeff3c7ee09cf11ca, $r30=0xb2af9e86d443d8ce, $r4=0xf9e3c6d18372d0d3 +mul.d $r25, $r17, $r29 :: +before: $r25=0xa09d11d50056b350, $r17=0x6609b14ca65f9aff, $r29=0x692def5a14a3278c +after: $r25=0xbd4098e529429c74, $r17=0x6609b14ca65f9aff, $r29=0x692def5a14a3278c +mul.d $r13, $r15, $r26 :: +before: $r13=0xd528ed047af75775, $r15=0x896658fe826a0817, $r26=0xa456f53d5f2760b1 +after: $r13=0x630a2082b2d937e7, $r15=0x896658fe826a0817, $r26=0xa456f53d5f2760b1 +mul.d $r23, $r9, $r7 :: +before: $r23=0x5d33f63ce8637a69, $r9=0xad38922264c721ff, $r7=0xe0514fea4ee52aca +after: $r23=0x9d478a3f4bcfa936, $r9=0xad38922264c721ff, $r7=0xe0514fea4ee52aca +mul.d $r25, $r23, $r30 :: +before: $r25=0x5d74125f059662f3, $r23=0xa708100731e88710, $r30=0x739e4de71fec92e0 +after: $r25=0xeb30fae9bb3d4e00, $r23=0xa708100731e88710, $r30=0x739e4de71fec92e0 +mul.d $r26, $r18, $r30 :: +before: $r26=0x110a94ffa2e12f32, $r18=0x01b770d6c423d4f8, $r30=0x38bf04d66f91531a +after: $r26=0x5937a05ab2280930, $r18=0x01b770d6c423d4f8, $r30=0x38bf04d66f91531a +mulh.d $r5, $r15, $r12 :: +before: $r5=0xd72f46d42ca4db6b, $r15=0xe1771af0e69e49a6, $r12=0xd796f52fbd01a4bb +after: $r5=0x04d1eb3a7f530298, $r15=0xe1771af0e69e49a6, $r12=0xd796f52fbd01a4bb +mulh.d $r28, $r18, $r14 :: +before: $r28=0x904e699bcbe32b08, $r18=0x9b5b69b4d817779c, $r14=0xa02ca97cc4e37f13 +after: $r28=0x25ac2970a5b47a76, $r18=0x9b5b69b4d817779c, $r14=0xa02ca97cc4e37f13 +mulh.d $r6, $r12, $r7 :: +before: $r6=0xc75e1065b8dbcd34, $r12=0xec7d8ae6a65f2fd3, $r7=0xb7e32b52f40bc8ef +after: $r6=0x057ee36929066010, $r12=0xec7d8ae6a65f2fd3, $r7=0xb7e32b52f40bc8ef +mulh.d $r5, $r25, $r19 :: +before: $r5=0x7b2e04c0c2f95e4f, $r25=0x9a5037ff200e982a, $r19=0xf862c0c6425ff2bc +after: $r5=0x03064462e05709fc, $r25=0x9a5037ff200e982a, $r19=0xf862c0c6425ff2bc +mulh.d $r14, $r8, $r23 :: +before: $r14=0x5fd7ae31ad151daa, $r8=0x444243172f499ec0, $r23=0x9003c8aeabc39884 +after: $r14=0xe22404eefbd57910, $r8=0x444243172f499ec0, $r23=0x9003c8aeabc39884 +mulh.d $r7, $r23, $r13 :: +before: $r7=0x0bc21ca397041a2b, $r23=0xe886455c8737b2ca, $r13=0xd5ccec2f631a1d60 +after: $r7=0x03dea7b02a86f5c2, $r23=0xe886455c8737b2ca, $r13=0xd5ccec2f631a1d60 +mulh.d $r26, $r16, $r13 :: +before: $r26=0xd3894783f187ee9c, $r16=0xa7a6c4abeda9a22c, $r13=0x4375f7e49ed91384 +after: $r26=0xe8b7ef23e33e1269, $r16=0xa7a6c4abeda9a22c, $r13=0x4375f7e49ed91384 +mulh.d $r17, $r31, $r16 :: +before: $r17=0xa93bd0cf9137745e, $r31=0x3a1b2b922b7645f1, $r16=0x7e33f64c19972ae3 +after: $r17=0x1ca52ac301413b29, $r31=0x3a1b2b922b7645f1, $r16=0x7e33f64c19972ae3 +mulh.d $r20, $r19, $r8 :: +before: $r20=0xda9224c9ab488939, $r19=0xb7f5978bf509641d, $r8=0xf6fcd615333c30c0 +after: $r20=0x028941970b9c41ae, $r19=0xb7f5978bf509641d, $r8=0xf6fcd615333c30c0 +mulh.d $r12, $r17, $r20 :: +before: $r12=0xcdbd51e35d5c1df3, $r17=0x254bd8eaadc946fe, $r20=0x9de163435088598b +after: $r12=0xf1b4813d0885ff33, $r17=0x254bd8eaadc946fe, $r20=0x9de163435088598b +mulh.du $r25, $r28, $r29 :: +before: $r25=0xf7ef0dbf1bf7938a, $r28=0xd267d11ae422f604, $r29=0x089d6fd68226e13d +after: $r25=0x0714a41f660b233e, $r28=0xd267d11ae422f604, $r29=0x089d6fd68226e13d +mulh.du $r7, $r28, $r24 :: +before: $r7=0xe568cf4a6d6bc199, $r28=0x6efedad6fbe95f2a, $r24=0xdf55853ed22d024e +after: $r7=0x60d51505935d32a4, $r28=0x6efedad6fbe95f2a, $r24=0xdf55853ed22d024e +mulh.du $r25, $r8, $r9 :: +before: $r25=0x0bf7c0226b0c2072, $r8=0x794fd44a65c65ebb, $r9=0xa0391c3fa3cf1e5c +after: $r25=0x4becf4d7a7a9ffeb, $r8=0x794fd44a65c65ebb, $r9=0xa0391c3fa3cf1e5c +mulh.du $r30, $r16, $r7 :: +before: $r30=0x3df3f3b3ff17f61a, $r16=0xcadd1f7e7150ad7b, $r7=0xbdc63d3f762cf02d +after: $r30=0x966257cfb0059e70, $r16=0xcadd1f7e7150ad7b, $r7=0xbdc63d3f762cf02d +mulh.du $r6, $r10, $r19 :: +before: $r6=0x6601e05fc5f801cb, $r10=0xbc10a70104969251, $r19=0x2f50a00036fb7821 +after: $r6=0x22c24967f0edf696, $r10=0xbc10a70104969251, $r19=0x2f50a00036fb7821 +mulh.du $r17, $r9, $r5 :: +before: $r17=0xffabc0cbdc8aa7b0, $r9=0x5288bc60da558afb, $r5=0x2795644a58b2668f +after: $r17=0x0cc2fe9dc756ea23, $r9=0x5288bc60da558afb, $r5=0x2795644a58b2668f +mulh.du $r26, $r8, $r15 :: +before: $r26=0x68b64c997f561b59, $r8=0xe2ed2375e64b1bf3, $r15=0xe1033e583092ad96 +after: $r26=0xc7754c35a4f2f082, $r8=0xe2ed2375e64b1bf3, $r15=0xe1033e583092ad96 +mulh.du $r10, $r13, $r30 :: +before: $r10=0x6450ec488eb4753b, $r13=0x4287b82860366cf8, $r30=0x01c15ed3f051fe8c +after: $r10=0x0074c8aee8c0e7ce, $r13=0x4287b82860366cf8, $r30=0x01c15ed3f051fe8c +mulh.du $r24, $r13, $r15 :: +before: $r24=0x1169fa9dd6f8273d, $r13=0x6fd2cdb39e5d1fa3, $r15=0xff0526e206880684 +after: $r24=0x6f653afff4bd7810, $r13=0x6fd2cdb39e5d1fa3, $r15=0xff0526e206880684 +mulh.du $r8, $r9, $r10 :: +before: $r8=0xe9cb6416a1492fbf, $r9=0xaf89960e18913df0, $r10=0x76b4251409ff9830 +after: $r8=0x5164f154a1871400, $r9=0xaf89960e18913df0, $r10=0x76b4251409ff9830 +mulw.d.w $r6, $r31, $r7 :: +before: $r6=0x50ce021eb3b3f3a4, $r31=0xb859e7514e4c4d7c, $r7=0x372cb1e2b3200f36 +after: $r6=0xe87cdae260229c28, $r31=0xb859e7514e4c4d7c, $r7=0x372cb1e2b3200f36 +mulw.d.w $r31, $r7, $r28 :: +before: $r31=0x925642fa7e2de9ab, $r7=0x61404b6550238ceb, $r28=0x75ed502242ed0430 +after: $r31=0x14f35c8da06d1810, $r7=0x61404b6550238ceb, $r28=0x75ed502242ed0430 +mulw.d.w $r19, $r16, $r10 :: +before: $r19=0x0ef82de697f7239f, $r16=0xdf1c56dfe5c0e48d, $r10=0xbc7e740fe1b1dc25 +after: $r19=0x031b681eebc73461, $r16=0xdf1c56dfe5c0e48d, $r10=0xbc7e740fe1b1dc25 +mulw.d.w $r29, $r12, $r27 :: +before: $r29=0xc104a400fa0d1dbf, $r12=0x2aa34e8a5fad6c6f, $r27=0x7f8e4d23644b0d4d +after: $r29=0x257bcb22b6304063, $r12=0x2aa34e8a5fad6c6f, $r27=0x7f8e4d23644b0d4d +mulw.d.w $r25, $r16, $r25 :: +before: $r25=0x5b8ff9172c849fb9, $r16=0x843f90380af6f2af, $r25=0x12f7f8780cb8bfe0 +after: $r25=0x008b7d1678ecea20, $r16=0x843f90380af6f2af, $r25=0x008b7d1678ecea20 +mulw.d.w $r13, $r13, $r7 :: +before: $r13=0x6bba79a88056d891, $r13=0x6757a43d403285ab, $r7=0x2d2ea385888c2664 +after: $r13=0xe20b7699851798cc, $r13=0xe20b7699851798cc, $r7=0x2d2ea385888c2664 +mulw.d.w $r12, $r8, $r23 :: +before: $r12=0x5c96927dcf1fb14e, $r8=0x2b3767b9e9029d4b, $r23=0x252bbcc66b5d834b +after: $r12=0xf65bb1e7178075f9, $r8=0x2b3767b9e9029d4b, $r23=0x252bbcc66b5d834b +mulw.d.w $r6, $r13, $r10 :: +before: $r6=0x5fa5a8b36e8ec3e0, $r13=0xcbca4b4d518b9466, $r10=0xabdf2ec674f70c5b +after: $r6=0x2541f0d9edfc8842, $r13=0xcbca4b4d518b9466, $r10=0xabdf2ec674f70c5b +mulw.d.w $r16, $r15, $r23 :: +before: $r16=0x5b94eeb9c3c9fa01, $r15=0x5c4ebef486f83b43, $r23=0x73f3781c3a1e9216 +after: $r16=0xe485c9734afb4dc2, $r15=0x5c4ebef486f83b43, $r23=0x73f3781c3a1e9216 +mulw.d.w $r6, $r31, $r7 :: +before: $r6=0xbc263312a123caed, $r31=0xe9aa8545d3a99a97, $r7=0x71b5dbacf4f7f2b8 +after: $r6=0x01e91b5b89bada88, $r31=0xe9aa8545d3a99a97, $r7=0x71b5dbacf4f7f2b8 +mulw.d.wu $r14, $r17, $r30 :: +before: $r14=0x94452e0d7eb407b7, $r17=0x629b1902a484a77d, $r30=0x474359ca7f7165ed +after: $r14=0x51e6af2596105fb9, $r17=0x629b1902a484a77d, $r30=0x474359ca7f7165ed +mulw.d.wu $r26, $r7, $r5 :: +before: $r26=0xae9771f0d59319b3, $r7=0x1bcb563dea8f3a3f, $r5=0x759334cc2d543103 +after: $r26=0x29885124597fbdbd, $r7=0x1bcb563dea8f3a3f, $r5=0x759334cc2d543103 +mulw.d.wu $r25, $r28, $r27 :: +before: $r25=0x27ca0bf2d6cd2699, $r28=0x5a015da9b52ffc64, $r27=0x482a4fa5b5625914 +after: $r25=0x806088dd28c67bd0, $r28=0x5a015da9b52ffc64, $r27=0x482a4fa5b5625914 +mulw.d.wu $r8, $r4, $r16 :: +before: $r8=0x22f61239dad7bc92, $r4=0xe8c9964b31b0e199, $r16=0x99fdef421aa22322 +after: $r8=0x052b6faa1527e152, $r4=0xe8c9964b31b0e199, $r16=0x99fdef421aa22322 +mulw.d.wu $r29, $r17, $r15 :: +before: $r29=0xcc5eec6e4f2b5fdb, $r17=0x2d08ada074c2ac37, $r15=0x8967ce1cd4c2362e +after: $r29=0x6109cada18fc8be2, $r17=0x2d08ada074c2ac37, $r15=0x8967ce1cd4c2362e +mulw.d.wu $r27, $r23, $r16 :: +before: $r27=0x2d057e2ead214d6c, $r23=0x987e7a10a0f3ee5d, $r16=0xd515e2a2f06be633 +after: $r27=0x97288627099f0a87, $r23=0x987e7a10a0f3ee5d, $r16=0xd515e2a2f06be633 +mulw.d.wu $r15, $r19, $r12 :: +before: $r15=0xce24943d6fe20263, $r19=0xd6bbdcb20d76de15, $r12=0xcc277905bc41da62 +after: $r15=0x09e6c1c22ff3e60a, $r19=0xd6bbdcb20d76de15, $r12=0xcc277905bc41da62 +mulw.d.wu $r4, $r4, $r19 :: +before: $r4=0xe37942a26dc0e882, $r4=0x6a30fb04c3b5431f, $r19=0x4c937bed67cb6c73 +after: $r4=0x4f5971a615533aed, $r4=0x4f5971a615533aed, $r19=0x4c937bed67cb6c73 +mulw.d.wu $r7, $r12, $r9 :: +before: $r7=0xbdebe7a7b19b7dc0, $r12=0x3f6e790fb24d19f1, $r9=0x7a19c4fdd0d29f3e +after: $r7=0x9171573c297af75e, $r12=0x3f6e790fb24d19f1, $r9=0x7a19c4fdd0d29f3e +mulw.d.wu $r31, $r30, $r28 :: +before: $r31=0x690687056e169108, $r30=0xa8abab5bf1d42538, $r28=0x0636a31884ca1e99 +after: $r31=0x7d70517da256ce78, $r30=0xa8abab5bf1d42538, $r28=0x0636a31884ca1e99 +div.w $r13, $r28, $r23 :: +before: $r13=0x0000000016546290, $r28=0x00000000627aa138, $r23=0x000000000534168c +after: $r13=0x0000000000000012, $r28=0x00000000627aa138, $r23=0x000000000534168c +div.w $r28, $r19, $r9 :: +before: $r28=0xffffffffbe03930d, $r19=0x00000000223d0ec7, $r9=0xffffffff8404aa67 +after: $r28=000000000000000000, $r19=0x00000000223d0ec7, $r9=0xffffffff8404aa67 +div.w $r18, $r19, $r30 :: +before: $r18=0xffffffffac214649, $r19=0xffffffff8019c3b7, $r30=0xffffffff871cbf90 +after: $r18=0x0000000000000001, $r19=0xffffffff8019c3b7, $r30=0xffffffff871cbf90 +div.w $r24, $r25, $r7 :: +before: $r24=0xffffffffa144ed80, $r25=0x000000001c4370c7, $r7=0x000000004695aa29 +after: $r24=000000000000000000, $r25=0x000000001c4370c7, $r7=0x000000004695aa29 +div.w $r9, $r27, $r4 :: +before: $r9=0x000000003ae8b7c7, $r27=0xfffffffff3a6ebb2, $r4=0x00000000181d816a +after: $r9=000000000000000000, $r27=0xfffffffff3a6ebb2, $r4=0x00000000181d816a +div.w $r28, $r15, $r7 :: +before: $r28=0xffffffff956a7de4, $r15=0xffffffff9aab217b, $r7=0x000000003b061b78 +after: $r28=0xffffffffffffffff, $r15=0xffffffff9aab217b, $r7=0x000000003b061b78 +div.w $r25, $r24, $r12 :: +before: $r25=0x000000003c6167d4, $r24=0x000000002673145e, $r12=0x0000000001d5e391 +after: $r25=0x0000000000000014, $r24=0x000000002673145e, $r12=0x0000000001d5e391 +div.w $r23, $r15, $r4 :: +before: $r23=0x000000003e0820ee, $r15=0x0000000042793c51, $r4=0x00000000286cdb51 +after: $r23=0x0000000000000001, $r15=0x0000000042793c51, $r4=0x00000000286cdb51 +div.w $r28, $r16, $r30 :: +before: $r28=0xffffffffcf8fd242, $r16=0x000000002a76141e, $r30=0x0000000002429a52 +after: $r28=0x0000000000000012, $r16=0x000000002a76141e, $r30=0x0000000002429a52 +div.w $r29, $r8, $r18 :: +before: $r29=0x0000000074991388, $r8=0xffffffffd594ef43, $r18=0x000000006d3f9603 +after: $r29=000000000000000000, $r8=0xffffffffd594ef43, $r18=0x000000006d3f9603 +mod.w $r8, $r13, $r14 :: +before: $r8=0x000000005cc9e6db, $r13=0xfffffffff7327c6d, $r14=0x0000000023eef833 +after: $r8=0xfffffffff7327c6d, $r13=0xfffffffff7327c6d, $r14=0x0000000023eef833 +mod.w $r25, $r24, $r25 :: +before: $r25=0x00000000539195e4, $r24=0xffffffffd94f10c8, $r25=0x000000002c5786d9 +after: $r25=0xffffffffd94f10c8, $r24=0xffffffffd94f10c8, $r25=0xffffffffd94f10c8 +mod.w $r10, $r16, $r23 :: +before: $r10=0xffffffff9b15f725, $r16=0x00000000448a831d, $r23=0xffffffffd5d7d92b +after: $r10=0x000000001a625c48, $r16=0x00000000448a831d, $r23=0xffffffffd5d7d92b +mod.w $r6, $r5, $r29 :: +before: $r6=0x000000001794d969, $r5=0x000000002fba86b0, $r29=0x0000000040e6ab6b +after: $r6=0x000000002fba86b0, $r5=0x000000002fba86b0, $r29=0x0000000040e6ab6b +mod.w $r16, $r14, $r29 :: +before: $r16=0x000000006a503328, $r14=0xffffffffdf0b2ad2, $r29=0xffffffff90dc29c6 +after: $r16=0xffffffffdf0b2ad2, $r14=0xffffffffdf0b2ad2, $r29=0xffffffff90dc29c6 +mod.w $r30, $r14, $r18 :: +before: $r30=0xffffffffc7670acd, $r14=0x0000000053f3b34f, $r18=0xffffffff84b62159 +after: $r30=0x0000000053f3b34f, $r14=0x0000000053f3b34f, $r18=0xffffffff84b62159 +mod.w $r31, $r6, $r18 :: +before: $r31=0xffffffff98334c95, $r6=0xfffffffff241ffd8, $r18=0xffffffffa73314aa +after: $r31=0xfffffffff241ffd8, $r6=0xfffffffff241ffd8, $r18=0xffffffffa73314aa +mod.w $r12, $r8, $r4 :: +before: $r12=0xffffffffd9f19db4, $r8=0xffffffffc89f9796, $r4=0xffffffffaa8e2a3b +after: $r12=0xffffffffc89f9796, $r8=0xffffffffc89f9796, $r4=0xffffffffaa8e2a3b +mod.w $r23, $r12, $r4 :: +before: $r23=0xffffffff94e93220, $r12=0xfffffffffea1587a, $r4=0xffffffffb88b2b87 +after: $r23=0xfffffffffea1587a, $r12=0xfffffffffea1587a, $r4=0xffffffffb88b2b87 +mod.w $r13, $r9, $r18 :: +before: $r13=0x0000000000f718c0, $r9=0xffffffffe264a3a5, $r18=0x0000000002f29ef3 +after: $r13=0xffffffffffded923, $r9=0xffffffffe264a3a5, $r18=0x0000000002f29ef3 +div.wu $r24, $r5, $r16 :: +before: $r24=0x000000000ddf57c5, $r5=0x000000006b1a808c, $r16=0x000000000576fe70 +after: $r24=0x0000000000000013, $r5=0x000000006b1a808c, $r16=0x000000000576fe70 +div.wu $r26, $r7, $r9 :: +before: $r26=0x00000000665e82ff, $r7=0x00000000344d887f, $r9=0x000000007fd6d6d8 +after: $r26=000000000000000000, $r7=0x00000000344d887f, $r9=0x000000007fd6d6d8 +div.wu $r13, $r18, $r15 :: +before: $r13=0xffffffffe82e2cf8, $r18=0x000000007c66b628, $r15=0x000000000305c899 +after: $r13=0x0000000000000029, $r18=0x000000007c66b628, $r15=0x000000000305c899 +div.wu $r15, $r14, $r7 :: +before: $r15=0x0000000000b06b1f, $r14=0x0000000056016282, $r7=0x00000000095a8701 +after: $r15=0x0000000000000009, $r14=0x0000000056016282, $r7=0x00000000095a8701 +div.wu $r19, $r12, $r31 :: +before: $r19=0xffffffffb3a487d1, $r12=0xffffffffbe2fe16e, $r31=0xffffffff8dc0ff7f +after: $r19=0x0000000000000001, $r12=0xffffffffbe2fe16e, $r31=0xffffffff8dc0ff7f +div.wu $r6, $r10, $r20 :: +before: $r6=0x000000001bb491e9, $r10=0x00000000064e382e, $r20=0x000000005977f9f1 +after: $r6=000000000000000000, $r10=0x00000000064e382e, $r20=0x000000005977f9f1 +div.wu $r9, $r29, $r28 :: +before: $r9=0x00000000498c3349, $r29=0x0000000014cbb257, $r28=0xffffffff95165a4a +after: $r9=000000000000000000, $r29=0x0000000014cbb257, $r28=0xffffffff95165a4a +div.wu $r10, $r29, $r15 :: +before: $r10=0xffffffffbb3f9c5d, $r29=0x000000002755057d, $r15=0x0000000014039cc4 +after: $r10=0x0000000000000001, $r29=0x000000002755057d, $r15=0x0000000014039cc4 +div.wu $r24, $r31, $r7 :: +before: $r24=0xffffffffe5a9a3cd, $r31=0xffffffffa1f84b49, $r7=0xffffffffe45bd3b9 +after: $r24=000000000000000000, $r31=0xffffffffa1f84b49, $r7=0xffffffffe45bd3b9 +div.wu $r23, $r18, $r6 :: +before: $r23=0x0000000054e07e9f, $r18=0xffffffffaccbdd8c, $r6=0xfffffffff3729b57 +after: $r23=000000000000000000, $r18=0xffffffffaccbdd8c, $r6=0xfffffffff3729b57 +mod.wu $r5, $r20, $r18 :: +before: $r5=0xffffffffa1ce2e4e, $r20=0xffffffffdbeb0e2d, $r18=0x0000000070157135 +after: $r5=0x000000006bd59cf8, $r20=0xffffffffdbeb0e2d, $r18=0x0000000070157135 +mod.wu $r14, $r30, $r17 :: +before: $r14=0x0000000010e75d07, $r30=0x00000000039c3080, $r17=0x000000001658d87b +after: $r14=0x00000000039c3080, $r30=0x00000000039c3080, $r17=0x000000001658d87b +mod.wu $r28, $r7, $r4 :: +before: $r28=0x000000006df194db, $r7=0x0000000055fae7c9, $r4=0xffffffff9a87c1ef +after: $r28=0x0000000055fae7c9, $r7=0x0000000055fae7c9, $r4=0xffffffff9a87c1ef +mod.wu $r6, $r14, $r10 :: +before: $r6=0xffffffff8feb78cc, $r14=0xffffffffe5032316, $r10=0x0000000018ab441e +after: $r6=0x0000000006fdbe08, $r14=0xffffffffe5032316, $r10=0x0000000018ab441e +mod.wu $r13, $r15, $r9 :: +before: $r13=0xffffffffbb28952c, $r15=0x000000002d43f57d, $r9=0x000000002dfbf584 +after: $r13=0x000000002d43f57d, $r15=0x000000002d43f57d, $r9=0x000000002dfbf584 +mod.wu $r7, $r30, $r5 :: +before: $r7=0x0000000009bfb2cf, $r30=0x000000006595d7b3, $r5=0xfffffffffffd1025 +after: $r7=0x000000006595d7b3, $r30=0x000000006595d7b3, $r5=0xfffffffffffd1025 +mod.wu $r10, $r9, $r16 :: +before: $r10=0x00000000342671c6, $r9=0xfffffffff1ff8be3, $r16=0xfffffffffaea052b +after: $r10=0xfffffffff1ff8be3, $r9=0xfffffffff1ff8be3, $r16=0xfffffffffaea052b +mod.wu $r16, $r16, $r23 :: +before: $r16=0xffffffffc0356055, $r16=0x000000002ac1f414, $r23=0x000000004a75c890 +after: $r16=0x000000002ac1f414, $r16=0x000000002ac1f414, $r23=0x000000004a75c890 +mod.wu $r19, $r8, $r7 :: +before: $r19=0xfffffffff8ed6580, $r8=0x000000005fef460e, $r7=0x0000000068eedef2 +after: $r19=0x000000005fef460e, $r8=0x000000005fef460e, $r7=0x0000000068eedef2 +mod.wu $r29, $r25, $r25 :: +before: $r29=0xffffffff9ea76eb0, $r25=0xffffffff818904b9, $r25=0xffffffffe92f4f30 +after: $r29=000000000000000000, $r25=0xffffffffe92f4f30, $r25=0xffffffffe92f4f30 +div.d $r7, $r17, $r7 :: +before: $r7=0xc8f25fb958f2d668, $r17=0x074a14cbaa00fdea, $r7=0xcf95f3de82ceb015 +after: $r7=000000000000000000, $r17=0x074a14cbaa00fdea, $r7=000000000000000000 +div.d $r10, $r19, $r12 :: +before: $r10=0x9ead8a6f6ea63534, $r19=0xaf80d344d48e6cd5, $r12=0xe1f40f759cbfe0e7 +after: $r10=0x0000000000000002, $r19=0xaf80d344d48e6cd5, $r12=0xe1f40f759cbfe0e7 +div.d $r23, $r28, $r28 :: +before: $r23=0x35481a5285093e04, $r28=0xfd79e3c19b697fa8, $r28=0x6ffab603b9e1b7fb +after: $r23=0x0000000000000001, $r28=0x6ffab603b9e1b7fb, $r28=0x6ffab603b9e1b7fb +div.d $r30, $r25, $r4 :: +before: $r30=0x3eacf1d695a34b95, $r25=0xfbff957ab051d494, $r4=0x0670724b8930d53f +after: $r30=000000000000000000, $r25=0xfbff957ab051d494, $r4=0x0670724b8930d53f +div.d $r31, $r29, $r6 :: +before: $r31=0xce8d3df48871d655, $r29=0xf351f7f35927e83d, $r6=0x93a3085686f4101f +after: $r31=000000000000000000, $r29=0xf351f7f35927e83d, $r6=0x93a3085686f4101f +div.d $r17, $r23, $r8 :: +before: $r17=0xfc913f8b14dda5a5, $r23=0x001f938af81988de, $r8=0x9d021a9f06b46953 +after: $r17=000000000000000000, $r23=0x001f938af81988de, $r8=0x9d021a9f06b46953 +div.d $r7, $r29, $r15 :: +before: $r7=0x4593da2923f2ac5b, $r29=0x11fc5a958b182a55, $r15=0x2edafaf2857c6697 +after: $r7=000000000000000000, $r29=0x11fc5a958b182a55, $r15=0x2edafaf2857c6697 +div.d $r13, $r31, $r27 :: +before: $r13=0x97236145608dd8c3, $r31=0x1f0ee96afd23910b, $r27=0xe35e4d5efd2204d3 +after: $r13=0xffffffffffffffff, $r31=0x1f0ee96afd23910b, $r27=0xe35e4d5efd2204d3 +div.d $r13, $r26, $r14 :: +before: $r13=0x2c057bd222f216df, $r26=0x1e006853720971c3, $r14=0x81e35a993e6a15b5 +after: $r13=000000000000000000, $r26=0x1e006853720971c3, $r14=0x81e35a993e6a15b5 +div.d $r5, $r9, $r4 :: +before: $r5=0x93c0d85c66f2c5ab, $r9=0x774fbe894b2ed067, $r4=0x2c46387d55732742 +after: $r5=0x0000000000000002, $r9=0x774fbe894b2ed067, $r4=0x2c46387d55732742 +mod.d $r19, $r26, $r16 :: +before: $r19=0x63304d2181f4a4da, $r26=0x9ed948849ddee475, $r16=0x18a360d3ab980398 +after: $r19=0xe8c36affa0a6ef3d, $r26=0x9ed948849ddee475, $r16=0x18a360d3ab980398 +mod.d $r27, $r23, $r13 :: +before: $r27=0xf7156e74db7a8d92, $r23=0x324e7001287ce2a8, $r13=0x3cc7524686bed31c +after: $r27=0x324e7001287ce2a8, $r23=0x324e7001287ce2a8, $r13=0x3cc7524686bed31c +mod.d $r8, $r26, $r19 :: +before: $r8=0x7bda37a222135803, $r26=0x1daf8fd66ff987ed, $r19=0x334631279104fc3b +after: $r8=0x1daf8fd66ff987ed, $r26=0x1daf8fd66ff987ed, $r19=0x334631279104fc3b +mod.d $r25, $r15, $r7 :: +before: $r25=0xd1a0f45d5b463d53, $r15=0x9c4cd7bef3bf0712, $r7=0x420a5c702006f3cc +after: $r25=0xde57342f13c5fade, $r15=0x9c4cd7bef3bf0712, $r7=0x420a5c702006f3cc +mod.d $r25, $r18, $r7 :: +before: $r25=0x93487a905cb08a75, $r18=0x8c79cafa8bebf0a8, $r7=0x1478409d192c144b +after: $r25=0xf2d30e0c09c8561f, $r18=0x8c79cafa8bebf0a8, $r7=0x1478409d192c144b +mod.d $r8, $r27, $r27 :: +before: $r8=0x8756a1690dd7896d, $r27=0x35273279ea76319f, $r27=0xc5292f2331abc6dd +after: $r8=000000000000000000, $r27=0xc5292f2331abc6dd, $r27=0xc5292f2331abc6dd +mod.d $r15, $r10, $r24 :: +before: $r15=0xf8c476adbc930802, $r10=0x8b5832bcd0f6c87e, $r24=0x6cba54a72da38702 +after: $r15=0xf8128763fe9a4f80, $r10=0x8b5832bcd0f6c87e, $r24=0x6cba54a72da38702 +mod.d $r27, $r7, $r6 :: +before: $r27=0x2387015bddb2c076, $r7=0x231e30de7a72ad90, $r6=0x81f1285973e8dc11 +after: $r27=0x231e30de7a72ad90, $r7=0x231e30de7a72ad90, $r6=0x81f1285973e8dc11 +mod.d $r16, $r9, $r12 :: +before: $r16=0x3388d23c07feb1da, $r9=0xe8c01f744b310474, $r12=0xa29071d702959009 +after: $r16=0xe8c01f744b310474, $r9=0xe8c01f744b310474, $r12=0xa29071d702959009 +mod.d $r13, $r10, $r20 :: +before: $r13=0xbd45a261f8de4fe4, $r10=0x6fb0a8c9a2681a8e, $r20=0x2f1b7055cf2409ec +after: $r13=0x1179c81e042006b6, $r10=0x6fb0a8c9a2681a8e, $r20=0x2f1b7055cf2409ec +div.du $r17, $r10, $r24 :: +before: $r17=0x4d363fd48a626fda, $r10=0x7ccdeeaa6c24885f, $r24=0xfcc68e72f59750ae +after: $r17=000000000000000000, $r10=0x7ccdeeaa6c24885f, $r24=0xfcc68e72f59750ae +div.du $r20, $r20, $r10 :: +before: $r20=0x808fa5cb6a75fd6f, $r20=0x0f3f712970031005, $r10=0x1709a8adab2fa578 +after: $r20=000000000000000000, $r20=000000000000000000, $r10=0x1709a8adab2fa578 +div.du $r15, $r14, $r19 :: +before: $r15=0xcd3107423486c8fe, $r14=0xf6bc56277282cd14, $r19=0x0961ac833f00f3e3 +after: $r15=0x000000000000001a, $r14=0xf6bc56277282cd14, $r19=0x0961ac833f00f3e3 +div.du $r4, $r29, $r18 :: +before: $r4=0xa0bfc2fc5b35fa79, $r29=0x2b28c09aa5f12845, $r18=0xed44da2fdf5dce00 +after: $r4=000000000000000000, $r29=0x2b28c09aa5f12845, $r18=0xed44da2fdf5dce00 +div.du $r4, $r6, $r25 :: +before: $r4=0x1fc6e23fd0f09ed0, $r6=0xeaa71d9fb42223ca, $r25=0x045689545e60381c +after: $r4=0x0000000000000036, $r6=0xeaa71d9fb42223ca, $r25=0x045689545e60381c +div.du $r10, $r8, $r12 :: +before: $r10=0xa3710c512d4c006c, $r8=0xc011778733c50a6e, $r12=0xb44475ee048d8167 +after: $r10=0x0000000000000001, $r8=0xc011778733c50a6e, $r12=0xb44475ee048d8167 +div.du $r29, $r4, $r29 :: +before: $r29=0x46d27abff0da1972, $r4=0x17a4e863a182dcd0, $r29=0x59a7b82980ac6a6d +after: $r29=000000000000000000, $r4=0x17a4e863a182dcd0, $r29=000000000000000000 +div.du $r15, $r8, $r30 :: +before: $r15=0x68120919dbbd9b19, $r8=0x4c296c89a6f7a6df, $r30=0x9d9166c1cd0eecfa +after: $r15=000000000000000000, $r8=0x4c296c89a6f7a6df, $r30=0x9d9166c1cd0eecfa +div.du $r7, $r18, $r17 :: +before: $r7=0xd2389cb7af92be89, $r18=0x9a1f65b2c59cfda3, $r17=0xe316cf92f8f0574f +after: $r7=000000000000000000, $r18=0x9a1f65b2c59cfda3, $r17=0xe316cf92f8f0574f +div.du $r15, $r25, $r17 :: +before: $r15=0x49651d72d87da955, $r25=0xd22c499c27908743, $r17=0x08d824b01058ecb8 +after: $r15=0x0000000000000017, $r25=0xd22c499c27908743, $r17=0x08d824b01058ecb8 +mod.du $r26, $r8, $r23 :: +before: $r26=0xb0bd66f10c34fe23, $r8=0x5eb9b775d83b4893, $r23=0x08867d4b638f2622 +after: $r26=0x00f255389114a51d, $r8=0x5eb9b775d83b4893, $r23=0x08867d4b638f2622 +mod.du $r8, $r10, $r25 :: +before: $r8=0xe236349cd47eeb11, $r10=0x119102fd7b236a81, $r25=0x08fd72a09e4fb45f +after: $r8=0x0893905cdcd3b622, $r10=0x119102fd7b236a81, $r25=0x08fd72a09e4fb45f +mod.du $r25, $r4, $r5 :: +before: $r25=0x1b669725a0c3a970, $r4=0x0175359099c87b83, $r5=0xcad295c79f1d835a +after: $r25=0x0175359099c87b83, $r4=0x0175359099c87b83, $r5=0xcad295c79f1d835a +mod.du $r7, $r28, $r20 :: +before: $r7=0x7117e70798869df4, $r28=0xe35b93aa0c37fe97, $r20=0x741084dead7970d0 +after: $r7=0x6f4b0ecb5ebe8dc7, $r28=0xe35b93aa0c37fe97, $r20=0x741084dead7970d0 +mod.du $r30, $r24, $r9 :: +before: $r30=0xc4d432a8ce91f693, $r24=0x77c03aceb2ea6b45, $r9=0xb8cd7773fb72b7ca +after: $r30=0x77c03aceb2ea6b45, $r24=0x77c03aceb2ea6b45, $r9=0xb8cd7773fb72b7ca +mod.du $r23, $r9, $r28 :: +before: $r23=0x13f1f3e1891b6b73, $r9=0x9811699becce53a9, $r28=0xed15e264f0c39b88 +after: $r23=0x9811699becce53a9, $r9=0x9811699becce53a9, $r28=0xed15e264f0c39b88 +mod.du $r13, $r12, $r14 :: +before: $r13=0xb8b22bcb0cb970e8, $r12=0x16cdecd7c0091cd2, $r14=0x4fcab819ebadbdfd +after: $r13=0x16cdecd7c0091cd2, $r12=0x16cdecd7c0091cd2, $r14=0x4fcab819ebadbdfd +mod.du $r30, $r17, $r12 :: +before: $r30=0xbf96226d2de1240d, $r17=0x9fe4b2c7557d6b9a, $r12=0x3668e581a5de6efd +after: $r30=0x3312e7c409c08da0, $r17=0x9fe4b2c7557d6b9a, $r12=0x3668e581a5de6efd +mod.du $r14, $r4, $r6 :: +before: $r14=0x9bc8f8a69a7f55c2, $r4=0x530a9c5a21769bab, $r6=0x2805bef72d33cbd5 +after: $r14=0x02ff1e6bc70f0401, $r4=0x530a9c5a21769bab, $r6=0x2805bef72d33cbd5 +mod.du $r23, $r28, $r12 :: +before: $r23=0x82a854f86e642cba, $r28=0x0dd0fd63485d6c3d, $r12=0x56b21f15cb9d2bf2 +after: $r23=0x0dd0fd63485d6c3d, $r28=0x0dd0fd63485d6c3d, $r12=0x56b21f15cb9d2bf2 +alsl.w $r18, $r10, $r15, 2 :: +before: $r18=0xafb40df16156827b, $r10=0x9b0b86116a0d89cb, $r15=0x80086c066ea6842b +after: $r18=0x0000000016dcab57, $r10=0x9b0b86116a0d89cb, $r15=0x80086c066ea6842b +alsl.w $r24, $r5, $r4, 2 :: +before: $r24=0xb8b63b8205a919df, $r5=0x7319260322fa2d6d, $r4=0x1efce6644a51ebf9 +after: $r24=0xffffffffd63aa1ad, $r5=0x7319260322fa2d6d, $r4=0x1efce6644a51ebf9 +alsl.w $r24, $r5, $r27, 2 :: +before: $r24=0xb4f0fd355869e078, $r5=0x26abeea20b7d1ac1, $r27=0x4108f7f27e321c8f +after: $r24=0xffffffffac268793, $r5=0x26abeea20b7d1ac1, $r27=0x4108f7f27e321c8f +alsl.w $r24, $r29, $r10, 1 :: +before: $r24=0x4b948e9a0b82df22, $r29=0x11893c9dd43d0112, $r10=0x51a030165671a055 +after: $r24=0xfffffffffeeba279, $r29=0x11893c9dd43d0112, $r10=0x51a030165671a055 +alsl.w $r5, $r10, $r18, 1 :: +before: $r5=0xfc253ac9e2b55590, $r10=0x2682507563a85b07, $r18=0xa467083f66457d1d +after: $r5=0x000000002d96332b, $r10=0x2682507563a85b07, $r18=0xa467083f66457d1d +alsl.w $r20, $r13, $r10, 3 :: +before: $r20=0x76e8c346a721cdab, $r13=0x548f2762bfb1bc01, $r10=0xa6e0d27e62dcc594 +after: $r20=0x00000000606aa59c, $r13=0x548f2762bfb1bc01, $r10=0xa6e0d27e62dcc594 +alsl.w $r16, $r6, $r24, 3 :: +before: $r16=0x039f77b88fc3b663, $r6=0x281818bf4a36a7e5, $r24=0x86cd2a06ef475a61 +after: $r16=0x0000000040fc9989, $r6=0x281818bf4a36a7e5, $r24=0x86cd2a06ef475a61 +alsl.w $r14, $r18, $r9, 4 :: +before: $r14=0x08a58ea94346ff16, $r18=0x4ff191f91397adea, $r9=0x4cda359b03c97a53 +after: $r14=0x000000003d4458f3, $r18=0x4ff191f91397adea, $r9=0x4cda359b03c97a53 +alsl.w $r8, $r6, $r29, 1 :: +before: $r8=0xae0bfa182556c725, $r6=0xda179bc2f41d03d3, $r29=0x1d23e4da08af7978 +after: $r8=0xfffffffff0e9811e, $r6=0xda179bc2f41d03d3, $r29=0x1d23e4da08af7978 +alsl.w $r31, $r26, $r30, 1 :: +before: $r31=0xd6af9fcd7ffd8e75, $r26=0x3e88bb77d6665633, $r30=0x23a0414c69b804c1 +after: $r31=0x000000001684b127, $r26=0x3e88bb77d6665633, $r30=0x23a0414c69b804c1 +alsl.wu $r20, $r24, $r18, 2 :: +before: $r20=0xc714872ff3c39370, $r24=0xcaea31ddabb275f9, $r18=0xedbfc2cedca8eb7a +after: $r20=0x000000008b72c35e, $r24=0xcaea31ddabb275f9, $r18=0xedbfc2cedca8eb7a +alsl.wu $r13, $r26, $r15, 3 :: +before: $r13=0xe1a0ba1adcb75aa4, $r26=0x8adbed432acf321a, $r15=0xeae447eaa60bb142 +after: $r13=0x00000000fc854212, $r26=0x8adbed432acf321a, $r15=0xeae447eaa60bb142 +alsl.wu $r4, $r17, $r27, 3 :: +before: $r4=0xb153f9ecea23068c, $r17=0xd2066b089c9499a3, $r27=0x36ed3c96ac4751aa +after: $r4=0x0000000090ec1ec2, $r17=0xd2066b089c9499a3, $r27=0x36ed3c96ac4751aa +alsl.wu $r20, $r10, $r4, 4 :: +before: $r20=0x8fb2705357e98d66, $r10=0xd353329585fc71dd, $r4=0x739237ed6a677f00 +after: $r20=0x00000000ca2e9cd0, $r10=0xd353329585fc71dd, $r4=0x739237ed6a677f00 +alsl.wu $r31, $r12, $r23, 2 :: +before: $r31=0x6caac60acd9bc6f4, $r12=0xc87131b9171530df, $r23=0x39c8e321a6e131c0 +after: $r31=0x000000000335f53c, $r12=0xc87131b9171530df, $r23=0x39c8e321a6e131c0 +alsl.wu $r13, $r14, $r19, 2 :: +before: $r13=0xd2c7072036f54e45, $r14=0x35ea1627556f8f98, $r19=0x97054728433042d3 +after: $r13=0x0000000098ee8133, $r14=0x35ea1627556f8f98, $r19=0x97054728433042d3 +alsl.wu $r7, $r14, $r5, 1 :: +before: $r7=0x5a0f1fae80105d64, $r14=0xd300b74879e33a53, $r5=0x3a1e7389d0669d4c +after: $r7=0x00000000c42d11f2, $r14=0xd300b74879e33a53, $r5=0x3a1e7389d0669d4c +alsl.wu $r28, $r4, $r9, 1 :: +before: $r28=0xcd7fd8389b4f4062, $r4=0xad1830d644c205e7, $r9=0xced1c031d73f9087 +after: $r28=0x0000000060c39c55, $r4=0xad1830d644c205e7, $r9=0xced1c031d73f9087 +alsl.wu $r13, $r9, $r29, 4 :: +before: $r13=0x081601560f53b081, $r9=0xd3ee3c45f08cd218, $r29=0xa7d5a43a1df2aa1d +after: $r13=0x0000000026bfcb9d, $r9=0xd3ee3c45f08cd218, $r29=0xa7d5a43a1df2aa1d +alsl.wu $r30, $r29, $r31, 2 :: +before: $r30=0xf383bd5bfae7e46d, $r29=0x67862a0151c65567, $r31=0x9cdcbf604f46c48a +after: $r30=0x0000000096601a26, $r29=0x67862a0151c65567, $r31=0x9cdcbf604f46c48a +alsl.d $r18, $r28, $r16, 4 :: +before: $r18=0x53e533e973dfa49c, $r28=0x6665a9d32abaaf55, $r16=0xf70490874fb75e6e +after: $r18=0x5d5f2db9fb6253be, $r28=0x6665a9d32abaaf55, $r16=0xf70490874fb75e6e +alsl.d $r10, $r30, $r18, 2 :: +before: $r10=0xfb14c3e6acd722c3, $r30=0xcae19862ab088fcc, $r18=0x87c434d85259d923 +after: $r10=0xb34a9662fe7c1853, $r30=0xcae19862ab088fcc, $r18=0x87c434d85259d923 +alsl.d $r17, $r25, $r26, 1 :: +before: $r17=0x95e79a567c313ec7, $r25=0x83a0e706c2c4c534, $r26=0x2f49f1e9d5b91fc9 +after: $r17=0x368bbff75b42aa31, $r25=0x83a0e706c2c4c534, $r26=0x2f49f1e9d5b91fc9 +alsl.d $r7, $r24, $r24, 2 :: +before: $r7=0x35b966d0db9f681c, $r24=0xc0bc97593f1054fc, $r24=0x7e564928b0a53ac6 +after: $r7=0x77af6dcb733a25de, $r24=0x7e564928b0a53ac6, $r24=0x7e564928b0a53ac6 +alsl.d $r6, $r30, $r24, 3 :: +before: $r6=0x38ad1fb21e071421, $r30=0xb959c439b0436d6d, $r24=0x647c742c9ce02fc5 +after: $r6=0x2f4a95fa1efb9b2d, $r30=0xb959c439b0436d6d, $r24=0x647c742c9ce02fc5 +alsl.d $r18, $r28, $r10, 2 :: +before: $r18=0x1bde2962dc5bb68b, $r28=0x67c403d00c9389bd, $r10=0x8fc18921f225d05a +after: $r18=0x2ed198622473f74e, $r28=0x67c403d00c9389bd, $r10=0x8fc18921f225d05a +alsl.d $r8, $r27, $r15, 3 :: +before: $r8=0x5b8de9d8b393fa06, $r27=0x393ec1c28e89e9d8, $r15=0x1a59f9d852c3f8ba +after: $r8=0xe45007ecc713477a, $r27=0x393ec1c28e89e9d8, $r15=0x1a59f9d852c3f8ba +alsl.d $r27, $r24, $r6, 4 :: +before: $r27=0x72195c1ca51cc4db, $r24=0x4ee5b51e1e161ab2, $r6=0x08a10acb4b625fef +after: $r27=0xf6fc5cad2cc40b0f, $r24=0x4ee5b51e1e161ab2, $r6=0x08a10acb4b625fef +alsl.d $r29, $r4, $r18, 2 :: +before: $r29=0xf3ed9e39d83d3dec, $r4=0xa3816509b9a6c23d, $r18=0x6949e8e534450dd5 +after: $r29=0xf74f7d0c1ae016c9, $r4=0xa3816509b9a6c23d, $r18=0x6949e8e534450dd5 +alsl.d $r16, $r13, $r8, 1 :: +before: $r16=0x588f388f25a342df, $r13=0xde33a74109c7be30, $r8=0x8b02cf06997a065a +after: $r16=0x476a1d88ad0982ba, $r13=0xde33a74109c7be30, $r8=0x8b02cf06997a065a +lu12i.w $r9, 94146 :: +before: $r9=0xdf45bd002ccf48e1 +after: $r9=0x0000000016fc2000 +lu12i.w $r10, 129014 :: +before: $r10=0xa5138a37d09ada8a +after: $r10=0x000000001f7f6000 +lu12i.w $r18, -130138 :: +before: $r18=0x0efe46a52b8b3e5e +after: $r18=0xffffffffe03a6000 +lu12i.w $r7, -467080 :: +before: $r7=0x29084adf6d033a88 +after: $r7=0xffffffff8df78000 +lu12i.w $r10, 360675 :: +before: $r10=0xe9072e7fec2a5d1c +after: $r10=0x00000000580e3000 +lu12i.w $r28, 205272 :: +before: $r28=0x2f7d41c7bd959cd5 +after: $r28=0x00000000321d8000 +lu12i.w $r16, -266298 :: +before: $r16=0xcb48200d89b48566 +after: $r16=0xffffffffbefc6000 +lu12i.w $r12, -186346 :: +before: $r12=0xd605223c244f4a50 +after: $r12=0xffffffffd2816000 +lu12i.w $r15, 247864 :: +before: $r15=0x22c035c8c90016be +after: $r15=0x000000003c838000 +lu12i.w $r20, -511005 :: +before: $r20=0x6b2fd1aa0b603fec +after: $r20=0xffffffff833e3000 +lu32i.d $r8, -310956 :: +before: $r8=0xb331616751ed8877 +after: $r8=0xfffb415451ed8877 +lu32i.d $r17, 35590 :: +before: $r17=0x0e49bab8d80e1dd7 +after: $r17=0x00008b06d80e1dd7 +lu32i.d $r4, 500474 :: +before: $r4=0x842cdc9ac0a0adf6 +after: $r4=0x0007a2fac0a0adf6 +lu32i.d $r23, -447277 :: +before: $r23=0xc9ca69b8e5ab079e +after: $r23=0xfff92cd3e5ab079e +lu32i.d $r12, -503028 :: +before: $r12=0x27d83e1c77dec50a +after: $r12=0xfff8530c77dec50a +lu32i.d $r26, -355708 :: +before: $r26=0xc00dcc918a89f350 +after: $r26=0xfffa92848a89f350 +lu32i.d $r16, -231989 :: +before: $r16=0xd180188cdc073491 +after: $r16=0xfffc75cbdc073491 +lu32i.d $r26, 250642 :: +before: $r26=0x4efae034432bbb3b +after: $r26=0x0003d312432bbb3b +lu32i.d $r15, 237105 :: +before: $r15=0x7bf2141e673e336f +after: $r15=0x00039e31673e336f +lu32i.d $r4, -312071 :: +before: $r4=0x187c50bfc5eb8f32 +after: $r4=0xfffb3cf9c5eb8f32 +lu52i.d $r8, $r25, 1920 :: +before: $r8=0x1da74dfcb33d471a, $r25=0x453ae9f1200f4d41 +after: $r8=0x780ae9f1200f4d41, $r25=0x453ae9f1200f4d41 +lu52i.d $r14, $r25, -2008 :: +before: $r14=0x5e954055ebaec78f, $r25=0xb7637f9119e12e31 +after: $r14=0x82837f9119e12e31, $r25=0xb7637f9119e12e31 +lu52i.d $r26, $r24, -1803 :: +before: $r26=0xead69e40b96b23bf, $r24=0x779862b03d1ab575 +after: $r26=0x8f5862b03d1ab575, $r24=0x779862b03d1ab575 +lu52i.d $r5, $r25, -1406 :: +before: $r5=0x452236306da7c667, $r25=0x9f16a6e48cca3a7b +after: $r5=0xa826a6e48cca3a7b, $r25=0x9f16a6e48cca3a7b +lu52i.d $r26, $r23, -667 :: +before: $r26=0x5604b9744291e45a, $r23=0x70eecb3116b1795c +after: $r26=0xd65ecb3116b1795c, $r23=0x70eecb3116b1795c +lu52i.d $r14, $r27, -1221 :: +before: $r14=0x6d9a8cfe459c1c48, $r27=0x85452bdd40205e0d +after: $r14=0xb3b52bdd40205e0d, $r27=0x85452bdd40205e0d +lu52i.d $r25, $r8, 423 :: +before: $r25=0x1a8d72e42f68a33d, $r8=0x7089b6fe4c1f7a70 +after: $r25=0x1a79b6fe4c1f7a70, $r8=0x7089b6fe4c1f7a70 +lu52i.d $r30, $r10, -177 :: +before: $r30=0x7c4fe646acac7ac0, $r10=0xe7d222ba1fd5cae2 +after: $r30=0xf4f222ba1fd5cae2, $r10=0xe7d222ba1fd5cae2 +lu52i.d $r6, $r13, -1438 :: +before: $r6=0xdb3d6a615a9e492f, $r13=0xaa9303648ff489f2 +after: $r6=0xa62303648ff489f2, $r13=0xaa9303648ff489f2 +lu52i.d $r25, $r4, -634 :: +before: $r25=0x8b41b813d85b8ee8, $r4=0xe4d31961e42e713c +after: $r25=0xd8631961e42e713c, $r4=0xe4d31961e42e713c +addi.w $r6, $r27, 1727 :: +before: $r6=0x12845f036198fa6f, $r27=0xda77c63c764655da +after: $r6=0x0000000076465c99, $r27=0xda77c63c764655da +addi.w $r9, $r8, -381 :: +before: $r9=0x21a7e3cfa2649a4f, $r8=0xc64c73b3bd4c1dcb +after: $r9=0xffffffffbd4c1c4e, $r8=0xc64c73b3bd4c1dcb +addi.w $r16, $r6, -186 :: +before: $r16=0x6c47b02ef52a3502, $r6=0x24ca1a646dac5cc3 +after: $r16=0x000000006dac5c09, $r6=0x24ca1a646dac5cc3 +addi.w $r20, $r31, 1503 :: +before: $r20=0xb6144d8f9513c78e, $r31=0xc4b808764e894e6c +after: $r20=0x000000004e89544b, $r31=0xc4b808764e894e6c +addi.w $r19, $r17, -1918 :: +before: $r19=0xcf97c9215c961121, $r17=0x9b714c4cb899399b +after: $r19=0xffffffffb899321d, $r17=0x9b714c4cb899399b +addi.w $r14, $r8, -1781 :: +before: $r14=0xe1abf22f6c3c82ec, $r8=0x4110e9c1b5f59ef6 +after: $r14=0xffffffffb5f59801, $r8=0x4110e9c1b5f59ef6 +addi.w $r29, $r18, 2047 :: +before: $r29=0x4b64427195dda12d, $r18=0xadf5af70b7b3f37b +after: $r29=0xffffffffb7b3fb7a, $r18=0xadf5af70b7b3f37b +addi.w $r4, $r30, 244 :: +before: $r4=0xfc785d46f5bbdff4, $r30=0x1e061e9d51362d9c +after: $r4=0x0000000051362e90, $r30=0x1e061e9d51362d9c +addi.w $r7, $r23, -376 :: +before: $r7=0xe037576d82c12e8d, $r23=0xa77c8da72af708f1 +after: $r7=0x000000002af70779, $r23=0xa77c8da72af708f1 +addi.w $r23, $r17, 1924 :: +before: $r23=0x00a10df57c4103ef, $r17=0x26d2628746ad0a3e +after: $r23=0x0000000046ad11c2, $r17=0x26d2628746ad0a3e +addi.d $r14, $r14, 152 :: +before: $r14=0x61b497fb58a816d9, $r14=0x29eb218dd65d9d6c +after: $r14=0x29eb218dd65d9e04, $r14=0x29eb218dd65d9e04 +addi.d $r20, $r13, -640 :: +before: $r20=0xd80db8387a8cdd93, $r13=0x5e23e4b01f2bbd6d +after: $r20=0x5e23e4b01f2bbaed, $r13=0x5e23e4b01f2bbd6d +addi.d $r13, $r25, -743 :: +before: $r13=0x5dfea060c6e8f587, $r25=0x95f49b783954f9f9 +after: $r13=0x95f49b783954f712, $r25=0x95f49b783954f9f9 +addi.d $r4, $r30, 676 :: +before: $r4=0xd72f370f6ce7bc4c, $r30=0x148550b0f97ce601 +after: $r4=0x148550b0f97ce8a5, $r30=0x148550b0f97ce601 +addi.d $r26, $r8, 1630 :: +before: $r26=0xa4120a67f8d6df1a, $r8=0xa83f4bbcaf5bc52e +after: $r26=0xa83f4bbcaf5bcb8c, $r8=0xa83f4bbcaf5bc52e +addi.d $r20, $r29, -1971 :: +before: $r20=0xa8f9c82780ac16d5, $r29=0x7ab169a5751642bc +after: $r20=0x7ab169a575163b09, $r29=0x7ab169a5751642bc +addi.d $r8, $r8, 1160 :: +before: $r8=0x6f22bdb480c14540, $r8=0x94e1253c331b17f2 +after: $r8=0x94e1253c331b1c7a, $r8=0x94e1253c331b1c7a +addi.d $r15, $r27, 844 :: +before: $r15=0x0312473547bcfe03, $r27=0x7a786cbc8149d818 +after: $r15=0x7a786cbc8149db64, $r27=0x7a786cbc8149d818 +addi.d $r8, $r26, -1185 :: +before: $r8=0xee2b1be852671bc3, $r26=0x6a36d61dfee3a6fb +after: $r8=0x6a36d61dfee3a25a, $r26=0x6a36d61dfee3a6fb +addi.d $r17, $r27, -2046 :: +before: $r17=0x70e068b54ed72e20, $r27=0x922681ab8837027b +after: $r17=0x922681ab8836fa7d, $r27=0x922681ab8837027b +addu16i.d $r20, $r29, -14564 :: +before: $r20=0x8232770e3472bdc3, $r29=0x4d28c5567787c26e +after: $r20=0x4d28c5563ea3c26e, $r29=0x4d28c5567787c26e +addu16i.d $r29, $r4, -3511 :: +before: $r29=0x9076403ed2f0fdf4, $r4=0x471cafb4183a389f +after: $r29=0x471cafb40a83389f, $r4=0x471cafb4183a389f +addu16i.d $r26, $r15, 25897 :: +before: $r26=0x0dec118b1eb13234, $r15=0x06ff5ce56111b301 +after: $r26=0x06ff5ce5c63ab301, $r15=0x06ff5ce56111b301 +addu16i.d $r9, $r5, -21829 :: +before: $r9=0x73209239d98fb81a, $r5=0x1dc8f0ba4710eba3 +after: $r9=0x1dc8f0b9f1cbeba3, $r5=0x1dc8f0ba4710eba3 +addu16i.d $r28, $r25, -23832 :: +before: $r28=0xa39ba8429a9c13a6, $r25=0x4fffb32851c13ff2 +after: $r28=0x4fffb327f4a93ff2, $r25=0x4fffb32851c13ff2 +addu16i.d $r23, $r30, -32189 :: +before: $r23=0x08abd919f5ea43b1, $r30=0x40078826f7336f0e +after: $r23=0x4007882679766f0e, $r30=0x40078826f7336f0e +addu16i.d $r28, $r24, 16372 :: +before: $r28=0x695e543e25e7d3e4, $r24=0x30279db606efa8ec +after: $r28=0x30279db646e3a8ec, $r24=0x30279db606efa8ec +addu16i.d $r4, $r18, -28041 :: +before: $r4=0xa125cadb71209757, $r18=0xff287b5e7fb2a2ba +after: $r4=0xff287b5e1229a2ba, $r18=0xff287b5e7fb2a2ba +addu16i.d $r5, $r17, -11268 :: +before: $r5=0xd5d3e6da7c594ca9, $r17=0x2bc9be0ef252584c +after: $r5=0x2bc9be0ec64e584c, $r17=0x2bc9be0ef252584c +addu16i.d $r29, $r28, -15645 :: +before: $r29=0x0ee0391151007613, $r28=0xae616c39d87c4b6e +after: $r29=0xae616c399b5f4b6e, $r28=0xae616c39d87c4b6e +andi $r28, $r18, 1288 :: +before: $r28=0xd62f833fbbd483b3, $r18=0xa2f268cdcf18dd00 +after: $r28=0x0000000000000500, $r18=0xa2f268cdcf18dd00 +andi $r12, $r13, 153 :: +before: $r12=0xc40efc9a74a3a13b, $r13=0xfd609200795f877c +after: $r12=0x0000000000000018, $r13=0xfd609200795f877c +andi $r6, $r18, 3633 :: +before: $r6=0x79ee7ee7a7865b79, $r18=0x644bec92dca1ad7f +after: $r6=0x0000000000000c31, $r18=0x644bec92dca1ad7f +andi $r5, $r31, 3299 :: +before: $r5=0x2d64be0e5c2ec0f6, $r31=0x87253b6589f182c7 +after: $r5=0x00000000000000c3, $r31=0x87253b6589f182c7 +andi $r28, $r5, 3189 :: +before: $r28=0xf2e4ed85d98a1860, $r5=0x9f58e4edd98b60d1 +after: $r28=0x0000000000000051, $r5=0x9f58e4edd98b60d1 +andi $r18, $r29, 4031 :: +before: $r18=0x3c067920d48cf0d2, $r29=0x2bf35e68c503ecfe +after: $r18=0x0000000000000cbe, $r29=0x2bf35e68c503ecfe +andi $r20, $r24, 3252 :: +before: $r20=0xe1d95be05fd57a64, $r24=0xd33e771521b24bd3 +after: $r20=0x0000000000000890, $r24=0xd33e771521b24bd3 +andi $r6, $r23, 1665 :: +before: $r6=0x23341b2d86d02365, $r23=0x16de10f2b4a45064 +after: $r6=000000000000000000, $r23=0x16de10f2b4a45064 +andi $r27, $r14, 325 :: +before: $r27=0xd7db9d77aea4dcf5, $r14=0x142272b737435eb7 +after: $r27=0x0000000000000005, $r14=0x142272b737435eb7 +andi $r23, $r16, 1056 :: +before: $r23=0x57fee53581b09718, $r16=0x02ace25d9e2ddbaa +after: $r23=0x0000000000000020, $r16=0x02ace25d9e2ddbaa +ori $r26, $r13, 3251 :: +before: $r26=0x6d47cf7e5bb5c13e, $r13=0x93aed4996805ba3b +after: $r26=0x93aed4996805bebb, $r13=0x93aed4996805ba3b +ori $r10, $r25, 568 :: +before: $r10=0x42f0332098f938af, $r25=0xd7916fe8d569567b +after: $r10=0xd7916fe8d569567b, $r25=0xd7916fe8d569567b +ori $r12, $r17, 1798 :: +before: $r12=0xc507d4150a742b76, $r17=0x2b9a102a5b5b15f7 +after: $r12=0x2b9a102a5b5b17f7, $r17=0x2b9a102a5b5b15f7 +ori $r15, $r15, 1781 :: +before: $r15=0xa54ad5ecc0e72adb, $r15=0x37c18ad4ec6e678c +after: $r15=0x37c18ad4ec6e67fd, $r15=0x37c18ad4ec6e67fd +ori $r5, $r4, 682 :: +before: $r5=0x1f388b2a2b18004d, $r4=0xb5fa23fbb02eeedb +after: $r5=0xb5fa23fbb02eeefb, $r4=0xb5fa23fbb02eeedb +ori $r27, $r24, 1931 :: +before: $r27=0x73b086f8a8b4d7b5, $r24=0xd23e30ab1e45470a +after: $r27=0xd23e30ab1e45478b, $r24=0xd23e30ab1e45470a +ori $r28, $r6, 3593 :: +before: $r28=0x972967beac695928, $r6=0x2c701d0bc28816c5 +after: $r28=0x2c701d0bc2881ecd, $r6=0x2c701d0bc28816c5 +ori $r27, $r4, 3679 :: +before: $r27=0x54fecbbf0a06e5a6, $r4=0xf0b6d846464a3331 +after: $r27=0xf0b6d846464a3f7f, $r4=0xf0b6d846464a3331 +ori $r9, $r16, 905 :: +before: $r9=0x71f3cd001c729062, $r16=0xc5720758095e4592 +after: $r9=0xc5720758095e479b, $r16=0xc5720758095e4592 +ori $r26, $r7, 3473 :: +before: $r26=0xd7ce86800c3c0f4b, $r7=0xc4a58f787cdf5bb2 +after: $r26=0xc4a58f787cdf5fb3, $r7=0xc4a58f787cdf5bb2 +xori $r27, $r31, 2690 :: +before: $r27=0xe6d49c2dc629fbc7, $r31=0x91832665d1a898e2 +after: $r27=0x91832665d1a89260, $r31=0x91832665d1a898e2 +xori $r15, $r5, 697 :: +before: $r15=0xada49c0d48beffc5, $r5=0x0e3cf426f1be4766 +after: $r15=0x0e3cf426f1be45df, $r5=0x0e3cf426f1be4766 +xori $r9, $r20, 2268 :: +before: $r9=0x174a71d6d3757e3e, $r20=0x25ed4678037622be +after: $r9=0x25ed467803762a62, $r20=0x25ed4678037622be +xori $r31, $r15, 3817 :: +before: $r31=0x1fac1694b40fbf2e, $r15=0x4fe4fb2e0b660ca2 +after: $r31=0x4fe4fb2e0b66024b, $r15=0x4fe4fb2e0b660ca2 +xori $r17, $r14, 3929 :: +before: $r17=0x2dc443400df4e153, $r14=0x1db25e602ef8ece5 +after: $r17=0x1db25e602ef8e3bc, $r14=0x1db25e602ef8ece5 +xori $r4, $r28, 2735 :: +before: $r4=0x5fb5ad5a84e97835, $r28=0xc52da11293641639 +after: $r4=0xc52da11293641c96, $r28=0xc52da11293641639 +xori $r5, $r13, 1153 :: +before: $r5=0x5c5fc4ba45da005f, $r13=0xe46f853b7d602b84 +after: $r5=0xe46f853b7d602f05, $r13=0xe46f853b7d602b84 +xori $r30, $r26, 3867 :: +before: $r30=0x1419915b6f92678b, $r26=0xa984612f1266da94 +after: $r30=0xa984612f1266d58f, $r26=0xa984612f1266da94 +xori $r13, $r13, 3426 :: +before: $r13=0xc2b8fd036ba6314b, $r13=0x4cf49604f644713c +after: $r13=0x4cf49604f6447c5e, $r13=0x4cf49604f6447c5e +xori $r25, $r23, 2669 :: +before: $r25=0xde46e3673c9a75dc, $r23=0xfa1177a89f08c81e +after: $r25=0xfa1177a89f08c273, $r23=0xfa1177a89f08c81e +sll.w $r13, $r8, $r12 :: +before: $r13=0x26131fa72f4b76f1, $r8=0xf34f7108538078d0, $r12=0x10bbd12a8e087501 +after: $r13=0xffffffffa700f1a0, $r8=0xf34f7108538078d0, $r12=0x10bbd12a8e087501 +sll.w $r29, $r8, $r15 :: +before: $r29=0xb6f529da4017d0d9, $r8=0x49fbfb11ef643171, $r15=0x9d0425e747d11bde +after: $r29=0x0000000040000000, $r8=0x49fbfb11ef643171, $r15=0x9d0425e747d11bde +sll.w $r30, $r31, $r12 :: +before: $r30=0xcfc5236f5c070644, $r31=0xba8301a1087b3a96, $r12=0xff7589561824e1be +after: $r30=0xffffffff80000000, $r31=0xba8301a1087b3a96, $r12=0xff7589561824e1be +sll.w $r28, $r10, $r7 :: +before: $r28=0x37fa51674df87149, $r10=0x39212605c5d0cf7d, $r7=0x18a8e323326ce5aa +after: $r28=0x00000000433df400, $r10=0x39212605c5d0cf7d, $r7=0x18a8e323326ce5aa +sll.w $r8, $r9, $r14 :: +before: $r8=0x707a9e0ece8abe40, $r9=0x94b7b20a80c16c7b, $r14=0x6887c46efb4cc181 +after: $r8=0x000000000182d8f6, $r9=0x94b7b20a80c16c7b, $r14=0x6887c46efb4cc181 +sll.w $r8, $r4, $r24 :: +before: $r8=0xd718a01b03a53964, $r4=0x8ebd8bfeec304e2a, $r24=0x06b4a83a6838b5d1 +after: $r8=0xffffffff9c540000, $r4=0x8ebd8bfeec304e2a, $r24=0x06b4a83a6838b5d1 +sll.w $r23, $r31, $r27 :: +before: $r23=0xf50cab824a06d30e, $r31=0xa8ee12cbd8dec935, $r27=0x118002b3f0cecbab +after: $r23=0xfffffffff649a800, $r31=0xa8ee12cbd8dec935, $r27=0x118002b3f0cecbab +sll.w $r8, $r25, $r26 :: +before: $r8=0x8163368243faadee, $r25=0x3a04f47bf19a4cc8, $r26=0x6a58cd3a57b4eeb4 +after: $r8=0xffffffffcc800000, $r25=0x3a04f47bf19a4cc8, $r26=0x6a58cd3a57b4eeb4 +sll.w $r25, $r13, $r12 :: +before: $r25=0x3d6831e1afab1b1a, $r13=0x9ee672580cb39777, $r12=0x9084acd2bc7404ca +after: $r25=0xffffffffce5ddc00, $r13=0x9ee672580cb39777, $r12=0x9084acd2bc7404ca +sll.w $r20, $r5, $r29 :: +before: $r20=0x90f7ee3ff75817a6, $r5=0xe4ae07989d6148d7, $r29=0x3e208bfcf046fffd +after: $r20=0xffffffffe0000000, $r5=0xe4ae07989d6148d7, $r29=0x3e208bfcf046fffd +srl.w $r20, $r29, $r30 :: +before: $r20=0xff3f6b79b5e2b56d, $r29=0x1195aa09fa92d26b, $r30=0xa93a8fd11ad5ae99 +after: $r20=0x000000000000007d, $r29=0x1195aa09fa92d26b, $r30=0xa93a8fd11ad5ae99 +srl.w $r8, $r15, $r4 :: +before: $r8=0x5d2fb7cd04ecd00c, $r15=0x47bf914b6eca2852, $r4=0x1bc63138cc45a75c +after: $r8=0x0000000000000006, $r15=0x47bf914b6eca2852, $r4=0x1bc63138cc45a75c +srl.w $r20, $r12, $r18 :: +before: $r20=0x61fa22abda7c7b02, $r12=0x9341cf09aa2e106e, $r18=0x2dea831e9e121355 +after: $r20=0x0000000000000551, $r12=0x9341cf09aa2e106e, $r18=0x2dea831e9e121355 +srl.w $r30, $r20, $r26 :: +before: $r30=0x43e0249584da52db, $r20=0x482a209e436cda53, $r26=0xb323a7f463f80660 +after: $r30=0x00000000436cda53, $r20=0x482a209e436cda53, $r26=0xb323a7f463f80660 +srl.w $r31, $r16, $r28 :: +before: $r31=0x4b10d05d93bf7288, $r16=0x6d0330e88122d7c1, $r28=0xc531cf8c92d53d03 +after: $r31=0x0000000010245af8, $r16=0x6d0330e88122d7c1, $r28=0xc531cf8c92d53d03 +srl.w $r31, $r15, $r31 :: +before: $r31=0xd4654233c7648c3a, $r15=0x12e6fc2a04cbf809, $r31=0xcfe1c1b558a94808 +after: $r31=0x000000000004cbf8, $r15=0x12e6fc2a04cbf809, $r31=0x000000000004cbf8 +srl.w $r10, $r30, $r19 :: +before: $r10=0x602dee9c45a3b99b, $r30=0x3ce0a6ac2acf19fa, $r19=0xdb5fab4bc2f82e7a +after: $r10=0x000000000000000a, $r30=0x3ce0a6ac2acf19fa, $r19=0xdb5fab4bc2f82e7a +srl.w $r17, $r9, $r23 :: +before: $r17=0x45106f11d4a57641, $r9=0x05354795b675edac, $r23=0xc67578c28ed7b6c7 +after: $r17=0x00000000016cebdb, $r9=0x05354795b675edac, $r23=0xc67578c28ed7b6c7 +srl.w $r25, $r26, $r29 :: +before: $r25=0x1dc3b8477fba650c, $r26=0x0814377a71768e75, $r29=0x60276c0e316db833 +after: $r25=0x0000000000000e2e, $r26=0x0814377a71768e75, $r29=0x60276c0e316db833 +srl.w $r31, $r7, $r30 :: +before: $r31=0x360fc92a085c2e14, $r7=0x1b44ec96def89449, $r30=0x56d6c5d85a81ed1f +after: $r31=0x0000000000000001, $r7=0x1b44ec96def89449, $r30=0x56d6c5d85a81ed1f +sra.w $r10, $r17, $r19 :: +before: $r10=0x576f2bfc771641b8, $r17=0xfb1fb20b98a54405, $r19=0xb20e9dae5a212078 +after: $r10=0xffffffffffffff98, $r17=0xfb1fb20b98a54405, $r19=0xb20e9dae5a212078 +sra.w $r12, $r16, $r31 :: +before: $r12=0xbfdbb9a90ccc08a0, $r16=0xb5d3c7f3b1a800a6, $r31=0x57c3ff79f3b4198b +after: $r12=0xfffffffffff63500, $r16=0xb5d3c7f3b1a800a6, $r31=0x57c3ff79f3b4198b +sra.w $r18, $r16, $r5 :: +before: $r18=0xadcb6c153538b6b1, $r16=0x99e245813e90b5e9, $r5=0x7adff58363d5ebd2 +after: $r18=0x0000000000000fa4, $r16=0x99e245813e90b5e9, $r5=0x7adff58363d5ebd2 +sra.w $r17, $r28, $r25 :: +before: $r17=0x7faea6a29686caf9, $r28=0x801d40ea40b19bee, $r25=0x0f5174f678600d3f +after: $r17=000000000000000000, $r28=0x801d40ea40b19bee, $r25=0x0f5174f678600d3f +sra.w $r8, $r27, $r13 :: +before: $r8=0x86e5534832150e05, $r27=0x47bb53d1cdc3560f, $r13=0x917e2b49633a0f44 +after: $r8=0xfffffffffcdc3560, $r27=0x47bb53d1cdc3560f, $r13=0x917e2b49633a0f44 +sra.w $r26, $r18, $r20 :: +before: $r26=0xbfb83a0d762c171a, $r18=0xbf67ed78d934d37c, $r20=0x9f377995293fcc6b +after: $r26=0xfffffffffffb269a, $r18=0xbf67ed78d934d37c, $r20=0x9f377995293fcc6b +sra.w $r5, $r25, $r19 :: +before: $r5=0x266703af59334b0f, $r25=0x4ed92cdab9f641c9, $r19=0x5da1d0b8846d1a3d +after: $r5=0xfffffffffffffffd, $r25=0x4ed92cdab9f641c9, $r19=0x5da1d0b8846d1a3d +sra.w $r19, $r27, $r24 :: +before: $r19=0x72557561b3b40007, $r27=0xd5db278ea099b3b5, $r24=0x50b4a888b898610f +after: $r19=0xffffffffffff4133, $r27=0xd5db278ea099b3b5, $r24=0x50b4a888b898610f +sra.w $r16, $r10, $r4 :: +before: $r16=0xb349f888f1809ba3, $r10=0x23d60a1fc100d89e, $r4=0xc2846cc882dbc8e2 +after: $r16=0xfffffffff0403627, $r10=0x23d60a1fc100d89e, $r4=0xc2846cc882dbc8e2 +sra.w $r23, $r10, $r31 :: +before: $r23=0xd7bdeddd344bb5af, $r10=0xa015a07c13ff2234, $r31=0x7c0fe410ce063a85 +after: $r23=0x00000000009ff911, $r10=0xa015a07c13ff2234, $r31=0x7c0fe410ce063a85 +sll.d $r28, $r17, $r10 :: +before: $r28=0x167adf26efd66416, $r17=0xb861ba6e0aadf304, $r10=0xa19e21ba0f406c33 +after: $r28=0x9820000000000000, $r17=0xb861ba6e0aadf304, $r10=0xa19e21ba0f406c33 +sll.d $r18, $r29, $r13 :: +before: $r18=0x3e8ea4dc3a9d9b44, $r29=0x28ccf5dfa9cdc3b2, $r13=0x33ef837a5a476bdc +after: $r18=0xfa9cdc3b20000000, $r29=0x28ccf5dfa9cdc3b2, $r13=0x33ef837a5a476bdc +sll.d $r23, $r27, $r29 :: +before: $r23=0x23e29c76deed70ca, $r27=0x09e2265d8422e78d, $r29=0xe9cc62bfd8a7c913 +after: $r23=0x32ec21173c680000, $r27=0x09e2265d8422e78d, $r29=0xe9cc62bfd8a7c913 +sll.d $r16, $r17, $r17 :: +before: $r16=0xf5e858c7445fcedd, $r17=0x6735e4cf2fcb78fb, $r17=0x726dd10e13b62663 +after: $r16=0x9db1331800000000, $r17=0x726dd10e13b62663, $r17=0x726dd10e13b62663 +sll.d $r17, $r15, $r29 :: +before: $r17=0xfc1dbfc0551f8813, $r15=0xec45100b21a74025, $r29=0x186d3b737cbfd39a +after: $r17=0x2c869d0094000000, $r15=0xec45100b21a74025, $r29=0x186d3b737cbfd39a +sll.d $r19, $r15, $r9 :: +before: $r19=0xbb01afe39a1e17b6, $r15=0x3e66dd1100acc44a, $r9=0xa9c74257f6e39cdf +after: $r19=0x8056622500000000, $r15=0x3e66dd1100acc44a, $r9=0xa9c74257f6e39cdf +sll.d $r23, $r9, $r31 :: +before: $r23=0x945b101751c38d12, $r9=0x262d14baae546199, $r31=0x7ccdd8a7840948df +after: $r23=0x572a30cc80000000, $r9=0x262d14baae546199, $r31=0x7ccdd8a7840948df +sll.d $r5, $r31, $r28 :: +before: $r5=0xa88eaecc1405995b, $r31=0xd96ed500aff4596b, $r28=0x6994841a196c562e +after: $r5=0x165ac00000000000, $r31=0xd96ed500aff4596b, $r28=0x6994841a196c562e +sll.d $r27, $r10, $r25 :: +before: $r27=0x1e9540fa8237a849, $r10=0x9aad6101b2470a60, $r25=0x90c95628696f752f +after: $r27=0x8530000000000000, $r10=0x9aad6101b2470a60, $r25=0x90c95628696f752f +sll.d $r4, $r26, $r18 :: +before: $r4=0xb4dc3cdeab2e8454, $r26=0x0d27a92db3b2906c, $r18=0x2bc7647c40c0b375 +after: $r4=0x0d80000000000000, $r26=0x0d27a92db3b2906c, $r18=0x2bc7647c40c0b375 +srl.d $r6, $r27, $r13 :: +before: $r6=0x66ebeca9a7fad574, $r27=0xdc837ce646ea6b51, $r13=0xa57259e1758c564b +after: $r6=0x001b906f9cc8dd4d, $r27=0xdc837ce646ea6b51, $r13=0xa57259e1758c564b +srl.d $r6, $r20, $r5 :: +before: $r6=0x091794316e6c5e65, $r20=0x0dc7c47d39d64a16, $r5=0x35f029b9942e11c8 +after: $r6=0x000dc7c47d39d64a, $r20=0x0dc7c47d39d64a16, $r5=0x35f029b9942e11c8 +srl.d $r15, $r5, $r4 :: +before: $r15=0xbc963842b3ebc906, $r5=0x42ea773b0bd19807, $r4=0xd05cd2c4b01ea630 +after: $r15=0x00000000000042ea, $r5=0x42ea773b0bd19807, $r4=0xd05cd2c4b01ea630 +srl.d $r18, $r25, $r28 :: +before: $r18=0x30d908baaa31230e, $r25=0x779272ae228746a5, $r28=0xf7b665809a3f303b +after: $r18=0x000000000000000e, $r25=0x779272ae228746a5, $r28=0xf7b665809a3f303b +srl.d $r5, $r28, $r27 :: +before: $r5=0x01f1d414f1d0f1fe, $r28=0x647277d3759d74bf, $r27=0xa5c5fce39b4a1810 +after: $r5=0x0000647277d3759d, $r28=0x647277d3759d74bf, $r27=0xa5c5fce39b4a1810 +srl.d $r24, $r9, $r26 :: +before: $r24=0x5fa44419162fc2c8, $r9=0x9d2a589e6f6b3440, $r26=0x810a615115238d8d +after: $r24=0x0004e952c4f37b59, $r9=0x9d2a589e6f6b3440, $r26=0x810a615115238d8d +srl.d $r31, $r23, $r30 :: +before: $r31=0xfa1a7ad64758b758, $r23=0xe3d69d99e87b4297, $r30=0x87fd8dc0a78e86bb +after: $r31=0x000000000000001c, $r23=0xe3d69d99e87b4297, $r30=0x87fd8dc0a78e86bb +srl.d $r26, $r10, $r24 :: +before: $r26=0x540888639a787231, $r10=0x168791cefeb1660a, $r24=0xd02b158115db9cdf +after: $r26=0x000000002d0f239d, $r10=0x168791cefeb1660a, $r24=0xd02b158115db9cdf +srl.d $r23, $r15, $r12 :: +before: $r23=0xff3e950565409999, $r15=0xe15a01fa0e34ea3b, $r12=0x237aba34fe552f8e +after: $r23=0x0003856807e838d3, $r15=0xe15a01fa0e34ea3b, $r12=0x237aba34fe552f8e +srl.d $r8, $r16, $r4 :: +before: $r8=0x825bafd36cc0d32e, $r16=0x321677304d1b1406, $r4=0xca68c6c83dfa5837 +after: $r8=0x0000000000000064, $r16=0x321677304d1b1406, $r4=0xca68c6c83dfa5837 +sra.d $r23, $r19, $r16 :: +before: $r23=0x4cab63abd8f64774, $r19=0x2c007c3ac68d7c80, $r16=0xd8f4ac963a8b2c01 +after: $r23=0x16003e1d6346be40, $r19=0x2c007c3ac68d7c80, $r16=0xd8f4ac963a8b2c01 +sra.d $r18, $r30, $r25 :: +before: $r18=0x531de73fca30361a, $r30=0x2857ba730cd281ff, $r25=0xacab0fe400e4c113 +after: $r18=0x0000050af74e619a, $r30=0x2857ba730cd281ff, $r25=0xacab0fe400e4c113 +sra.d $r31, $r13, $r10 :: +before: $r31=0x3184416bc93a5e26, $r13=0xad5864bc4022de96, $r10=0xf7007bdbf1f728ab +after: $r31=0xfffffffffff5ab0c, $r13=0xad5864bc4022de96, $r10=0xf7007bdbf1f728ab +sra.d $r6, $r25, $r23 :: +before: $r6=0x9184d2df291f3402, $r25=0x7c0b117dcad80c03, $r23=0x35b29b0dde1a94bd +after: $r6=0x0000000000000003, $r25=0x7c0b117dcad80c03, $r23=0x35b29b0dde1a94bd +sra.d $r16, $r6, $r29 :: +before: $r16=0x2849e543d35dff5f, $r6=0x009f13f36a632a3f, $r29=0xf31f881e12072fe2 +after: $r16=0x000000000027c4fc, $r6=0x009f13f36a632a3f, $r29=0xf31f881e12072fe2 +sra.d $r7, $r29, $r10 :: +before: $r7=0x25c763f8366139dd, $r29=0xfd77fd6e69e371c6, $r10=0xcaa2ec6ad4f3b996 +after: $r7=0xfffffff5dff5b9a7, $r29=0xfd77fd6e69e371c6, $r10=0xcaa2ec6ad4f3b996 +sra.d $r24, $r25, $r26 :: +before: $r24=0x472602300b4f04c9, $r25=0x54ceea832a5677e9, $r26=0x5f63e9d9d6eb4af0 +after: $r24=0x00000000000054ce, $r25=0x54ceea832a5677e9, $r26=0x5f63e9d9d6eb4af0 +sra.d $r23, $r4, $r27 :: +before: $r23=0xe8b449325a0ed51e, $r4=0xd96928476f8441a5, $r27=0x7e1ae8fd9c849dce +after: $r23=0xffff65a4a11dbe11, $r4=0xd96928476f8441a5, $r27=0x7e1ae8fd9c849dce +sra.d $r15, $r9, $r12 :: +before: $r15=0x71601a1a2b155f51, $r9=0x0bcbb1d162563240, $r12=0x5a906ad2f4abb4c7 +after: $r15=0x00179763a2c4ac64, $r9=0x0bcbb1d162563240, $r12=0x5a906ad2f4abb4c7 +sra.d $r16, $r29, $r23 :: +before: $r16=0x1686886f27d397fb, $r29=0x851328b2655e5689, $r23=0x1634457590cd4033 +after: $r16=0xfffffffffffff0a2, $r29=0x851328b2655e5689, $r23=0x1634457590cd4033 +rotr.w $r8, $r5, $r18 :: +before: $r8=0xc4394aae4c13908b, $r5=0xa0c5728d1211b595, $r18=0x3d562746b3943f3b +after: $r8=0x000000004236b2a2, $r5=0xa0c5728d1211b595, $r18=0x3d562746b3943f3b +rotr.w $r19, $r18, $r10 :: +before: $r19=0x284b501639de116b, $r18=0x4248ad6cc0107902, $r10=0xb41907b756bf8004 +after: $r19=0x000000002c010790, $r18=0x4248ad6cc0107902, $r10=0xb41907b756bf8004 +rotr.w $r29, $r8, $r4 :: +before: $r29=0x2656b50c7d689f19, $r8=0x7b5d21fdce9bcb73, $r4=0x5b212fbe9e6b8522 +after: $r29=0xfffffffff3a6f2dc, $r8=0x7b5d21fdce9bcb73, $r4=0x5b212fbe9e6b8522 +rotr.w $r25, $r6, $r30 :: +before: $r25=0x4c79ed7a1695fc25, $r6=0x6bac1698a978f50f, $r30=0xf1d58570dfb10203 +after: $r25=0xfffffffff52f1ea1, $r6=0x6bac1698a978f50f, $r30=0xf1d58570dfb10203 +rotr.w $r14, $r18, $r6 :: +before: $r14=0xe894476b4ebbff23, $r18=0x1398b65ae1e91c98, $r6=0xebb6c3f5f689d2d8 +after: $r14=0xffffffffe91c98e1, $r18=0x1398b65ae1e91c98, $r6=0xebb6c3f5f689d2d8 +rotr.w $r19, $r29, $r26 :: +before: $r19=0x2595423cc93ecd7c, $r29=0x6c462c2d29d8f908, $r26=0x19142efd8e0b48b8 +after: $r19=0xffffffffd8f90829, $r29=0x6c462c2d29d8f908, $r26=0x19142efd8e0b48b8 +rotr.w $r23, $r10, $r25 :: +before: $r23=0x68b4d913b267a3a2, $r10=0x69afb673907e4506, $r25=0xbd09ff2ed890862d +after: $r23=0x00000000283483f2, $r10=0x69afb673907e4506, $r25=0xbd09ff2ed890862d +rotr.w $r9, $r14, $r27 :: +before: $r9=0x17a45b8cbdebd6ef, $r14=0x33effef864846356, $r27=0x3f52e437f2d5da62 +after: $r9=0xffffffff992118d5, $r14=0x33effef864846356, $r27=0x3f52e437f2d5da62 +rotr.w $r5, $r12, $r23 :: +before: $r5=0x2d191b1a9707cf26, $r12=0x86fa75433dac3d39, $r23=0x21136a02424e5da4 +after: $r5=0xffffffff93dac3d3, $r12=0x86fa75433dac3d39, $r23=0x21136a02424e5da4 +rotr.w $r29, $r18, $r27 :: +before: $r29=0x7d989f74f9944f8d, $r18=0x0050fe5829a153e6, $r27=0x926776f9140b06fc +after: $r29=0xffffffff9a153e62, $r18=0x0050fe5829a153e6, $r27=0x926776f9140b06fc +rotr.d $r29, $r19, $r13 :: +before: $r29=0x1e02c0c28ec3f9b1, $r19=0xf2e79e6ff240b188, $r13=0x60f500663eddf444 +after: $r29=0x8f2e79e6ff240b18, $r19=0xf2e79e6ff240b188, $r13=0x60f500663eddf444 +rotr.d $r30, $r4, $r14 :: +before: $r30=0x97f6be8229e2e822, $r4=0xf79aaeb2c03a2113, $r14=0xbbdb2cb642605ed7 +after: $r30=0x744227ef355d6580, $r4=0xf79aaeb2c03a2113, $r14=0xbbdb2cb642605ed7 +rotr.d $r6, $r19, $r7 :: +before: $r6=0x1611806010ce99d8, $r19=0xcb64270e0fc5b4c7, $r7=0x0eda6972c46af03c +after: $r6=0xb64270e0fc5b4c7c, $r19=0xcb64270e0fc5b4c7, $r7=0x0eda6972c46af03c +rotr.d $r4, $r15, $r30 :: +before: $r4=0xe63084e97bd0efb3, $r15=0x6e1aa322e38e9b66, $r30=0xa7df0f1d92106e2d +after: $r4=0x19171c74db3370d5, $r15=0x6e1aa322e38e9b66, $r30=0xa7df0f1d92106e2d +rotr.d $r16, $r27, $r10 :: +before: $r16=0x1ff92fbb0f10ff9a, $r27=0x015c2eb91c9ae124, $r10=0x8b4c97ee7f9bc2fa +after: $r16=0x570bae4726b84900, $r27=0x015c2eb91c9ae124, $r10=0x8b4c97ee7f9bc2fa +rotr.d $r28, $r7, $r25 :: +before: $r28=0xbd766a63bbead21c, $r7=0x0d97b509610db5e7, $r25=0x3151203010315af5 +after: $r28=0xbda84b086daf386c, $r7=0x0d97b509610db5e7, $r25=0x3151203010315af5 +rotr.d $r9, $r20, $r23 :: +before: $r9=0x8a2bb5eacea50d68, $r20=0x947ec1930151adb9, $r23=0xc2f39e045d278b7b +after: $r9=0x8fd832602a35b732, $r20=0x947ec1930151adb9, $r23=0xc2f39e045d278b7b +rotr.d $r25, $r13, $r23 :: +before: $r25=0xcaddb8ea7bd492c7, $r13=0x416a1b790dbf45cb, $r23=0x44c59965e1c6af25 +after: $r25=0xc86dfa2e5a0b50db, $r13=0x416a1b790dbf45cb, $r23=0x44c59965e1c6af25 +rotr.d $r14, $r7, $r31 :: +before: $r14=0x8ca18b58047c8b5a, $r7=0x93a6cdc3585b5446, $r31=0x70cd84ec07e33cef +after: $r14=0x9b86b0b6a88d274d, $r7=0x93a6cdc3585b5446, $r31=0x70cd84ec07e33cef +rotr.d $r14, $r9, $r4 :: +before: $r14=0x48bd5c133004f490, $r9=0xad095be0915fe20b, $r4=0xc1fff6ff603a47b3 +after: $r14=0x2b7c122bfc4175a1, $r9=0xad095be0915fe20b, $r4=0xc1fff6ff603a47b3 +slli.w $r18, $r8, 10 :: +before: $r18=0xe7f8823a2989c395, $r8=0xf0ccc85519ad1e0a +after: $r18=0xffffffffb4782800, $r8=0xf0ccc85519ad1e0a +slli.w $r27, $r17, 30 :: +before: $r27=0x2e66b550a3bb071d, $r17=0x20943aa3eaa4024e +after: $r27=0xffffffff80000000, $r17=0x20943aa3eaa4024e +slli.w $r27, $r23, 31 :: +before: $r27=0x70daa2bee8209243, $r23=0x2e9160afd2e28a64 +after: $r27=000000000000000000, $r23=0x2e9160afd2e28a64 +slli.w $r10, $r13, 12 :: +before: $r10=0x701c424632b5dc29, $r13=0x591054db6afe1725 +after: $r10=0xffffffffe1725000, $r13=0x591054db6afe1725 +slli.w $r7, $r15, 19 :: +before: $r7=0xdd1d7fe3ae579499, $r15=0x2e077f689088c0c7 +after: $r7=0x0000000006380000, $r15=0x2e077f689088c0c7 +slli.w $r6, $r8, 12 :: +before: $r6=0xff732113ddaab79b, $r8=0x9cacf8e6d9e37f97 +after: $r6=0x0000000037f97000, $r8=0x9cacf8e6d9e37f97 +slli.w $r5, $r19, 22 :: +before: $r5=0xcef75ddd2adc5853, $r19=0xcc24ed9167fd06ea +after: $r5=0xffffffffba800000, $r19=0xcc24ed9167fd06ea +slli.w $r17, $r8, 7 :: +before: $r17=0x3c8788fed3e8a049, $r8=0xccf9b2d2c2e80251 +after: $r17=0x0000000074012880, $r8=0xccf9b2d2c2e80251 +slli.w $r14, $r29, 10 :: +before: $r14=0x0e1b0b077db4f08e, $r29=0x76aea4b9ae43cdfb +after: $r14=0x000000000f37ec00, $r29=0x76aea4b9ae43cdfb +slli.w $r23, $r30, 26 :: +before: $r23=0x13d8514aeb0dc12b, $r30=0x9c8352804e7e8ccb +after: $r23=0x000000002c000000, $r30=0x9c8352804e7e8ccb +slli.d $r27, $r28, 5 :: +before: $r27=0x689a2c4141835926, $r28=0x1b6ff38e611d1e4d +after: $r27=0x6dfe71cc23a3c9a0, $r28=0x1b6ff38e611d1e4d +slli.d $r5, $r20, 1 :: +before: $r5=0xff3391c2323defa6, $r20=0xe99a134a0c1a2574 +after: $r5=0xd334269418344ae8, $r20=0xe99a134a0c1a2574 +slli.d $r27, $r7, 61 :: +before: $r27=0xc32d8fb319ba47e6, $r7=0xc6530e0e601d3631 +after: $r27=0x2000000000000000, $r7=0xc6530e0e601d3631 +slli.d $r5, $r26, 45 :: +before: $r5=0x979553ff112cdf52, $r26=0x931e420364fdcaca +after: $r5=0xb959400000000000, $r26=0x931e420364fdcaca +slli.d $r27, $r5, 60 :: +before: $r27=0xa7f70b048a4087b0, $r5=0xc1b829210c3cd5a9 +after: $r27=0x9000000000000000, $r5=0xc1b829210c3cd5a9 +slli.d $r23, $r10, 59 :: +before: $r23=0xcd547af78ac66ca7, $r10=0xa2c0802de6c82645 +after: $r23=0x2800000000000000, $r10=0xa2c0802de6c82645 +slli.d $r13, $r30, 56 :: +before: $r13=0x0410b8f25e1234ee, $r30=0xdbaacfe884cda24d +after: $r13=0x4d00000000000000, $r30=0xdbaacfe884cda24d +slli.d $r16, $r4, 20 :: +before: $r16=0x44a2ff35045ec37c, $r4=0xee2240010629a8ee +after: $r16=0x0010629a8ee00000, $r4=0xee2240010629a8ee +slli.d $r19, $r20, 25 :: +before: $r19=0x8617d88408d75cac, $r20=0xba15483820d66ae7 +after: $r19=0x7041acd5ce000000, $r20=0xba15483820d66ae7 +slli.d $r24, $r27, 13 :: +before: $r24=0x669e0e9b99d5b604, $r27=0xf5d1ffc374e53c7d +after: $r24=0x3ff86e9ca78fa000, $r27=0xf5d1ffc374e53c7d +srli.w $r20, $r16, 10 :: +before: $r20=0x7f5310ac5eaa9924, $r16=0x0ea8b69613d183ee +after: $r20=0x000000000004f460, $r16=0x0ea8b69613d183ee +srli.w $r13, $r15, 0 :: +before: $r13=0x5f4d9313f9224389, $r15=0xd544272206f4e814 +after: $r13=0x0000000006f4e814, $r15=0xd544272206f4e814 +srli.w $r17, $r18, 7 :: +before: $r17=0xd9b2c942f996cc8a, $r18=0x704cd1d89de5c2b4 +after: $r17=0x00000000013bcb85, $r18=0x704cd1d89de5c2b4 +srli.w $r27, $r28, 18 :: +before: $r27=0xa3eef8efc97e0d4f, $r28=0x8c449e6236daa7a2 +after: $r27=0x0000000000000db6, $r28=0x8c449e6236daa7a2 +srli.w $r9, $r10, 29 :: +before: $r9=0x6c044927152e5fc9, $r10=0x592a1607944e0109 +after: $r9=0x0000000000000004, $r10=0x592a1607944e0109 +srli.w $r8, $r24, 31 :: +before: $r8=0xcaa01b37d49db675, $r24=0x5e35848bbc958164 +after: $r8=0x0000000000000001, $r24=0x5e35848bbc958164 +srli.w $r6, $r16, 18 :: +before: $r6=0xe2fbe1accb343769, $r16=0x85f5e17c7d785222 +after: $r6=0x0000000000001f5e, $r16=0x85f5e17c7d785222 +srli.w $r18, $r25, 31 :: +before: $r18=0x4653c07e0627825f, $r25=0x44fffa524ffd0417 +after: $r18=000000000000000000, $r25=0x44fffa524ffd0417 +srli.w $r5, $r26, 22 :: +before: $r5=0x817ebd7154c8ed46, $r26=0xc7399a9899fc5958 +after: $r5=0x0000000000000267, $r26=0xc7399a9899fc5958 +srli.w $r27, $r4, 27 :: +before: $r27=0x3e4b17b34f2b08d0, $r4=0x5bedb97aefd697f4 +after: $r27=0x000000000000001d, $r4=0x5bedb97aefd697f4 +srli.d $r31, $r9, 51 :: +before: $r31=0x8fc21da189af52ed, $r9=0x235bf33e3e612a15 +after: $r31=0x000000000000046b, $r9=0x235bf33e3e612a15 +srli.d $r26, $r7, 36 :: +before: $r26=0xcd1eaac4df2531dd, $r7=0xe87216fce9c75788 +after: $r26=0x000000000e87216f, $r7=0xe87216fce9c75788 +srli.d $r6, $r31, 29 :: +before: $r6=0xc0282beeb7dc6618, $r31=0x8b58604d6be3e8e0 +after: $r6=0x000000045ac3026b, $r31=0x8b58604d6be3e8e0 +srli.d $r20, $r6, 18 :: +before: $r20=0x1546fdd9fc133e39, $r6=0x74067840bb05a992 +after: $r20=0x00001d019e102ec1, $r6=0x74067840bb05a992 +srli.d $r28, $r20, 28 :: +before: $r28=0xaa1f88b09e13e4c6, $r20=0x6e153faa5221e893 +after: $r28=0x00000006e153faa5, $r20=0x6e153faa5221e893 +srli.d $r26, $r4, 55 :: +before: $r26=0x2ba2151c80dbea7a, $r4=0x21246f3c7063edf9 +after: $r26=0x0000000000000042, $r4=0x21246f3c7063edf9 +srli.d $r28, $r29, 34 :: +before: $r28=0xcd72eff1b5aa0877, $r29=0x5d9488c1d61a1544 +after: $r28=0x0000000017652230, $r29=0x5d9488c1d61a1544 +srli.d $r13, $r7, 62 :: +before: $r13=0x5953b78fbd8109a9, $r7=0x862731652b653859 +after: $r13=0x0000000000000002, $r7=0x862731652b653859 +srli.d $r29, $r18, 25 :: +before: $r29=0xab821449d149a976, $r18=0xcb73553146cc4bdc +after: $r29=0x00000065b9aa98a3, $r18=0xcb73553146cc4bdc +srli.d $r28, $r7, 2 :: +before: $r28=0x31272fa88123357d, $r7=0x0e9359f7a9f92ec5 +after: $r28=0x03a4d67dea7e4bb1, $r7=0x0e9359f7a9f92ec5 +srai.w $r26, $r23, 2 :: +before: $r26=0xe73a55c2b7005c01, $r23=0xfcd659254f4b3fe7 +after: $r26=0x0000000013d2cff9, $r23=0xfcd659254f4b3fe7 +srai.w $r31, $r10, 0 :: +before: $r31=0x2e0c4330fae0890a, $r10=0xa76ca364a204c82b +after: $r31=0xffffffffa204c82b, $r10=0xa76ca364a204c82b +srai.w $r31, $r8, 0 :: +before: $r31=0x64790bb6e8674f68, $r8=0xce5594f964c4a026 +after: $r31=0x0000000064c4a026, $r8=0xce5594f964c4a026 +srai.w $r15, $r31, 27 :: +before: $r15=0xccfb53c708026acd, $r31=0xce185873627515b5 +after: $r15=0x000000000000000c, $r31=0xce185873627515b5 +srai.w $r16, $r28, 1 :: +before: $r16=0x994c4d22e90185a2, $r28=0x49995d51019e1050 +after: $r16=0x0000000000cf0828, $r28=0x49995d51019e1050 +srai.w $r13, $r16, 16 :: +before: $r13=0x0484408b57b3ab89, $r16=0x437401347e23c399 +after: $r13=0x0000000000007e23, $r16=0x437401347e23c399 +srai.w $r4, $r9, 7 :: +before: $r4=0x0d1d936105b7cca3, $r9=0xd49c3c65e292b942 +after: $r4=0xffffffffffc52572, $r9=0xd49c3c65e292b942 +srai.w $r24, $r15, 10 :: +before: $r24=0xaa9377005232ec93, $r15=0xde29d0172b40f03d +after: $r24=0x00000000000ad03c, $r15=0xde29d0172b40f03d +srai.w $r19, $r14, 24 :: +before: $r19=0xa49c65a4c2cde36d, $r14=0x782e0d4b8a7a28d0 +after: $r19=0xffffffffffffff8a, $r14=0x782e0d4b8a7a28d0 +srai.w $r24, $r27, 24 :: +before: $r24=0x404f816ff696bbc8, $r27=0x1b6900e15f252315 +after: $r24=0x000000000000005f, $r27=0x1b6900e15f252315 +srai.d $r24, $r4, 22 :: +before: $r24=0x96250384fede78c7, $r4=0x6c501d9ec5e9e731 +after: $r24=0x000001b140767b17, $r4=0x6c501d9ec5e9e731 +srai.d $r30, $r19, 17 :: +before: $r30=0xcfc52d7caaf7bf47, $r19=0x82499a30d50f8b83 +after: $r30=0xffffc124cd186a87, $r19=0x82499a30d50f8b83 +srai.d $r12, $r12, 5 :: +before: $r12=0x628a1a46bbe30c16, $r12=0xaba392c50d63ea53 +after: $r12=0xfd5d1c96286b1f52, $r12=0xfd5d1c96286b1f52 +srai.d $r24, $r9, 2 :: +before: $r24=0x021c1bb01f0253d8, $r9=0xb35e31d92548a2fe +after: $r24=0xecd78c76495228bf, $r9=0xb35e31d92548a2fe +srai.d $r28, $r7, 62 :: +before: $r28=0x2a5ac0a983332ec3, $r7=0x2297ae499a473c6d +after: $r28=000000000000000000, $r7=0x2297ae499a473c6d +srai.d $r8, $r17, 31 :: +before: $r8=0xa27cf36651750e09, $r17=0x1984e046b042d0cf +after: $r8=0x000000003309c08d, $r17=0x1984e046b042d0cf +srai.d $r25, $r16, 37 :: +before: $r25=0x7df3822fb20b8ded, $r16=0xb4e464563029fac8 +after: $r25=0xfffffffffda72322, $r16=0xb4e464563029fac8 +srai.d $r14, $r5, 57 :: +before: $r14=0xe8c1939c13a2e6ca, $r5=0x6a22077c63497a9a +after: $r14=0x0000000000000035, $r5=0x6a22077c63497a9a +srai.d $r25, $r15, 10 :: +before: $r25=0xf2df68e25cccf72e, $r15=0xe0af648201f919fc +after: $r25=0xfff82bd920807e46, $r15=0xe0af648201f919fc +srai.d $r6, $r15, 49 :: +before: $r6=0xa24591b35142aa9c, $r15=0x12b20ac67de77b8d +after: $r6=0x0000000000000959, $r15=0x12b20ac67de77b8d +rotri.w $r18, $r6, 20 :: +before: $r18=0xf0c65b137926ba00, $r6=0x95e0f5f057a212c5 +after: $r18=0x00000000212c557a, $r6=0x95e0f5f057a212c5 +rotri.w $r9, $r16, 27 :: +before: $r9=0xe36356471d2a7e18, $r16=0xb8af3071021bd869 +after: $r9=0x00000000437b0d20, $r16=0xb8af3071021bd869 +rotri.w $r5, $r31, 1 :: +before: $r5=0x5992fc9cfce2ebe9, $r31=0x6c427c821603d01a +after: $r5=0x000000000b01e80d, $r31=0x6c427c821603d01a +rotri.w $r27, $r13, 23 :: +before: $r27=0x0239c57dca2ab060, $r13=0xed54e28825b25471 +after: $r27=0x0000000064a8e24b, $r13=0xed54e28825b25471 +rotri.w $r18, $r18, 7 :: +before: $r18=0xb84df2305a710936, $r18=0x8aae5248c6d4973c +after: $r18=0x00000000798da92e, $r18=0x00000000798da92e +rotri.w $r4, $r27, 29 :: +before: $r4=0x730e1701570ac9fc, $r27=0xd55b9d54232536e7 +after: $r4=0x000000001929b739, $r27=0xd55b9d54232536e7 +rotri.w $r19, $r18, 0 :: +before: $r19=0x36dbceffa501d8dc, $r18=0x8415238fa1dd314f +after: $r19=0xffffffffa1dd314f, $r18=0x8415238fa1dd314f +rotri.w $r13, $r24, 21 :: +before: $r13=0x00c1ac428ddf5193, $r24=0x3b588028fcfbb0a8 +after: $r13=0xffffffffdd8547e7, $r24=0x3b588028fcfbb0a8 +rotri.w $r14, $r25, 29 :: +before: $r14=0x733414543ca8145e, $r25=0xded24831de35be08 +after: $r14=0xfffffffff1adf046, $r25=0xded24831de35be08 +rotri.w $r27, $r5, 8 :: +before: $r27=0x60afaebb36d22ba0, $r5=0x0fd31a16f03582b5 +after: $r27=0xffffffffb5f03582, $r5=0x0fd31a16f03582b5 +rotri.d $r20, $r7, 53 :: +before: $r20=0xe112a6d47c0444c1, $r7=0xbd9bbb91bdc381c5 +after: $r20=0xdddc8dee1c0e2dec, $r7=0xbd9bbb91bdc381c5 +rotri.d $r27, $r16, 62 :: +before: $r27=0xf254a827c1ef7351, $r16=0x3de084650f757ceb +after: $r27=0xf78211943dd5f3ac, $r16=0x3de084650f757ceb +rotri.d $r30, $r17, 10 :: +before: $r30=0x31c36a8c83999eb2, $r17=0x107098a9863e85d5 +after: $r30=0x75441c262a618fa1, $r17=0x107098a9863e85d5 +rotri.d $r29, $r8, 46 :: +before: $r29=0xf2e7a25c121af3c3, $r8=0xb177c110c3dd3225 +after: $r29=0x04430f74c896c5df, $r8=0xb177c110c3dd3225 +rotri.d $r4, $r26, 45 :: +before: $r4=0xdd94ff60f2e1abff, $r26=0xb76d3e4a0af02e4d +after: $r4=0xf2505781726dbb69, $r26=0xb76d3e4a0af02e4d +rotri.d $r10, $r9, 42 :: +before: $r10=0x6064d48d901beca7, $r9=0xea20b33360134ab2 +after: $r10=0xccd804d2acba882c, $r9=0xea20b33360134ab2 +rotri.d $r4, $r26, 27 :: +before: $r4=0x27f1e63c8f7f71cf, $r26=0xf4c5c8a69f37a1bd +after: $r4=0xe6f437be98b914d3, $r26=0xf4c5c8a69f37a1bd +rotri.d $r9, $r16, 20 :: +before: $r9=0x7d4cb07a3ab72944, $r16=0xd5ee210421c6080e +after: $r9=0x6080ed5ee210421c, $r16=0xd5ee210421c6080e +rotri.d $r24, $r26, 4 :: +before: $r24=0x1ce66a79f3e45e6f, $r26=0x6e1767144ffa6e2d +after: $r24=0xd6e1767144ffa6e2, $r26=0x6e1767144ffa6e2d +rotri.d $r4, $r18, 46 :: +before: $r4=0x04173f8102b03399, $r18=0xde7066568917d899 +after: $r4=0x995a245f626779c1, $r18=0xde7066568917d899 +ext.w.h $r17, $r14 :: +before: $r17=0x58af862c6fc4208d, $r14=0x6235b0cfe4eed6ed +after: $r17=0xffffffffffffd6ed, $r14=0x6235b0cfe4eed6ed +ext.w.h $r31, $r20 :: +before: $r31=0x425af3dcd83fa9fd, $r20=0x6e59403101a538f1 +after: $r31=0x00000000000038f1, $r20=0x6e59403101a538f1 +ext.w.h $r18, $r27 :: +before: $r18=0xcb140226bf788367, $r27=0x58a5430ee4e1616e +after: $r18=0x000000000000616e, $r27=0x58a5430ee4e1616e +ext.w.h $r15, $r10 :: +before: $r15=0xd3debaf05f7d909f, $r10=0x6f7083340247fb12 +after: $r15=0xfffffffffffffb12, $r10=0x6f7083340247fb12 +ext.w.h $r12, $r15 :: +before: $r12=0x5dc6f7191af80bcf, $r15=0xb1f1c8f4b11c03d9 +after: $r12=0x00000000000003d9, $r15=0xb1f1c8f4b11c03d9 +ext.w.h $r7, $r15 :: +before: $r7=0x5ffe304a5c9dc9d2, $r15=0x102fb4fa33193103 +after: $r7=0x0000000000003103, $r15=0x102fb4fa33193103 +ext.w.h $r16, $r16 :: +before: $r16=0x533616e37505799f, $r16=0xf988c7255086f4f5 +after: $r16=0xfffffffffffff4f5, $r16=0xfffffffffffff4f5 +ext.w.h $r13, $r25 :: +before: $r13=0x805a406557ed3fac, $r25=0xdc6ce0f2993b219b +after: $r13=0x000000000000219b, $r25=0xdc6ce0f2993b219b +ext.w.h $r19, $r20 :: +before: $r19=0xcc49c20125c4755d, $r20=0xde7b765222a9703a +after: $r19=0x000000000000703a, $r20=0xde7b765222a9703a +ext.w.h $r18, $r7 :: +before: $r18=0xe0dd9155cbe168c6, $r7=0xc1063421eae07663 +after: $r18=0x0000000000007663, $r7=0xc1063421eae07663 +ext.w.b $r16, $r23 :: +before: $r16=0x21666e814555aa02, $r23=0x926b8d68b5c40592 +after: $r16=0xffffffffffffff92, $r23=0x926b8d68b5c40592 +ext.w.b $r8, $r20 :: +before: $r8=0xf68ae0a0ac497ded, $r20=0x0bfb5d489716d0c5 +after: $r8=0xffffffffffffffc5, $r20=0x0bfb5d489716d0c5 +ext.w.b $r24, $r15 :: +before: $r24=0xbc84e54c82fd6e51, $r15=0x7d814b11e5eb07f6 +after: $r24=0xfffffffffffffff6, $r15=0x7d814b11e5eb07f6 +ext.w.b $r31, $r17 :: +before: $r31=0x14e575a8dda1f0d3, $r17=0x6a111e663a52244c +after: $r31=0x000000000000004c, $r17=0x6a111e663a52244c +ext.w.b $r16, $r8 :: +before: $r16=0x911acc218fcf640b, $r8=0xac1405ad05b23e43 +after: $r16=0x0000000000000043, $r8=0xac1405ad05b23e43 +ext.w.b $r28, $r8 :: +before: $r28=0x77fb13eaa8995607, $r8=0x05c97a81f12da7d3 +after: $r28=0xffffffffffffffd3, $r8=0x05c97a81f12da7d3 +ext.w.b $r9, $r23 :: +before: $r9=0xb88cfdb98683e15e, $r23=0x74893b34973e16cb +after: $r9=0xffffffffffffffcb, $r23=0x74893b34973e16cb +ext.w.b $r31, $r4 :: +before: $r31=0xc7168cb4f7d079e4, $r4=0xf4fc215bc2c5273e +after: $r31=0x000000000000003e, $r4=0xf4fc215bc2c5273e +ext.w.b $r4, $r18 :: +before: $r4=0x0e2e5dca4727b373, $r18=0xa1b97136f32e452b +after: $r4=0x000000000000002b, $r18=0xa1b97136f32e452b +ext.w.b $r8, $r29 :: +before: $r8=0x625eb5236f483daa, $r29=0x3ceca34ee347e7c8 +after: $r8=0xffffffffffffffc8, $r29=0x3ceca34ee347e7c8 +clo.w $r4, $r13 :: +before: $r4=0x0bcca747f77aca28, $r13=0x8df71972c1a17096 +after: $r4=0x0000000000000002, $r13=0x8df71972c1a17096 +clo.w $r27, $r5 :: +before: $r27=0x98a9e6d99d8e84cb, $r5=0xdc59d3c8fc1540e4 +after: $r27=0x0000000000000006, $r5=0xdc59d3c8fc1540e4 +clo.w $r9, $r14 :: +before: $r9=0xe8e78b162c95ed66, $r14=0xdfad6854bbf442e6 +after: $r9=0x0000000000000001, $r14=0xdfad6854bbf442e6 +clo.w $r13, $r26 :: +before: $r13=0xa3db2cf80f9112cd, $r26=0x7676463dd6f13f80 +after: $r13=0x0000000000000002, $r26=0x7676463dd6f13f80 +clo.w $r7, $r16 :: +before: $r7=0xb5213ab31b574031, $r16=0x478c19ebdeaa74c0 +after: $r7=0x0000000000000002, $r16=0x478c19ebdeaa74c0 +clo.w $r13, $r12 :: +before: $r13=0xd68d9661284fb9d7, $r12=0x702bf24fddd8bfe0 +after: $r13=0x0000000000000002, $r12=0x702bf24fddd8bfe0 +clo.w $r18, $r20 :: +before: $r18=0x510cd4002aff4c6c, $r20=0x4fc898e8b83669ee +after: $r18=0x0000000000000001, $r20=0x4fc898e8b83669ee +clo.w $r5, $r9 :: +before: $r5=0x53c0de96f709208d, $r9=0x0e56d87b898438b5 +after: $r5=0x0000000000000001, $r9=0x0e56d87b898438b5 +clo.w $r20, $r5 :: +before: $r20=0x96187854fcce4fd1, $r5=0xf1248bea6ed8be30 +after: $r20=000000000000000000, $r5=0xf1248bea6ed8be30 +clo.w $r20, $r31 :: +before: $r20=0xb1abb4795d411683, $r31=0x01025f914a9225e6 +after: $r20=000000000000000000, $r31=0x01025f914a9225e6 +clz.w $r19, $r8 :: +before: $r19=0x374348642747a8dc, $r8=0xd8ec1d547d95ada5 +after: $r19=0x0000000000000001, $r8=0xd8ec1d547d95ada5 +clz.w $r26, $r4 :: +before: $r26=0x741ab4d14b9ee1f8, $r4=0x99e2ef840817cfff +after: $r26=0x0000000000000004, $r4=0x99e2ef840817cfff +clz.w $r17, $r4 :: +before: $r17=0x45c9ce7217f501b3, $r4=0xa387a194cd03bcf1 +after: $r17=000000000000000000, $r4=0xa387a194cd03bcf1 +clz.w $r13, $r26 :: +before: $r13=0x69707656f354d758, $r26=0xd4a8f8ab02b876b0 +after: $r13=0x0000000000000006, $r26=0xd4a8f8ab02b876b0 +clz.w $r25, $r13 :: +before: $r25=0x103ce6ee41e094c3, $r13=0xd7a85bf4006e655a +after: $r25=0x0000000000000009, $r13=0xd7a85bf4006e655a +clz.w $r5, $r13 :: +before: $r5=0x3910578929e7cd4a, $r13=0x93c87b02b7b1b603 +after: $r5=000000000000000000, $r13=0x93c87b02b7b1b603 +clz.w $r18, $r29 :: +before: $r18=0x10639f8979feefe5, $r29=0x9d8b4b8f8493f844 +after: $r18=000000000000000000, $r29=0x9d8b4b8f8493f844 +clz.w $r25, $r16 :: +before: $r25=0x7b35b3e995b3b44d, $r16=0xad953d0ae0b3e870 +after: $r25=000000000000000000, $r16=0xad953d0ae0b3e870 +clz.w $r6, $r25 :: +before: $r6=0xda6cbd19f10ef86f, $r25=0x1d6665db1162cfb4 +after: $r6=0x0000000000000003, $r25=0x1d6665db1162cfb4 +clz.w $r5, $r12 :: +before: $r5=0x8a6f4d6ec8d7c00d, $r12=0x19b40cb8dd8d1679 +after: $r5=000000000000000000, $r12=0x19b40cb8dd8d1679 +cto.w $r7, $r15 :: +before: $r7=0x7285e9c364562d11, $r15=0x963655c7f58de520 +after: $r7=000000000000000000, $r15=0x963655c7f58de520 +cto.w $r4, $r15 :: +before: $r4=0x105dceebc6d7e641, $r15=0xfc01c17baaca9c46 +after: $r4=000000000000000000, $r15=0xfc01c17baaca9c46 +cto.w $r31, $r28 :: +before: $r31=0xdeff9742b93f0591, $r28=0x2cf98074b0151f33 +after: $r31=0x0000000000000002, $r28=0x2cf98074b0151f33 +cto.w $r13, $r8 :: +before: $r13=0xeee665743cd218ff, $r8=0xbdd700b2535aa3b7 +after: $r13=0x0000000000000003, $r8=0xbdd700b2535aa3b7 +cto.w $r23, $r13 :: +before: $r23=0x1cc22cfd7c0c869c, $r13=0x5b848b64decbee8f +after: $r23=0x0000000000000004, $r13=0x5b848b64decbee8f +cto.w $r12, $r18 :: +before: $r12=0x5c32b3db803e5988, $r18=0x2d5d1ebf93b79dd0 +after: $r12=000000000000000000, $r18=0x2d5d1ebf93b79dd0 +cto.w $r17, $r9 :: +before: $r17=0xc11d806786501f0e, $r9=0xd175fe2ca41bda38 +after: $r17=000000000000000000, $r9=0xd175fe2ca41bda38 +cto.w $r24, $r16 :: +before: $r24=0x504f9b43af62e2ad, $r16=0xfce545d98e2361da +after: $r24=000000000000000000, $r16=0xfce545d98e2361da +cto.w $r24, $r8 :: +before: $r24=0xc13ac5668538f5a4, $r8=0x3096912e575d64db +after: $r24=0x0000000000000002, $r8=0x3096912e575d64db +cto.w $r27, $r17 :: +before: $r27=0xd27f68629dd8d4fb, $r17=0x15ac43632e175a8b +after: $r27=0x0000000000000002, $r17=0x15ac43632e175a8b +ctz.w $r8, $r12 :: +before: $r8=0xfc9bd3736a3c08bd, $r12=0xaebba33c2e268daa +after: $r8=0x0000000000000001, $r12=0xaebba33c2e268daa +ctz.w $r5, $r27 :: +before: $r5=0x5dc8af7bac7db01a, $r27=0xabce2f0e113597aa +after: $r5=0x0000000000000001, $r27=0xabce2f0e113597aa +ctz.w $r18, $r6 :: +before: $r18=0xe4ac5b59d8442dfe, $r6=0x935d1b694e96bd04 +after: $r18=0x0000000000000002, $r6=0x935d1b694e96bd04 +ctz.w $r9, $r15 :: +before: $r9=0x9b760f465efbb52e, $r15=0x834c9974dba65d99 +after: $r9=000000000000000000, $r15=0x834c9974dba65d99 +ctz.w $r13, $r7 :: +before: $r13=0x95b5748f5f8bfb38, $r7=0x75dd7a9890cdf2d9 +after: $r13=000000000000000000, $r7=0x75dd7a9890cdf2d9 +ctz.w $r29, $r17 :: +before: $r29=0xa25119fd892d1b20, $r17=0x38c12e795dc52acf +after: $r29=000000000000000000, $r17=0x38c12e795dc52acf +ctz.w $r15, $r12 :: +before: $r15=0x95c2ce0f0446807c, $r12=0x623a5915ac8164b2 +after: $r15=0x0000000000000001, $r12=0x623a5915ac8164b2 +ctz.w $r6, $r17 :: +before: $r6=0xd9034892a300dca8, $r17=0x5911fea4e6ce1df3 +after: $r6=000000000000000000, $r17=0x5911fea4e6ce1df3 +ctz.w $r10, $r25 :: +before: $r10=0xda1e0d0eb34884ab, $r25=0x8d70d49a10ba8968 +after: $r10=0x0000000000000003, $r25=0x8d70d49a10ba8968 +ctz.w $r14, $r13 :: +before: $r14=0x207d275c076e5247, $r13=0xd243debc9b557922 +after: $r14=0x0000000000000001, $r13=0xd243debc9b557922 +clo.d $r7, $r16 :: +before: $r7=0x9432ccd773e86812, $r16=0x9f921ea959c97c2b +after: $r7=0x0000000000000001, $r16=0x9f921ea959c97c2b +clo.d $r7, $r12 :: +before: $r7=0xaf19ef0b422b09bf, $r12=0x8773ec5c72444fe2 +after: $r7=0x0000000000000001, $r12=0x8773ec5c72444fe2 +clo.d $r5, $r10 :: +before: $r5=0xa2912bc0ca36fa58, $r10=0x2c93a7506a8979b7 +after: $r5=000000000000000000, $r10=0x2c93a7506a8979b7 +clo.d $r7, $r28 :: +before: $r7=0x69dd3f71121c7380, $r28=0x1784b7c2c7558b4a +after: $r7=000000000000000000, $r28=0x1784b7c2c7558b4a +clo.d $r15, $r9 :: +before: $r15=0x95b40b42f113cecc, $r9=0xf0cdb7b9c17bb9e1 +after: $r15=0x0000000000000004, $r9=0xf0cdb7b9c17bb9e1 +clo.d $r9, $r27 :: +before: $r9=0x1961ee1499945d08, $r27=0x23c7a2252c1cbc78 +after: $r9=000000000000000000, $r27=0x23c7a2252c1cbc78 +clo.d $r30, $r19 :: +before: $r30=0xda0aa8b04f719a51, $r19=0x8f93c7a1b3cc9f12 +after: $r30=0x0000000000000001, $r19=0x8f93c7a1b3cc9f12 +clo.d $r26, $r20 :: +before: $r26=0xdd4f62bfe1237a28, $r20=0xd61c7bfe05165d04 +after: $r26=0x0000000000000002, $r20=0xd61c7bfe05165d04 +clo.d $r26, $r6 :: +before: $r26=0x44a1378e22d6ec81, $r6=0x1b21543ee9abd103 +after: $r26=000000000000000000, $r6=0x1b21543ee9abd103 +clo.d $r24, $r16 :: +before: $r24=0x51efcf6ef8eb9917, $r16=0x602cbdf020ee6da8 +after: $r24=000000000000000000, $r16=0x602cbdf020ee6da8 +clz.d $r27, $r7 :: +before: $r27=0x91df318f7b476077, $r7=0x6ca0b9cf9bb84c4a +after: $r27=0x0000000000000001, $r7=0x6ca0b9cf9bb84c4a +clz.d $r19, $r30 :: +before: $r19=0x435d7fb412d9c12c, $r30=0xc926e58bdb46104e +after: $r19=000000000000000000, $r30=0xc926e58bdb46104e +clz.d $r12, $r30 :: +before: $r12=0x906b06441b2ef62b, $r30=0x04b9b91966077ef0 +after: $r12=0x0000000000000005, $r30=0x04b9b91966077ef0 +clz.d $r28, $r6 :: +before: $r28=0x28bb3e3324f33e14, $r6=0x7628cd8752be6223 +after: $r28=0x0000000000000001, $r6=0x7628cd8752be6223 +clz.d $r14, $r15 :: +before: $r14=0xb7a5ae04bf2e60c0, $r15=0x41a328a79afda305 +after: $r14=0x0000000000000001, $r15=0x41a328a79afda305 +clz.d $r4, $r23 :: +before: $r4=0x5fd8327a265b1a3b, $r23=0x66b92d8b5b842d4a +after: $r4=0x0000000000000001, $r23=0x66b92d8b5b842d4a +clz.d $r18, $r29 :: +before: $r18=0x73df6808e38c72ad, $r29=0x6b91b11261dd26b6 +after: $r18=0x0000000000000001, $r29=0x6b91b11261dd26b6 +clz.d $r13, $r8 :: +before: $r13=0xd8d2dbd71d1783ad, $r8=0xdc50b7586ccab6a1 +after: $r13=000000000000000000, $r8=0xdc50b7586ccab6a1 +clz.d $r17, $r10 :: +before: $r17=0xee6f842bb7686b8d, $r10=0xdf52e003cd95f02f +after: $r17=000000000000000000, $r10=0xdf52e003cd95f02f +clz.d $r13, $r8 :: +before: $r13=0x91e717aef96cc046, $r8=0x5dd0743ed560ba78 +after: $r13=0x0000000000000001, $r8=0x5dd0743ed560ba78 +cto.d $r31, $r5 :: +before: $r31=0xf361d5d1fb232769, $r5=0x1530b67240d804cf +after: $r31=0x0000000000000004, $r5=0x1530b67240d804cf +cto.d $r5, $r26 :: +before: $r5=0xbedb393d17f69d40, $r26=0xcef56269ef7aecda +after: $r5=000000000000000000, $r26=0xcef56269ef7aecda +cto.d $r5, $r31 :: +before: $r5=0xadd75db878cdbf84, $r31=0x8e08acc65c97f0b2 +after: $r5=000000000000000000, $r31=0x8e08acc65c97f0b2 +cto.d $r31, $r31 :: +before: $r31=0x6a8a89827e4929f9, $r31=0x7df0f59d97924bb3 +after: $r31=0x0000000000000002, $r31=0x0000000000000002 +cto.d $r14, $r30 :: +before: $r14=0xefb0874ef3600b6d, $r30=0x97a4b45ab971a548 +after: $r14=000000000000000000, $r30=0x97a4b45ab971a548 +cto.d $r5, $r17 :: +before: $r5=0x144271fb49c8d2d8, $r17=0x787e6dbb4fec4d21 +after: $r5=0x0000000000000001, $r17=0x787e6dbb4fec4d21 +cto.d $r28, $r20 :: +before: $r28=0xd6d0953d2a12c998, $r20=0xafd578caad0dfa09 +after: $r28=0x0000000000000001, $r20=0xafd578caad0dfa09 +cto.d $r16, $r18 :: +before: $r16=0x0de650be54a7990c, $r18=0x3ea8f45e10441829 +after: $r16=0x0000000000000001, $r18=0x3ea8f45e10441829 +cto.d $r15, $r16 :: +before: $r15=0x0bbd328743f49a86, $r16=0x5cafc638b6b509be +after: $r15=000000000000000000, $r16=0x5cafc638b6b509be +cto.d $r6, $r20 :: +before: $r6=0x598ee27859cf8d0e, $r20=0x4bce530e537ad762 +after: $r6=000000000000000000, $r20=0x4bce530e537ad762 +ctz.d $r14, $r28 :: +before: $r14=0xf2e4d886a8fd3fe3, $r28=0x0dafbabdfefac692 +after: $r14=0x0000000000000001, $r28=0x0dafbabdfefac692 +ctz.d $r6, $r27 :: +before: $r6=0xe005a6a20d44fbca, $r27=0xe000ac4f4cfb2ce2 +after: $r6=0x0000000000000001, $r27=0xe000ac4f4cfb2ce2 +ctz.d $r15, $r26 :: +before: $r15=0x871c2ccd50ec0784, $r26=0xa82b0d96dd72f11c +after: $r15=0x0000000000000002, $r26=0xa82b0d96dd72f11c +ctz.d $r17, $r20 :: +before: $r17=0xebe7d9f4ec5055d5, $r20=0x65575957936d1d6e +after: $r17=0x0000000000000001, $r20=0x65575957936d1d6e +ctz.d $r19, $r8 :: +before: $r19=0x394effa243e5f14c, $r8=0xf6852349a7b00561 +after: $r19=000000000000000000, $r8=0xf6852349a7b00561 +ctz.d $r5, $r9 :: +before: $r5=0x3c67392fc408e9db, $r9=0xeff4bf8e886d7cc3 +after: $r5=000000000000000000, $r9=0xeff4bf8e886d7cc3 +ctz.d $r31, $r15 :: +before: $r31=0xbf5435775bd0435b, $r15=0x19760246c8d1d680 +after: $r31=0x0000000000000007, $r15=0x19760246c8d1d680 +ctz.d $r9, $r5 :: +before: $r9=0x0ccde230362ce06a, $r5=0x7590c6e73077c2bc +after: $r9=0x0000000000000002, $r5=0x7590c6e73077c2bc +ctz.d $r28, $r25 :: +before: $r28=0x2518777b06d608a0, $r25=0xb87647dad481ba32 +after: $r28=0x0000000000000001, $r25=0xb87647dad481ba32 +ctz.d $r23, $r19 :: +before: $r23=0xbe232a9fe2090e75, $r19=0x2dceda5cdc990d2e +after: $r23=0x0000000000000001, $r19=0x2dceda5cdc990d2e +revb.2h $r29, $r30 :: +before: $r29=0x75397084990a0745, $r30=0x0d4c83f5966c1c17 +after: $r29=0x000000006c96171c, $r30=0x0d4c83f5966c1c17 +revb.2h $r17, $r23 :: +before: $r17=0xecfbee2a69bbe344, $r23=0x5a42dc5dc5705f68 +after: $r17=0x0000000070c5685f, $r23=0x5a42dc5dc5705f68 +revb.2h $r6, $r14 :: +before: $r6=0xbfeffdbd68845522, $r14=0x3490af5b50fd56bf +after: $r6=0xfffffffffd50bf56, $r14=0x3490af5b50fd56bf +revb.2h $r13, $r6 :: +before: $r13=0x58e1821d319a1598, $r6=0x4c6711d021a72be6 +after: $r13=0xffffffffa721e62b, $r6=0x4c6711d021a72be6 +revb.2h $r18, $r8 :: +before: $r18=0x6e14994d4e16ff86, $r8=0x9fda01513ab5ceb8 +after: $r18=0xffffffffb53ab8ce, $r8=0x9fda01513ab5ceb8 +revb.2h $r7, $r30 :: +before: $r7=0x9979d3a3fcfc9323, $r30=0x504c708535bc136f +after: $r7=0xffffffffbc356f13, $r30=0x504c708535bc136f +revb.2h $r28, $r19 :: +before: $r28=0x9daf4aa3a33eec5f, $r19=0xaa376fc54f4be6f5 +after: $r28=0x000000004b4ff5e6, $r19=0xaa376fc54f4be6f5 +revb.2h $r30, $r8 :: +before: $r30=0x2e0bba43ec83e59e, $r8=0xaee8b8acd436f6da +after: $r30=0x0000000036d4daf6, $r8=0xaee8b8acd436f6da +revb.2h $r14, $r7 :: +before: $r14=0x9634787c9be10863, $r7=0xe9da521d42716c0a +after: $r14=0x0000000071420a6c, $r7=0xe9da521d42716c0a +revb.2h $r23, $r14 :: +before: $r23=0x687b89225667081a, $r14=0x9089e36a4f12f9c6 +after: $r23=0x00000000124fc6f9, $r14=0x9089e36a4f12f9c6 +revb.4h $r4, $r25 :: +before: $r4=0xc42859bd06b669d2, $r25=0x782e4ae6ab812191 +after: $r4=0x2e78e64a81ab9121, $r25=0x782e4ae6ab812191 +revb.4h $r18, $r19 :: +before: $r18=0x45ca4499d789fe5b, $r19=0x6e558c98b95d346d +after: $r18=0x556e988c5db96d34, $r19=0x6e558c98b95d346d +revb.4h $r24, $r10 :: +before: $r24=0x2d04871fd753c43f, $r10=0xbeab033e2b5a979e +after: $r24=0xabbe3e035a2b9e97, $r10=0xbeab033e2b5a979e +revb.4h $r24, $r8 :: +before: $r24=0xbc4deb39fb2ffe2e, $r8=0x5e3e50b8025e77f3 +after: $r24=0x3e5eb8505e02f377, $r8=0x5e3e50b8025e77f3 +revb.4h $r7, $r14 :: +before: $r7=0xf44a6ea6f42e0918, $r14=0x9f617a848e4ad8f2 +after: $r7=0x619f847a4a8ef2d8, $r14=0x9f617a848e4ad8f2 +revb.4h $r13, $r12 :: +before: $r13=0xda815ff8648e92b9, $r12=0xa401e74c4dd88e12 +after: $r13=0x01a44ce7d84d128e, $r12=0xa401e74c4dd88e12 +revb.4h $r31, $r19 :: +before: $r31=0x7964d861d2ecb8d5, $r19=0xe402e87f73fb4c68 +after: $r31=0x02e47fe8fb73684c, $r19=0xe402e87f73fb4c68 +revb.4h $r29, $r25 :: +before: $r29=0x6beff3fa6167cdcc, $r25=0x11e350b71aee0229 +after: $r29=0xe311b750ee1a2902, $r25=0x11e350b71aee0229 +revb.4h $r4, $r8 :: +before: $r4=0x357a56e8ae275376, $r8=0xdf8ebc175f4be7e3 +after: $r4=0x8edf17bc4b5fe3e7, $r8=0xdf8ebc175f4be7e3 +revb.4h $r15, $r27 :: +before: $r15=0xeb11b29acfe397d6, $r27=0x42d231083cd97aa0 +after: $r15=0xd2420831d93ca07a, $r27=0x42d231083cd97aa0 +revb.2w $r27, $r31 :: +before: $r27=0x0978f867dd7f0cb8, $r31=0x19eec2d357cd6a06 +after: $r27=0xd3c2ee19066acd57, $r31=0x19eec2d357cd6a06 +revb.2w $r10, $r10 :: +before: $r10=0x7897a40c4fda96d5, $r10=0xcb849783a18de892 +after: $r10=0x839784cb92e88da1, $r10=0x839784cb92e88da1 +revb.2w $r23, $r14 :: +before: $r23=0x018338c734be53a1, $r14=0x6258664ec1bb96b8 +after: $r23=0x4e665862b896bbc1, $r14=0x6258664ec1bb96b8 +revb.2w $r12, $r19 :: +before: $r12=0x7417ec4fef3451cc, $r19=0x216ad32ee149542b +after: $r12=0x2ed36a212b5449e1, $r19=0x216ad32ee149542b +revb.2w $r31, $r30 :: +before: $r31=0x8132835b9905b650, $r30=0x6fac007fbefdecf2 +after: $r31=0x7f00ac6ff2ecfdbe, $r30=0x6fac007fbefdecf2 +revb.2w $r25, $r10 :: +before: $r25=0x7336ebe375c83bed, $r10=0x643f76ac3010a6bb +after: $r25=0xac763f64bba61030, $r10=0x643f76ac3010a6bb +revb.2w $r31, $r29 :: +before: $r31=0x5d99f79f18e805b8, $r29=0xe65e70ca4cf299fa +after: $r31=0xca705ee6fa99f24c, $r29=0xe65e70ca4cf299fa +revb.2w $r30, $r19 :: +before: $r30=0xec10dd6d7249c5fa, $r19=0x3f6bb22d66caf299 +after: $r30=0x2db26b3f99f2ca66, $r19=0x3f6bb22d66caf299 +revb.2w $r6, $r30 :: +before: $r6=0x2c394783817c0870, $r30=0xd823cff07efd78db +after: $r6=0xf0cf23d8db78fd7e, $r30=0xd823cff07efd78db +revb.2w $r4, $r15 :: +before: $r4=0xc5acf61f075cd4e4, $r15=0xc154dd7479b90c6c +after: $r4=0x74dd54c16c0cb979, $r15=0xc154dd7479b90c6c +revb.d $r6, $r23 :: +before: $r6=0xe6e05a0dafda37ce, $r23=0x2ac7d047f197f6fb +after: $r6=0xfbf697f147d0c72a, $r23=0x2ac7d047f197f6fb +revb.d $r19, $r4 :: +before: $r19=0xc07a757bea6011ff, $r4=0xcef6cef3e0f941ff +after: $r19=0xff41f9e0f3cef6ce, $r4=0xcef6cef3e0f941ff +revb.d $r6, $r15 :: +before: $r6=0x711bb31e18fcb2f3, $r15=0x522068042cf5be1a +after: $r6=0x1abef52c04682052, $r15=0x522068042cf5be1a +revb.d $r9, $r7 :: +before: $r9=0xf9654c655c67392e, $r7=0xa1b065742110e3f4 +after: $r9=0xf4e310217465b0a1, $r7=0xa1b065742110e3f4 +revb.d $r29, $r4 :: +before: $r29=0x70c0dcad23609060, $r4=0x5d04b7b2ece6f6bb +after: $r29=0xbbf6e6ecb2b7045d, $r4=0x5d04b7b2ece6f6bb +revb.d $r15, $r4 :: +before: $r15=0x809930516f3136eb, $r4=0xda33327a8d42ef55 +after: $r15=0x55ef428d7a3233da, $r4=0xda33327a8d42ef55 +revb.d $r10, $r4 :: +before: $r10=0x1a7ee04b354f6af5, $r4=0xcda6c6943e46fed7 +after: $r10=0xd7fe463e94c6a6cd, $r4=0xcda6c6943e46fed7 +revb.d $r20, $r4 :: +before: $r20=0x315f95452d748459, $r4=0xa001e934745758e0 +after: $r20=0xe058577434e901a0, $r4=0xa001e934745758e0 +revb.d $r6, $r8 :: +before: $r6=0xabbd06000374627a, $r8=0x85441006689de89b +after: $r6=0x9be89d6806104485, $r8=0x85441006689de89b +revb.d $r27, $r24 :: +before: $r27=0x2d404e69f54afa48, $r24=0x46f47b822772f3cd +after: $r27=0xcdf37227827bf446, $r24=0x46f47b822772f3cd +revh.2w $r6, $r15 :: +before: $r6=0x5b764c7bfb1999eb, $r15=0x86603fc3f96843ed +after: $r6=0x3fc3866043edf968, $r15=0x86603fc3f96843ed +revh.2w $r19, $r10 :: +before: $r19=0xf39f8e6b43dd63ce, $r10=0x141d294d06276941 +after: $r19=0x294d141d69410627, $r10=0x141d294d06276941 +revh.2w $r5, $r20 :: +before: $r5=0x3ff54e5c35d83e69, $r20=0xd677d6a21384278a +after: $r5=0xd6a2d677278a1384, $r20=0xd677d6a21384278a +revh.2w $r4, $r31 :: +before: $r4=0xce463b02a2f840cc, $r31=0x6f87c9636f9cfca6 +after: $r4=0xc9636f87fca66f9c, $r31=0x6f87c9636f9cfca6 +revh.2w $r19, $r26 :: +before: $r19=0x34abc96ddde64e27, $r26=0x723ec7ce92720502 +after: $r19=0xc7ce723e05029272, $r26=0x723ec7ce92720502 +revh.2w $r8, $r18 :: +before: $r8=0x1454a1ee8739c235, $r18=0xd890efa373a6dfb0 +after: $r8=0xefa3d890dfb073a6, $r18=0xd890efa373a6dfb0 +revh.2w $r12, $r31 :: +before: $r12=0xf0c8b856751cae70, $r31=0xb675dff2568e6ebf +after: $r12=0xdff2b6756ebf568e, $r31=0xb675dff2568e6ebf +revh.2w $r24, $r9 :: +before: $r24=0xb36984e3a7a3eaea, $r9=0xa169cfa9f35f6a8a +after: $r24=0xcfa9a1696a8af35f, $r9=0xa169cfa9f35f6a8a +revh.2w $r25, $r27 :: +before: $r25=0x640b3e6b41180473, $r27=0x9bc307f0a2ef368f +after: $r25=0x07f09bc3368fa2ef, $r27=0x9bc307f0a2ef368f +revh.2w $r7, $r9 :: +before: $r7=0x897e1406a0eb2dc9, $r9=0x1921bcf657fecdcc +after: $r7=0xbcf61921cdcc57fe, $r9=0x1921bcf657fecdcc +revh.d $r14, $r25 :: +before: $r14=0xec3573411ea025e5, $r25=0x6976d4371b08f1ab +after: $r14=0xf1ab1b08d4376976, $r25=0x6976d4371b08f1ab +revh.d $r24, $r31 :: +before: $r24=0x9ef9e5cb1375d42a, $r31=0x9ce130c8a579e11d +after: $r24=0xe11da57930c89ce1, $r31=0x9ce130c8a579e11d +revh.d $r9, $r28 :: +before: $r9=0x3c8cd0055a5e7031, $r28=0xf05f9381753ded16 +after: $r9=0xed16753d9381f05f, $r28=0xf05f9381753ded16 +revh.d $r24, $r26 :: +before: $r24=0x6a4e5797f19041f6, $r26=0xd26a5ae65e21041c +after: $r24=0x041c5e215ae6d26a, $r26=0xd26a5ae65e21041c +revh.d $r14, $r24 :: +before: $r14=0xe2cb9a83aee22d97, $r24=0x6405d71e0bb63321 +after: $r14=0x33210bb6d71e6405, $r24=0x6405d71e0bb63321 +revh.d $r19, $r23 :: +before: $r19=0x91cdf3bcd9afe76d, $r23=0x171953826107396a +after: $r19=0x396a610753821719, $r23=0x171953826107396a +revh.d $r23, $r14 :: +before: $r23=0x93ed49255d084e12, $r14=0x374bd76990198b43 +after: $r23=0x8b439019d769374b, $r14=0x374bd76990198b43 +revh.d $r31, $r12 :: +before: $r31=0x08e54a908f04882b, $r12=0xf7e8756491b9d346 +after: $r31=0xd34691b97564f7e8, $r12=0xf7e8756491b9d346 +revh.d $r31, $r20 :: +before: $r31=0xbb7cd34502fdf01f, $r20=0x906b7289a6957d3f +after: $r31=0x7d3fa6957289906b, $r20=0x906b7289a6957d3f +revh.d $r27, $r30 :: +before: $r27=0xacbca1aacdd9dd3f, $r30=0x3072d9c69004d4b5 +after: $r27=0xd4b59004d9c63072, $r30=0x3072d9c69004d4b5 +bitrev.4b $r23, $r19 :: +before: $r23=0xb422f2854b491d92, $r19=0x7649084cec69098a +after: $r23=0x0000000037969051, $r19=0x7649084cec69098a +bitrev.4b $r27, $r16 :: +before: $r27=0xd14736328d74b448, $r16=0x1abee3a271c71db9 +after: $r27=0xffffffff8ee3b89d, $r16=0x1abee3a271c71db9 +bitrev.4b $r15, $r23 :: +before: $r15=0xf17c0f0ccfbb2c38, $r23=0x490107ff4155bd17 +after: $r15=0xffffffff82aabde8, $r23=0x490107ff4155bd17 +bitrev.4b $r5, $r18 :: +before: $r5=0x8408d6a30523619d, $r18=0x625d5aedf0add9fb +after: $r5=0x000000000fb59bdf, $r18=0x625d5aedf0add9fb +bitrev.4b $r8, $r15 :: +before: $r8=0xc41a2fdb60ba75a6, $r15=0xe2562eab3b333a00 +after: $r8=0xffffffffdccc5c00, $r15=0xe2562eab3b333a00 +bitrev.4b $r17, $r18 :: +before: $r17=0x6a409394f364c02a, $r18=0xea970d90edb343cc +after: $r17=0xffffffffb7cdc233, $r18=0xea970d90edb343cc +bitrev.4b $r25, $r29 :: +before: $r25=0xd8d1c9b8dcff266d, $r29=0xacca47ac7597ca65 +after: $r25=0xffffffffaee953a6, $r29=0xacca47ac7597ca65 +bitrev.4b $r26, $r24 :: +before: $r26=0xe2a0d11df8c5055b, $r24=0xc57559d03e3e216d +after: $r26=0x000000007c7c84b6, $r24=0xc57559d03e3e216d +bitrev.4b $r8, $r27 :: +before: $r8=0xb6a5815170d657f0, $r27=0x9f60901eefa1347a +after: $r8=0xfffffffff7852c5e, $r27=0x9f60901eefa1347a +bitrev.4b $r20, $r16 :: +before: $r20=0x432a2fbf2b073732, $r16=0x604b8d7ecb5e86dc +after: $r20=0xffffffffd37a613b, $r16=0x604b8d7ecb5e86dc +bitrev.8b $r25, $r7 :: +before: $r25=0x22b2e6007f742fd1, $r7=0xe8c23886def1bbc9 +after: $r25=0x17431c617b8fdd93, $r7=0xe8c23886def1bbc9 +bitrev.8b $r28, $r30 :: +before: $r28=0xf985d7779c5ca157, $r30=0x285cbdc0f47395d1 +after: $r28=0x143abd032fcea98b, $r30=0x285cbdc0f47395d1 +bitrev.8b $r29, $r13 :: +before: $r29=0xd9b8364a793bc50c, $r13=0xded35d7c7ba73d29 +after: $r29=0x7bcbba3edee5bc94, $r13=0xded35d7c7ba73d29 +bitrev.8b $r12, $r28 :: +before: $r12=0x18d7769bc1147dc5, $r28=0xfb6cda8c7f12313a +after: $r12=0xdf365b31fe488c5c, $r28=0xfb6cda8c7f12313a +bitrev.8b $r23, $r6 :: +before: $r23=0xeff84dc134b3acbe, $r6=0xee7c4e89e333eda8 +after: $r23=0x773e7291c7ccb715, $r6=0xee7c4e89e333eda8 +bitrev.8b $r24, $r20 :: +before: $r24=0xad65748f0bc46e9f, $r20=0xd0d88137a6284eac +after: $r24=0x0b1b81ec65147235, $r20=0xd0d88137a6284eac +bitrev.8b $r10, $r5 :: +before: $r10=0xe0e1c1e262352e89, $r5=0x9c43ebc4f7c65dc1 +after: $r10=0x39c2d723ef63ba83, $r5=0x9c43ebc4f7c65dc1 +bitrev.8b $r27, $r13 :: +before: $r27=0x444a53aa65d317dc, $r13=0x473eea7ea5691da7 +after: $r27=0xe27c577ea596b8e5, $r13=0x473eea7ea5691da7 +bitrev.8b $r13, $r9 :: +before: $r13=0xfc48d0fdf4c7a6e5, $r9=0x5dcad407df3401a5 +after: $r13=0xba532be0fb2c80a5, $r9=0x5dcad407df3401a5 +bitrev.8b $r12, $r5 :: +before: $r12=0x0ebef32fcbd91e9a, $r5=0xe1eeea527816355e +after: $r12=0x8777574a1e68ac7a, $r5=0xe1eeea527816355e +bitrev.w $r18, $r15 :: +before: $r18=0x02028b0c8691a767, $r15=0x5822df2950c9c2d3 +after: $r18=0xffffffffcb43930a, $r15=0x5822df2950c9c2d3 +bitrev.w $r30, $r27 :: +before: $r30=0x2a2d48209d9f377b, $r27=0xde9d59b836df41fc +after: $r30=0x000000003f82fb6c, $r27=0xde9d59b836df41fc +bitrev.w $r17, $r4 :: +before: $r17=0xe6fb8b07c90464e6, $r4=0x65976cb5c6c6a5b0 +after: $r17=0x000000000da56363, $r4=0x65976cb5c6c6a5b0 +bitrev.w $r9, $r31 :: +before: $r9=0x1b95159ec5c37644, $r31=0x62c549b741c2adad +after: $r9=0xffffffffb5b54382, $r31=0x62c549b741c2adad +bitrev.w $r17, $r14 :: +before: $r17=0x8b414dfa7156f0ce, $r14=0x9642d0186f420e7c +after: $r17=0x000000003e7042f6, $r14=0x9642d0186f420e7c +bitrev.w $r15, $r8 :: +before: $r15=0x2722ecb374b4d5e3, $r8=0xeaf151a286bbc4cf +after: $r15=0xfffffffff323dd61, $r8=0xeaf151a286bbc4cf +bitrev.w $r27, $r19 :: +before: $r27=0x058ec913c63634a5, $r19=0xe723c39df96a4fd2 +after: $r27=0x000000004bf2569f, $r19=0xe723c39df96a4fd2 +bitrev.w $r7, $r26 :: +before: $r7=0xa245e7dd80a324a2, $r26=0x0e7d6c2b2683291e +after: $r7=0x000000007894c164, $r26=0x0e7d6c2b2683291e +bitrev.w $r31, $r6 :: +before: $r31=0x114292ed02ba1255, $r6=0x13cd62afac5ac3d4 +after: $r31=0x000000002bc35a35, $r6=0x13cd62afac5ac3d4 +bitrev.w $r7, $r25 :: +before: $r7=0xbd46d88fc8d2933b, $r25=0x69ce9ccb487dadd1 +after: $r7=0xffffffff8bb5be12, $r25=0x69ce9ccb487dadd1 +bitrev.d $r4, $r29 :: +before: $r4=0xeaacaeb60b227eab, $r29=0x799f36da44887e2c +after: $r4=0x347e11225b6cf99e, $r29=0x799f36da44887e2c +bitrev.d $r29, $r6 :: +before: $r29=0xcfbb055ab1ebf7fa, $r6=0x2924f63fec744b02 +after: $r29=0x40d22e37fc6f2494, $r6=0x2924f63fec744b02 +bitrev.d $r28, $r31 :: +before: $r28=0xaac74a398d76900d, $r31=0xf6c75e45e33b4cb7 +after: $r28=0xed32dcc7a27ae36f, $r31=0xf6c75e45e33b4cb7 +bitrev.d $r24, $r12 :: +before: $r24=0xfc8bc33fb4a8d023, $r12=0xcccd98e9d53aa26a +after: $r24=0x56455cab9719b333, $r12=0xcccd98e9d53aa26a +bitrev.d $r8, $r7 :: +before: $r8=0x7502cd68289f4c3a, $r7=0x746ddfd3c3a512b1 +after: $r8=0x8d48a5c3cbfbb62e, $r7=0x746ddfd3c3a512b1 +bitrev.d $r6, $r16 :: +before: $r6=0xe8b94bfe615774ae, $r16=0x518770bbee53d619 +after: $r6=0x986bca77dd0ee18a, $r16=0x518770bbee53d619 +bitrev.d $r24, $r4 :: +before: $r24=0x6318c17dbae816c3, $r4=0x9ab684e129b57f07 +after: $r24=0xe0fead9487216d59, $r4=0x9ab684e129b57f07 +bitrev.d $r27, $r23 :: +before: $r27=0x8a22909b005a86b8, $r23=0x69337e8c3b1fc2bb +after: $r27=0xdd43f8dc317ecc96, $r23=0x69337e8c3b1fc2bb +bitrev.d $r20, $r9 :: +before: $r20=0x009f43885d40caf0, $r9=0x193cbf609dbc33d4 +after: $r20=0x2bcc3db906fd3c98, $r9=0x193cbf609dbc33d4 +bitrev.d $r30, $r19 :: +before: $r30=0x30fa02e0fc390ac9, $r19=0x21686c931c6260da +after: $r30=0x5b064638c9361684, $r19=0x21686c931c6260da +bytepick.w $r26, $r15, $r19, 1 :: +before: $r26=0x1b0b980dd3271273, $r15=0x8737ca6c8106ceee, $r19=0x02807e0dcb47d6ef +after: $r26=0x0000000047d6ef81, $r15=0x8737ca6c8106ceee, $r19=0x02807e0dcb47d6ef +bytepick.w $r15, $r17, $r7, 0 :: +before: $r15=0x3d2e3fbcbd032001, $r17=0x5eced8cf3da8b205, $r7=0xb8155b41321e09c0 +after: $r15=0x00000000321e09c0, $r17=0x5eced8cf3da8b205, $r7=0xb8155b41321e09c0 +bytepick.w $r12, $r15, $r17, 3 :: +before: $r12=0x2670c80f12a87520, $r15=0x29ab42125e3ea5c8, $r17=0x32a39ac435460f2f +after: $r12=0x000000002f5e3ea5, $r15=0x29ab42125e3ea5c8, $r17=0x32a39ac435460f2f +bytepick.w $r4, $r20, $r18, 3 :: +before: $r4=0x5a64271926277c04, $r20=0xcbde225cc736e5d5, $r18=0x18abacc874db47e9 +after: $r4=0xffffffffe9c736e5, $r20=0xcbde225cc736e5d5, $r18=0x18abacc874db47e9 +bytepick.w $r8, $r5, $r24, 3 :: +before: $r8=0xdb41606ce3f9df94, $r5=0xc3f6ce370d754a3f, $r24=0x34ad5a423a5c42e3 +after: $r8=0xffffffffe30d754a, $r5=0xc3f6ce370d754a3f, $r24=0x34ad5a423a5c42e3 +bytepick.w $r5, $r30, $r14, 2 :: +before: $r5=0xedb3aad221050d0b, $r30=0x46f5823389f2581a, $r14=0xf766f1e75349809e +after: $r5=0xffffffff809e89f2, $r30=0x46f5823389f2581a, $r14=0xf766f1e75349809e +bytepick.w $r4, $r19, $r18, 0 :: +before: $r4=0xf92ed0231f25c991, $r19=0xba59df0352ed6b3e, $r18=0x58d6fbce4e4325e8 +after: $r4=0x000000004e4325e8, $r19=0xba59df0352ed6b3e, $r18=0x58d6fbce4e4325e8 +bytepick.w $r18, $r28, $r24, 3 :: +before: $r18=0x177dcaf8fcd30180, $r28=0xbdc04b3b8f707462, $r24=0x6102168606deb3ed +after: $r18=0xffffffffed8f7074, $r28=0xbdc04b3b8f707462, $r24=0x6102168606deb3ed +bytepick.w $r13, $r27, $r29, 2 :: +before: $r13=0x383d82c5d717259b, $r27=0x495e30e5e680d7fc, $r29=0x1c17f315ebb3bec3 +after: $r13=0xffffffffbec3e680, $r27=0x495e30e5e680d7fc, $r29=0x1c17f315ebb3bec3 +bytepick.w $r5, $r29, $r4, 1 :: +before: $r5=0x26a0fb212ab80a3a, $r29=0x78b167aecd81f869, $r4=0x6daab499f228fef4 +after: $r5=0x0000000028fef4cd, $r29=0x78b167aecd81f869, $r4=0x6daab499f228fef4 +bytepick.d $r28, $r4, $r28, 7 :: +before: $r28=0x794fa22d52f7e834, $r4=0x2f084db071d3bcce, $r28=0xa0cf51d7020f10c1 +after: $r28=0xc12f084db071d3bc, $r4=0x2f084db071d3bcce, $r28=0xc12f084db071d3bc +bytepick.d $r10, $r18, $r4, 2 :: +before: $r10=0x9fd7a6b378604833, $r18=0x37da15f8a7154cab, $r4=0xaedd64328d27a0a8 +after: $r10=0x64328d27a0a837da, $r18=0x37da15f8a7154cab, $r4=0xaedd64328d27a0a8 +bytepick.d $r7, $r6, $r24, 3 :: +before: $r7=0xdee49920d429d3c2, $r6=0x15e3f61f2f82a2d1, $r24=0xdeba03c7761e4678 +after: $r7=0xc7761e467815e3f6, $r6=0x15e3f61f2f82a2d1, $r24=0xdeba03c7761e4678 +bytepick.d $r19, $r16, $r5, 4 :: +before: $r19=0x53bda4d18e61fc44, $r16=0xc79bd94439006673, $r5=0xa8024ab452a2bd52 +after: $r19=0x52a2bd52c79bd944, $r16=0xc79bd94439006673, $r5=0xa8024ab452a2bd52 +bytepick.d $r26, $r19, $r25, 7 :: +before: $r26=0xc8aae5136d925592, $r19=0xea109dd2837d3acf, $r25=0x30e93a75e695666a +after: $r26=0x6aea109dd2837d3a, $r19=0xea109dd2837d3acf, $r25=0x30e93a75e695666a +bytepick.d $r8, $r14, $r8, 2 :: +before: $r8=0xa03db273c845b37f, $r14=0xa7fd0053a136769f, $r8=0x6ab932903229b035 +after: $r8=0x32903229b035a7fd, $r14=0xa7fd0053a136769f, $r8=0x32903229b035a7fd +bytepick.d $r9, $r14, $r23, 2 :: +before: $r9=0x2f160a0d147b300f, $r14=0xdae9d5d15bb8f5b5, $r23=0xc4fdfbb29d49dfe4 +after: $r9=0xfbb29d49dfe4dae9, $r14=0xdae9d5d15bb8f5b5, $r23=0xc4fdfbb29d49dfe4 +bytepick.d $r20, $r18, $r15, 5 :: +before: $r20=0x30cefdebc30b841a, $r18=0xbfd016fb0312277c, $r15=0x44269b95d496912f +after: $r20=0x96912fbfd016fb03, $r18=0xbfd016fb0312277c, $r15=0x44269b95d496912f +bytepick.d $r12, $r17, $r5, 2 :: +before: $r12=0xde32bc5d3471eed2, $r17=0xdb807610c6e762e4, $r5=0xb2148e34e649d1b8 +after: $r12=0x8e34e649d1b8db80, $r17=0xdb807610c6e762e4, $r5=0xb2148e34e649d1b8 +bytepick.d $r5, $r24, $r28, 3 :: +before: $r5=0x9ab1be6a0faa61a8, $r24=0x97d4a12579967739, $r28=0xaa592ef1fd606bad +after: $r5=0xf1fd606bad97d4a1, $r24=0x97d4a12579967739, $r28=0xaa592ef1fd606bad +maskeqz $r14, $r28, $r25 :: +before: $r14=0xc263b6b8f3404c8d, $r28=0x90ef733c88c88866, $r25=0xd256888d94e8d21a +after: $r14=0x90ef733c88c88866, $r28=0x90ef733c88c88866, $r25=0xd256888d94e8d21a +maskeqz $r13, $r9, $r15 :: +before: $r13=0x5bdd86b962c61db4, $r9=0x8a78f7b88a728d92, $r15=0x69e707acb2c26a83 +after: $r13=0x8a78f7b88a728d92, $r9=0x8a78f7b88a728d92, $r15=0x69e707acb2c26a83 +maskeqz $r7, $r7, $r13 :: +before: $r7=0xea86abdbdea660cb, $r7=0xfb778deef0a5b893, $r13=0xad10e23c971d1a9f +after: $r7=0xfb778deef0a5b893, $r7=0xfb778deef0a5b893, $r13=0xad10e23c971d1a9f +maskeqz $r8, $r7, $r19 :: +before: $r8=0xf64df33b6146939f, $r7=0xe7376d3da44f4dfd, $r19=0x7987e122af2505ab +after: $r8=0xe7376d3da44f4dfd, $r7=0xe7376d3da44f4dfd, $r19=0x7987e122af2505ab +maskeqz $r10, $r27, $r29 :: +before: $r10=0x404a261c069b488b, $r27=0x81886c523ec2658c, $r29=0x3236dc83d0a27cc1 +after: $r10=0x81886c523ec2658c, $r27=0x81886c523ec2658c, $r29=0x3236dc83d0a27cc1 +maskeqz $r23, $r16, $r25 :: +before: $r23=0x8671050519b7bda0, $r16=0x26fa2567b106d73a, $r25=0x0d884011e0d767fe +after: $r23=0x26fa2567b106d73a, $r16=0x26fa2567b106d73a, $r25=0x0d884011e0d767fe +maskeqz $r5, $r19, $r18 :: +before: $r5=0xbd8d4cef53122132, $r19=0x4976c047c57ec148, $r18=0x602312f372049a5e +after: $r5=0x4976c047c57ec148, $r19=0x4976c047c57ec148, $r18=0x602312f372049a5e +maskeqz $r29, $r24, $r23 :: +before: $r29=0x07f390b695d8b12e, $r24=0x70043e7666a24a34, $r23=0xfee8f8f90ab3ac9b +after: $r29=0x70043e7666a24a34, $r24=0x70043e7666a24a34, $r23=0xfee8f8f90ab3ac9b +maskeqz $r25, $r4, $r18 :: +before: $r25=0x07eaffcb6dac1b5b, $r4=0x4b12f8c6738216a2, $r18=0x409acb80b7391511 +after: $r25=0x4b12f8c6738216a2, $r4=0x4b12f8c6738216a2, $r18=0x409acb80b7391511 +maskeqz $r30, $r6, $r24 :: +before: $r30=0x14d829636b628dc9, $r6=0xdb88a366a2271c2c, $r24=0x0ea0d5998835940a +after: $r30=0xdb88a366a2271c2c, $r6=0xdb88a366a2271c2c, $r24=0x0ea0d5998835940a +masknez $r14, $r24, $r5 :: +before: $r14=0x46b15bbb9507bd79, $r24=0xc92af628c880a454, $r5=0x846a586db0af0965 +after: $r14=000000000000000000, $r24=0xc92af628c880a454, $r5=0x846a586db0af0965 +masknez $r30, $r8, $r8 :: +before: $r30=0x43cd20b5234db4e8, $r8=0x7aeee6ab6b10561f, $r8=0x45ab4fdb4ca8b325 +after: $r30=000000000000000000, $r8=0x45ab4fdb4ca8b325, $r8=0x45ab4fdb4ca8b325 +masknez $r24, $r19, $r15 :: +before: $r24=0xd3d50bbb34b528e2, $r19=0xdd71746b0beedae3, $r15=0xa34d82fc50174094 +after: $r24=000000000000000000, $r19=0xdd71746b0beedae3, $r15=0xa34d82fc50174094 +masknez $r29, $r26, $r26 :: +before: $r29=0x576cb2da15b1462d, $r26=0x6c669f0195b50b7a, $r26=0xec1609ef36aa938f +after: $r29=000000000000000000, $r26=0xec1609ef36aa938f, $r26=0xec1609ef36aa938f +masknez $r4, $r29, $r10 :: +before: $r4=0xaa220f67a02617db, $r29=0x0ffcd18e3016e10f, $r10=0x4cf9bdd8dca7f88f +after: $r4=000000000000000000, $r29=0x0ffcd18e3016e10f, $r10=0x4cf9bdd8dca7f88f +masknez $r23, $r9, $r29 :: +before: $r23=0x774e1c840428fbde, $r9=0x391268694388d2a7, $r29=0xf06192a4e5780c53 +after: $r23=000000000000000000, $r9=0x391268694388d2a7, $r29=0xf06192a4e5780c53 +masknez $r7, $r25, $r28 :: +before: $r7=0x7b75099f16135faa, $r25=0xf95af681c18bf31c, $r28=0x2f6122581dfdef74 +after: $r7=000000000000000000, $r25=0xf95af681c18bf31c, $r28=0x2f6122581dfdef74 +masknez $r26, $r10, $r16 :: +before: $r26=0xe6006c9bd6bae204, $r10=0x7e84e5db1181249d, $r16=0x6ab2371059cdc875 +after: $r26=000000000000000000, $r10=0x7e84e5db1181249d, $r16=0x6ab2371059cdc875 +masknez $r26, $r15, $r28 :: +before: $r26=0xb4c9c784ef74245f, $r15=0x20cc1c4c169ca02c, $r28=0x606eeb8ce6278d16 +after: $r26=000000000000000000, $r15=0x20cc1c4c169ca02c, $r28=0x606eeb8ce6278d16 +masknez $r19, $r16, $r16 :: +before: $r19=0x75a721553f7c7054, $r16=0x7b63b7b7b3f5bd5f, $r16=0xf8c7933e92e155ee +after: $r19=000000000000000000, $r16=0xf8c7933e92e155ee, $r16=0xf8c7933e92e155ee +bstrins.w $r27, $r16, 31, 8 :: +before: $r27=0x431055863e78b187, $r16=0xe18dda9620a50e9d +after: $r27=0xffffffffa50e9d87, $r16=0xe18dda9620a50e9d +bstrins.w $r26, $r27, 30, 27 :: +before: $r26=0x19f800eab7e1ab51, $r27=0x61e7d86005d21d29 +after: $r26=0xffffffffcfe1ab51, $r27=0x61e7d86005d21d29 +bstrins.w $r15, $r4, 17, 14 :: +before: $r15=0xb141d462e777528d, $r4=0xb7aebff9bcca1643 +after: $r15=0xffffffffe774d28d, $r4=0xb7aebff9bcca1643 +bstrins.w $r30, $r17, 24, 6 :: +before: $r30=0xfac48083375844fe, $r17=0x6d3283ba14cc27eb +after: $r30=0x000000003709fafe, $r17=0x6d3283ba14cc27eb +bstrins.w $r12, $r12, 30, 25 :: +before: $r12=0x9b7629774f19f64a, $r12=0x84ee8d65b2842686 +after: $r12=0xffffffff8c842686, $r12=0xffffffff8c842686 +bstrins.w $r15, $r10, 26, 1 :: +before: $r15=0x290172844863090f, $r10=0x85ea298976069fcd +after: $r15=0x000000004c0d3f9b, $r10=0x85ea298976069fcd +bstrins.w $r10, $r13, 23, 8 :: +before: $r10=0x66942ba1c15e85aa, $r13=0xddb2dfa7474a4370 +after: $r10=0xffffffffc14370aa, $r13=0xddb2dfa7474a4370 +bstrins.w $r5, $r20, 18, 16 :: +before: $r5=0x3dcfecca80bf0d79, $r20=0x5044b246f2d3f890 +after: $r5=0xffffffff80b80d79, $r20=0x5044b246f2d3f890 +bstrins.w $r23, $r5, 25, 21 :: +before: $r23=0xa11723142f1472a7, $r5=0xcbaaa9a23d119663 +after: $r23=0x000000002c7472a7, $r5=0xcbaaa9a23d119663 +bstrins.w $r20, $r31, 13, 12 :: +before: $r20=0x6a1110240ba884b8, $r31=0x45cadf0ffe08cc25 +after: $r20=0x000000000ba894b8, $r31=0x45cadf0ffe08cc25 +bstrpick.w $r5, $r23, 23, 11 :: +before: $r5=0x6885eaa89f691954, $r23=0x94f8458597294f2e +after: $r5=0x0000000000000529, $r23=0x94f8458597294f2e +bstrpick.w $r25, $r8, 18, 11 :: +before: $r25=0x11be9b9923ebee96, $r8=0x23deda120a49df15 +after: $r25=0x000000000000003b, $r8=0x23deda120a49df15 +bstrpick.w $r6, $r6, 10, 3 :: +before: $r6=0x3546d655181289bc, $r6=0x7ee84a41c952b690 +after: $r6=0x00000000000000d2, $r6=0x00000000000000d2 +bstrpick.w $r25, $r5, 15, 9 :: +before: $r25=0xb2eec884ea77f548, $r5=0x23992bc40919416f +after: $r25=0x0000000000000020, $r5=0x23992bc40919416f +bstrpick.w $r26, $r14, 21, 8 :: +before: $r26=0x8e591161730ac582, $r14=0xf45f4435cc1cb138 +after: $r26=0x0000000000001cb1, $r14=0xf45f4435cc1cb138 +bstrpick.w $r9, $r14, 7, 3 :: +before: $r9=0x1ac92d930e8361f9, $r14=0xcc11dd56e96c6256 +after: $r9=0x000000000000000a, $r14=0xcc11dd56e96c6256 +bstrpick.w $r19, $r9, 8, 8 :: +before: $r19=0xd15fd80fafe60a58, $r9=0xb1426a8c680d628c +after: $r19=000000000000000000, $r9=0xb1426a8c680d628c +bstrpick.w $r17, $r13, 30, 12 :: +before: $r17=0xfa48c3cd091d2b5e, $r13=0x3a2827a58a014a72 +after: $r17=0x000000000000a014, $r13=0x3a2827a58a014a72 +bstrpick.w $r6, $r31, 16, 7 :: +before: $r6=0xca10a858ebfa78a1, $r31=0x202a38722f270884 +after: $r6=0x0000000000000211, $r31=0x202a38722f270884 +bstrpick.w $r20, $r10, 31, 15 :: +before: $r20=0xc010deb269ae6ba2, $r10=0x98f1d297734f9f4c +after: $r20=0x000000000000e69f, $r10=0x98f1d297734f9f4c +bstrins.d $r29, $r17, 60, 25 :: +before: $r29=0x7cf4a9ec79307e59, $r17=0xb1b5afc00eef90a3 +after: $r29=0x601ddf2147307e59, $r17=0xb1b5afc00eef90a3 +bstrins.d $r10, $r27, 31, 22 :: +before: $r10=0xc708602dee32579f, $r27=0x199d90a711e94375 +after: $r10=0xc708602ddd72579f, $r27=0x199d90a711e94375 +bstrins.d $r4, $r24, 58, 58 :: +before: $r4=0x4e5ce98e217a4b59, $r24=0xaf25b5661daefdea +after: $r4=0x4a5ce98e217a4b59, $r24=0xaf25b5661daefdea +bstrins.d $r12, $r30, 16, 6 :: +before: $r12=0x9505d862c56b1708, $r30=0x7f3f0c983ce27863 +after: $r12=0x9505d862c56a18c8, $r30=0x7f3f0c983ce27863 +bstrins.d $r29, $r5, 43, 0 :: +before: $r29=0x248f295ef3afe5aa, $r5=0x9469277db61227b7 +after: $r29=0x248f277db61227b7, $r5=0x9469277db61227b7 +bstrins.d $r31, $r31, 49, 23 :: +before: $r31=0xbc5f0c47c3a63a94, $r31=0x4aacc1c77ad0c09a +after: $r31=0x4aad68604d50c09a, $r31=0x4aad68604d50c09a +bstrins.d $r6, $r24, 12, 2 :: +before: $r6=0x79110235b8c34188, $r24=0x75e3e311aef2bef9 +after: $r6=0x79110235b8c35be4, $r24=0x75e3e311aef2bef9 +bstrins.d $r6, $r16, 43, 13 :: +before: $r6=0xaa6e63ffd80b76c5, $r16=0xb1ea7dcb3af0881d +after: $r6=0xaa6e675e1103b6c5, $r16=0xb1ea7dcb3af0881d +bstrins.d $r15, $r25, 53, 29 :: +before: $r15=0x5b68a802f26a1804, $r25=0xb4f651115b84591b +after: $r15=0x5b708b23726a1804, $r25=0xb4f651115b84591b +bstrins.d $r9, $r9, 61, 40 :: +before: $r9=0x3394218c965d5f1a, $r9=0xf3d30b5d4d4089b4 +after: $r9=0xc089b45d4d4089b4, $r9=0xc089b45d4d4089b4 +bstrpick.d $r27, $r27, 63, 33 :: +before: $r27=0x503c8fae2d6d7b58, $r27=0x9fd9869ca812de0c +after: $r27=0x000000004fecc34e, $r27=0x000000004fecc34e +bstrpick.d $r14, $r5, 52, 40 :: +before: $r14=0x65f05eaa5e13856a, $r5=0xd52c72fbeccc39f5 +after: $r14=0x0000000000000c72, $r5=0xd52c72fbeccc39f5 +bstrpick.d $r13, $r20, 48, 14 :: +before: $r13=0x9cea777df4d2eae0, $r20=0x6326727a36499800 +after: $r13=0x00000001c9e8d926, $r20=0x6326727a36499800 +bstrpick.d $r10, $r17, 43, 20 :: +before: $r10=0xf30a073a4a56604b, $r17=0x0c12d112f6a0c8f1 +after: $r10=0x0000000000112f6a, $r17=0x0c12d112f6a0c8f1 +bstrpick.d $r13, $r25, 55, 37 :: +before: $r13=0xe559d975e0d9ac85, $r25=0xcf41f30cc4a46713 +after: $r13=0x0000000000020f98, $r25=0xcf41f30cc4a46713 +bstrpick.d $r29, $r4, 34, 20 :: +before: $r29=0x41843db6c2a206cb, $r4=0x343f795d45fcff8c +after: $r29=0x000000000000545f, $r4=0x343f795d45fcff8c +bstrpick.d $r27, $r28, 27, 10 :: +before: $r27=0xb359821297377fee, $r28=0x4fc51c5773e64f69 +after: $r27=0x000000000000f993, $r28=0x4fc51c5773e64f69 +bstrpick.d $r24, $r24, 63, 20 :: +before: $r24=0xed3cb5d1e8f0e55e, $r24=0x9cdbb70a8b8d3945 +after: $r24=0x000009cdbb70a8b8, $r24=0x000009cdbb70a8b8 +bstrpick.d $r7, $r30, 34, 30 :: +before: $r7=0x11b7344343be1ccf, $r30=0xa3422c671803480f +after: $r7=0x000000000000001c, $r30=0xa3422c671803480f +bstrpick.d $r15, $r4, 55, 4 :: +before: $r15=0x3670c6b869f28085, $r4=0x2caa9d9c1351e402 +after: $r15=0x000aa9d9c1351e40, $r4=0x2caa9d9c1351e402 +crc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +after: $r12=0xfffffffff8cd11f5, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +crc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +after: $r12=0xfffffffff896edce, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +crc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +after: $r12=0xffffffffef4aad58, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +crc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +after: $r12=0xffffffffa0b9747b, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +crc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +after: $r12=0xffffffff96afcb8f, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +crc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +after: $r12=0x000000005b57dc92, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +crc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +after: $r12=0xffffffff8fa18d00, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +crc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +after: $r12=0xffffffff862b1fc5, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +crc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +after: $r12=0xffffffff9a47255b, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +crc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +after: $r12=0xffffffffa7886ccc, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +crc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +after: $r12=0xffffffffb6c69449, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +crc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +after: $r12=0xffffffffb04637e9, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +crc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +after: $r12=0xfffffffffb8f1bb9, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +crc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +after: $r12=0xffffffffc7580939, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +crc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +after: $r12=0xffffffffb24959b6, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +crc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +after: $r12=0x00000000532cb693, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +crc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +after: $r12=0xffffffffffe2757b, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +crc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +after: $r12=0xffffffffc3c8592d, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +crc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +after: $r12=0xffffffffe44ccdd5, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +crc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +after: $r12=0x0000000004826ea7, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +crc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +after: $r12=0x00000000784b67ea, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +crc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +after: $r12=0xffffffffbaef431f, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +crc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +after: $r12=0xffffffffe7361109, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +crc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +after: $r12=0xfffffffff9af6423, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +crc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +after: $r12=0x000000006d4f1805, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +crc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +after: $r12=0xffffffffb22e077e, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +crc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +after: $r12=0xffffffff8cb8356f, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +crc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +after: $r12=0xffffffffbe1261f9, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +crcc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +after: $r12=0x000000006c5412e4, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +crcc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +after: $r12=0x000000006c0feedf, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +crcc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +after: $r12=0x0000000052b4533a, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +crcc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +after: $r12=0xffffffffe3833e19, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +crcc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +after: $r12=0x000000002a3f5685, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +crcc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +after: $r12=0xffffffffec8f3c62, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +crcc.w.b.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +after: $r12=0xffffffff9e543d84, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +crcc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +after: $r12=0x00000000318af1d5, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +crcc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +after: $r12=0xffffffff92c4f3f9, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +crcc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +after: $r12=0xffffffffa40568c3, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +crcc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +after: $r12=0xffffffffeeee153e, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +crcc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +after: $r12=0x0000000071b26b5b, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +crcc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +after: $r12=0xfffffffffcb406be, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +crcc.w.h.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +after: $r12=0xffffffffade3076c, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +crcc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +after: $r12=0x000000004f6e8750, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +crcc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +after: $r12=0x000000004548949c, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +crcc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +after: $r12=0x0000000050fc77a7, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +crcc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +after: $r12=0x000000000b0f3746, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +crcc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +after: $r12=0xffffffff92a3acf2, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +crcc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +after: $r12=0xffffffffd91fb7ba, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +crcc.w.w.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +after: $r12=0x000000006b548718, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +crcc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +after: $r12=0xffffffff8547ffea, $r13=0x4b154113f7d32514, $r14=0xcce230caafbf9cc9 +crcc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +after: $r12=0x000000001a265977, $r13=0x33d5d595721d4f13, $r14=0xf4509311f443a7ce +crcc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +after: $r12=0x000000000e1737b7, $r13=0x4a3c6de6954cbc17, $r14=0x111b21e39fbd7254 +crcc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +after: $r12=0x000000007c13f4c5, $r13=0xfbb5c64ed1b044c6, $r14=0x33ca4c4fb3960326 +crcc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +after: $r12=0xffffffff9d9455e3, $r13=0x2b7c5939d7c0f528, $r14=0xb73870a5a6630162 +crcc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +after: $r12=0x000000006df1745f, $r13=0x02fe41918ac5cdba, $r14=0x48e0815289728f05 +crcc.w.d.w $r12, $r13, $r14 :: +before: $r12=0x0123456789abcdef, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 +after: $r12=0xffffffffb7862239, $r13=0xb60a8f381f187bae, $r14=0x008c208cc413ff72 diff --git a/none/tests/loongarch64/integer.vgtest b/none/tests/loongarch64/integer.vgtest new file mode 100644 index 0000000..daa0591 --- /dev/null +++ b/none/tests/loongarch64/integer.vgtest @@ -0,0 +1,2 @@ +prog: integer +vgopts: -q diff --git a/none/tests/loongarch64/llsc.c b/none/tests/loongarch64/llsc.c new file mode 100644 index 0000000..fcb7e3c --- /dev/null +++ b/none/tests/loongarch64/llsc.c @@ -0,0 +1,69 @@ +#include + +#define TESTINST_LLSC_W(insn, res, addr, offs) \ + { \ + __asm__ __volatile__( \ + "move $t1, %1 \n\t" \ + "ll.w $t0, $t1, %2 \n\t" \ + insn " \n\t" \ + "sc.w $t0, $t1, %2 \n\t" \ + "move %0, $t0 \n\t" \ + : "=r" (res) \ + : "r" (addr), "i" (offs) \ + : "$t0", "$t1", "memory"); \ + } + +#define TESTINST_LLSC_D(insn, res, addr, offs) \ + { \ + __asm__ __volatile__( \ + "move $t1, %1 \n\t" \ + "ll.d $t0, $t1, %2 \n\t" \ + insn " \n\t" \ + "sc.d $t0, $t1, %2 \n\t" \ + "move %0, $t0 \n\t" \ + : "=r" (res) \ + : "r" (addr), "i" (offs) \ + : "$t0", "$t1", "memory"); \ + } + +void test(void) +{ + int res_i; + long res_l; + int val_i[2] = { 6, 10 }; + long val_l[2] = { 6, 10 }; + + /* ---------------- ll.w rd, rj, si14 ---------------- */ + /* ---------------- sc.w rd, rj, si14 ---------------- */ + printf("ll.w sc.w ::\n"); + + do { + TESTINST_LLSC_W("addi.w $t0, $t0, 1", res_i, val_i, 0); + } while (res_i != 1); + printf("res: %d val: %d\n", res_i, val_i[0]); + + do { + TESTINST_LLSC_W("sub.w $t0, $zero, $t0", res_i, val_i, 4); + } while (res_i != 1); + printf("res: %d val: %d\n", res_i, val_i[1]); + + /* ---------------- ll.d rd, rj, si14 ---------------- */ + /* ---------------- sc.d rd, rj, si14 ---------------- */ + printf("ll.d sc.d ::\n"); + + do { + TESTINST_LLSC_D("addi.d $t0, $t0, 1", res_l, val_l, 0); + } while (res_l != 1); + printf("res: %ld val: %ld\n", res_l, val_l[0]); + + do { + TESTINST_LLSC_D("sub.d $t0, $zero, $t0", res_l, val_l, 8); + } while (res_l != 1); + printf("res: %ld val: %ld\n", res_l, val_l[1]); +} + +int main(void) +{ + test(); + return 0; +} diff --git a/none/tests/loongarch64/llsc.stderr.exp b/none/tests/loongarch64/llsc.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/llsc.stdout.exp b/none/tests/loongarch64/llsc.stdout.exp new file mode 100644 index 0000000..dd19251 --- /dev/null +++ b/none/tests/loongarch64/llsc.stdout.exp @@ -0,0 +1,6 @@ +ll.w sc.w :: +res: 1 val: 7 +res: 1 val: -10 +ll.d sc.d :: +res: 1 val: 7 +res: 1 val: -10 diff --git a/none/tests/loongarch64/llsc.vgtest b/none/tests/loongarch64/llsc.vgtest new file mode 100644 index 0000000..685c279 --- /dev/null +++ b/none/tests/loongarch64/llsc.vgtest @@ -0,0 +1,2 @@ +prog: llsc +vgopts: -q diff --git a/none/tests/loongarch64/memory.c b/none/tests/loongarch64/memory.c new file mode 100644 index 0000000..385efc0 --- /dev/null +++ b/none/tests/loongarch64/memory.c @@ -0,0 +1,345 @@ +#include + +#define NUM 24 + +unsigned long mem[NUM] = { + 0x121f1e1f0000e680, 0x0000000000010700, 0x000000030000e7dc, + 0xffffffff0000b0d0, 0x232f2e2f2ab05fd0, 0x242c2b2b0000b6a0, + 0x252a2e2b0000be80, 0x262d2d2a0000de10, 0x3f343f3e0000df20, + 0x3e353d3c2ab05fe0, 0x363a3c3b0000dfd0, 0x3b373b3a00010300, + 0x0000e680121f1e1f, 0x0001070000000000, 0x0000e7dc00000003, + 0x0000b0d0ffffffff, 0x2ab05fd0232f2e2f, 0x0000b6a0242c2b2b, + 0x0000be80252a2e2b, 0x0000de10262d2d2a, 0x0000df203f343f3e, + 0x2ab05fe03e353d3c, 0x0000dfd0363a3c3b, 0x000103003b373b3a +}; + +#define TESTINST_LOAD_RRI(insn, val, addr, offs) \ + { \ + __asm__ __volatile__( \ + insn " %0, %1, " #offs " \n\t" \ + : "=r" (val) \ + : "r" (addr) \ + : "memory"); \ + } + +#define TESTINST_LOAD_RRR(insn, val, addr, offs) \ + { \ + __asm__ __volatile__( \ + insn " %0, %1, %2 \n\t" \ + : "=r" (val) \ + : "r" (addr), "r" (offs) \ + : "memory"); \ + } + +#define TESTINST_LOAD_FRI(insn, val, addr, offs) \ + { \ + __asm__ __volatile__( \ + insn " %0, %1, " #offs " \n\t" \ + : "=f" (val) \ + : "r" (addr) \ + : "memory"); \ + } + +#define TESTINST_LOAD_FRR(insn, val, addr, offs) \ + { \ + __asm__ __volatile__( \ + insn " %0, %1, %2 \n\t" \ + : "=f" (val) \ + : "r" (addr), "r" (offs) \ + : "memory"); \ + } + +#define TESTINST_STORE_RRI(insn, val, addr, offs) \ + { \ + __asm__ __volatile__( \ + insn " %0, %1, " #offs " \n\t" \ + : \ + : "r" (val), "r" (addr) \ + : "memory"); \ + } + +#define TESTINST_STORE_RRR(insn, val, addr, offs) \ + { \ + __asm__ __volatile__( \ + insn " %0, %1, %2 \n\t" \ + : \ + : "r" (val), "r" (addr), "r" (offs) \ + : "memory"); \ + } + +#define TESTINST_STORE_FRI(insn, val, addr, offs) \ + { \ + __asm__ __volatile__( \ + insn " %0, %1, " #offs " \n\t" \ + : \ + : "f" (val), "r" (addr) \ + : "memory"); \ + } + +#define TESTINST_STORE_FRR(insn, val, addr, offs) \ + { \ + __asm__ __volatile__( \ + insn " %0, %1, %2 \n\t" \ + : \ + : "f" (val), "r" (addr), "r" (offs) \ + : "memory"); \ + } + +static inline void show(void) +{ + int i; + printf("memory block:\n"); + for (i = 0; i < NUM; i++) + printf("0x%lx:\t%#018lx\n", i * sizeof(unsigned long), mem[i]); +} + +void test(void) +{ + char s8; + unsigned char u8; + short s16; + unsigned short u16; + int s32; + unsigned int u32; + long s64; + unsigned long u64; + + show(); + + /* ---------------- ld.b rd, rj, si12 ---------------- */ + printf("test ld.b: "); + TESTINST_LOAD_RRI("ld.b", s8, mem, 0); + printf("%d ", (int)s8); + TESTINST_LOAD_RRI("ld.b", s8, mem, 24); + printf("%d\n", (int)s8); + + /* ---------------- ld.bu rd, rj, si12 ---------------- */ + printf("test ld.bu: "); + TESTINST_LOAD_RRI("ld.b", u8, mem, 0); + printf("%u ", (unsigned)s8); + TESTINST_LOAD_RRI("ld.b", u8, mem, 24); + printf("%u\n", (unsigned)s8); + + /* ---------------- ld.h rd, rj, si12 ---------------- */ + printf("test ld.h: "); + TESTINST_LOAD_RRI("ld.h", s16, mem, 0); + printf("%hd ", s16); + TESTINST_LOAD_RRI("ld.h", s16, mem, 24); + printf("%hd\n", s16); + + /* ---------------- ld.hu rd, rj, si12 ---------------- */ + printf("test ld.hu: "); + TESTINST_LOAD_RRI("ld.hu", u16, mem, 0); + printf("%hu ", u16); + TESTINST_LOAD_RRI("ld.hu", u16, mem, 24); + printf("%hu\n", u16); + + /* ---------------- ld.w rd, rj, si12 ---------------- */ + printf("test ld.w: "); + TESTINST_LOAD_RRI("ld.w", s32, mem, 0); + printf("%d ", s32); + TESTINST_LOAD_RRI("ld.w", s32, mem, 24); + printf("%d\n", s32); + + /* ---------------- ld.wu rd, rj, si12 ---------------- */ + printf("test ld.wu: "); + TESTINST_LOAD_RRI("ld.wu", u32, mem, 0); + printf("%u ", u32); + TESTINST_LOAD_RRI("ld.wu", u32, mem, 24); + printf("%u\n", u32); + + /* ---------------- ld.d rd, rj, si12 ---------------- */ + printf("test ld.d: "); + TESTINST_LOAD_RRI("ld.d", s64, mem, 0); + printf("%ld ", s64); + TESTINST_LOAD_RRI("ld.d", s64, mem, 24); + printf("%ld ", s64); + TESTINST_LOAD_RRI("ld.d", u64, mem, 0); + printf("%lu ", u64); + TESTINST_LOAD_RRI("ld.d", u64, mem, 24); + printf("%lu\n", u64); + + /* ---------------- ldx.b rd, rj, rk ---------------- */ + printf("test ldx.b: "); + TESTINST_LOAD_RRR("ldx.b", s8, mem, 0); + printf("%d ", (int)s8); + TESTINST_LOAD_RRR("ldx.b", s8, mem, 24); + printf("%d\n", (int)s8); + + /* ---------------- ldx.bu rd, rj, rk ---------------- */ + printf("test ldx.bu: "); + TESTINST_LOAD_RRR("ldx.b", u8, mem, 0); + printf("%u ", (unsigned)s8); + TESTINST_LOAD_RRR("ldx.b", u8, mem, 24); + printf("%u\n", (unsigned)s8); + + /* ---------------- ldx.h rd, rj, rk ---------------- */ + printf("test ldx.h: "); + TESTINST_LOAD_RRR("ldx.h", s16, mem, 0); + printf("%hd ", s16); + TESTINST_LOAD_RRR("ldx.h", s16, mem, 24); + printf("%hd\n", s16); + + /* ---------------- ldx.hu rd, rj, rk ---------------- */ + printf("test ld.hu: "); + TESTINST_LOAD_RRR("ldx.hu", u16, mem, 0); + printf("%hu ", u16); + TESTINST_LOAD_RRR("ldx.hu", u16, mem, 24); + printf("%hu\n", u16); + + /* ---------------- ldx.w rd, rj, rk ---------------- */ + printf("test ldx.w: "); + TESTINST_LOAD_RRR("ldx.w", s32, mem, 0); + printf("%d ", s32); + TESTINST_LOAD_RRR("ldx.w", s32, mem, 24); + printf("%d\n", s32); + + /* ---------------- ldx.wu rd, rj, rk ---------------- */ + printf("test ldx.wu: "); + TESTINST_LOAD_RRR("ldx.wu", u32, mem, 0); + printf("%u ", u32); + TESTINST_LOAD_RRR("ldx.wu", u32, mem, 24); + printf("%u\n", u32); + + /* ---------------- ldx.d rd, rj, rk ---------------- */ + printf("test ldx.d: "); + TESTINST_LOAD_RRR("ldx.d", s64, mem, 0); + printf("%ld ", s64); + TESTINST_LOAD_RRR("ldx.d", s64, mem, 24); + printf("%ld ", s64); + TESTINST_LOAD_RRR("ldx.d", u64, mem, 0); + printf("%lu ", u64); + TESTINST_LOAD_RRR("ldx.d", u64, mem, 24); + printf("%lu\n", u64); + + /* ---------------- ldptr.w rd, rj, si14 ---------------- */ + printf("test ldptr.w: "); + TESTINST_LOAD_RRI("ldptr.w", s32, mem, 0); + printf("%d ", s32); + TESTINST_LOAD_RRI("ldptr.w", s32, mem, 24); + printf("%d\n", s32); + + /* ---------------- ldptr.d rd, rj, si14 ---------------- */ + printf("test ldptr.d: "); + TESTINST_LOAD_RRI("ldptr.d", s64, mem, 0); + printf("%ld ", s64); + TESTINST_LOAD_RRI("ldptr.d", s64, mem, 24); + printf("%ld\n", s64); + + /* ---------------- fld.s fd, rj, si12 ---------------- */ + printf("test fld.s: "); + TESTINST_LOAD_FRI("fld.s", u32, mem, 0); + printf("%#x ", u32); + TESTINST_LOAD_FRI("fld.s", u32, mem, 24); + printf("%#x\n", u32); + + /* ---------------- fld.d fd, rj, si12 ---------------- */ + printf("test fld.d: "); + TESTINST_LOAD_FRI("fld.d", u64, mem, 0); + printf("%#lx ", u64); + TESTINST_LOAD_FRI("fld.d", u64, mem, 24); + printf("%#lx\n", u64); + + /* ---------------- fldx.s fd, rj, rk ---------------- */ + printf("test fldx.s: "); + TESTINST_LOAD_FRR("fldx.s", u32, mem, 0); + printf("%#x ", u32); + TESTINST_LOAD_FRR("fldx.s", u32, mem, 24); + printf("%#x\n", u32); + + /* ---------------- fldx.d fd, rj, rk ---------------- */ + printf("test fldx.d: "); + TESTINST_LOAD_FRR("fldx.d", u64, mem, 0); + printf("%#lx ", u64); + TESTINST_LOAD_FRR("fldx.d", u64, mem, 24); + printf("%#lx\n", u64); + + show(); + + u8 = 0xfe; + s8 = (char)u8; + u16 = 0xfedc; + s16 = (short)u16; + u32 = 0xfedcba98; + s32 = (int)u32; + u64 = 0xfedcba9876543210; + s64 = (long)u64; + + /* ---------------- st.b rd, rj, si12 ---------------- */ + printf("test st.b\n"); + TESTINST_STORE_RRI("st.b", s8, mem, 0); + TESTINST_STORE_RRI("st.b", u8, mem, 1); + + /* ---------------- st.h rd, rj, si12 ---------------- */ + printf("test st.h\n"); + TESTINST_STORE_RRI("st.h", s16, mem, 2); + TESTINST_STORE_RRI("st.h", u16, mem, 4); + + /* ---------------- st.w rd, rj, si12 ---------------- */ + printf("test st.w\n"); + TESTINST_STORE_RRI("st.w", s32, mem, 8); + TESTINST_STORE_RRI("st.w", u32, mem, 12); + + /* ---------------- st.d rd, rj, si12 ---------------- */ + printf("test st.d\n"); + TESTINST_STORE_RRI("st.d", s64, mem, 16); + TESTINST_STORE_RRI("st.d", u64, mem, 24); + + /* ---------------- stx.b rd, rj, rk ---------------- */ + printf("test stx.b\n"); + TESTINST_STORE_RRR("stx.b", s8, mem, 32); + TESTINST_STORE_RRR("stx.b", u8, mem, 33); + + /* ---------------- stx.h rd, rj, rk ---------------- */ + printf("test stx.h\n"); + TESTINST_STORE_RRR("stx.h", s16, mem, 34); + TESTINST_STORE_RRR("stx.h", u16, mem, 36); + + /* ---------------- stx.w rd, rj, rk ---------------- */ + printf("test stx.w\n"); + TESTINST_STORE_RRR("stx.w", s32, mem, 40); + TESTINST_STORE_RRR("stx.w", u32, mem, 44); + + /* ---------------- stx.d rd, rj, rk ---------------- */ + printf("test stx.d\n"); + TESTINST_STORE_RRR("stx.d", s64, mem, 48); + TESTINST_STORE_RRR("stx.d", u64, mem, 56); + + /* ---------------- stptr.w rd, rj, si14 ---------------- */ + printf("test stptr.w\n"); + TESTINST_STORE_RRI("stptr.w", s64, mem, 64); + TESTINST_STORE_RRI("stptr.w", u64, mem, 68); + + /* ---------------- stptr.d rd, rj, si14 ---------------- */ + printf("test stptr.d\n"); + TESTINST_STORE_RRI("stptr.d", s64, mem, 72); + TESTINST_STORE_RRI("stptr.d", u64, mem, 80); + + /* ---------------- fst.s rd, rj, si12 ---------------- */ + printf("test fst.w\n"); + TESTINST_STORE_FRI("fst.s", u32, mem, 84); + TESTINST_STORE_FRI("fst.s", u32, mem, 88); + + /* ---------------- fst.d rd, rj, si12 ---------------- */ + printf("test fst.d\n"); + TESTINST_STORE_FRI("fst.d", u64, mem, 96); + TESTINST_STORE_FRI("fst.d", u64, mem, 104); + + /* ---------------- fstx.s rd, rj, rk ---------------- */ + printf("test fstx.w\n"); + TESTINST_STORE_FRR("fstx.s", u32, mem, 108); + TESTINST_STORE_FRR("fstx.s", u32, mem, 112); + + /* ---------------- fstx.d rd, rj, rk ---------------- */ + printf("test fstx.d\n"); + TESTINST_STORE_FRR("fstx.d", u64, mem, 120); + TESTINST_STORE_FRR("fstx.d", u64, mem, 128); + + show(); +} + +int main(void) +{ + test(); + return 0; +} diff --git a/none/tests/loongarch64/memory.stderr.exp b/none/tests/loongarch64/memory.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/memory.stdout.exp b/none/tests/loongarch64/memory.stdout.exp new file mode 100644 index 0000000..928961d --- /dev/null +++ b/none/tests/loongarch64/memory.stdout.exp @@ -0,0 +1,109 @@ +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x0000000000010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0x232f2e2f2ab05fd0 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test ld.b: -128 -48 +test ld.bu: 4294967248 4294967248 +test ld.h: -6528 -20272 +test ld.hu: 59008 45264 +test ld.w: 59008 45264 +test ld.wu: 59008 45264 +test ld.d: 1305795535453611648 -4294922032 1305795535453611648 18446744069414629584 +test ldx.b: -128 -48 +test ldx.bu: 4294967248 4294967248 +test ldx.h: -6528 -20272 +test ld.hu: 59008 45264 +test ldx.w: 59008 45264 +test ldx.wu: 59008 45264 +test ldx.d: 1305795535453611648 -4294922032 1305795535453611648 18446744069414629584 +test ldptr.w: 59008 45264 +test ldptr.d: 1305795535453611648 -4294922032 +test fld.s: 0xe680 0xb0d0 +test fld.d: 0x121f1e1f0000e680 0xffffffff0000b0d0 +test fldx.s: 0xe680 0xb0d0 +test fldx.d: 0x121f1e1f0000e680 0xffffffff0000b0d0 +memory block: +0x0: 0x121f1e1f0000e680 +0x8: 0x0000000000010700 +0x10: 0x000000030000e7dc +0x18: 0xffffffff0000b0d0 +0x20: 0x232f2e2f2ab05fd0 +0x28: 0x242c2b2b0000b6a0 +0x30: 0x252a2e2b0000be80 +0x38: 0x262d2d2a0000de10 +0x40: 0x3f343f3e0000df20 +0x48: 0x3e353d3c2ab05fe0 +0x50: 0x363a3c3b0000dfd0 +0x58: 0x3b373b3a00010300 +0x60: 0x0000e680121f1e1f +0x68: 0x0001070000000000 +0x70: 0x0000e7dc00000003 +0x78: 0x0000b0d0ffffffff +0x80: 0x2ab05fd0232f2e2f +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a +test st.b +test st.h +test st.w +test st.d +test stx.b +test stx.h +test stx.w +test stx.d +test stptr.w +test stptr.d +test fst.w +test fst.d +test fstx.w +test fstx.d +memory block: +0x0: 0x121ffedcfedcfefe +0x8: 0xfedcba98fedcba98 +0x10: 0xfedcba9876543210 +0x18: 0xfedcba9876543210 +0x20: 0x232ffedcfedcfefe +0x28: 0xfedcba98fedcba98 +0x30: 0xfedcba9876543210 +0x38: 0xfedcba9876543210 +0x40: 0x7654321076543210 +0x48: 0xfedcba9876543210 +0x50: 0xfedcba9876543210 +0x58: 0x3b373b3afedcba98 +0x60: 0xfedcba9876543210 +0x68: 0xfedcba9876543210 +0x70: 0x0000e7dcfedcba98 +0x78: 0xfedcba9876543210 +0x80: 0xfedcba9876543210 +0x88: 0x0000b6a0242c2b2b +0x90: 0x0000be80252a2e2b +0x98: 0x0000de10262d2d2a +0xa0: 0x0000df203f343f3e +0xa8: 0x2ab05fe03e353d3c +0xb0: 0x0000dfd0363a3c3b +0xb8: 0x000103003b373b3a diff --git a/none/tests/loongarch64/memory.vgtest b/none/tests/loongarch64/memory.vgtest new file mode 100644 index 0000000..be6895e --- /dev/null +++ b/none/tests/loongarch64/memory.vgtest @@ -0,0 +1,2 @@ +prog: memory +vgopts: -q diff --git a/none/tests/loongarch64/move.c b/none/tests/loongarch64/move.c new file mode 100644 index 0000000..3b7f46d --- /dev/null +++ b/none/tests/loongarch64/move.c @@ -0,0 +1,112 @@ +#include + +#define TESTINST_MOV(v1, v2, v3, v4, v5, v6, val) \ + { \ + unsigned long res1 = (unsigned long)v1; \ + unsigned long res2 = (unsigned long)v2; \ + unsigned long res3 = (unsigned long)v3; \ + unsigned long res4 = (unsigned long)v4; \ + unsigned long res5 = (unsigned long)v5; \ + unsigned long res6 = (unsigned long)v6; \ + __asm__ __volatile__( \ + "movgr2fr.w %0, %6 \n\t" \ + "movgr2fr.d %1, %6 \n\t" \ + "movgr2frh.w %2, %6 \n\t" \ + "movfr2gr.s %3, %7 \n\t" \ + "movfrh2gr.s %4, %7 \n\t" \ + "movfr2gr.d %5, %7 \n\t" \ + : "+f" (res1), "+f" (res2), "+f" (res3), \ + "+r" (res4), "+r" (res5), "+r" (res6) \ + : "r" (val), "f" (val) \ + : "memory"); \ + printf("movgr2fr.w ::\n"); \ + printf("input: %#018lx %#018lx\n", v1, val); \ + printf("output: %#018lx\n", res1); \ + printf("movgr2fr.d ::\n"); \ + printf("input: %#018lx %#018lx\n", v2, val); \ + printf("output: %#018lx\n", res2); \ + printf("movgr2frh.w ::\n"); \ + printf("input: %#018lx %#018lx\n", v3, val); \ + printf("output: %#018lx\n", res3); \ + printf("movfr2gr.s ::\n"); \ + printf("input: %#018lx %#018lx\n", v4, val); \ + printf("output: %#018lx\n", res4); \ + printf("movfrh2gr.s ::\n"); \ + printf("input: %#018lx %#018lx\n", v5, val); \ + printf("output: %#018lx\n", res5); \ + printf("movfr2gr.d ::\n"); \ + printf("input: %#018lx %#018lx\n", v6, val); \ + printf("output: %#018lx\n", res6); \ + } + +#define TESTINST_FSCR(fcsr, val) \ + { \ + unsigned long res; \ + __asm__ __volatile__( \ + "movgr2fcsr " fcsr ", %1 \n\t" \ + "movfcsr2gr %0, " fcsr " \n\t" \ + : "=r" (res) \ + : "r" (val) \ + : "memory"); \ + printf("movgr2fcsr movfcsr2gr ::\n"); \ + printf("input: %#018lx\n", val); \ + printf("output: %#018lx\n", res); \ + } + +#define TESTINST_CF(fcc, v1, v2, val) \ + { \ + unsigned long res1 = (unsigned long)v1; \ + unsigned long res2 = (unsigned long)v2; \ + __asm__ __volatile__( \ + "movfr2cf " fcc ", %2 \n\t" \ + "movcf2fr %0, " fcc " \n\t" \ + "movgr2cf " fcc ", %3 \n\t" \ + "movcf2gr %1, " fcc " \n\t" \ + : "+f" (res1), "+r" (res2) \ + : "f" (val), "r" (val) \ + : "memory"); \ + printf("movfr2cf movcf2fr ::\n"); \ + printf("input: %#018lx %#018lx\n", v1, val); \ + printf("output: %lx\n", res1); \ + printf("movgr2cf movcf2gr ::\n"); \ + printf("input: %#018lx %#018lx\n", v2, val); \ + printf("output: %lx\n", res2); \ + } + +void test(void) +{ + TESTINST_MOV(0x1234123412341234UL, 0x5678567856785678UL, 0x9abc9abc9abc9abcUL, 0xdef0def0def0def0UL, 0x2468246824682468UL, 0x3579357935793579UL, 0x0123456789abcdefUL); + TESTINST_MOV(0x1234123412341234UL, 0x5678567856785678UL, 0x9abc9abc9abc9abcUL, 0xdef0def0def0def0UL, 0x2468246824682468UL, 0x3579357935793579UL, 0xfedcba9876543210UL); + + TESTINST_FSCR("$r0", 0x0123456789abcdefUL); + TESTINST_FSCR("$r0", 0xfedcba9876543210UL); + TESTINST_FSCR("$r1", 0x0123456789abcdefUL); + TESTINST_FSCR("$r1", 0xfedcba9876543210UL); + TESTINST_FSCR("$r2", 0x0123456789abcdefUL); + TESTINST_FSCR("$r2", 0xfedcba9876543210UL); + TESTINST_FSCR("$r3", 0x0123456789abcdefUL); + TESTINST_FSCR("$r3", 0xfedcba9876543210UL); + + TESTINST_CF("$fcc0", 0x1234123412341234UL, 0x5678567856785678UL, 0xffffffffffffffffUL); + TESTINST_CF("$fcc0", 0x1234123412341234UL, 0x5678567856785678UL, 0xdef0def0def0def0UL); + TESTINST_CF("$fcc1", 0x1234123412341234UL, 0x5678567856785678UL, 0xffffffffffffffffUL); + TESTINST_CF("$fcc1", 0x1234123412341234UL, 0x5678567856785678UL, 0xdef0def0def0def0UL); + TESTINST_CF("$fcc2", 0x1234123412341234UL, 0x5678567856785678UL, 0xffffffffffffffffUL); + TESTINST_CF("$fcc2", 0x1234123412341234UL, 0x5678567856785678UL, 0xdef0def0def0def0UL); + TESTINST_CF("$fcc3", 0x1234123412341234UL, 0x5678567856785678UL, 0xffffffffffffffffUL); + TESTINST_CF("$fcc3", 0x1234123412341234UL, 0x5678567856785678UL, 0xdef0def0def0def0UL); + TESTINST_CF("$fcc4", 0x1234123412341234UL, 0x5678567856785678UL, 0xffffffffffffffffUL); + TESTINST_CF("$fcc4", 0x1234123412341234UL, 0x5678567856785678UL, 0xdef0def0def0def0UL); + TESTINST_CF("$fcc5", 0x1234123412341234UL, 0x5678567856785678UL, 0xffffffffffffffffUL); + TESTINST_CF("$fcc5", 0x1234123412341234UL, 0x5678567856785678UL, 0xdef0def0def0def0UL); + TESTINST_CF("$fcc6", 0x1234123412341234UL, 0x5678567856785678UL, 0xffffffffffffffffUL); + TESTINST_CF("$fcc6", 0x1234123412341234UL, 0x5678567856785678UL, 0xdef0def0def0def0UL); + TESTINST_CF("$fcc7", 0x1234123412341234UL, 0x5678567856785678UL, 0xffffffffffffffffUL); + TESTINST_CF("$fcc7", 0x1234123412341234UL, 0x5678567856785678UL, 0xdef0def0def0def0UL); +} + +int main(void) +{ + test(); + return 0; +} diff --git a/none/tests/loongarch64/move.stderr.exp b/none/tests/loongarch64/move.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/move.stdout.exp b/none/tests/loongarch64/move.stdout.exp new file mode 100644 index 0000000..12baf38 --- /dev/null +++ b/none/tests/loongarch64/move.stdout.exp @@ -0,0 +1,156 @@ +movgr2fr.w :: +input: 0x1234123412341234 0x0123456789abcdef +output: 0x0123456789abcdef +movgr2fr.d :: +input: 0x5678567856785678 0x0123456789abcdef +output: 0x0123456789abcdef +movgr2frh.w :: +input: 0x9abc9abc9abc9abc 0x0123456789abcdef +output: 0x89abcdef9abc9abc +movfr2gr.s :: +input: 0xdef0def0def0def0 0x0123456789abcdef +output: 0xffffffff89abcdef +movfrh2gr.s :: +input: 0x2468246824682468 0x0123456789abcdef +output: 0x0000000001234567 +movfr2gr.d :: +input: 0x3579357935793579 0x0123456789abcdef +output: 0x0123456789abcdef +movgr2fr.w :: +input: 0x1234123412341234 0xfedcba9876543210 +output: 0xfedcba9876543210 +movgr2fr.d :: +input: 0x5678567856785678 0xfedcba9876543210 +output: 0xfedcba9876543210 +movgr2frh.w :: +input: 0x9abc9abc9abc9abc 0xfedcba9876543210 +output: 0x765432109abc9abc +movfr2gr.s :: +input: 0xdef0def0def0def0 0xfedcba9876543210 +output: 0x0000000076543210 +movfrh2gr.s :: +input: 0x2468246824682468 0xfedcba9876543210 +output: 0xfffffffffedcba98 +movfr2gr.d :: +input: 0x3579357935793579 0xfedcba9876543210 +output: 0xfedcba9876543210 +movgr2fcsr movfcsr2gr :: +input: 0x0123456789abcdef +output: 0x00000000090b01cf +movgr2fcsr movfcsr2gr :: +input: 0xfedcba9876543210 +output: 0x0000000016140210 +movgr2fcsr movfcsr2gr :: +input: 0x0123456789abcdef +output: 0x000000000000008f +movgr2fcsr movfcsr2gr :: +input: 0xfedcba9876543210 +output: 0x0000000000000010 +movgr2fcsr movfcsr2gr :: +input: 0x0123456789abcdef +output: 0x00000000090b0000 +movgr2fcsr movfcsr2gr :: +input: 0xfedcba9876543210 +output: 0x0000000016140000 +movgr2fcsr movfcsr2gr :: +input: 0x0123456789abcdef +output: 0x0000000000000100 +movgr2fcsr movfcsr2gr :: +input: 0xfedcba9876543210 +output: 0x0000000000000200 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xffffffffffffffff +output: 1 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xffffffffffffffff +output: 1 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xdef0def0def0def0 +output: 0 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xdef0def0def0def0 +output: 0 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xffffffffffffffff +output: 1 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xffffffffffffffff +output: 1 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xdef0def0def0def0 +output: 0 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xdef0def0def0def0 +output: 0 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xffffffffffffffff +output: 1 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xffffffffffffffff +output: 1 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xdef0def0def0def0 +output: 0 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xdef0def0def0def0 +output: 0 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xffffffffffffffff +output: 1 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xffffffffffffffff +output: 1 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xdef0def0def0def0 +output: 0 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xdef0def0def0def0 +output: 0 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xffffffffffffffff +output: 1 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xffffffffffffffff +output: 1 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xdef0def0def0def0 +output: 0 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xdef0def0def0def0 +output: 0 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xffffffffffffffff +output: 1 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xffffffffffffffff +output: 1 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xdef0def0def0def0 +output: 0 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xdef0def0def0def0 +output: 0 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xffffffffffffffff +output: 1 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xffffffffffffffff +output: 1 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xdef0def0def0def0 +output: 0 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xdef0def0def0def0 +output: 0 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xffffffffffffffff +output: 1 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xffffffffffffffff +output: 1 +movfr2cf movcf2fr :: +input: 0x1234123412341234 0xdef0def0def0def0 +output: 0 +movgr2cf movcf2gr :: +input: 0x5678567856785678 0xdef0def0def0def0 +output: 0 diff --git a/none/tests/loongarch64/move.vgtest b/none/tests/loongarch64/move.vgtest new file mode 100644 index 0000000..358d44b --- /dev/null +++ b/none/tests/loongarch64/move.vgtest @@ -0,0 +1,3 @@ +prereq: ../../../tests/loongarch64_features fpu +prog: move +vgopts: -q diff --git a/none/tests/loongarch64/pc.c b/none/tests/loongarch64/pc.c new file mode 100644 index 0000000..a493846 --- /dev/null +++ b/none/tests/loongarch64/pc.c @@ -0,0 +1,66 @@ +#include +#include + +#define TESTINST_RI(insn, imm, offs, clear) \ + { \ + unsigned long res, exp; \ + __asm__ __volatile__( \ + " la.local $t0, 1f \n\t" \ + " jirl %0, $t0, 0 \n\t" \ + "1: \n\t" \ + insn " %1," #imm " \n\t" \ + : "=r" (exp), "=r" (res) \ + : \ + : "$t0", "memory"); \ + printf("test %s\n", insn); \ + exp += (long)imm << 40 >> (40 - offs); \ + if (clear) \ + exp &= 0xfffffffffffff000UL; \ + if (res != exp) \ + printf("res: %#lx, exp: %#lx\n", res, exp); \ + } + +void test(void) +{ + /* ---------------- pcaddi rd, si20 ---------------- */ + TESTINST_RI("pcaddi", 0, 2, false); + TESTINST_RI("pcaddi", 1, 2, false); + TESTINST_RI("pcaddi", 100, 2, false); + TESTINST_RI("pcaddi", 12345, 2, false); + TESTINST_RI("pcaddi", -12345, 2, false); + TESTINST_RI("pcaddi", 524287, 2, false); + TESTINST_RI("pcaddi", -524288, 2, false); + + /* ---------------- pcaddu12i rd, si20 ---------------- */ + TESTINST_RI("pcaddu12i", 0, 12, false); + TESTINST_RI("pcaddu12i", 1, 12, false); + TESTINST_RI("pcaddu12i", 100, 12, false); + TESTINST_RI("pcaddu12i", 12345, 12, false); + TESTINST_RI("pcaddu12i", -12345, 12, false); + TESTINST_RI("pcaddu12i", 524287, 12, false); + TESTINST_RI("pcaddu12i", -524288, 12, false); + + /* ---------------- pcaddu18i rd, si20 ---------------- */ + TESTINST_RI("pcaddu18i", 0, 18, false); + TESTINST_RI("pcaddu18i", 1, 18, false); + TESTINST_RI("pcaddu18i", 100, 18, false); + TESTINST_RI("pcaddu18i", 12345, 18, false); + TESTINST_RI("pcaddu18i", -12345, 18, false); + TESTINST_RI("pcaddu18i", 524287, 18, false); + TESTINST_RI("pcaddu18i", -524288, 18, false); + + /* ---------------- pcalau12i rd, si20 ---------------- */ + TESTINST_RI("pcalau12i", 0, 12, true); + TESTINST_RI("pcalau12i", 1, 12, true); + TESTINST_RI("pcalau12i", 100, 12, true); + TESTINST_RI("pcalau12i", 12345, 12, true); + TESTINST_RI("pcalau12i", -12345, 12, true); + TESTINST_RI("pcalau12i", 524287, 12, true); + TESTINST_RI("pcalau12i", -524288, 12, true); +} + +int main(void) +{ + test(); + return 0; +} diff --git a/none/tests/loongarch64/pc.stderr.exp b/none/tests/loongarch64/pc.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/pc.stdout.exp b/none/tests/loongarch64/pc.stdout.exp new file mode 100644 index 0000000..422ea40 --- /dev/null +++ b/none/tests/loongarch64/pc.stdout.exp @@ -0,0 +1,28 @@ +test pcaddi +test pcaddi +test pcaddi +test pcaddi +test pcaddi +test pcaddi +test pcaddi +test pcaddu12i +test pcaddu12i +test pcaddu12i +test pcaddu12i +test pcaddu12i +test pcaddu12i +test pcaddu12i +test pcaddu18i +test pcaddu18i +test pcaddu18i +test pcaddu18i +test pcaddu18i +test pcaddu18i +test pcaddu18i +test pcalau12i +test pcalau12i +test pcalau12i +test pcalau12i +test pcalau12i +test pcalau12i +test pcalau12i diff --git a/none/tests/loongarch64/pc.vgtest b/none/tests/loongarch64/pc.vgtest new file mode 100644 index 0000000..468226d --- /dev/null +++ b/none/tests/loongarch64/pc.vgtest @@ -0,0 +1,2 @@ +prog: pc +vgopts: -q diff --git a/none/tests/loongarch64/special.c b/none/tests/loongarch64/special.c new file mode 100644 index 0000000..e1e8c94 --- /dev/null +++ b/none/tests/loongarch64/special.c @@ -0,0 +1,112 @@ +#include + +#define TESTINST_HRI(insn, hint, addr, offs) \ + { \ + __asm__ __volatile__( \ + insn " " #hint ", %0, " #offs " \n\t" \ + : \ + : "r" (addr) \ + : "memory" \ + ); \ + printf("test %s\n", insn); \ + } + +#define TESTINST_HRR(insn, hint, addr, offs) \ + { \ + __asm__ __volatile__( \ + insn " %0, %1, \n\t" \ + : \ + : "r" (addr), "r" (offs) \ + : "memory" \ + ); \ + printf("test %s\n", insn); \ + } + +#define TESTINST_CODE(insn, code) \ + { \ + __asm__ __volatile__( \ + insn " " #code " \n\t" \ + : \ + : \ + : "memory" \ + ); \ + printf("test %s\n", insn); \ + } + +#define TESTINST_RR(insn, id) \ + { \ + unsigned long res = 0; \ + __asm__ __volatile__( \ + insn " %0, %1 \n\t" \ + : "+r" (res) \ + : "r" (id) \ + : "memory" \ + ); \ + printf("test %s\n", insn); \ + printf("res: %ld\n", res); \ + } + +unsigned long mem[8]; + +void test(void) +{ + /* ---------------- preld hint, rj, si12 ---------------- */ + TESTINST_HRI("preld", 0, mem, 0); + TESTINST_HRI("preld", 1, mem, 1); + TESTINST_HRI("preld", 2, mem, 2); + TESTINST_HRI("preld", 3, mem, 3); + TESTINST_HRI("preld", 4, mem, 4); + TESTINST_HRI("preld", 5, mem, 5); + TESTINST_HRI("preld", 6, mem, 6); + TESTINST_HRI("preld", 7, mem, 7); + TESTINST_HRI("preld", 8, mem, 8); + TESTINST_HRI("preld", 9, mem, 9); + + /* ---------------- preldx hint, rj, rk ---------------- */ + TESTINST_HRI("preld", 31, mem, 10); + TESTINST_HRI("preld", 30, mem, 12); + TESTINST_HRI("preld", 29, mem, 14); + TESTINST_HRI("preld", 28, mem, 16); + TESTINST_HRI("preld", 27, mem, 18); + TESTINST_HRI("preld", 26, mem, 20); + TESTINST_HRI("preld", 25, mem, 22); + TESTINST_HRI("preld", 24, mem, 24); + TESTINST_HRI("preld", 23, mem, 26); + TESTINST_HRI("preld", 22, mem, 28); + + /* ---------------- dbar code ---------------- */ + TESTINST_CODE("dbar", 0); + TESTINST_CODE("dbar", 2); + TESTINST_CODE("dbar", 4); + TESTINST_CODE("dbar", 6); + TESTINST_CODE("dbar", 8); + + /* ---------------- ibar code ---------------- */ + TESTINST_CODE("ibar", 9); + TESTINST_CODE("ibar", 7); + TESTINST_CODE("ibar", 5); + TESTINST_CODE("ibar", 3); + TESTINST_CODE("ibar", 1); + + /* ---------------- rdtimel.w rd, rj ---------------- */ + TESTINST_RR("rdtimel.w", 0); + TESTINST_RR("rdtimel.w", 1); + TESTINST_RR("rdtimel.w", 2); + + /* ---------------- rdtimeh.w rd, rj ---------------- */ + TESTINST_RR("rdtimeh.w", 0); + TESTINST_RR("rdtimeh.w", 1); + TESTINST_RR("rdtimeh.w", 2); + + + /* ---------------- rdtime.d rd, rj ---------------- */ + TESTINST_RR("rdtime.d", 0); + TESTINST_RR("rdtime.d", 1); + TESTINST_RR("rdtime.d", 2); +} + +int main(void) +{ + test(); + return 0; +} diff --git a/none/tests/loongarch64/special.stderr.exp b/none/tests/loongarch64/special.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/special.stdout.exp b/none/tests/loongarch64/special.stdout.exp new file mode 100644 index 0000000..7bd523e --- /dev/null +++ b/none/tests/loongarch64/special.stdout.exp @@ -0,0 +1,48 @@ +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test preld +test dbar +test dbar +test dbar +test dbar +test dbar +test ibar +test ibar +test ibar +test ibar +test ibar +test rdtimel.w +res: 0 +test rdtimel.w +res: 0 +test rdtimel.w +res: 0 +test rdtimeh.w +res: 0 +test rdtimeh.w +res: 0 +test rdtimeh.w +res: 0 +test rdtime.d +res: 0 +test rdtime.d +res: 0 +test rdtime.d +res: 0 diff --git a/none/tests/loongarch64/special.vgtest b/none/tests/loongarch64/special.vgtest new file mode 100644 index 0000000..b2f2ae9 --- /dev/null +++ b/none/tests/loongarch64/special.vgtest @@ -0,0 +1,2 @@ +prog: special +vgopts: -q diff --git a/none/tests/loongarch64/vector128.c b/none/tests/loongarch64/vector128.c new file mode 100644 index 0000000..bfa07c2 --- /dev/null +++ b/none/tests/loongarch64/vector128.c @@ -0,0 +1,12 @@ +#include + +void test(void) +{ + // TODO +} + +int main(void) +{ + test(); + return 0; +} diff --git a/none/tests/loongarch64/vector128.stderr.exp b/none/tests/loongarch64/vector128.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/vector128.stdout.exp b/none/tests/loongarch64/vector128.stdout.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/vector128.vgtest b/none/tests/loongarch64/vector128.vgtest new file mode 100644 index 0000000..5bfdc28 --- /dev/null +++ b/none/tests/loongarch64/vector128.vgtest @@ -0,0 +1,3 @@ +prereq: ../../../tests/loongarch64_features lsx +prog: vector128 +vgopts: -q diff --git a/none/tests/loongarch64/vector256.c b/none/tests/loongarch64/vector256.c new file mode 100644 index 0000000..bfa07c2 --- /dev/null +++ b/none/tests/loongarch64/vector256.c @@ -0,0 +1,12 @@ +#include + +void test(void) +{ + // TODO +} + +int main(void) +{ + test(); + return 0; +} diff --git a/none/tests/loongarch64/vector256.stderr.exp b/none/tests/loongarch64/vector256.stderr.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/vector256.stdout.exp b/none/tests/loongarch64/vector256.stdout.exp new file mode 100644 index 0000000..e69de29 diff --git a/none/tests/loongarch64/vector256.vgtest b/none/tests/loongarch64/vector256.vgtest new file mode 100644 index 0000000..2b32ff1 --- /dev/null +++ b/none/tests/loongarch64/vector256.vgtest @@ -0,0 +1,3 @@ +prereq: ../../../tests/loongarch64_features lasx +prog: vector256 +vgopts: -q diff --git a/none/tests/mips32/Makefile.in b/none/tests/mips32/Makefile.in index 6ed6e3a..1bb4622 100644 --- a/none/tests/mips32/Makefile.in +++ b/none/tests/mips32/Makefile.in @@ -742,6 +742,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -789,6 +795,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/mips64/Makefile.in b/none/tests/mips64/Makefile.in index de13b52..e0a325b 100644 --- a/none/tests/mips64/Makefile.in +++ b/none/tests/mips64/Makefile.in @@ -813,6 +813,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -860,6 +866,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/nanomips/Makefile.in b/none/tests/nanomips/Makefile.in index 3bf14c7..7d38dd9 100644 --- a/none/tests/nanomips/Makefile.in +++ b/none/tests/nanomips/Makefile.in @@ -607,6 +607,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -654,6 +660,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/ppc32/Makefile.in b/none/tests/ppc32/Makefile.in index 6e855d4..0c5fc01 100644 --- a/none/tests/ppc32/Makefile.in +++ b/none/tests/ppc32/Makefile.in @@ -742,6 +742,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -789,6 +795,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/ppc64/Makefile.in b/none/tests/ppc64/Makefile.in index e9e4390..43ac01f 100644 --- a/none/tests/ppc64/Makefile.in +++ b/none/tests/ppc64/Makefile.in @@ -845,6 +845,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -892,6 +898,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/s390x/Makefile.in b/none/tests/s390x/Makefile.in index b90cb39..72dce45 100644 --- a/none/tests/s390x/Makefile.in +++ b/none/tests/s390x/Makefile.in @@ -1152,6 +1152,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -1199,6 +1205,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/scripts/Makefile.in b/none/tests/scripts/Makefile.in index e032753..95567b7 100644 --- a/none/tests/scripts/Makefile.in +++ b/none/tests/scripts/Makefile.in @@ -529,6 +529,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -576,6 +582,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/solaris/Makefile.in b/none/tests/solaris/Makefile.in index 46f5282..e1f441e 100644 --- a/none/tests/solaris/Makefile.in +++ b/none/tests/solaris/Makefile.in @@ -673,6 +673,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -720,6 +726,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/x86-darwin/Makefile.in b/none/tests/x86-darwin/Makefile.in index 6b943b3..2bc0b24 100644 --- a/none/tests/x86-darwin/Makefile.in +++ b/none/tests/x86-darwin/Makefile.in @@ -574,6 +574,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -621,6 +627,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/x86-freebsd/Makefile.in b/none/tests/x86-freebsd/Makefile.in index 58e1161..38d9646 100644 --- a/none/tests/x86-freebsd/Makefile.in +++ b/none/tests/x86-freebsd/Makefile.in @@ -566,6 +566,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -613,6 +619,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/x86-linux/Makefile.in b/none/tests/x86-linux/Makefile.in index 0c55ea2..2d79442 100644 --- a/none/tests/x86-linux/Makefile.in +++ b/none/tests/x86-linux/Makefile.in @@ -588,6 +588,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -635,6 +641,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/x86-solaris/Makefile.in b/none/tests/x86-solaris/Makefile.in index a008c19..f4c7fd3 100644 --- a/none/tests/x86-solaris/Makefile.in +++ b/none/tests/x86-solaris/Makefile.in @@ -582,6 +582,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -629,6 +635,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/none/tests/x86/Makefile.in b/none/tests/x86/Makefile.in index ead5ce4..c43ae96 100644 --- a/none/tests/x86/Makefile.in +++ b/none/tests/x86/Makefile.in @@ -813,6 +813,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -860,6 +866,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/perf/Makefile.in b/perf/Makefile.in index aa93d3b..5809ff6 100644 --- a/perf/Makefile.in +++ b/perf/Makefile.in @@ -616,6 +616,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -663,6 +669,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ diff --git a/tests/Makefile.am b/tests/Makefile.am index 916e508..e21f68b 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -52,7 +52,8 @@ check_PROGRAMS = \ power_insn_available \ is_ppc64_BE \ min_power_isa \ - arm64_features + arm64_features \ + loongarch64_features AM_CFLAGS += $(AM_FLAG_M3264_PRI) diff --git a/tests/Makefile.in b/tests/Makefile.in index bf7d5a1..846b98c 100644 --- a/tests/Makefile.in +++ b/tests/Makefile.in @@ -129,7 +129,8 @@ check_PROGRAMS = arch_test$(EXEEXT) os_test$(EXEEXT) \ libc_test$(EXEEXT) true$(EXEEXT) x86_amd64_features$(EXEEXT) \ s390x_features$(EXEEXT) mips_features$(EXEEXT) \ power_insn_available$(EXEEXT) is_ppc64_BE$(EXEEXT) \ - min_power_isa$(EXEEXT) arm64_features$(EXEEXT) + min_power_isa$(EXEEXT) arm64_features$(EXEEXT) \ + loongarch64_features$(EXEEXT) subdir = tests ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac @@ -153,6 +154,9 @@ is_ppc64_BE_LDADD = $(LDADD) libc_test_SOURCES = libc_test.c libc_test_OBJECTS = libc_test.$(OBJEXT) libc_test_LDADD = $(LDADD) +loongarch64_features_SOURCES = loongarch64_features.c +loongarch64_features_OBJECTS = loongarch64_features.$(OBJEXT) +loongarch64_features_LDADD = $(LDADD) min_power_isa_SOURCES = min_power_isa.c min_power_isa_OBJECTS = min_power_isa-min_power_isa.$(OBJEXT) min_power_isa_LDADD = $(LDADD) @@ -197,7 +201,7 @@ depcomp = $(SHELL) $(top_srcdir)/depcomp am__maybe_remake_depfiles = depfiles am__depfiles_remade = ./$(DEPDIR)/arch_test.Po \ ./$(DEPDIR)/arm64_features.Po ./$(DEPDIR)/is_ppc64_BE.Po \ - ./$(DEPDIR)/libc_test.Po \ + ./$(DEPDIR)/libc_test.Po ./$(DEPDIR)/loongarch64_features.Po \ ./$(DEPDIR)/min_power_isa-min_power_isa.Po \ ./$(DEPDIR)/mips_features.Po ./$(DEPDIR)/os_test.Po \ ./$(DEPDIR)/power_insn_available.Po \ @@ -221,12 +225,12 @@ am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@) am__v_CCLD_0 = @echo " CCLD " $@; am__v_CCLD_1 = SOURCES = arch_test.c arm64_features.c is_ppc64_BE.c libc_test.c \ - min_power_isa.c mips_features.c os_test.c \ - power_insn_available.c s390x_features.c true.c \ + loongarch64_features.c min_power_isa.c mips_features.c \ + os_test.c power_insn_available.c s390x_features.c true.c \ x86_amd64_features.c DIST_SOURCES = arch_test.c arm64_features.c is_ppc64_BE.c libc_test.c \ - min_power_isa.c mips_features.c os_test.c \ - power_insn_available.c s390x_features.c true.c \ + loongarch64_features.c min_power_isa.c mips_features.c \ + os_test.c power_insn_available.c s390x_features.c true.c \ x86_amd64_features.c am__can_run_installinfo = \ case $$AM_UPDATE_INFO_DIR in \ @@ -626,6 +630,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ $(AM_CFLAGS_PSO_BASE) AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g +AM_FLAG_M3264_LOONGARCH64_LINUX = @FLAG_M64@ +AM_CFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) +AM_CFLAGS_PSO_LOONGARCH64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + +AM_CCASFLAGS_LOONGARCH64_LINUX = @FLAG_M64@ -g AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ @@ -673,6 +683,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ +PRELOAD_LDFLAGS_LOONGARCH64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ @@ -785,6 +796,10 @@ libc_test$(EXEEXT): $(libc_test_OBJECTS) $(libc_test_DEPENDENCIES) $(EXTRA_libc_ @rm -f libc_test$(EXEEXT) $(AM_V_CCLD)$(LINK) $(libc_test_OBJECTS) $(libc_test_LDADD) $(LIBS) +loongarch64_features$(EXEEXT): $(loongarch64_features_OBJECTS) $(loongarch64_features_DEPENDENCIES) $(EXTRA_loongarch64_features_DEPENDENCIES) + @rm -f loongarch64_features$(EXEEXT) + $(AM_V_CCLD)$(LINK) $(loongarch64_features_OBJECTS) $(loongarch64_features_LDADD) $(LIBS) + min_power_isa$(EXEEXT): $(min_power_isa_OBJECTS) $(min_power_isa_DEPENDENCIES) $(EXTRA_min_power_isa_DEPENDENCIES) @rm -f min_power_isa$(EXEEXT) $(AM_V_CCLD)$(min_power_isa_LINK) $(min_power_isa_OBJECTS) $(min_power_isa_LDADD) $(LIBS) @@ -823,6 +838,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm64_features.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is_ppc64_BE.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libc_test.Po@am__quote@ # am--include-marker +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/loongarch64_features.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/min_power_isa-min_power_isa.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mips_features.Po@am__quote@ # am--include-marker @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/os_test.Po@am__quote@ # am--include-marker @@ -1010,6 +1026,7 @@ distclean: distclean-am -rm -f ./$(DEPDIR)/arm64_features.Po -rm -f ./$(DEPDIR)/is_ppc64_BE.Po -rm -f ./$(DEPDIR)/libc_test.Po + -rm -f ./$(DEPDIR)/loongarch64_features.Po -rm -f ./$(DEPDIR)/min_power_isa-min_power_isa.Po -rm -f ./$(DEPDIR)/mips_features.Po -rm -f ./$(DEPDIR)/os_test.Po @@ -1066,6 +1083,7 @@ maintainer-clean: maintainer-clean-am -rm -f ./$(DEPDIR)/arm64_features.Po -rm -f ./$(DEPDIR)/is_ppc64_BE.Po -rm -f ./$(DEPDIR)/libc_test.Po + -rm -f ./$(DEPDIR)/loongarch64_features.Po -rm -f ./$(DEPDIR)/min_power_isa-min_power_isa.Po -rm -f ./$(DEPDIR)/mips_features.Po -rm -f ./$(DEPDIR)/os_test.Po diff --git a/tests/arch_test.c b/tests/arch_test.c index 37cc1bc..97b6bc7 100644 --- a/tests/arch_test.c +++ b/tests/arch_test.c @@ -34,6 +34,7 @@ char* all_archs[] = { "mips32", "mips64", "nanomips", + "loongarch64", NULL }; @@ -79,6 +80,10 @@ static Bool go(char* arch) #elif defined(VGP_nanomips_linux) if ( 0 == strcmp( arch, "nanomips" ) ) return True; + +#elif defined(VGP_loongarch64_linux) + if ( 0 == strcmp( arch, "loongarch64" ) ) return True; + #else # error Unknown platform #endif // VGP_* diff --git a/tests/loongarch64_features.c b/tests/loongarch64_features.c new file mode 100644 index 0000000..45ba2d1 --- /dev/null +++ b/tests/loongarch64_features.c @@ -0,0 +1,81 @@ +#include +#include +#include + +// This file determines loongarch64 features a processor supports. +// For now, we only support loongarch64-linux. +// +// We return: +// - 0 if the machine has the asked-for feature. +// - 1 if the machine doesn't have the asked-for feature. +// - 2 if the asked-for feature isn't recognised (this will always be the case +// for any feature if run on a non-loongarch64 machine). +// - 3 if there was a usage error (it also prints an error message). +#define FEATURE_PRESENT 0 +#define FEATURE_NOT_PRESENT 1 +#define UNRECOGNISED_FEATURE 2 +#define USAGE_ERROR 3 + +#if defined(VGA_loongarch64) + +static int go(const char* feature_name) +{ + int i, len, found; + FILE* fp; + char buf[256]; + const char* features[] = { + "cpucfg", "lam", "ual", "fpu", + "lsx", "lasx", "complex", "crypto", + "lvz", "lbt_x86", "lbt_arm", "lbt_mips" + }; + + found = 0; + len = sizeof(features) / sizeof(features[0]); + for (i = 0; i < len; i++) { + if (strcmp(feature_name, features[i]) == 0) { + found = 1; + break; + } + } + + if (!found) + return UNRECOGNISED_FEATURE; + + fp = fopen("/proc/cpuinfo", "r"); + if(fp == NULL) + return UNRECOGNISED_FEATURE; + + while (fgets(buf, sizeof(buf), fp) != NULL) { + if (strstr(buf, feature_name) != NULL) { + fclose(fp); + return FEATURE_PRESENT; + } + } + + fclose(fp); + return FEATURE_NOT_PRESENT; +} + +#else + +static int go(const char* feature_name) +{ + // Feature not recognised (non-loongarch64 machine!) + return UNRECOGNISED_FEATURE; +} + +#endif // defined(VGA_loongarch64) + + +//--------------------------------------------------------------------------- +// main +//--------------------------------------------------------------------------- +int main(int argc, char **argv) +{ + if (argc != 2) { + fprintf(stderr, "usage: loongarch64_features \n"); + exit(USAGE_ERROR); + } + + return go(argv[1]); +} diff --git a/tests/platform_test b/tests/platform_test index c23a4f6..a1eaf8f 100644 --- a/tests/platform_test +++ b/tests/platform_test @@ -14,6 +14,7 @@ all_platforms= all_platforms="$all_platforms x86-linux amd64-linux ppc32-linux ppc64-linux" all_platforms="$all_platforms arm-linux arm64-linux" all_platforms="$all_platforms s390x-linux mips32-linux mips64-linux" +all_platforms="$all_platforms loongarch64-linux" all_platforms="$all_platforms x86-darwin amd64-darwin" all_platforms="$all_platforms x86-solaris amd64-solaris" all_platforms="$all_platforms x86-freebsd amd64-freebsd" -- 2.33.0