c98bb6b512
Signed-off-by: Jie Yang <yangjieyj.yang@huawei.com> (cherry picked from commit e9cfa81784d4a86efd4392a487c0294d440c03c0)
62 lines
2.9 KiB
Diff
62 lines
2.9 KiB
Diff
From afe05089a4284acef30a97fb88435fea46e29d8e Mon Sep 17 00:00:00 2001
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From: zhouli57 <zhouli57@huawei.com>
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Date: Fri, 11 Mar 2022 14:22:07 +0800
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Subject: [PATCH 3/8] arm: use the HighPcieEcam region
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We use 16MB ECAM region on arm, which only support 16 pcie buses, and
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now we use the high ECAM region, which can support 256 pcie buses.
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Signed-off-by: zhouli57 <zhouli57@huawei.com>
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---
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machine/src/standard_vm/aarch64/mod.rs | 14 +++++++-------
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1 file changed, 7 insertions(+), 7 deletions(-)
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diff --git a/machine/src/standard_vm/aarch64/mod.rs b/machine/src/standard_vm/aarch64/mod.rs
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index 1e6fc6c..ddf8a41 100644
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--- a/machine/src/standard_vm/aarch64/mod.rs
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+++ b/machine/src/standard_vm/aarch64/mod.rs
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@@ -141,8 +141,8 @@ impl StdMachine {
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sysbus,
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pci_host: Arc::new(Mutex::new(PciHost::new(
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&sys_mem,
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- MEM_LAYOUT[LayoutEntryType::PcieEcam as usize],
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- MEM_LAYOUT[LayoutEntryType::PcieMmio as usize],
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+ MEM_LAYOUT[LayoutEntryType::HighPcieEcam as usize],
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+ MEM_LAYOUT[LayoutEntryType::HighPcieMmio as usize],
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))),
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boot_source: Arc::new(Mutex::new(vm_config.clone().boot_source)),
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vm_state: Arc::new((Mutex::new(KvmVmState::Created), Condvar::new())),
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@@ -221,14 +221,14 @@ impl StdMachineOps for StdMachine {
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let root_bus = Arc::downgrade(&self.pci_host.lock().unwrap().root_bus);
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let mmconfig_region_ops = PciHost::build_mmconfig_ops(self.pci_host.clone());
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let mmconfig_region = Region::init_io_region(
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- MEM_LAYOUT[LayoutEntryType::PcieEcam as usize].1,
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+ MEM_LAYOUT[LayoutEntryType::HighPcieEcam as usize].1,
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mmconfig_region_ops,
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);
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self.sys_mem
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.root()
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.add_subregion(
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mmconfig_region,
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- MEM_LAYOUT[LayoutEntryType::PcieEcam as usize].0,
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+ MEM_LAYOUT[LayoutEntryType::HighPcieEcam as usize].0,
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)
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.chain_err(|| "Failed to register ECAM in memory space.")?;
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@@ -645,9 +645,9 @@ impl EventLoopManager for StdMachine {
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//
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// * `fdt` - Flatted device-tree blob where node will be filled into.
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fn generate_pci_host_node(fdt: &mut FdtBuilder) -> util::errors::Result<()> {
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- let pcie_ecam_base = MEM_LAYOUT[LayoutEntryType::PcieEcam as usize].0;
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- let pcie_ecam_size = MEM_LAYOUT[LayoutEntryType::PcieEcam as usize].1;
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- let pcie_buses_num = MEM_LAYOUT[LayoutEntryType::PcieEcam as usize].1 >> 20;
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+ let pcie_ecam_base = MEM_LAYOUT[LayoutEntryType::HighPcieEcam as usize].0;
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+ let pcie_ecam_size = MEM_LAYOUT[LayoutEntryType::HighPcieEcam as usize].1;
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+ let pcie_buses_num = MEM_LAYOUT[LayoutEntryType::HighPcieEcam as usize].1 >> 20;
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let node = format!("pcie@{:x}", pcie_ecam_base);
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let pci_node_dep = fdt.begin_node(&node)?;
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fdt.set_property_string("compatible", "pci-host-ecam-generic")?;
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--
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2.20.1
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