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rdma-core/0046-libhns-Disable-local-invalidate-operation.patch
Zhou Juan bade32c716 Fix the sge number related errors and remove local invalidate operation 
1. The hns hardware logic requires wr->num_sge to be 1 when
performing atomic operations. The code does not judge this
condition, and the current patch adds this constraint.

2. In the sq inline scenario, when num_sge in post_send is not 1, sge
array appears in the for loop without rotation and directly copy
out of bounds.

3. Currently local invalidate operation don't work properly.
Disable it for the time being.
HIP08 and HIP09 hardware does not support this feature, so
delete the associated code.

Signed-off-by: Juan Zhou <zhoujuan51@h-partners.com>
(cherry picked from commit 43c14b73409cf6e63278d5ff68e2694e592e9015)
2023-10-31 16:20:15 +08:00

154 lines
5.5 KiB
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From b3cea3522d575fdb60b6f426e43d45cec3deb847 Mon Sep 17 00:00:00 2001
From: Yangyang Li <liyangyang20@huawei.com>
Date: Sat, 6 May 2023 18:06:40 +0800
Subject: [PATCH 3/3] libhns: Disable local invalidate operation
mainline inclusion
commit d8eec872
category: bugfix
bugzilla: https://gitee.com/src-openeuler/rdma-core/issues/I72F0U
CVE: NA
----------------------------------------------------------------------
Currently local invalidate operation don't work properly.
Disable it for the time being.
HIP08 and HIP09 hardware does not support this feature, so
delete the associated code.
Fixes: a9ae7e9bfb5d ("libhns: Add local invalidate MR support for hip08")
Signed-off-by: Yangyang Li <liyangyang20@huawei.com>
Signed-off-by: Zhou Juan <nnuzj07170227@163.com>
---
providers/hns/hns_roce_u_hw_v2.c | 30 +-----------------------------
providers/hns/hns_roce_u_hw_v2.h | 2 --
2 files changed, 1 insertion(+), 31 deletions(-)
diff --git a/providers/hns/hns_roce_u_hw_v2.c b/providers/hns/hns_roce_u_hw_v2.c
index 3d46f35..b929bbf 100644
--- a/providers/hns/hns_roce_u_hw_v2.c
+++ b/providers/hns/hns_roce_u_hw_v2.c
@@ -50,7 +50,6 @@ static const uint32_t hns_roce_opcode[] = {
HR_IBV_OPC_MAP(RDMA_READ, RDMA_READ),
HR_IBV_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOMIC_COM_AND_SWAP),
HR_IBV_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOMIC_FETCH_AND_ADD),
- HR_IBV_OPC_MAP(LOCAL_INV, LOCAL_INV),
HR_IBV_OPC_MAP(BIND_MW, BIND_MW_TYPE),
HR_IBV_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
};
@@ -429,7 +428,6 @@ static const unsigned int wc_send_op_map[] = {
[HNS_ROCE_SQ_OP_RDMA_READ] = IBV_WC_RDMA_READ,
[HNS_ROCE_SQ_OP_ATOMIC_COMP_AND_SWAP] = IBV_WC_COMP_SWAP,
[HNS_ROCE_SQ_OP_ATOMIC_FETCH_AND_ADD] = IBV_WC_FETCH_ADD,
- [HNS_ROCE_SQ_OP_LOCAL_INV] = IBV_WC_LOCAL_INV,
[HNS_ROCE_SQ_OP_BIND_MW] = IBV_WC_BIND_MW,
};
@@ -597,9 +595,6 @@ static void parse_cqe_for_req(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc,
case HNS_ROCE_SQ_OP_RDMA_WRITE_WITH_IMM:
wc->wc_flags = IBV_WC_WITH_IMM;
break;
- case HNS_ROCE_SQ_OP_LOCAL_INV:
- wc->wc_flags = IBV_WC_WITH_INV;
- break;
case HNS_ROCE_SQ_OP_RDMA_READ:
case HNS_ROCE_SQ_OP_ATOMIC_COMP_AND_SWAP:
case HNS_ROCE_SQ_OP_ATOMIC_FETCH_AND_ADD:
@@ -1338,9 +1333,6 @@ static int check_rc_opcode(struct hns_roce_rc_sq_wqe *wqe,
wqe->rkey = htole32(wr->wr.atomic.rkey);
wqe->va = htole64(wr->wr.atomic.remote_addr);
break;
- case IBV_WR_LOCAL_INV:
- hr_reg_enable(wqe, RCWQE_SO);
- /* fallthrough */
case IBV_WR_SEND_WITH_INV:
wqe->inv_key = htole32(wr->invalidate_rkey);
break;
@@ -1372,7 +1364,6 @@ static int set_rc_wqe(void *wqe, struct hns_roce_qp *qp, struct ibv_send_wr *wr,
!!(wr->send_flags & IBV_SEND_SOLICITED));
hr_reg_write_bool(wqe, RCWQE_INLINE,
!!(wr->send_flags & IBV_SEND_INLINE));
- hr_reg_clear(wqe, RCWQE_SO);
ret = check_rc_opcode(rc_sq_wqe, wr);
if (ret)
@@ -2092,8 +2083,6 @@ static unsigned int get_wc_flags_for_sq(uint8_t opcode)
case HNS_ROCE_SQ_OP_SEND_WITH_IMM:
case HNS_ROCE_SQ_OP_RDMA_WRITE_WITH_IMM:
return IBV_WC_WITH_IMM;
- case HNS_ROCE_SQ_OP_LOCAL_INV:
- return IBV_WC_WITH_INV;
default:
return 0;
}
@@ -2202,7 +2191,6 @@ init_rc_wqe(struct hns_roce_qp *qp, uint64_t wr_id, unsigned int opcode)
hr_reg_write_bool(wqe, RCWQE_FENCE, send_flags & IBV_SEND_FENCE);
hr_reg_write_bool(wqe, RCWQE_SE, send_flags & IBV_SEND_SOLICITED);
hr_reg_clear(wqe, RCWQE_INLINE);
- hr_reg_clear(wqe, RCWQE_SO);
if (check_qp_dca_enable(qp))
fill_rc_dca_fields(qp->verbs_qp.qp.qp_num, wqe);
@@ -2332,20 +2320,6 @@ static void wr_send_inv_rc(struct ibv_qp_ex *ibv_qp, uint32_t invalidate_rkey)
wqe->inv_key = htole32(invalidate_rkey);
}
-static void wr_local_inv_rc(struct ibv_qp_ex *ibv_qp, uint32_t invalidate_rkey)
-{
- struct hns_roce_qp *qp = to_hr_qp(&ibv_qp->qp_base);
- struct hns_roce_rc_sq_wqe *wqe;
-
- wqe = init_rc_wqe(qp, ibv_qp->wr_id, HNS_ROCE_WQE_OP_LOCAL_INV);
- if (!wqe)
- return;
-
- hr_reg_enable(wqe, RCWQE_SO);
- wqe->inv_key = htole32(invalidate_rkey);
- enable_wqe(qp, wqe, qp->sq.head);
-}
-
static void wr_set_xrc_srqn(struct ibv_qp_ex *ibv_qp, uint32_t remote_srqn)
{
struct hns_roce_qp *qp = to_hr_qp(&ibv_qp->qp_base);
@@ -2833,8 +2807,7 @@ enum {
IBV_QP_EX_WITH_RDMA_WRITE_WITH_IMM |
IBV_QP_EX_WITH_RDMA_READ |
IBV_QP_EX_WITH_ATOMIC_CMP_AND_SWP |
- IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD |
- IBV_QP_EX_WITH_LOCAL_INV,
+ IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD,
HNS_SUPPORTED_SEND_OPS_FLAGS_UD =
IBV_QP_EX_WITH_SEND |
IBV_QP_EX_WITH_SEND_WITH_IMM,
@@ -2850,7 +2823,6 @@ static void fill_send_wr_ops_rc_xrc(struct ibv_qp_ex *qp_ex)
qp_ex->wr_rdma_write_imm = wr_rdma_write_imm;
qp_ex->wr_set_inline_data = wr_set_inline_data_rc;
qp_ex->wr_set_inline_data_list = wr_set_inline_data_list_rc;
- qp_ex->wr_local_inv = wr_local_inv_rc;
qp_ex->wr_atomic_cmp_swp = wr_atomic_cmp_swp;
qp_ex->wr_atomic_fetch_add = wr_atomic_fetch_add;
qp_ex->wr_set_sge = wr_set_sge_rc;
diff --git a/providers/hns/hns_roce_u_hw_v2.h b/providers/hns/hns_roce_u_hw_v2.h
index a22995d..d628d76 100644
--- a/providers/hns/hns_roce_u_hw_v2.h
+++ b/providers/hns/hns_roce_u_hw_v2.h
@@ -60,7 +60,6 @@ enum {
HNS_ROCE_WQE_OP_ATOMIC_MASK_COMP_AND_SWAP = 0x8,
HNS_ROCE_WQE_OP_ATOMIC_MASK_FETCH_AND_ADD = 0x9,
HNS_ROCE_WQE_OP_FAST_REG_PMR = 0xa,
- HNS_ROCE_WQE_OP_LOCAL_INV = 0xb,
HNS_ROCE_WQE_OP_BIND_MW_TYPE = 0xc,
HNS_ROCE_WQE_OP_MASK = 0x1f
};
@@ -85,7 +84,6 @@ enum {
HNS_ROCE_SQ_OP_ATOMIC_MASK_COMP_AND_SWAP = 0x8,
HNS_ROCE_SQ_OP_ATOMIC_MASK_FETCH_AND_ADD = 0x9,
HNS_ROCE_SQ_OP_FAST_REG_PMR = 0xa,
- HNS_ROCE_SQ_OP_LOCAL_INV = 0xb,
HNS_ROCE_SQ_OP_BIND_MW = 0xc,
};
--
2.25.1
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