19429f69c9
Currently, if compiler does not support SVE, hns_roce_sve_write512() will be a empty function, which means that this doorbell will be missed when HNS_ROCE_QP_CAP_SVE_DIRECT_WQE is set in qp flag. This patch ensures that driver will at least generate the DB regardless of whether SVE DWQE is supported or not. Signed-off-by: Chengchang Tang <tangchengchang@huawei.com Signed-off-by: Ran Zhou <zhouran10@h-partners.com> (cherry picked from commit e5fcbc2552eda0d654e55ae0758280d6e51804ea)
84 lines
2.6 KiB
Diff
84 lines
2.6 KiB
Diff
From cad30f3d98525d14796094b2905de222c894464f Mon Sep 17 00:00:00 2001
|
|
From: Chengchang Tang <tangchengchang@huawei.com>
|
|
Date: Fri, 8 Dec 2023 09:49:42 +0800
|
|
Subject: [PATCH] libhns: Fix missing DB when compiler does not support SVE
|
|
|
|
driver inclusion
|
|
category: bugfix
|
|
bugzilla: https://gitee.com/openeuler/kernel/issues/I8MPTX
|
|
|
|
----------------------------------------------------------------------
|
|
|
|
Currently, if compiler does not support SVE, hns_roce_sve_write512() will
|
|
be a empty function, which means that this doorbell will be missed when
|
|
HNS_ROCE_QP_CAP_SVE_DIRECT_WQE is set in qp flag.
|
|
|
|
This patch ensures that driver will at least generate the DB regardless
|
|
of whether SVE DWQE is supported or not.
|
|
|
|
Fixes: 7b1f5c5654c2 ("libhns: Add support for SVE Direct WQE function")
|
|
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
|
|
Signed-off-by: Ran Zhou <zhouran10@h-partners.com>
|
|
---
|
|
providers/hns/hns_roce_u_hw_v2.c | 33 +++++++++++++-------------------
|
|
1 file changed, 13 insertions(+), 20 deletions(-)
|
|
|
|
diff --git a/providers/hns/hns_roce_u_hw_v2.c b/providers/hns/hns_roce_u_hw_v2.c
|
|
index acbc854..be4c9f3 100644
|
|
--- a/providers/hns/hns_roce_u_hw_v2.c
|
|
+++ b/providers/hns/hns_roce_u_hw_v2.c
|
|
@@ -318,26 +318,22 @@ static void hns_roce_update_sq_db(struct hns_roce_context *ctx,
|
|
hns_roce_write64(ctx, qp->sq.db_reg, (__le32 *)&sq_db);
|
|
}
|
|
|
|
-static void hns_roce_write512(uint64_t *dest, uint64_t *val)
|
|
+static void hns_roce_qp_write512(struct hns_roce_qp *qp, uint64_t *val)
|
|
{
|
|
- mmio_memcpy_x64(dest, val, sizeof(struct hns_roce_rc_sq_wqe));
|
|
-}
|
|
+ uint64_t *dest = qp->sq.db_reg;
|
|
|
|
#if defined(HNS_SVE)
|
|
-static void hns_roce_sve_write512(uint64_t *dest, uint64_t *val)
|
|
-{
|
|
- asm volatile(
|
|
- "ldr z0, [%0]\n"
|
|
- "str z0, [%1]\n"
|
|
- ::"r" (val), "r"(dest):"cc", "memory"
|
|
- );
|
|
-}
|
|
-#else
|
|
-static void hns_roce_sve_write512(uint64_t *dest, uint64_t *val)
|
|
-{
|
|
- return;
|
|
-}
|
|
+ if (qp->flags & HNS_ROCE_QP_CAP_SVE_DIRECT_WQE) {
|
|
+ asm volatile(
|
|
+ "ldr z0, [%0]\n"
|
|
+ "str z0, [%1]\n"
|
|
+ ::"r" (val), "r"(dest):"cc", "memory"
|
|
+ );
|
|
+ return;
|
|
+ }
|
|
#endif
|
|
+ mmio_memcpy_x64(dest, val, sizeof(struct hns_roce_rc_sq_wqe));
|
|
+}
|
|
|
|
static void hns_roce_write_dwqe(struct hns_roce_qp *qp, void *wqe)
|
|
{
|
|
@@ -355,10 +351,7 @@ static void hns_roce_write_dwqe(struct hns_roce_qp *qp, void *wqe)
|
|
hr_reg_write(rc_sq_wqe, RCWQE_DB_SL_H, qp->sl >> HNS_ROCE_SL_SHIFT);
|
|
hr_reg_write(rc_sq_wqe, RCWQE_WQE_IDX, qp->sq.head);
|
|
|
|
- if (qp->flags & HNS_ROCE_QP_CAP_SVE_DIRECT_WQE)
|
|
- hns_roce_sve_write512(qp->sq.db_reg, wqe);
|
|
- else
|
|
- hns_roce_write512(qp->sq.db_reg, wqe);
|
|
+ hns_roce_qp_write512(qp, wqe);
|
|
}
|
|
|
|
static void update_cq_db(struct hns_roce_context *ctx, struct hns_roce_cq *cq)
|
|
--
|
|
2.25.1
|
|
|