92 lines
3.0 KiB
Diff
92 lines
3.0 KiB
Diff
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From b5127a009336e0e6947433148c6c7422c277bce7 Mon Sep 17 00:00:00 2001
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From: Luoyouming <luoyouming@huawei.com>
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Date: Sat, 6 May 2023 18:06:38 +0800
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Subject: [PATCH 1/3] libhns: Fix the sge num problem of atomic op
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mainline inclusion
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commit b4793235
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category: bugfix
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bugzilla: https://gitee.com/src-openeuler/rdma-core/issues/I72EWP
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CVE: NA
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----------------------------------------------------------------------
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The hns hardware logic requires wr->num_sge to be 1 when
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performing atomic operations. The code does not judge this
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condition, and the current patch adds this constraint.
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Fixes: 3507f87f7760 ("libhns: Optimize set_sge process")
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Fixes: 36446a56eea5 ("libhns: Extended QP supports the new post send mechanism")
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Signed-off-by: Luoyouming <luoyouming@huawei.com>
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Signed-off-by: Zhou Juan <nnuzj07170227@163.com>
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---
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providers/hns/hns_roce_u_hw_v2.c | 23 ++++++++++++++++++-----
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1 file changed, 18 insertions(+), 5 deletions(-)
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diff --git a/providers/hns/hns_roce_u_hw_v2.c b/providers/hns/hns_roce_u_hw_v2.c
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index a49b50d..5533cdb 100644
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--- a/providers/hns/hns_roce_u_hw_v2.c
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+++ b/providers/hns/hns_roce_u_hw_v2.c
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@@ -106,6 +106,9 @@ static int set_atomic_seg(struct hns_roce_qp *qp, struct ibv_send_wr *wr,
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void *buf[ATOMIC_BUF_NUM_MAX];
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unsigned int buf_sge_num;
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+ /* There is only one sge in atomic wr, and data_len is the data length
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+ * in the first sge
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+ */
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if (is_std_atomic(data_len)) {
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if (wr->opcode == IBV_WR_ATOMIC_CMP_AND_SWP) {
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aseg->fetchadd_swap_data = htole64(wr->wr.atomic.swap);
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@@ -923,16 +926,19 @@ static void set_rc_sge(struct hns_roce_v2_wqe_data_seg *dseg,
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uint32_t mask = qp->ex_sge.sge_cnt - 1;
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uint32_t index = sge_info->start_idx;
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struct ibv_sge *sge = wr->sg_list;
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+ int total_sge = wr->num_sge;
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+ bool flag = false;
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uint32_t len = 0;
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uint32_t cnt = 0;
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- int flag;
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int i;
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- flag = (wr->send_flags & IBV_SEND_INLINE &&
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- wr->opcode != IBV_WR_ATOMIC_FETCH_AND_ADD &&
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- wr->opcode != IBV_WR_ATOMIC_CMP_AND_SWP);
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+ if (wr->opcode == IBV_WR_ATOMIC_FETCH_AND_ADD ||
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+ wr->opcode == IBV_WR_ATOMIC_CMP_AND_SWP)
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+ total_sge = 1;
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+ else
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+ flag = !!(wr->send_flags & IBV_SEND_INLINE);
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- for (i = 0; i < wr->num_sge; i++, sge++) {
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+ for (i = 0; i < total_sge; i++, sge++) {
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if (unlikely(!sge->length))
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continue;
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@@ -2267,6 +2273,7 @@ static void wr_set_sge_list_rc(struct ibv_qp_ex *ibv_qp, size_t num_sge,
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struct hns_roce_qp *qp = to_hr_qp(&ibv_qp->qp_base);
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struct hns_roce_rc_sq_wqe *wqe = qp->cur_wqe;
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struct hns_roce_v2_wqe_data_seg *dseg;
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+ uint32_t opcode;
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if (!wqe)
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return;
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@@ -2276,9 +2283,15 @@ static void wr_set_sge_list_rc(struct ibv_qp_ex *ibv_qp, size_t num_sge,
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return;
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}
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+
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hr_reg_write(wqe, RCWQE_MSG_START_SGE_IDX,
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qp->sge_info.start_idx & (qp->ex_sge.sge_cnt - 1));
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+ opcode = hr_reg_read(wqe, RCWQE_OPCODE);
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+ if (opcode == HNS_ROCE_WQE_OP_ATOMIC_COM_AND_SWAP ||
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+ opcode == HNS_ROCE_WQE_OP_ATOMIC_FETCH_AND_ADD)
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+ num_sge = 1;
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+
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dseg = (void *)(wqe + 1);
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set_sgl_rc(dseg, qp, sg_list, num_sge);
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--
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2.25.1
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