packages/qt6-qtwebengine
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

!11 [sync] PR-10: Add support for riscv64

Browse Source 
From: @openeuler-sync-bot 
Reviewed-by: @open-bot 
Signed-off-by: @open-bot
This commit is contained in:
openeuler-ci-bot 2024-04-15 07:59:07 +00:00 committed by Gitee
commit 2b332b5f4c
No known key found for this signature in database
GPG Key ID: 173E9B9CA92EEF8F
6 changed files with 3390 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
qt6-qtwebengine.spec
View File

@ -39,7 +39,7 @@
Summary: Qt6 - QtWebEngine components
Name: qt6-qtwebengine
Version: 6.5.2
Release: 1
Release: 2
# See LICENSE.GPL LICENSE.LGPL LGPL_EXCEPTION.txt, for details
# See also http://qt-project.org/doc/qt-5.0/qtdoc/licensing.html
@ -86,10 +86,17 @@ Patch111: CVE-2023-6112.patch
# handled by qt6-srpm-macros, which defines %%qt6_qtwebengine_arches
# FIXME use/update qt6_qtwebengine_arches
# 32-bit arches not supported (https://bugreports.qt.io/browse/QTBUG-102143)
ExclusiveArch: aarch64 x86_64
ExclusiveArch: aarch64 x86_64 riscv64
Patch120: qtwebengine-icu-74.patch
## Add riscv64 patches
Patch1000: riscv-angle.patch
Patch1001: riscv-breakpad.patch
Patch1002: riscv-crashpad.patch
Patch1003: riscv-dav1d.patch
Patch1004: riscv-sandbox.patch
BuildRequires: cmake
BuildRequires: make
BuildRequires: qt6-srpm-macros
@ -372,6 +379,13 @@ popd
%patch120 -p1
## Add riscv64 patches
%patch1000 -p0 -d src/3rdparty
%patch1001 -p0 -d src/3rdparty
%patch1002 -p0 -d src/3rdparty
%patch1003 -p0 -d src/3rdparty
%patch1004 -p0 -d src/3rdparty
# delete all "toolprefix = " lines from build/toolchain/linux/BUILD.gn, as we
# never cross-compile in native Fedora RPMs, fixes ARM and aarch64 FTBFS
sed -i -e '/toolprefix = /d' -e 's/\${toolprefix}//g' \
@ -650,6 +664,9 @@ done
%changelog
* Fri Apr 12 2024 misaka00251 <liuxin@iscas.ac.cn> - 6.5.2-2
- Add support for riscv64
* Fri Mar 08 2024 peijiankang <peijiankang@kylinos.cn> - 6.5.2-1
- update version to 6.5.2

27
riscv-angle.patch Normal file
View File

@ -0,0 +1,27 @@
Index: chromium/third_party/angle/gni/angle.gni
===================================================================
--- chromium/third_party/angle/gni/angle.gni
+++ chromium/third_party/angle/gni/angle.gni
@@ -97,7 +97,8 @@ declare_args() {
if (current_cpu == "arm64" || current_cpu == "x64" ||
current_cpu == "mips64el" || current_cpu == "s390x" ||
- current_cpu == "ppc64" || current_cpu == "loong64") {
+ current_cpu == "ppc64" || current_cpu == "loong64" ||
+ current_cpu == "riscv64") {
angle_64bit_current_cpu = true
} else if (current_cpu == "arm" || current_cpu == "x86" ||
current_cpu == "mipsel" || current_cpu == "s390" ||
Index: chromium/third_party/angle/src/common/platform.h
===================================================================
--- chromium/third_party/angle/src/common/platform.h
+++ chromium/third_party/angle/src/common/platform.h
@@ -102,7 +102,7 @@
#endif
// Mips and arm devices need to include stddef for size_t.
-#if defined(__mips__) || defined(__arm__) || defined(__aarch64__)
+#if defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(__riscv)
# include <stddef.h>
#endif

569
riscv-breakpad.patch Normal file
View File

@ -0,0 +1,569 @@
Index: chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h
+++ chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h
@@ -44,6 +44,8 @@ typedef MDRawContextARM RawContextCPU;
typedef MDRawContextARM64_Old RawContextCPU;
#elif defined(__mips__)
typedef MDRawContextMIPS RawContextCPU;
+#elif defined(__riscv)
+typedef MDRawContextRISCV64 RawContextCPU;
#else
#error "This code has not been ported to your platform yet."
#endif
Index: chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc
+++ chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc
@@ -270,7 +270,23 @@ void ThreadInfo::FillCPUContext(RawConte
out->float_save.fir = mcontext.fpc_eir;
#endif
}
-#endif // __mips__
+#elif defined(__riscv)
+
+uintptr_t ThreadInfo::GetInstructionPointer() const {
+ return mcontext.__gregs[REG_PC];
+}
+
+void ThreadInfo::FillCPUContext(RawContextCPU* out) const {
+ out->context_flags = MD_CONTEXT_RISCV64_FULL;
+
+ my_memcpy (out->iregs, mcontext.__gregs, MD_CONTEXT_RISCV64_GPR_COUNT * 8);
+
+ out->float_save.fcsr = mcontext.__fpregs.__d.__fcsr;
+ my_memcpy(&out->float_save.regs, &mcontext.__fpregs.__d.__f,
+ MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT * 8);
+}
+
+#endif // __riscv
void ThreadInfo::GetGeneralPurposeRegisters(void** gp_regs, size_t* size) {
assert(gp_regs || size);
@@ -279,6 +295,11 @@ void ThreadInfo::GetGeneralPurposeRegist
*gp_regs = mcontext.gregs;
if (size)
*size = sizeof(mcontext.gregs);
+#elif defined(__riscv)
+ if (gp_regs)
+ *gp_regs = mcontext.__gregs;
+ if (size)
+ *size = sizeof(mcontext.__gregs);
#else
if (gp_regs)
*gp_regs = &regs;
@@ -294,6 +315,11 @@ void ThreadInfo::GetFloatingPointRegiste
*fp_regs = &mcontext.fpregs;
if (size)
*size = sizeof(mcontext.fpregs);
+#elif defined(__riscv)
+ if (fp_regs)
+ *fp_regs = &mcontext.__fpregs;
+ if (size)
+ *size = sizeof(mcontext.__fpregs);
#else
if (fp_regs)
*fp_regs = &fpregs;
Index: chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h
+++ chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h
@@ -68,7 +68,7 @@ struct ThreadInfo {
// Use the structures defined in <sys/user.h>
struct user_regs_struct regs;
struct user_fpsimd_struct fpregs;
-#elif defined(__mips__)
+#elif defined(__mips__) || defined(__riscv)
// Use the structure defined in <sys/ucontext.h>.
mcontext_t mcontext;
#endif
Index: chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc
+++ chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc
@@ -254,6 +254,27 @@ void UContextReader::FillCPUContext(RawC
out->float_save.fir = uc->uc_mcontext.fpc_eir; // Unused.
#endif
}
+
+#elif defined(__riscv)
+
+uintptr_t UContextReader::GetStackPointer(const ucontext_t* uc) {
+ return uc->uc_mcontext.__gregs[REG_SP];
+}
+
+uintptr_t UContextReader::GetInstructionPointer(const ucontext_t* uc) {
+ return uc->uc_mcontext.__gregs[REG_PC];
+}
+
+void UContextReader::FillCPUContext(RawContextCPU* out, const ucontext_t* uc) {
+ out->context_flags = MD_CONTEXT_RISCV64_FULL;
+
+ for (int i = 0; i < MD_CONTEXT_RISCV64_GPR_COUNT; ++i)
+ out->iregs[i] = uc->uc_mcontext.__gregs[i];
+
+ out->float_save.fcsr = uc->uc_mcontext.__fpregs.__d.__fcsr;
+ for (int i = 0; i < MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT; ++i)
+ out->float_save.regs[i] = uc->uc_mcontext.__fpregs.__d.__f[i];
+}
#endif
} // namespace google_breakpad
Index: chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc
+++ chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc
@@ -461,7 +461,7 @@ bool ExceptionHandler::HandleSignal(int
memcpy(&g_crash_context_.float_state, fp_ptr,
sizeof(g_crash_context_.float_state));
}
-#elif !defined(__ARM_EABI__) && !defined(__mips__)
+#elif !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
// FP state is not part of user ABI on ARM Linux.
// In case of MIPS Linux FP state is already part of ucontext_t
// and 'float_state' is not a member of CrashContext.
@@ -701,7 +701,7 @@ bool ExceptionHandler::WriteMinidump() {
}
#endif
-#if !defined(__ARM_EABI__) && !defined(__aarch64__) && !defined(__mips__)
+#if !defined(__ARM_EABI__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__riscv)
// FPU state is not part of ARM EABI ucontext_t.
memcpy(&context.float_state, context.context.uc_mcontext.fpregs,
sizeof(context.float_state));
@@ -726,6 +726,9 @@ bool ExceptionHandler::WriteMinidump() {
#elif defined(__mips__)
context.siginfo.si_addr =
reinterpret_cast<void*>(context.context.uc_mcontext.pc);
+#elif defined(__riscv)
+ context.siginfo.si_addr =
+ reinterpret_cast<void*>(context.context.uc_mcontext.__gregs[REG_PC]);
#else
#error "This code has not been ported to your platform yet."
#endif
Index: chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h
+++ chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h
@@ -192,7 +192,7 @@ class ExceptionHandler {
siginfo_t siginfo;
pid_t tid; // the crashing thread.
ucontext_t context;
-#if !defined(__ARM_EABI__) && !defined(__mips__)
+#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
// #ifdef this out because FP state is not part of user ABI for Linux ARM.
// In case of MIPS Linux FP state is already part of ucontext_t so
// 'float_state' is not required.
Index: chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc
+++ chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc
@@ -138,7 +138,7 @@ class MicrodumpWriter {
const MicrodumpExtraInfo& microdump_extra_info,
LinuxDumper* dumper)
: ucontext_(context ? &context->context : NULL),
-#if !defined(__ARM_EABI__) && !defined(__mips__)
+#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
float_state_(context ? &context->float_state : NULL),
#endif
dumper_(dumper),
@@ -337,6 +337,12 @@ class MicrodumpWriter {
# else
# error "This mips ABI is currently not supported (n32)"
#endif
+#elif defined(__riscv)
+# if __riscv_xlen == 64
+ const char kArch[] = "riscv64";
+# else
+# error "This RISC-V ABI is currently not supported"
+#endif
#else
#error "This code has not been ported to your platform yet"
#endif
@@ -409,7 +415,7 @@ class MicrodumpWriter {
void DumpCPUState() {
RawContextCPU cpu;
my_memset(&cpu, 0, sizeof(RawContextCPU));
-#if !defined(__ARM_EABI__) && !defined(__mips__)
+#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
UContextReader::FillCPUContext(&cpu, ucontext_, float_state_);
#else
UContextReader::FillCPUContext(&cpu, ucontext_);
@@ -605,7 +611,7 @@ class MicrodumpWriter {
void* Alloc(unsigned bytes) { return dumper_->allocator()->Alloc(bytes); }
const ucontext_t* const ucontext_;
-#if !defined(__ARM_EABI__) && !defined(__mips__)
+#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
const google_breakpad::fpstate_t* const float_state_;
#endif
LinuxDumper* dumper_;
Index: chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc
+++ chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc
@@ -112,6 +112,9 @@ bool LinuxCoreDumper::GetThreadInfoByInd
#elif defined(__mips__)
stack_pointer =
reinterpret_cast<uint8_t*>(info->mcontext.gregs[MD_CONTEXT_MIPS_REG_SP]);
+#elif defined(__riscv)
+ stack_pointer =
+ reinterpret_cast<uint8_t*>(info->mcontext.__gregs[MD_CONTEXT_RISCV64_REG_SP]);
#else
#error "This code hasn't been ported to your platform yet."
#endif
@@ -218,6 +221,8 @@ bool LinuxCoreDumper::EnumerateThreads()
info.mcontext.mdlo = status->pr_reg[EF_LO];
info.mcontext.mdhi = status->pr_reg[EF_HI];
info.mcontext.pc = status->pr_reg[EF_CP0_EPC];
+#elif defined(__riscv)
+ memcpy(info.mcontext.__gregs, status->pr_reg, sizeof(info.mcontext.__gregs));
#else // __mips__
memcpy(&info.regs, status->pr_reg, sizeof(info.regs));
#endif // __mips__
Index: chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h
+++ chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h
@@ -63,7 +63,8 @@ namespace google_breakpad {
(defined(__mips__) && _MIPS_SIM == _ABIO32)
typedef Elf32_auxv_t elf_aux_entry;
#elif defined(__x86_64) || defined(__aarch64__) || \
- (defined(__mips__) && _MIPS_SIM != _ABIO32)
+ (defined(__mips__) && _MIPS_SIM != _ABIO32) || \
+ (defined(__riscv) && __riscv_xlen == 64)
typedef Elf64_auxv_t elf_aux_entry;
#endif
Index: chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc
+++ chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc
@@ -298,6 +298,9 @@ bool LinuxPtraceDumper::GetThreadInfoByI
#elif defined(__mips__)
stack_pointer =
reinterpret_cast<uint8_t*>(info->mcontext.gregs[MD_CONTEXT_MIPS_REG_SP]);
+#elif defined(__riscv)
+ stack_pointer =
+ reinterpret_cast<uint8_t*>(info->mcontext.__gregs[MD_CONTEXT_RISCV64_REG_SP]);
#else
#error "This code hasn't been ported to your platform yet."
#endif
Index: chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc
+++ chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc
@@ -141,7 +141,7 @@ class MinidumpWriter {
: fd_(minidump_fd),
path_(minidump_path),
ucontext_(context ? &context->context : NULL),
-#if !defined(__ARM_EABI__) && !defined(__mips__)
+#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
float_state_(context ? &context->float_state : NULL),
#endif
dumper_(dumper),
@@ -473,7 +473,7 @@ class MinidumpWriter {
if (!cpu.Allocate())
return false;
my_memset(cpu.get(), 0, sizeof(RawContextCPU));
-#if !defined(__ARM_EABI__) && !defined(__mips__)
+#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
UContextReader::FillCPUContext(cpu.get(), ucontext_, float_state_);
#else
UContextReader::FillCPUContext(cpu.get(), ucontext_);
@@ -950,7 +950,7 @@ class MinidumpWriter {
dirent->location.rva = 0;
}
-#if defined(__i386__) || defined(__x86_64__) || defined(__mips__)
+#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || defined(__riscv)
bool WriteCPUInformation(MDRawSystemInfo* sys_info) {
char vendor_id[sizeof(sys_info->cpu.x86_cpu_info.vendor_id) + 1] = {0};
static const char vendor_id_name[] = "vendor_id";
@@ -978,6 +978,12 @@ class MinidumpWriter {
# else
# error "This mips ABI is currently not supported (n32)"
#endif
+#elif defined(__riscv)
+# if __riscv_xlen == 64
+ MD_CPU_ARCHITECTURE_RISCV64;
+# else
+# error "This RISC-V ABI is currently not supported"
+# endif
#elif defined(__i386__)
MD_CPU_ARCHITECTURE_X86;
#else
@@ -1386,7 +1392,7 @@ class MinidumpWriter {
const char* path_; // Path to the file where the minidum should be written.
const ucontext_t* const ucontext_; // also from the signal handler
-#if !defined(__ARM_EABI__) && !defined(__mips__)
+#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
const google_breakpad::fpstate_t* const float_state_; // ditto
#endif
LinuxDumper* dumper_;
Index: chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h
===================================================================
--- chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h
+++ chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h
@@ -48,7 +48,7 @@ class ExceptionHandler;
#if defined(__aarch64__)
typedef struct fpsimd_context fpstate_t;
-#elif !defined(__ARM_EABI__) && !defined(__mips__)
+#elif !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
typedef std::remove_pointer<fpregset_t>::type fpstate_t;
#endif
Index: chromium/third_party/breakpad/breakpad/src/common/linux/breakpad_getcontext.S
===================================================================
--- chromium/third_party/breakpad/breakpad/src/common/linux/breakpad_getcontext.S
+++ chromium/third_party/breakpad/breakpad/src/common/linux/breakpad_getcontext.S
@@ -527,6 +527,68 @@ breakpad_getcontext:
.cfi_endproc
.size breakpad_getcontext, . - breakpad_getcontext
+#elif defined(__riscv) && __riscv_xlen == 64
+
+#define __NR_rt_sigprocmask 135
+#define _NSIG8 64 / 8
+#define SIG_BLOCK 0
+
+ .text
+ .global breakpad_getcontext
+ .hidden breakpad_getcontext
+ .type breakpad_getcontext, @function
+ .align 2
+breakpad_getcontext:
+ sd ra, MCONTEXT_GREGS_OFFSET + 0*8(a0)
+ sd ra, MCONTEXT_GREGS_OFFSET + 1*8(a0)
+ sd sp, MCONTEXT_GREGS_OFFSET + 2*8(a0)
+ sd s0, MCONTEXT_GREGS_OFFSET + 8*8(a0)
+ sd s1, MCONTEXT_GREGS_OFFSET + 9*8(a0)
+ sd x0, MCONTEXT_GREGS_OFFSET + 10*8(a0) /* return 0 by overwriting a0. */
+ sd s2, MCONTEXT_GREGS_OFFSET + 18*8(a0)
+ sd s3, MCONTEXT_GREGS_OFFSET + 19*8(a0)
+ sd s4, MCONTEXT_GREGS_OFFSET + 20*8(a0)
+ sd s5, MCONTEXT_GREGS_OFFSET + 21*8(a0)
+ sd s6, MCONTEXT_GREGS_OFFSET + 22*8(a0)
+ sd s7, MCONTEXT_GREGS_OFFSET + 23*8(a0)
+ sd s8, MCONTEXT_GREGS_OFFSET + 24*8(a0)
+ sd s9, MCONTEXT_GREGS_OFFSET + 25*8(a0)
+ sd s10, MCONTEXT_GREGS_OFFSET + 26*8(a0)
+ sd s11, MCONTEXT_GREGS_OFFSET + 27*8(a0)
+
+#ifndef __riscv_float_abi_soft
+ frsr a1
+
+ fsd fs0, MCONTEXT_FPREGS_OFFSET + 8*8(a0)
+ fsd fs1, MCONTEXT_FPREGS_OFFSET + 9*8(a0)
+ fsd fs2, MCONTEXT_FPREGS_OFFSET + 18*8(a0)
+ fsd fs3, MCONTEXT_FPREGS_OFFSET + 19*8(a0)
+ fsd fs4, MCONTEXT_FPREGS_OFFSET + 20*8(a0)
+ fsd fs5, MCONTEXT_FPREGS_OFFSET + 21*8(a0)
+ fsd fs6, MCONTEXT_FPREGS_OFFSET + 22*8(a0)
+ fsd fs7, MCONTEXT_FPREGS_OFFSET + 23*8(a0)
+ fsd fs8, MCONTEXT_FPREGS_OFFSET + 24*8(a0)
+ fsd fs9, MCONTEXT_FPREGS_OFFSET + 25*8(a0)
+ fsd fs10, MCONTEXT_FPREGS_OFFSET + 26*8(a0)
+ fsd fs11, MCONTEXT_FPREGS_OFFSET + 27*8(a0)
+
+ sw a1, MCONTEXT_FSR_OFFSET(a0)
+#endif /* __riscv_float_abi_soft */
+
+/* rt_sigprocmask (SIG_BLOCK, NULL, &ucp->uc_sigmask, _NSIG / 8) */
+ li a3, _NSIG8
+ add a2, a0, UCONTEXT_SIGMASK_OFFSET
+ mv a1, zero
+ li a0, SIG_BLOCK
+
+ li a7, __NR_rt_sigprocmask
+ scall
+
+ /* Always return 0 for success, even if sigprocmask failed. */
+ mv a0, zero
+ ret
+ .size breakpad_getcontext, . - breakpad_getcontext
+
#else
#error "This file has not been ported for your CPU!"
#endif
Index: chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc
===================================================================
--- chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc
+++ chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc
@@ -65,7 +65,8 @@ bool MemoryMappedFile::Map(const char* p
}
#if defined(__x86_64__) || defined(__aarch64__) || \
- (defined(__mips__) && _MIPS_SIM == _ABI64)
+ (defined(__mips__) && _MIPS_SIM == _ABI64) || \
+ (defined(__riscv) && __riscv_xlen == 64)
struct kernel_stat st;
if (sys_fstat(fd, &st) == -1 || st.st_size < 0) {
Index: chromium/third_party/breakpad/breakpad/src/common/linux/ucontext_constants.h
===================================================================
--- chromium/third_party/breakpad/breakpad/src/common/linux/ucontext_constants.h
+++ chromium/third_party/breakpad/breakpad/src/common/linux/ucontext_constants.h
@@ -146,6 +146,14 @@
#endif
#define FPREGS_OFFSET_MXCSR 24
+#elif defined(__riscv)
+
+#define UCONTEXT_SIGMASK_OFFSET 40
+
+#define MCONTEXT_GREGS_OFFSET 176
+#define MCONTEXT_FPREGS_OFFSET 432
+#define MCONTEXT_FSR_OFFSET (MCONTEXT_FPREGS_OFFSET + 32*8)
+
#else
#error "This header has not been ported for your CPU"
#endif
Index: chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_cpu_riscv64.h
===================================================================
--- /dev/null
+++ chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_cpu_riscv64.h
@@ -0,0 +1,121 @@
+/* Copyright 2013 Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+/* minidump_format.h: A cross-platform reimplementation of minidump-related
+ * portions of DbgHelp.h from the Windows Platform SDK.
+ *
+ * (This is C99 source, please don't corrupt it with C++.)
+ *
+ * This file contains the necessary definitions to read minidump files
+ * produced on ARM. These files may be read on any platform provided
+ * that the alignments of these structures on the processing system are
+ * identical to the alignments of these structures on the producing system.
+ * For this reason, precise-sized types are used. The structures defined
+ * by this file have been laid out to minimize alignment problems by
+ * ensuring that all members are aligned on their natural boundaries.
+ * In some cases, tail-padding may be significant when different ABIs specify
+ * different tail-padding behaviors. To avoid problems when reading or
+ * writing affected structures, MD_*_SIZE macros are provided where needed,
+ * containing the useful size of the structures without padding.
+ *
+ * Structures that are defined by Microsoft to contain a zero-length array
+ * are instead defined here to contain an array with one element, as
+ * zero-length arrays are forbidden by standard C and C++. In these cases,
+ * *_minsize constants are provided to be used in place of sizeof. For a
+ * cleaner interface to these sizes when using C++, see minidump_size.h.
+ *
+ * These structures are also sufficient to populate minidump files.
+ *
+ * Because precise data type sizes are crucial for this implementation to
+ * function properly and portably, a set of primitive types with known sizes
+ * are used as the basis of each structure defined by this file.
+ *
+ * Author: Colin Blundell
+ */
+
+/*
+ * RISCV64 support
+ */
+
+#ifndef GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__
+#define GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__
+
+#include "google_breakpad/common/breakpad_types.h"
+
+#define MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT 32
+#define MD_CONTEXT_RISCV64_GPR_COUNT 32
+
+typedef struct {
+ /* 32 64-bit floating point registers, f0 .. f31. */
+ uint64_t regs[MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT];
+
+ uint32_t fcsr; /* FPU control and status register */
+} MDFloatingSaveAreaRISCV64;
+
+/* For (MDRawContextRISCV64).context_flags. These values indicate the type of
+ * context stored in the structure. */
+#define MD_CONTEXT_RISCV64 0x00400000
+#define MD_CONTEXT_RISCV64_CONTROL (MD_CONTEXT_RISCV64 | 0x00000001)
+#define MD_CONTEXT_RISCV64_INTEGER (MD_CONTEXT_RISCV64 | 0x00000002)
+#define MD_CONTEXT_RISCV64_FLOATING_POINT (MD_CONTEXT_RISCV64 | 0x00000004)
+#define MD_CONTEXT_RISCV64_DEBUG (MD_CONTEXT_RISCV64 | 0x00000008)
+#define MD_CONTEXT_RISCV64_FULL (MD_CONTEXT_RISCV64_CONTROL | \
+ MD_CONTEXT_RISCV64_INTEGER | \
+ MD_CONTEXT_RISCV64_FLOATING_POINT)
+#define MD_CONTEXT_RISCV64_ALL (MD_CONTEXT_RISCV64_FULL | MD_CONTEXT_RISCV64_DEBUG)
+
+typedef struct {
+ /* Determines which fields of this struct are populated */
+ uint32_t context_flags;
+
+ /* 32 64-bit integer registers, x1 .. x31 + the PC
+ * Note the following fixed uses:
+ * x8 is the frame pointer
+ * x1 is the link register
+ * x2 is the stack pointer
+ * The PC is effectively x0.
+ */
+ uint64_t iregs[MD_CONTEXT_RISCV64_GPR_COUNT];
+
+ /* The next field is included with MD_CONTEXT64_ARM_FLOATING_POINT */
+ MDFloatingSaveAreaRISCV64 float_save;
+
+} MDRawContextRISCV64;
+
+/* Indices into iregs for registers with a dedicated or conventional
+ * purpose.
+ */
+enum MDRISCV64RegisterNumbers {
+ MD_CONTEXT_RISCV64_REG_FP = 8,
+ MD_CONTEXT_RISCV64_REG_RA = 1,
+ MD_CONTEXT_RISCV64_REG_SP = 2,
+ MD_CONTEXT_RISCV64_REG_PC = 0
+};
+
+#endif /* GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__ */
Index: chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_format.h
===================================================================
--- chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_format.h
+++ chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_format.h
@@ -118,6 +118,7 @@ typedef struct {
#include "minidump_cpu_mips.h"
#include "minidump_cpu_ppc.h"
#include "minidump_cpu_ppc64.h"
+#include "minidump_cpu_riscv64.h"
#include "minidump_cpu_sparc.h"
#include "minidump_cpu_x86.h"
@@ -684,6 +685,7 @@ typedef enum {
MD_CPU_ARCHITECTURE_PPC64 = 0x8002, /* Breakpad-defined value for PPC64 */
MD_CPU_ARCHITECTURE_ARM64_OLD = 0x8003, /* Breakpad-defined value for ARM64 */
MD_CPU_ARCHITECTURE_MIPS64 = 0x8004, /* Breakpad-defined value for MIPS64 */
+ MD_CPU_ARCHITECTURE_RISCV64 = 0x8005, /* Breakpad-defined value for RISCV64 */
MD_CPU_ARCHITECTURE_UNKNOWN = 0xffff /* PROCESSOR_ARCHITECTURE_UNKNOWN */
} MDCPUArchitecture;

777
riscv-crashpad.patch Normal file
View File

@ -0,0 +1,777 @@
Index: chromium/third_party/crashpad/crashpad/minidump/minidump_context.h
===================================================================
--- chromium/third_party/crashpad/crashpad/minidump/minidump_context.h
+++ chromium/third_party/crashpad/crashpad/minidump/minidump_context.h
@@ -637,6 +637,41 @@ struct MinidumpContextMIPS64 {
uint64_t fir;
};
+//! \brief 64bit RISC-V-specifc flags for MinidumpContextRISCV64::context_flags.
+//! Based on minidump_cpu_riscv64.h from breakpad
+enum MinidumpContextRISCV64Flags : uint32_t {
+ //! \brief Identifies the context structure as RISCV64.
+ kMinidumpContextRISCV64 = 0x00080000,
+
+ //! \brief Indicates the validity of integer registers.
+ //!
+ //! Registers `x1`-`x31` and pc are valid.
+ kMinidumpContextRISCV64Integer = kMinidumpContextRISCV64 | 0x00000002,
+
+ //! \brief Indicates the validity of floating point registers.
+ //!
+ //! Floating point registers `f0`-`f31`, and `fcsr` are valid
+ kMinidumpContextRISCV64FloatingPoint = kMinidumpContextRISCV64 | 0x00000004,
+
+ //! \brief Indicates the validity of all registers.
+ kMinidumpContextRISCV64All = kMinidumpContextRISCV64Integer |
+ kMinidumpContextRISCV64FloatingPoint,
+};
+
+//! \brief A 64bit RISCV CPU context (register state) carried in a minidump file.
+struct MinidumpContextRISCV64 {
+ uint64_t context_flags;
+
+ //! \brief General purpose registers.
+ uint64_t regs[32];
+
+ //! \brief FPU registers.
+ uint64_t fpregs[32];
+
+ //! \brief FPU status register.
+ uint64_t fcsr;
+};
+
} // namespace crashpad
#endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_
Index: chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc
+++ chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc
@@ -102,6 +102,13 @@ MinidumpContextWriter::CreateFromSnapsho
break;
}
+ case kCPUArchitectureRISCV64: {
+ context = std::make_unique<MinidumpContextRISCV64Writer>();
+ reinterpret_cast<MinidumpContextRISCV64Writer*>(context.get())
+ ->InitializeFromSnapshot(context_snapshot->riscv64);
+ break;
+ }
+
default: {
LOG(ERROR) << "unknown context architecture "
<< context_snapshot->architecture;
@@ -555,5 +562,42 @@ size_t MinidumpContextMIPS64Writer::Cont
DCHECK_GE(state(), kStateFrozen);
return sizeof(context_);
}
+
+MinidumpContextRISCV64Writer::MinidumpContextRISCV64Writer()
+ : MinidumpContextWriter(), context_() {
+ context_.context_flags = kMinidumpContextRISCV64;
+}
+
+MinidumpContextRISCV64Writer::~MinidumpContextRISCV64Writer() = default;
+
+void MinidumpContextRISCV64Writer::InitializeFromSnapshot(
+ const CPUContextRISCV64* context_snapshot) {
+ DCHECK_EQ(state(), kStateMutable);
+ DCHECK_EQ(context_.context_flags, kMinidumpContextRISCV64);
+
+ context_.context_flags = kMinidumpContextRISCV64All;
+
+ static_assert(sizeof(context_.regs) == sizeof(context_snapshot->regs),
+ "GPRs size mismatch");
+ memcpy(context_.regs, context_snapshot->regs, sizeof(context_.regs));
+
+ static_assert(sizeof(context_.fpregs) == sizeof(context_snapshot->fpregs),
+ "FPRs size mismatch");
+ memcpy(context_.fpregs,
+ context_snapshot->fpregs,
+ sizeof(context_.fpregs));
+ context_.fcsr = context_snapshot->fcsr;
+}
+
+bool MinidumpContextRISCV64Writer::WriteObject(
+ FileWriterInterface* file_writer) {
+ DCHECK_EQ(state(), kStateWritable);
+ return file_writer->Write(&context_, sizeof(context_));
+}
+
+size_t MinidumpContextRISCV64Writer::ContextSize() const {
+ DCHECK_GE(state(), kStateFrozen);
+ return sizeof(context_);
+}
} // namespace crashpad
Index: chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.h
===================================================================
--- chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.h
+++ chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.h
@@ -369,6 +369,49 @@ class MinidumpContextMIPS64Writer final
MinidumpContextMIPS64 context_;
};
+//! \brief The writer for a MinidumpContextRISCV64 structure in a minidump file.
+class MinidumpContextRISCV64Writer final : public MinidumpContextWriter {
+ public:
+ MinidumpContextRISCV64Writer();
+
+ MinidumpContextRISCV64Writer(const MinidumpContextRISCV64Writer&) = delete;
+ MinidumpContextRISCV64Writer& operator=(const MinidumpContextRISCV64Writer&) =
+ delete;
+
+ ~MinidumpContextRISCV64Writer() override;
+
+ //! \brief Initializes the MinidumpContextRISCV based on \a context_snapshot.
+ //!
+ //! \param[in] context_snapshot The context snapshot to use as source data.
+ //!
+ //! \note Valid in #kStateMutable. No mutation of context() may be done before
+ //! calling this method, and it is not normally necessary to alter
+ //! context() after calling this method.
+ void InitializeFromSnapshot(const CPUContextRISCV64* context_snapshot);
+
+ //! \brief Returns a pointer to the context structure that this object will
+ //! write.
+ //!
+ //! \attention This returns a non-`const` pointer to this object’s private
+ //! data so that a caller can populate the context structure directly.
+ //! This is done because providing setter interfaces to each field in the
+ //! context structure would be unwieldy and cumbersome. Care must be taken
+ //! to populate the context structure correctly. The context structure
+ //! must only be modified while this object is in the #kStateMutable
+ //! state.
+ MinidumpContextRISCV64* context() { return &context_; }
+
+ protected:
+ // MinidumpWritable:
+ bool WriteObject(FileWriterInterface* file_writer) override;
+
+ // MinidumpContextWriter:
+ size_t ContextSize() const override;
+
+ private:
+ MinidumpContextRISCV64 context_;
+};
+
} // namespace crashpad
#endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_WRITER_H_
Index: chromium/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc
+++ chromium/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc
@@ -175,6 +175,10 @@ std::string MinidumpMiscInfoDebugBuildSt
static constexpr char kCPU[] = "mips";
#elif defined(ARCH_CPU_MIPS64EL)
static constexpr char kCPU[] = "mips64";
+#elif defined(ARCH_CPU_RISCV32)
+ static constexpr char kCPU[] = "riscv32";
+#elif defined(ARCH_CPU_RISCV64)
+ static constexpr char kCPU[] = "riscv64";
#else
#error define kCPU for this CPU
#endif
Index: chromium/third_party/crashpad/crashpad/snapshot/capture_memory.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/capture_memory.cc
+++ chromium/third_party/crashpad/crashpad/snapshot/capture_memory.cc
@@ -117,6 +117,16 @@ void CaptureMemory::PointedToByContext(c
for (size_t i = 0; i < std::size(context.mipsel->regs); ++i) {
MaybeCaptureMemoryAround(delegate, context.mipsel->regs[i]);
}
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ if (context.architecture == kCPUArchitectureRISCV64) {
+ for (size_t i = 0; i < std::size(context.riscv64->regs); ++i) {
+ MaybeCaptureMemoryAround(delegate, context.riscv64->regs[i]);
+ }
+ } else {
+ for (size_t i = 0; i < std::size(context.riscv32->regs); ++i) {
+ MaybeCaptureMemoryAround(delegate, context.riscv32->regs[i]);
+ }
+ }
#else
#error Port.
#endif
Index: chromium/third_party/crashpad/crashpad/snapshot/cpu_architecture.h
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/cpu_architecture.h
+++ chromium/third_party/crashpad/crashpad/snapshot/cpu_architecture.h
@@ -43,7 +43,13 @@ enum CPUArchitecture {
kCPUArchitectureMIPSEL,
//! \brief 64-bit MIPSEL.
- kCPUArchitectureMIPS64EL
+ kCPUArchitectureMIPS64EL,
+
+ //! \brief 32-bit RISCV.
+ kCPUArchitectureRISCV32,
+
+ //! \brief 64-bit RISCV.
+ kCPUArchitectureRISCV64
};
} // namespace crashpad
Index: chromium/third_party/crashpad/crashpad/snapshot/cpu_context.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/cpu_context.cc
+++ chromium/third_party/crashpad/crashpad/snapshot/cpu_context.cc
@@ -226,10 +226,12 @@ bool CPUContext::Is64Bit() const {
case kCPUArchitectureX86_64:
case kCPUArchitectureARM64:
case kCPUArchitectureMIPS64EL:
+ case kCPUArchitectureRISCV64:
return true;
case kCPUArchitectureX86:
case kCPUArchitectureARM:
case kCPUArchitectureMIPSEL:
+ case kCPUArchitectureRISCV32:
return false;
default:
NOTREACHED();
Index: chromium/third_party/crashpad/crashpad/snapshot/cpu_context.h
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/cpu_context.h
+++ chromium/third_party/crashpad/crashpad/snapshot/cpu_context.h
@@ -362,6 +362,20 @@ struct CPUContextMIPS64 {
uint64_t fir;
};
+//! \brief A context structure carrying RISCV32 CPU state.
+struct CPUContextRISCV32 {
+ uint32_t regs[32];
+ uint64_t fpregs[32];
+ uint32_t fcsr;
+};
+
+//! \brief A context structure carrying RISCV64 CPU state.
+struct CPUContextRISCV64 {
+ uint64_t regs[32];
+ uint64_t fpregs[32];
+ uint32_t fcsr;
+};
+
//! \brief A context structure capable of carrying the context of any supported
//! CPU architecture.
struct CPUContext {
@@ -402,6 +416,8 @@ struct CPUContext {
CPUContextARM64* arm64;
CPUContextMIPS* mipsel;
CPUContextMIPS64* mips64;
+ CPUContextRISCV32* riscv32;
+ CPUContextRISCV64* riscv64;
};
};
Index: chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.cc
+++ chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.cc
@@ -266,6 +266,30 @@ void InitializeCPUContextARM64_OnlyFPSIM
context->fpcr = float_context.fpcr;
}
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+
+template <typename Traits>
+void InitializeCPUContextRISCV(
+ const typename Traits::SignalThreadContext& thread_context,
+ const typename Traits::SignalFloatContext& float_context,
+ typename Traits::CPUContext* context) {
+ static_assert(sizeof(context->regs) == sizeof(thread_context),
+ "registers size mismatch");
+ static_assert(sizeof(context->fpregs) == sizeof(float_context.f),
+ "fp registers size mismatch");
+ memcpy(&context->regs, &thread_context, sizeof(context->regs));
+ memcpy(&context->fpregs, &float_context.f, sizeof(context->fpregs));
+ context->fcsr = float_context.fcsr;
+}
+template void InitializeCPUContextRISCV<ContextTraits32>(
+ const ContextTraits32::SignalThreadContext& thread_context,
+ const ContextTraits32::SignalFloatContext& float_context,
+ ContextTraits32::CPUContext* context);
+template void InitializeCPUContextRISCV<ContextTraits64>(
+ const ContextTraits64::SignalThreadContext& thread_context,
+ const ContextTraits64::SignalFloatContext& float_context,
+ ContextTraits64::CPUContext* context);
+
#endif // ARCH_CPU_X86_FAMILY
} // namespace internal
Index: chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h
+++ chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h
@@ -174,6 +174,22 @@ void InitializeCPUContextMIPS(
#endif // ARCH_CPU_MIPS_FAMILY || DOXYGEN
+#if defined(ARCH_CPU_RISCV_FAMILY) || DOXYGEN
+
+//! \brief Initializes a CPUContextRISCV structure from native context
+//! structures on Linux.
+//!
+//! \param[in] thread_context The native thread context.
+//! \param[in] float_context The native float context.
+//! \param[out] context The CPUContextRISCV structure to initialize.
+template <typename Traits>
+void InitializeCPUContextRISCV(
+ const typename Traits::SignalThreadContext& thread_context,
+ const typename Traits::SignalFloatContext& float_context,
+ typename Traits::CPUContext* context);
+
+#endif // ARCH_CPU_RISCV_FAMILY || DOXYGEN
+
} // namespace internal
} // namespace crashpad
Index: chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc
+++ chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc
@@ -325,6 +325,61 @@ bool ExceptionSnapshotLinux::ReadContext
reader, context_address, context_.mips64);
}
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+
+template <typename Traits>
+static bool ReadContext(ProcessReaderLinux* reader,
+ LinuxVMAddress context_address,
+ typename Traits::CPUContext* dest_context) {
+ const ProcessMemory* memory = reader->Memory();
+
+ LinuxVMAddress gregs_address = context_address +
+ offsetof(UContext<Traits>, mcontext) +
+ offsetof(typename Traits::MContext, gregs);
+
+ typename Traits::SignalThreadContext thread_context;
+ if (!memory->Read(gregs_address, sizeof(thread_context), &thread_context)) {
+ LOG(ERROR) << "Couldn't read gregs";
+ return false;
+ }
+
+ LinuxVMAddress fpregs_address = context_address +
+ offsetof(UContext<Traits>, mcontext) +
+ offsetof(typename Traits::MContext, fpregs);
+
+ typename Traits::SignalFloatContext fp_context;
+ if (!memory->Read(fpregs_address, sizeof(fp_context), &fp_context)) {
+ LOG(ERROR) << "Couldn't read fpregs";
+ return false;
+ }
+
+ InitializeCPUContextRISCV<Traits>(thread_context, fp_context, dest_context);
+
+ return true;
+}
+
+template <>
+bool ExceptionSnapshotLinux::ReadContext<ContextTraits32>(
+ ProcessReaderLinux* reader,
+ LinuxVMAddress context_address) {
+ context_.architecture = kCPUArchitectureRISCV32;
+ context_.riscv32 = &context_union_.riscv32;
+
+ return internal::ReadContext<ContextTraits32>(
+ reader, context_address, context_.riscv32);
+}
+
+template <>
+bool ExceptionSnapshotLinux::ReadContext<ContextTraits64>(
+ ProcessReaderLinux* reader,
+ LinuxVMAddress context_address) {
+ context_.architecture = kCPUArchitectureRISCV64;
+ context_.riscv64 = &context_union_.riscv64;
+
+ return internal::ReadContext<ContextTraits64>(
+ reader, context_address, context_.riscv64);
+}
+
#endif // ARCH_CPU_X86_FAMILY
bool ExceptionSnapshotLinux::Initialize(
Index: chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h
+++ chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h
@@ -89,6 +89,9 @@ class ExceptionSnapshotLinux final : pub
#elif defined(ARCH_CPU_MIPS_FAMILY)
CPUContextMIPS mipsel;
CPUContextMIPS64 mips64;
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ CPUContextRISCV32 riscv32;
+ CPUContextRISCV64 riscv64;
#endif
} context_union_;
CPUContext context_;
Index: chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc
+++ chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc
@@ -127,6 +127,9 @@ void ProcessReaderLinux::Thread::Initial
#elif defined(ARCH_CPU_MIPS_FAMILY)
stack_pointer = reader->Is64Bit() ? thread_info.thread_context.t64.regs[29]
: thread_info.thread_context.t32.regs[29];
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ stack_pointer = reader->Is64Bit() ? thread_info.thread_context.t64.sp
+ : thread_info.thread_context.t32.sp;
#else
#error Port.
#endif
Index: chromium/third_party/crashpad/crashpad/snapshot/linux/signal_context.h
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/linux/signal_context.h
+++ chromium/third_party/crashpad/crashpad/snapshot/linux/signal_context.h
@@ -422,6 +422,67 @@ static_assert(offsetof(UContext<ContextT
"context offset mismatch");
#endif
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+
+struct MContext32 {
+ uint32_t gregs[32];
+ uint64_t fpregs[32];
+ unsigned int fcsr;
+};
+
+struct MContext64 {
+ uint64_t gregs[32];
+ uint64_t fpregs[32];
+ unsigned int fcsr;
+};
+
+struct ContextTraits32 : public Traits32 {
+ using MContext = MContext32;
+ using SignalThreadContext = ThreadContext::t32_t;
+ using SignalFloatContext = FloatContext::f32_t;
+ using CPUContext = CPUContextRISCV32;
+};
+
+struct ContextTraits64 : public Traits64 {
+ using MContext = MContext64;
+ using SignalThreadContext = ThreadContext::t64_t;
+ using SignalFloatContext = FloatContext::f64_t;
+ using CPUContext = CPUContextRISCV64;
+};
+
+template <typename Traits>
+struct UContext {
+ typename Traits::ULong flags;
+ typename Traits::Address link;
+ SignalStack<Traits> stack;
+ Sigset<Traits> sigmask;
+ char padding[128 - sizeof(sigmask)];
+ typename Traits::Char_64Only padding2[8];
+ typename Traits::MContext mcontext;
+};
+
+#if defined(ARCH_CPU_RISCV32)
+static_assert(offsetof(UContext<ContextTraits32>, mcontext) ==
+ offsetof(ucontext_t, uc_mcontext),
+ "context offset mismatch");
+static_assert(offsetof(UContext<ContextTraits32>, mcontext.gregs) ==
+ offsetof(ucontext_t, uc_mcontext.__gregs),
+ "context offset mismatch");
+static_assert(offsetof(UContext<ContextTraits32>, mcontext.fpregs) ==
+ offsetof(ucontext_t, uc_mcontext.__fpregs),
+ "context offset mismatch");
+#elif defined(ARCH_CPU_RISCV64)
+static_assert(offsetof(UContext<ContextTraits64>, mcontext) ==
+ offsetof(ucontext_t, uc_mcontext),
+ "context offset mismatch");
+static_assert(offsetof(UContext<ContextTraits64>, mcontext.gregs) ==
+ offsetof(ucontext_t, uc_mcontext.__gregs),
+ "context offset mismatch");
+static_assert(offsetof(UContext<ContextTraits64>, mcontext.fpregs) ==
+ offsetof(ucontext_t, uc_mcontext.__fpregs),
+ "context offset mismatch");
+#endif
+
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
Index: chromium/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc
+++ chromium/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc
@@ -205,6 +205,9 @@ CPUArchitecture SystemSnapshotLinux::Get
#elif defined(ARCH_CPU_MIPS_FAMILY)
return process_reader_->Is64Bit() ? kCPUArchitectureMIPS64EL
: kCPUArchitectureMIPSEL;
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ return process_reader_->Is64Bit() ? kCPUArchitectureRISCV64
+ : kCPUArchitectureRISCV32;
#else
#error port to your architecture
#endif
@@ -220,6 +223,9 @@ uint32_t SystemSnapshotLinux::CPURevisio
#elif defined(ARCH_CPU_MIPS_FAMILY)
// Not implementable on MIPS
return 0;
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ // Not implementable on RISCV
+ return 0;
#else
#error port to your architecture
#endif
@@ -240,6 +246,9 @@ std::string SystemSnapshotLinux::CPUVend
#elif defined(ARCH_CPU_MIPS_FAMILY)
// Not implementable on MIPS
return std::string();
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ // Not implementable on RISCV
+ return std::string();
#else
#error port to your architecture
#endif
@@ -373,6 +382,9 @@ bool SystemSnapshotLinux::NXEnabled() co
#elif defined(ARCH_CPU_MIPS_FAMILY)
// Not implementable on MIPS
return false;
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ // Not implementable on RISCV
+ return false;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
Index: chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc
+++ chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc
@@ -190,6 +190,22 @@ bool ThreadSnapshotLinux::Initialize(
thread.thread_info.float_context.f32,
context_.mipsel);
}
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ if (process_reader->Is64Bit()) {
+ context_.architecture = kCPUArchitectureRISCV64;
+ context_.riscv64 = &context_union_.riscv64;
+ InitializeCPUContextRISCV<ContextTraits64>(
+ thread.thread_info.thread_context.t64,
+ thread.thread_info.float_context.f64,
+ context_.riscv64);
+ } else {
+ context_.architecture = kCPUArchitectureRISCV32;
+ context_.riscv32 = &context_union_.riscv32;
+ InitializeCPUContextRISCV<ContextTraits32>(
+ thread.thread_info.thread_context.t32,
+ thread.thread_info.float_context.f32,
+ context_.riscv32);
+ }
#else
#error Port.
#endif
Index: chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h
===================================================================
--- chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h
+++ chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h
@@ -74,6 +74,9 @@ class ThreadSnapshotLinux final : public
#elif defined(ARCH_CPU_MIPS_FAMILY)
CPUContextMIPS mipsel;
CPUContextMIPS64 mips64;
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ CPUContextRISCV32 riscv32;
+ CPUContextRISCV64 riscv64;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
Index: chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc
+++ chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc
@@ -398,6 +398,51 @@ bool GetThreadArea64(pid_t tid,
return true;
}
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+
+template <typename Destination>
+bool GetRegisterSet(pid_t tid, int set, Destination* dest, bool can_log) {
+ iovec iov;
+ iov.iov_base = dest;
+ iov.iov_len = sizeof(*dest);
+ if (ptrace(PTRACE_GETREGSET, tid, reinterpret_cast<void*>(set), &iov) != 0) {
+ PLOG_IF(ERROR, can_log) << "ptrace";
+ return false;
+ }
+ if (iov.iov_len != sizeof(*dest)) {
+ LOG_IF(ERROR, can_log) << "Unexpected registers size";
+ return false;
+ }
+ return true;
+}
+
+bool GetFloatingPointRegisters32(pid_t tid,
+ FloatContext* context,
+ bool can_log) {
+ return false;
+}
+
+bool GetFloatingPointRegisters64(pid_t tid,
+ FloatContext* context,
+ bool can_log) {
+ return GetRegisterSet(tid, NT_PRFPREG, &context->f64.f, can_log);
+}
+
+bool GetThreadArea32(pid_t tid,
+ const ThreadContext& context,
+ LinuxVMAddress* address,
+ bool can_log) {
+ return false;
+}
+
+bool GetThreadArea64(pid_t tid,
+ const ThreadContext& context,
+ LinuxVMAddress* address,
+ bool can_log) {
+ *address = context.t64.tp;
+ return true;
+}
+
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
Index: chromium/third_party/crashpad/crashpad/util/linux/thread_info.h
===================================================================
--- chromium/third_party/crashpad/crashpad/util/linux/thread_info.h
+++ chromium/third_party/crashpad/crashpad/util/linux/thread_info.h
@@ -79,6 +79,40 @@ union ThreadContext {
uint32_t cp0_status;
uint32_t cp0_cause;
uint32_t padding1_;
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ // Reflects user_regs_struct in asm/ptrace.h.
+ uint32_t pc;
+ uint32_t ra;
+ uint32_t sp;
+ uint32_t gp;
+ uint32_t tp;
+ uint32_t t0;
+ uint32_t t1;
+ uint32_t t2;
+ uint32_t s0;
+ uint32_t s1;
+ uint32_t a0;
+ uint32_t a1;
+ uint32_t a2;
+ uint32_t a3;
+ uint32_t a4;
+ uint32_t a5;
+ uint32_t a6;
+ uint32_t a7;
+ uint32_t s2;
+ uint32_t s3;
+ uint32_t s4;
+ uint32_t s5;
+ uint32_t s6;
+ uint32_t s7;
+ uint32_t s8;
+ uint32_t s9;
+ uint32_t s10;
+ uint32_t s11;
+ uint32_t t3;
+ uint32_t t4;
+ uint32_t t5;
+ uint32_t t6;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
@@ -132,6 +166,40 @@ union ThreadContext {
uint64_t cp0_badvaddr;
uint64_t cp0_status;
uint64_t cp0_cause;
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ // Reflects user_regs_struct in asm/ptrace.h.
+ uint64_t pc;
+ uint64_t ra;
+ uint64_t sp;
+ uint64_t gp;
+ uint64_t tp;
+ uint64_t t0;
+ uint64_t t1;
+ uint64_t t2;
+ uint64_t s0;
+ uint64_t s1;
+ uint64_t a0;
+ uint64_t a1;
+ uint64_t a2;
+ uint64_t a3;
+ uint64_t a4;
+ uint64_t a5;
+ uint64_t a6;
+ uint64_t a7;
+ uint64_t s2;
+ uint64_t s3;
+ uint64_t s4;
+ uint64_t s5;
+ uint64_t s6;
+ uint64_t s7;
+ uint64_t s8;
+ uint64_t s9;
+ uint64_t s10;
+ uint64_t s11;
+ uint64_t t3;
+ uint64_t t4;
+ uint64_t t5;
+ uint64_t t6;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
@@ -143,11 +211,12 @@ union ThreadContext {
using NativeThreadContext = user_regs;
#elif defined(ARCH_CPU_MIPS_FAMILY)
// No appropriate NativeThreadsContext type available for MIPS
+#elif defined(ARCH_CPU_RISCV_FAMILY)
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY || ARCH_CPU_ARM64
-#if !defined(ARCH_CPU_MIPS_FAMILY)
+#if !defined(ARCH_CPU_MIPS_FAMILY) && !defined(ARCH_CPU_RISCV_FAMILY)
#if defined(ARCH_CPU_32_BITS)
static_assert(sizeof(t32_t) == sizeof(NativeThreadContext), "Size mismatch");
#else // ARCH_CPU_64_BITS
@@ -218,6 +287,9 @@ union FloatContext {
} fpregs[32];
uint32_t fpcsr;
uint32_t fpu_id;
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ uint64_t f[32];
+ uint32_t fcsr;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
@@ -252,6 +324,9 @@ union FloatContext {
double fpregs[32];
uint32_t fpcsr;
uint32_t fpu_id;
+#elif defined(ARCH_CPU_RISCV_FAMILY)
+ uint64_t f[32];
+ uint32_t fcsr;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
@@ -281,6 +356,7 @@ union FloatContext {
static_assert(sizeof(f64) == sizeof(user_fpsimd_struct), "Size mismatch");
#elif defined(ARCH_CPU_MIPS_FAMILY)
// No appropriate floating point context native type for available MIPS.
+#elif defined(ARCH_CPU_RISCV_FAMILY)
#else
#error Port.
#endif // ARCH_CPU_X86
Index: chromium/third_party/crashpad/crashpad/util/net/http_transport_libcurl.cc
===================================================================
--- chromium/third_party/crashpad/crashpad/util/net/http_transport_libcurl.cc
+++ chromium/third_party/crashpad/crashpad/util/net/http_transport_libcurl.cc
@@ -237,6 +237,8 @@ std::string UserAgent() {
#elif defined(ARCH_CPU_BIG_ENDIAN)
static constexpr char arch[] = "aarch64_be";
#endif
+#elif defined(ARCH_CPU_RISCV64)
+ static constexpr char arch[] = "riscv64";
#else
#error Port
#endif

43
riscv-dav1d.patch Normal file
View File

@ -0,0 +1,43 @@
Index: chromium/third_party/dav1d/config/linux/riscv64/config.h
===================================================================
--- /dev/null
+++ chromium/third_party/dav1d/config/linux/riscv64/config.h
@@ -0,0 +1,38 @@
+/*
+ * Autogenerated by the Meson build system.
+ * Do not edit, your changes will be lost.
+ */
+
+#pragma once
+
+#define ARCH_AARCH64 0
+
+#define ARCH_ARM 0
+
+#define ARCH_PPC64LE 0
+
+#define ARCH_X86 0
+
+#define ARCH_X86_32 0
+
+#define ARCH_X86_64 0
+
+#define CONFIG_16BPC 1
+
+#define CONFIG_8BPC 1
+
+// #define CONFIG_LOG 1 -- Logging is controlled by Chromium
+
+#define ENDIANNESS_BIG 0
+
+#define HAVE_ASM 0
+
+#define HAVE_AS_FUNC 0
+
+#define HAVE_CLOCK_GETTIME 1
+
+#define HAVE_GETAUXVAL 1
+
+#define HAVE_POSIX_MEMALIGN 1
+
+#define HAVE_UNISTD_H 1

1955
riscv-sandbox.patch Normal file
View File

File diff suppressed because it is too large Load Diff