5636aff5b1
- target/i386: csv: Support inject secret for CSV3 guest only if the extension is enabled
- target/i386: csv: Support load kernel hashes for CSV3 guest only if the extension is enabled
- target/i386: csv: Request to set private memory of CSV3 guest if the extension is enabled
- target/i386: kvm: Support to get and enable extensions for Hygon CoCo guest
- qapi/qom,target/i386: csv-guest: Introduce secret-header-file=str and secret-file=str options
- bakcend: VirtCCA:resolve hugepage memory waste issue in vhost-user scenario
- parallels: fix ext_off assertion failure due to overflow
- backends/cryptodev-vhost-user: Fix local_error leaks
- hw/usb/hcd-ehci: Fix debug printf format string
- target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
- target/riscv/vector_helper.c: optimize loops in ldst helpers
- target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
- target/hexagon: don't look for static glib
- virtio-net: Fix network stall at the host side waiting for kick
- Add if condition to avoid assertion failed error in blockdev_init
- target/arm: Use float_status copy in sme_fmopa_s
- target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
- target/arm: Reinstate "vfp" property on AArch32 CPUs
- target/i386/cpu: Fix notes for CPU models
- target/arm: LDAPR should honour SCTLR_ELx.nAA
- target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()
- hvf: remove unused but set variable
- hw/misc/nrf51_rng: Don't use BIT_MASK() when we mean BIT()
- Avoid taking address of out-of-bounds array index
- target/arm: Fix VCMLA Dd, Dn, Dm[idx]
- target/arm: Fix UMOPA/UMOPS of 16-bit values
- target/arm: Fix SVE/SME gross MTE suppression checks
- target/arm: Fix nregs computation in do_{ld,st}_zpa
- crypto: fix error check on gcry_md_open
- Change vmstate_cpuhp_sts vmstateDescription version_id
- hw/pci: Remove unused pci_irq_pulse() method
- hw/intc: Don't clear pending bits on IRQ lowering
- target/arm: Drop user-only special case in sve_stN_r
- migration: Ensure vmstate_save() sets errp
- target/i386: fix hang when using slow path for ptw_setl
- contrib/plugins: add compat for g_memdup2
- hw/audio/hda: fix memory leak on audio setup
- crypto: perform runtime check for hash/hmac support in gcrypt
- target/arm: Fix incorrect aa64_tidcp1 feature check
- target/arm: fix exception syndrome for AArch32 bkpt insn
- target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
- linux-user: Print tid not pid with strace
- target/arm: Fix A64 scalar SQSHRN and SQRSHRN
- target/arm: Don't assert for 128-bit tile accesses when SVL is 128
- hw/timer/exynos4210_mct: fix possible int overflow
- target/arm: Avoid shifts by -1 in tszimm_shr() and tszimm_shl()
- hw/audio/virtio-snd: Always use little endian audio format
- target/riscv: Fix vcompress with rvv_ta_all_1s
- usb-hub: Fix handling port power control messages
Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
(cherry picked from commit d4a20b24ff377fd07fcbf2b72eecaf07a3ac4cc0)
62 lines
2.4 KiB
Diff
62 lines
2.4 KiB
Diff
From 9e0b6c4df61aced66c5b3ee9ca93c6ac33868dc0 Mon Sep 17 00:00:00 2001
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From: gubin <gubin_yewu@cmss.chinamobile.com>
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Date: Thu, 28 Nov 2024 14:06:44 +0800
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Subject: [PATCH] target/arm: Don't assert for 128-bit tile accesses when SVL
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is 128
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cherry-pick from 56f1c0db928aae0b83fd91c89ddb226b137e2b21
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For an instruction which accesses a 128-bit element tile when
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the SVL is also 128 (for example MOV z0.Q, p0/M, ZA0H.Q[w0,0]),
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we will assert in get_tile_rowcol():
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qemu-system-aarch64: ../../tcg/tcg-op.c:926: tcg_gen_deposit_z_i32: Assertion `len > 0' failed.
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This happens because we calculate
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len = ctz32(streaming_vec_reg_size(s)) - esz;$
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but if the SVL and the element size are the same len is 0, and
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the deposit operation asserts.
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In this case the ZA storage contains exactly one 128 bit
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element ZA tile, and the horizontal or vertical slice is just
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that tile. This means that regardless of the index value in
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the Ws register, we always access that tile. (In pseudocode terms,
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we calculate (index + offset) MOD 1, which is 0.)
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Special case the len == 0 case to avoid hitting the assertion
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in tcg_gen_deposit_z_i32().
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20240722172957.1041231-2-peter.maydell@linaro.org
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Signed-off-by: gubin <gubin_yewu@cmss.chinamobile.com>
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---
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target/arm/tcg/translate-sme.c | 10 +++++++++-
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1 file changed, 9 insertions(+), 1 deletion(-)
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diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
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index 8f0dfc884e..1e89516736 100644
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--- a/target/arm/tcg/translate-sme.c
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+++ b/target/arm/tcg/translate-sme.c
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@@ -49,7 +49,15 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
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/* Prepare a power-of-two modulo via extraction of @len bits. */
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len = ctz32(streaming_vec_reg_size(s)) - esz;
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- if (vertical) {
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+ if (!len) {
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+ /*
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+ * SVL is 128 and the element size is 128. There is exactly
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+ * one 128x128 tile in the ZA storage, and so we calculate
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+ * (Rs + imm) MOD 1, which is always 0. We need to special case
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+ * this because TCG doesn't allow deposit ops with len 0.
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+ */
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+ tcg_gen_movi_i32(tmp, 0);
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+ } else if (vertical) {
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/*
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* Compute the byte offset of the index within the tile:
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* (index % (svl / size)) * size
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--
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2.41.0.windows.1
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