7428290d4a
- fix compile error on loongarch
- hw/loongarch: fix cpu hotplug reset
- hw/loongarch/boot: Use warn_report when no kernel filename
- hw/loongarch: clean code
- hw/loongarch: Add KVM pch msi device support
- hw/loongarch: Add KVM pch pic device support
- hw/loongarch: Add KVM extioi device support
- hw/loongarch: Add KVM IPI device support
- hw/loongarch/virt: Update the ACPI table for hotplug cpu
- hw/loongarch/virt: Add basic CPU plug support
- hw/loongarch/virt: Add CPU topology support
- accel/kvm/kvm-all: Fixes the missing break in vCPU unpark logic
- gdbstub: Add helper function to unregister GDB register space
- physmem: Add helper function to destroy CPU AddressSpace
- hw/acpi: Update CPUs AML with cpu-(ctrl)dev change
- hw/acpi: Update ACPI GED framework to support vCPU Hotplug
- hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file
- accel/kvm: Extract common KVM vCPU {creation,parking} code
- target/loongarch: Add steal time support on migration
- linux-headers: loongarch: Add kvm_para.h and unistd_64.h
- target/loongarch/kvm: Implement LoongArch PMU extension
- target/loongarch: Implement lbt registers save/restore function
- target/loongarch: Add loongson binary translation feature
- sync loongarch linux-headers
- target/loongarch: Avoid bits shift exceeding width of bool type
- target/loongarch: Use explicit little-endian LD/ST API
- target/loongarch: fix -Werror=maybe-uninitialized false-positive
- target/loongarch: Support QMP dump-guest-memory
- target/loongarch/kvm: Add vCPU reset function
- target/loongarch: Add compatible support about VM reboot
- target/loongarch: Fix cpu_reset set wrong CSR_CRMD
- target/loongarch: Set CSR_PRCFG1 and CSR_PRCFG2 values
- target/loongarch: Remove avail_64 in trans_srai_w() and simplify it
- target/loongarch/kvm: Add software breakpoint support
- target/loongarch: Add loongarch vector property unconditionally
- target/loongarch/kvm: Fix VM recovery from disk failures
- target/loongarch: Put cpucfg operation before CSR register
- target/loongarch: Add TCG macro in structure CPUArchState
- hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
- hw/loongarch/virt: Add FDT table support with acpi ged pm register
- hw/loongarch/virt: Add description for virt machine type
- hw/loongarch: Add acpi SPCR table support
- hw/loongarch: virt: pass random seed to fdt
- hw/loongarch: virt: support up to 4 serial ports
- hw/loongarch: Remove default enable with VIRTIO_VGA device
- hw/loongarch: Fix length for lowram in ACPI SRAT
- hw/loongarch/virt: Remove unused assignment
- hw/loongarch: Change the tpm support by default
- hw/loongarch/boot.c: fix out-of-bound reading
- hw/loongarch/virt: Use MemTxAttrs interface for misc ops
- tests/libqos: Add loongarch virt machine node
- hw/loongarch: Remove minimum and default memory size
- hw/loongarch: Refine system dram memory region
- hw/loongarch: Refine fwcfg memory map
- hw/loongarch: Refine fadt memory table for numa memory
- hw/loongarch: Refine acpi srat table for numa memory
- hw/loongarch: Add VM mode in IOCSR feature register in kvm mode
- hw/loongarch: Refine default numa id calculation
- hw/loongarch: Rename LoongArchMachineState with LoongArchVirtMachineState
- hw/loongarch: Rename LOONGARCH_MACHINE with LOONGARCH_VIRT_MACHINE
- hw/loongarch: move memory map to boot.c
- loongarch: switch boards to "default y"
- hw/loongarch: Add cells missing from rtc node
- hw/loongarch: Add cells missing from uart node
- hw/loongarch: fdt remove unused irqchip node
- hw/loongarch: fdt adds pcie irq_map node
- hw/loongarch: fdt adds pch_msi Controller
- hw/loongarch: fdt adds pch_pic Controller
- hw/loongarch: fdt adds Extend I/O Interrupt Controller
- hw/loongarch: fdt adds cpu interrupt controller node
- hw/loongarch: Init efi_fdt table
- hw/loongarch: Init efi_initrd table
- hw/loongarch: Init efi_boot_memmap table
- hw/loongarch: Init efi_system_table
- hw/loongarch: Add init_cmdline
- hw/loongarch: Add slave cpu boot_code
- hw/loongarch: Add load initrd
- hw/loongarch: Move boot functions to boot.c
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
(cherry picked from commit 04ca9e6c8ff19630116722240ae0136cea831c5c)
104 lines
4.3 KiB
Diff
104 lines
4.3 KiB
Diff
From 2e3e7bcf92284f41c08fce29f6c6d45849721e71 Mon Sep 17 00:00:00 2001
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From: Song Gao <gaosong@loongson.cn>
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Date: Fri, 26 Apr 2024 17:15:37 +0800
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Subject: [PATCH 03/78] hw/loongarch: Add slave cpu boot_code
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Load the slave CPU boot code at pflash0 and set
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the slave CPU elf_address to VIRT_FLASH0_BASE.
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Signed-off-by: Song Gao <gaosong@loongson.cn>
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Reviewed-by: Bibo Mao <maobibo@loongson.cn>
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Message-Id: <20240426091551.2397867-4-gaosong@loongson.cn>
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Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
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---
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hw/loongarch/boot.c | 62 ++++++++++++++++++++++++++++++++++++++++++++-
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1 file changed, 61 insertions(+), 1 deletion(-)
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diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
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index a5135fe542..fb6effbaff 100644
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--- a/hw/loongarch/boot.c
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+++ b/hw/loongarch/boot.c
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@@ -15,6 +15,54 @@
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#include "sysemu/reset.h"
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#include "sysemu/qtest.h"
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+static const unsigned int slave_boot_code[] = {
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+ /* Configure reset ebase. */
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+ 0x0400302c, /* csrwr $t0, LOONGARCH_CSR_EENTRY */
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+
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+ /* Disable interrupt. */
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+ 0x0380100c, /* ori $t0, $zero,0x4 */
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+ 0x04000180, /* csrxchg $zero, $t0, LOONGARCH_CSR_CRMD */
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+
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+ /* Clear mailbox. */
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+ 0x1400002d, /* lu12i.w $t1, 1(0x1) */
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+ 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
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+ 0x06481da0, /* iocsrwr.d $zero, $t1 */
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+
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+ /* Enable IPI interrupt. */
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+ 0x1400002c, /* lu12i.w $t0, 1(0x1) */
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+ 0x0400118c, /* csrxchg $t0, $t0, LOONGARCH_CSR_ECFG */
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+ 0x02fffc0c, /* addi.d $t0, $r0,-1(0xfff) */
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+ 0x1400002d, /* lu12i.w $t1, 1(0x1) */
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+ 0x038011ad, /* ori $t1, $t1, CORE_EN_OFF */
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+ 0x064819ac, /* iocsrwr.w $t0, $t1 */
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+ 0x1400002d, /* lu12i.w $t1, 1(0x1) */
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+ 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
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+
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+ /* Wait for wakeup <.L11>: */
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+ 0x06488000, /* idle 0x0 */
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+ 0x03400000, /* andi $zero, $zero, 0x0 */
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+ 0x064809ac, /* iocsrrd.w $t0, $t1 */
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+ 0x43fff59f, /* beqz $t0, -12(0x7ffff4) # 48 <.L11> */
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+
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+ /* Read and clear IPI interrupt. */
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+ 0x1400002d, /* lu12i.w $t1, 1(0x1) */
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+ 0x064809ac, /* iocsrrd.w $t0, $t1 */
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+ 0x1400002d, /* lu12i.w $t1, 1(0x1) */
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+ 0x038031ad, /* ori $t1, $t1, CORE_CLEAR_OFF */
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+ 0x064819ac, /* iocsrwr.w $t0, $t1 */
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+
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+ /* Disable IPI interrupt. */
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+ 0x1400002c, /* lu12i.w $t0, 1(0x1) */
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+ 0x04001180, /* csrxchg $zero, $t0, LOONGARCH_CSR_ECFG */
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+
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+ /* Read mail buf and jump to specified entry */
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+ 0x1400002d, /* lu12i.w $t1, 1(0x1) */
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+ 0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
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+ 0x06480dac, /* iocsrrd.d $t0, $t1 */
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+ 0x00150181, /* move $ra, $t0 */
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+ 0x4c000020, /* jirl $zero, $ra,0 */
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+};
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+
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static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
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{
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return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
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@@ -125,11 +173,23 @@ static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
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}
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}
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+ /* Load slave boot code at pflash0 . */
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+ void *boot_code = g_malloc0(VIRT_FLASH0_SIZE);
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+ memcpy(boot_code, &slave_boot_code, sizeof(slave_boot_code));
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+ rom_add_blob_fixed("boot_code", boot_code, VIRT_FLASH0_SIZE, VIRT_FLASH0_BASE);
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+
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CPU_FOREACH(cs) {
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lacpu = LOONGARCH_CPU(cs);
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lacpu->env.load_elf = true;
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- lacpu->env.elf_address = kernel_addr;
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+ if (cs == first_cpu) {
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+ lacpu->env.elf_address = kernel_addr;
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+ } else {
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+ lacpu->env.elf_address = VIRT_FLASH0_BASE;
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+ }
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+ lacpu->env.boot_info = info;
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}
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+
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+ g_free(boot_code);
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}
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void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info)
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--
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2.39.1
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