Chen Qun dadccf3646 spec: Update patch and changelog with !161 x86: new CPU models for Denverton (server-class Atom-based SoC), Snowridge, and Dhyana !161
target/i386: Introduce Denverton CPU model
target/i386: Add Snowridge-v2 (no MPX) CPU model
i386: Add CPUID bit for CLZERO and XSAVEERPTR

Signed-off-by: Chen Qun<kuhn.chenqun@huawei.com>
2021-07-20 16:27:34 +08:00
2019-11-06 19:50:55 +08:00
2019-09-30 11:15:46 -04:00
2019-09-30 11:15:46 -04:00
2020-06-01 09:13:38 +00:00
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