0c39e725b0
To support CPU feature in AArch64, we need to move some field from ARMCPU to ARMISARegisters, add more definitions of ID fields, and add suport query-cpu-model-expansion qmp command. Let's backport upstream patches to do these. Signed-off-by: Peng Liang <liangpeng10@huawei.com>
37 lines
1.2 KiB
Diff
37 lines
1.2 KiB
Diff
From f54cdca97bf86f5ca1df8471bc229b89797b287e Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Fri, 14 Feb 2020 17:51:02 +0000
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Subject: [PATCH 04/13] target/arm: Use FIELD macros for clearing ID_DFR0
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PERFMON field
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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We already define FIELD macros for ID_DFR0, so use them in the
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one place where we're doing direct bit value manipulation.
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20200214175116.9164-8-peter.maydell@linaro.org
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---
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target/arm/cpu.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/cpu.c b/target/arm/cpu.c
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index dbd05e01..6ad211b1 100644
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--- a/target/arm/cpu.c
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+++ b/target/arm/cpu.c
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@@ -1523,7 +1523,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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#endif
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} else {
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cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
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- cpu->id_dfr0 &= ~(0xf << 24);
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+ cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0);
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cpu->pmceid0 = 0;
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cpu->pmceid1 = 0;
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}
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--
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2.25.1
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