- fix compile error on loongarch
- hw/loongarch: fix cpu hotplug reset
- hw/loongarch/boot: Use warn_report when no kernel filename
- hw/loongarch: clean code
- hw/loongarch: Add KVM pch msi device support
- hw/loongarch: Add KVM pch pic device support
- hw/loongarch: Add KVM extioi device support
- hw/loongarch: Add KVM IPI device support
- hw/loongarch/virt: Update the ACPI table for hotplug cpu
- hw/loongarch/virt: Add basic CPU plug support
- hw/loongarch/virt: Add CPU topology support
- accel/kvm/kvm-all: Fixes the missing break in vCPU unpark logic
- gdbstub: Add helper function to unregister GDB register space
- physmem: Add helper function to destroy CPU AddressSpace
- hw/acpi: Update CPUs AML with cpu-(ctrl)dev change
- hw/acpi: Update ACPI GED framework to support vCPU Hotplug
- hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file
- accel/kvm: Extract common KVM vCPU {creation,parking} code
- target/loongarch: Add steal time support on migration
- linux-headers: loongarch: Add kvm_para.h and unistd_64.h
- target/loongarch/kvm: Implement LoongArch PMU extension
- target/loongarch: Implement lbt registers save/restore function
- target/loongarch: Add loongson binary translation feature
- sync loongarch linux-headers
- target/loongarch: Avoid bits shift exceeding width of bool type
- target/loongarch: Use explicit little-endian LD/ST API
- target/loongarch: fix -Werror=maybe-uninitialized false-positive
- target/loongarch: Support QMP dump-guest-memory
- target/loongarch/kvm: Add vCPU reset function
- target/loongarch: Add compatible support about VM reboot
- target/loongarch: Fix cpu_reset set wrong CSR_CRMD
- target/loongarch: Set CSR_PRCFG1 and CSR_PRCFG2 values
- target/loongarch: Remove avail_64 in trans_srai_w() and simplify it
- target/loongarch/kvm: Add software breakpoint support
- target/loongarch: Add loongarch vector property unconditionally
- target/loongarch/kvm: Fix VM recovery from disk failures
- target/loongarch: Put cpucfg operation before CSR register
- target/loongarch: Add TCG macro in structure CPUArchState
- hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
- hw/loongarch/virt: Add FDT table support with acpi ged pm register
- hw/loongarch/virt: Add description for virt machine type
- hw/loongarch: Add acpi SPCR table support
- hw/loongarch: virt: pass random seed to fdt
- hw/loongarch: virt: support up to 4 serial ports
- hw/loongarch: Remove default enable with VIRTIO_VGA device
- hw/loongarch: Fix length for lowram in ACPI SRAT
- hw/loongarch/virt: Remove unused assignment
- hw/loongarch: Change the tpm support by default
- hw/loongarch/boot.c: fix out-of-bound reading
- hw/loongarch/virt: Use MemTxAttrs interface for misc ops
- tests/libqos: Add loongarch virt machine node
- hw/loongarch: Remove minimum and default memory size
- hw/loongarch: Refine system dram memory region
- hw/loongarch: Refine fwcfg memory map
- hw/loongarch: Refine fadt memory table for numa memory
- hw/loongarch: Refine acpi srat table for numa memory
- hw/loongarch: Add VM mode in IOCSR feature register in kvm mode
- hw/loongarch: Refine default numa id calculation
- hw/loongarch: Rename LoongArchMachineState with LoongArchVirtMachineState
- hw/loongarch: Rename LOONGARCH_MACHINE with LOONGARCH_VIRT_MACHINE
- hw/loongarch: move memory map to boot.c
- loongarch: switch boards to "default y"
- hw/loongarch: Add cells missing from rtc node
- hw/loongarch: Add cells missing from uart node
- hw/loongarch: fdt remove unused irqchip node
- hw/loongarch: fdt adds pcie irq_map node
- hw/loongarch: fdt adds pch_msi Controller
- hw/loongarch: fdt adds pch_pic Controller
- hw/loongarch: fdt adds Extend I/O Interrupt Controller
- hw/loongarch: fdt adds cpu interrupt controller node
- hw/loongarch: Init efi_fdt table
- hw/loongarch: Init efi_initrd table
- hw/loongarch: Init efi_boot_memmap table
- hw/loongarch: Init efi_system_table
- hw/loongarch: Add init_cmdline
- hw/loongarch: Add slave cpu boot_code
- hw/loongarch: Add load initrd
- hw/loongarch: Move boot functions to boot.c
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
(cherry picked from commit 04ca9e6c8ff19630116722240ae0136cea831c5c)
201 lines
6.3 KiB
Diff
201 lines
6.3 KiB
Diff
From 962f649aa5a06169f0ac23f61e273f0860942ebb Mon Sep 17 00:00:00 2001
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From: Bibo Mao <maobibo@loongson.cn>
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Date: Sun, 29 Sep 2024 15:04:04 +0800
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Subject: [PATCH 57/78] target/loongarch: Add loongson binary translation
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feature
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Loongson Binary Translation (LBT) is used to accelerate binary
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translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
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eflags (eflags) and x87 fpu stack pointer (ftop).
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Now LBT feature is added in kvm mode, not supported in TCG mode since
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it is not emulated. Feature variable lbt is added with OnOffAuto type,
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If lbt feature is not supported with KVM host, it reports error if there
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is lbt=on command line.
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If there is no any command line about lbt parameter, it checks whether
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KVM host supports lbt feature and set the corresponding value in cpucfg.
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Signed-off-by: Bibo Mao <maobibo@loongson.cn>
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Reviewed-by: Song Gao <gaosong@loongson.cn>
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Message-Id: <20240929070405.235200-2-maobibo@loongson.cn>
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Signed-off-by: Song Gao <gaosong@loongson.cn>
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Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
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---
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target/loongarch/cpu.c | 20 ++++++++++
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target/loongarch/cpu.h | 6 +++
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target/loongarch/kvm/kvm.c | 57 ++++++++++++++++++++++++++-
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target/loongarch/loongarch-qmp-cmds.c | 2 +-
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4 files changed, 83 insertions(+), 2 deletions(-)
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diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
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index d6a13de901..a57067938d 100644
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--- a/target/loongarch/cpu.c
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+++ b/target/loongarch/cpu.c
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@@ -737,6 +737,18 @@ static void loongarch_set_pmnum(Object *obj, Visitor *v,
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}
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}
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+static bool loongarch_get_lbt(Object *obj, Error **errp)
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+{
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+ return LOONGARCH_CPU(obj)->lbt != ON_OFF_AUTO_OFF;
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+}
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+
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+static void loongarch_set_lbt(Object *obj, bool value, Error **errp)
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+{
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+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
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+
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+ cpu->lbt = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
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+}
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+
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void loongarch_cpu_post_init(Object *obj)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(obj);
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@@ -756,6 +768,14 @@ void loongarch_cpu_post_init(Object *obj)
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loongarch_set_pmnum, NULL,
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(void *)&value);
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}
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+
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+ cpu->lbt = ON_OFF_AUTO_AUTO;
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+ object_property_add_bool(obj, "lbt", loongarch_get_lbt,
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+ loongarch_set_lbt);
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+ object_property_set_description(obj, "lbt",
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+ "Set off to disable Binary Tranlation.");
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+ } else {
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+ cpu->lbt = ON_OFF_AUTO_OFF;
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}
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}
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diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
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index 19bcad28de..3e2bcbf608 100644
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--- a/target/loongarch/cpu.h
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+++ b/target/loongarch/cpu.h
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@@ -155,6 +155,7 @@ FIELD(CPUCFG2, LLFTP_VER, 15, 3)
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FIELD(CPUCFG2, LBT_X86, 18, 1)
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FIELD(CPUCFG2, LBT_ARM, 19, 1)
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FIELD(CPUCFG2, LBT_MIPS, 20, 1)
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+FIELD(CPUCFG2, LBT_ALL, 18, 3)
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FIELD(CPUCFG2, LSPW, 21, 1)
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FIELD(CPUCFG2, LAM, 22, 1)
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@@ -285,6 +286,10 @@ struct LoongArchTLB {
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typedef struct LoongArchTLB LoongArchTLB;
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#endif
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+enum loongarch_features {
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+ LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
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+};
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+
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typedef struct CPUArchState {
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uint64_t gpr[32];
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uint64_t pc;
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@@ -388,6 +393,7 @@ struct ArchCPU {
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CPULoongArchState env;
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QEMUTimer timer;
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uint32_t phy_id;
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+ OnOffAuto lbt;
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/* 'compatible' string for this CPU for Linux device trees */
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const char *dtb_compatible;
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diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
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index 90c8379c46..567404bdb5 100644
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--- a/target/loongarch/kvm/kvm.c
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+++ b/target/loongarch/kvm/kvm.c
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@@ -9,6 +9,7 @@
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#include <sys/ioctl.h>
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#include <linux/kvm.h>
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+#include "qapi/error.h"
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#include "qemu/timer.h"
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#include "qemu/error-report.h"
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#include "qemu/main-loop.h"
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@@ -786,17 +787,71 @@ static void kvm_loongarch_vm_stage_change(void *opaque, bool running,
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}
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}
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+static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
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+{
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+ int ret;
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+ struct kvm_device_attr attr;
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+
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+ switch (feature) {
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+ case LOONGARCH_FEATURE_LBT:
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+ /*
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+ * Return all if all the LBT features are supported such as:
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+ * KVM_LOONGARCH_VM_FEAT_X86BT
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+ * KVM_LOONGARCH_VM_FEAT_ARMBT
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+ * KVM_LOONGARCH_VM_FEAT_MIPSBT
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+ */
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+ attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
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+ attr.attr = KVM_LOONGARCH_VM_FEAT_X86BT;
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+ ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
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+ attr.attr = KVM_LOONGARCH_VM_FEAT_ARMBT;
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+ ret |= kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
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+ attr.attr = KVM_LOONGARCH_VM_FEAT_MIPSBT;
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+ ret |= kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
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+ return (ret == 0);
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+ default:
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+ return false;
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+ }
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+}
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+
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+static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
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+{
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+ CPULoongArchState *env = cpu_env(cs);
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+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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+ bool kvm_supported;
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+
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+ kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LBT);
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+ if (cpu->lbt == ON_OFF_AUTO_ON) {
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+ if (kvm_supported) {
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+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LBT_ALL, 7);
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+ } else {
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+ error_setg(errp, "'lbt' feature not supported by KVM on this host");
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+ return -ENOTSUP;
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+ }
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+ } else if ((cpu->lbt == ON_OFF_AUTO_AUTO) && kvm_supported) {
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+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LBT_ALL, 7);
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+ }
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+
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+ return 0;
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+}
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+
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int kvm_arch_init_vcpu(CPUState *cs)
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{
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uint64_t val;
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+ int ret;
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+ Error *local_err = NULL;
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+ ret = 0;
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qemu_add_vm_change_state_handler(kvm_loongarch_vm_stage_change, cs);
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if (!kvm_get_one_reg(cs, KVM_REG_LOONGARCH_DEBUG_INST, &val)) {
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brk_insn = val;
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}
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- return 0;
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+ ret = kvm_cpu_check_lbt(cs, &local_err);
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+ if (ret < 0) {
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+ error_report_err(local_err);
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+ }
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+ return ret;
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}
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int kvm_arch_destroy_vcpu(CPUState *cs)
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diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loongarch-qmp-cmds.c
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index 2612f43de9..644b528824 100644
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--- a/target/loongarch/loongarch-qmp-cmds.c
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+++ b/target/loongarch/loongarch-qmp-cmds.c
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@@ -42,7 +42,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
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}
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static const char *cpu_model_advertised_features[] = {
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- "lsx", "lasx", "pmu", "pmnum", NULL
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+ "lsx", "lasx", "lbt", "pmu", "pmnum", NULL
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};
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CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
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--
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2.39.1
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