5636aff5b1
- target/i386: csv: Support inject secret for CSV3 guest only if the extension is enabled
- target/i386: csv: Support load kernel hashes for CSV3 guest only if the extension is enabled
- target/i386: csv: Request to set private memory of CSV3 guest if the extension is enabled
- target/i386: kvm: Support to get and enable extensions for Hygon CoCo guest
- qapi/qom,target/i386: csv-guest: Introduce secret-header-file=str and secret-file=str options
- bakcend: VirtCCA:resolve hugepage memory waste issue in vhost-user scenario
- parallels: fix ext_off assertion failure due to overflow
- backends/cryptodev-vhost-user: Fix local_error leaks
- hw/usb/hcd-ehci: Fix debug printf format string
- target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
- target/riscv/vector_helper.c: optimize loops in ldst helpers
- target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
- target/hexagon: don't look for static glib
- virtio-net: Fix network stall at the host side waiting for kick
- Add if condition to avoid assertion failed error in blockdev_init
- target/arm: Use float_status copy in sme_fmopa_s
- target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
- target/arm: Reinstate "vfp" property on AArch32 CPUs
- target/i386/cpu: Fix notes for CPU models
- target/arm: LDAPR should honour SCTLR_ELx.nAA
- target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()
- hvf: remove unused but set variable
- hw/misc/nrf51_rng: Don't use BIT_MASK() when we mean BIT()
- Avoid taking address of out-of-bounds array index
- target/arm: Fix VCMLA Dd, Dn, Dm[idx]
- target/arm: Fix UMOPA/UMOPS of 16-bit values
- target/arm: Fix SVE/SME gross MTE suppression checks
- target/arm: Fix nregs computation in do_{ld,st}_zpa
- crypto: fix error check on gcry_md_open
- Change vmstate_cpuhp_sts vmstateDescription version_id
- hw/pci: Remove unused pci_irq_pulse() method
- hw/intc: Don't clear pending bits on IRQ lowering
- target/arm: Drop user-only special case in sve_stN_r
- migration: Ensure vmstate_save() sets errp
- target/i386: fix hang when using slow path for ptw_setl
- contrib/plugins: add compat for g_memdup2
- hw/audio/hda: fix memory leak on audio setup
- crypto: perform runtime check for hash/hmac support in gcrypt
- target/arm: Fix incorrect aa64_tidcp1 feature check
- target/arm: fix exception syndrome for AArch32 bkpt insn
- target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
- linux-user: Print tid not pid with strace
- target/arm: Fix A64 scalar SQSHRN and SQRSHRN
- target/arm: Don't assert for 128-bit tile accesses when SVL is 128
- hw/timer/exynos4210_mct: fix possible int overflow
- target/arm: Avoid shifts by -1 in tszimm_shr() and tszimm_shl()
- hw/audio/virtio-snd: Always use little endian audio format
- target/riscv: Fix vcompress with rvv_ta_all_1s
- usb-hub: Fix handling port power control messages
Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
(cherry picked from commit d4a20b24ff377fd07fcbf2b72eecaf07a3ac4cc0)
57 lines
2.4 KiB
Diff
57 lines
2.4 KiB
Diff
From 626103c76d0d8db8dee3f613b6e3159c8ddd5a57 Mon Sep 17 00:00:00 2001
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From: gubin <gubin_yewu@cmss.chinamobile.com>
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Date: Thu, 2 Jan 2025 10:25:00 +0800
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Subject: [PATCH] target/arm: LDAPR should honour SCTLR_ELx.nAA
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cherry-pick from 25489b521b61b874c4c6583956db0012a3674e3a
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In commit c1a1f80518d360b when we added the FEAT_LSE2 relaxations to
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the alignment requirements for atomic and ordered loads and stores,
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we didn't quite get it right for LDAPR/LDAPRH/LDAPRB with no
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immediate offset. These instructions were handled in the old decoder
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as part of disas_ldst_atomic(), but unlike all the other insns that
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function decoded (LDADD, LDCLR, etc) these insns are "ordered", not
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"atomic", so they should be using check_ordered_align() rather than
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check_atomic_align(). Commit c1a1f80518d360b used
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check_atomic_align() regardless for everything in
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disas_ldst_atomic(). We then carried that incorrect check over in
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the decodetree conversion, where LDAPR/LDAPRH/LDAPRB are now handled
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by trans_LDAPR().
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The effect is that when FEAT_LSE2 is implemented, these instructions
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don't honour the SCTLR_ELx.nAA bit and will generate alignment
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faults when they should not.
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(The LDAPR insns with an immediate offset were in disas_ldst_ldapr_stlr()
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and then in trans_LDAPR_i() and trans_STLR_i(), and have always used
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the correct check_ordered_align().)
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Use check_ordered_align() in trans_LDAPR().
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Cc: qemu-stable@nongnu.org
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Fixes: c1a1f80518d360b ("target/arm: Relax ordered/atomic alignment checks for LSE2")
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20240709134504.3500007-3-peter.maydell@linaro.org
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Signed-off-by: gubin <gubin_yewu@cmss.chinamobile.com>
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---
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target/arm/tcg/translate-a64.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
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index a05182b57f..5beac07b60 100644
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--- a/target/arm/tcg/translate-a64.c
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+++ b/target/arm/tcg/translate-a64.c
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@@ -3306,7 +3306,7 @@ static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a)
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if (a->rn == 31) {
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gen_check_sp_alignment(s);
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}
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- mop = check_atomic_align(s, a->rn, a->sz);
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+ mop = check_ordered_align(s, a->rn, 0, false, a->sz);
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), false,
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a->rn != 31, mop);
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/*
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--
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2.41.0.windows.1
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