0c39e725b0
To support CPU feature in AArch64, we need to move some field from ARMCPU to ARMISARegisters, add more definitions of ID fields, and add suport query-cpu-model-expansion qmp command. Let's backport upstream patches to do these. Signed-off-by: Peng Liang <liangpeng10@huawei.com>
88 lines
3.4 KiB
Diff
88 lines
3.4 KiB
Diff
From 3451fb922aa7b0fe532e508ca13d4ab4b3ec75bf Mon Sep 17 00:00:00 2001
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Sat, 8 Feb 2020 12:58:13 +0000
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Subject: [PATCH 02/13] target/arm: Add ID_AA64MMFR2_EL1
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Add definitions for all of the fields, up to ARMv8.5.
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Convert the existing RESERVED register to a full register.
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Query KVM for the value of the register for the host.
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20200208125816.14954-18-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/cpu.h | 17 +++++++++++++++++
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target/arm/helper.c | 4 ++--
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target/arm/kvm64.c | 2 ++
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3 files changed, 21 insertions(+), 2 deletions(-)
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index fe310828..3e65bc50 100644
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--- a/target/arm/cpu.h
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+++ b/target/arm/cpu.h
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@@ -866,6 +866,7 @@ struct ARMCPU {
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uint64_t id_aa64pfr1;
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uint64_t id_aa64mmfr0;
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uint64_t id_aa64mmfr1;
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+ uint64_t id_aa64mmfr2;
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} isar;
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uint32_t midr;
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uint32_t revidr;
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@@ -1762,6 +1763,22 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4)
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FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
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FIELD(ID_AA64MMFR1, XNX, 28, 4)
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+FIELD(ID_AA64MMFR2, CNP, 0, 4)
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+FIELD(ID_AA64MMFR2, UAO, 4, 4)
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+FIELD(ID_AA64MMFR2, LSM, 8, 4)
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+FIELD(ID_AA64MMFR2, IESB, 12, 4)
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+FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
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+FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
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+FIELD(ID_AA64MMFR2, NV, 24, 4)
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+FIELD(ID_AA64MMFR2, ST, 28, 4)
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+FIELD(ID_AA64MMFR2, AT, 32, 4)
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+FIELD(ID_AA64MMFR2, IDS, 36, 4)
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+FIELD(ID_AA64MMFR2, FWB, 40, 4)
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+FIELD(ID_AA64MMFR2, TTL, 48, 4)
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+FIELD(ID_AA64MMFR2, BBM, 52, 4)
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+FIELD(ID_AA64MMFR2, EVT, 56, 4)
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+FIELD(ID_AA64MMFR2, E0PD, 60, 4)
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+
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FIELD(ID_DFR0, COPDBG, 0, 4)
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FIELD(ID_DFR0, COPSDBG, 4, 4)
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FIELD(ID_DFR0, MMAPDBG, 8, 4)
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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index b74c23a9..c50b1ba1 100644
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--- a/target/arm/helper.c
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+++ b/target/arm/helper.c
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@@ -6182,10 +6182,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
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.access = PL1_R, .type = ARM_CP_CONST,
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.resetvalue = cpu->isar.id_aa64mmfr1 },
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- { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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+ { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
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.access = PL1_R, .type = ARM_CP_CONST,
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- .resetvalue = 0 },
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+ .resetvalue = cpu->isar.id_aa64mmfr2 },
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{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
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.access = PL1_R, .type = ARM_CP_CONST,
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index 4f0bf000..b794108a 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -541,6 +541,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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ARM64_SYS_REG(3, 0, 0, 7, 0));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
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ARM64_SYS_REG(3, 0, 0, 7, 1));
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+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
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+ ARM64_SYS_REG(3, 0, 0, 7, 2));
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/*
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* Note that if AArch32 support is not present in the host,
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--
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2.25.1
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