b3ccd965a7
If a device is plugged in the pcie-root-port when VM kernel is booting, the kernel may wrongly disable the device. This bug was brought in by two patches of the linux kernel: https://patchwork.kernel.org/patch/10575355/ https://patchwork.kernel.org/patch/10766219/ VM runtime like kata uses this feature to boot microVM, so we must fix it up. We hack into the pcie native hotplug patch so that hotplug/unplug will work under this circumstance. Signed-off-by: Ying Fang <fangying1@huawei.com>
123 lines
4.8 KiB
Diff
123 lines
4.8 KiB
Diff
From 55c4f093b3a527c52cc8ed7138c330512973c9e6 Mon Sep 17 00:00:00 2001
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From: fangying <fangying1@huawei.com>
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Date: Wed, 18 Mar 2020 12:49:33 +0800
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Subject: [PATCH 1/2] pcie: Add pcie-root-port fast plug/unplug feature
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If a device is plugged in the pcie-root-port when VM kernel is
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booting, the kernel may wrongly disable the device.
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This bug was brought in by two patches of the linux kernel:
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https://patchwork.kernel.org/patch/10575355/
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https://patchwork.kernel.org/patch/10766219/
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VM runtime like kata uses this feature to boot microVM,
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so we must fix it up. We hack into the pcie native hotplug
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patch so that hotplug/unplug will work under this circumstance.
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Signed-off-by: Ying Fang <fangying1@huawei.com>
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---
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hw/core/machine.c | 1 +
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hw/pci-bridge/gen_pcie_root_port.c | 3 ++-
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hw/pci/pcie.c | 23 +++++++++++++++++++----
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include/hw/pci/pcie_port.h | 3 ++-
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4 files changed, 24 insertions(+), 6 deletions(-)
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diff --git a/hw/core/machine.c b/hw/core/machine.c
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index 2baf9ec3..3138f97b 100644
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--- a/hw/core/machine.c
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+++ b/hw/core/machine.c
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@@ -33,6 +33,7 @@ GlobalProperty hw_compat_3_1[] = {
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{ "pcie-root-port", "x-speed", "2_5" },
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{ "pcie-root-port", "x-width", "1" },
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{ "pcie-root-port", "fast-plug", "0" },
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+ { "pcie-root-port", "fast-unplug", "0" },
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{ "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" },
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{ "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" },
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{ "tpm-crb", "ppi", "false" },
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diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c
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index 3179c4ea..2fbb11d0 100644
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--- a/hw/pci-bridge/gen_pcie_root_port.c
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+++ b/hw/pci-bridge/gen_pcie_root_port.c
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@@ -131,7 +131,8 @@ static Property gen_rp_props[] = {
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speed, PCIE_LINK_SPEED_16),
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DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
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width, PCIE_LINK_WIDTH_32),
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- DEFINE_PROP_UINT8("fast-plug", PCIESlot, disable_lnksta_dllla, 0),
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+ DEFINE_PROP_UINT8("fast-plug", PCIESlot, fast_plug, 0),
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+ DEFINE_PROP_UINT8("fast-unplug", PCIESlot, fast_unplug, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
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index c0d6ff13..2a8ff86d 100644
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--- a/hw/pci/pcie.c
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+++ b/hw/pci/pcie.c
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@@ -85,7 +85,7 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version)
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* To fix this up, let's enable the PCI_EXP_LNKSTA_DLLLA
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* only if it is a PCIESlot device.
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*/
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- if (s == NULL || s->disable_lnksta_dllla == 0) {
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+ if (s == NULL || s->fast_plug == 0) {
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if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
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PCI_EXP_LNKSTA_DLLLA);
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@@ -136,8 +136,11 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev)
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*/
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pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP,
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PCI_EXP_LNKCAP_DLLLARC);
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- pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
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- PCI_EXP_LNKSTA_DLLLA);
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+
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+ if(s->fast_plug == 0) {
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+ pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
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+ PCI_EXP_LNKSTA_DLLLA);
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+ }
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/*
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* Target Link Speed defaults to the highest link speed supported by
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@@ -477,6 +480,8 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
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Error *local_err = NULL;
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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PCIBus *bus = pci_get_bus(pci_dev);
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+ PCIESlot *s = PCIE_SLOT(PCI_DEVICE(hotplug_dev));
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+ uint8_t *exp_cap = pci_dev->config + pci_dev->exp.exp_cap;
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pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, &local_err);
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if (local_err) {
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@@ -495,7 +500,17 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
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return;
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}
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- pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev));
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+ if ((pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) && s->fast_plug) {
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+ pci_word_test_and_clear_mask(exp_cap+ PCI_EXP_LNKSTA,
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+ PCI_EXP_LNKSTA_DLLLA);
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+ }
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+
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+ if (s->fast_unplug) {
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+ pcie_cap_slot_event(PCI_DEVICE(hotplug_dev),
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+ PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
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+ } else {
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+ pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev));
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+ }
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}
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/* pci express slot for pci express root/downstream port
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diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h
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index c3969921..b57af4ee 100644
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--- a/include/hw/pci/pcie_port.h
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+++ b/include/hw/pci/pcie_port.h
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@@ -50,7 +50,8 @@ struct PCIESlot {
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uint8_t chassis;
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uint16_t slot;
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- uint8_t disable_lnksta_dllla;
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+ uint8_t fast_plug;
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+ uint8_t fast_unplug;
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PCIExpLinkSpeed speed;
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PCIExpLinkWidth width;
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--
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2.19.1
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