e9095b76ae
- support dirty restraint on vCPU - support SPR AMX in Qemu - fix compilation errors of sw64 Signed-off-by: yezengruan <yezengruan@huawei.com>
67 lines
2.2 KiB
Diff
67 lines
2.2 KiB
Diff
From 52eed626a2200da02e67aa93c2a8d59cb529737b Mon Sep 17 00:00:00 2001
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From: Jing Liu <jing2.liu@intel.com>
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Date: Wed, 16 Feb 2022 22:04:30 -0800
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Subject: [PATCH 05/10] x86: Add XFD faulting bit for state components
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from mainline-v7.0.0-rc0
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commit 0f17f6b30f3b051f0f96ccc98c9f7f395713699f
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category: feature
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feature: SPR AMX support for Qemu
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bugzilla: https://gitee.com/openeuler/intel-qemu/issues/I5VHOB
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Intel-SIG: commit 0f17f6b30f3b ("x86: Add XFD faulting bit for state
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components")
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-------------------------------------------------
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x86: Add XFD faulting bit for state components
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Intel introduces XFD faulting mechanism for extended
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XSAVE features to dynamically enable the features in
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runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
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as 1, it indicates support for XFD faulting of this
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state component.
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Signed-off-by: Jing Liu <jing2.liu@intel.com>
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Signed-off-by: Yang Zhong <yang.zhong@intel.com>
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Message-Id: <20220217060434.52460-5-yang.zhong@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Jason Zeng <jason.zeng@intel.com>
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---
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target/i386/cpu.c | 3 ++-
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target/i386/cpu.h | 2 ++
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2 files changed, 4 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index fb6b4c86de..da81e47dc3 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -5515,7 +5515,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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const ExtSaveArea *esa = &x86_ext_save_areas[count];
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*eax = esa->size;
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*ebx = esa->offset;
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- *ecx = esa->ecx & ESA_FEATURE_ALIGN64_MASK;
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+ *ecx = esa->ecx &
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+ (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK);
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}
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}
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break;
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 93d1c60ac1..09c725ee13 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -556,8 +556,10 @@ typedef enum X86Seg {
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#define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK)
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#define ESA_FEATURE_ALIGN64_BIT 1
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+#define ESA_FEATURE_XFD_BIT 2
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#define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
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+#define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT)
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/* CPUID feature words */
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--
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2.27.0
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