c9a7e0fa18
The bit 6, 7 and 8 of MSR_IA32_ARCH_CAPABILITIES are recently disclosed for some security issues. Add the definitions for them to be used by named CPU models. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20191225063018.20038-2-xiaoyao.li@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
48 lines
1.7 KiB
Diff
48 lines
1.7 KiB
Diff
From 05b13a8de90abc6c1cfeca8b9c436e60e6d3142e Mon Sep 17 00:00:00 2001
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From: Xiaoyao Li <xiaoyao.li@intel.com>
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Date: Wed, 25 Dec 2019 14:30:17 +0800
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Subject: [PATCH] target/i386: Add new bit definitions of
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MSR_IA32_ARCH_CAPABILITIES
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The bit 6, 7 and 8 of MSR_IA32_ARCH_CAPABILITIES are recently disclosed
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for some security issues. Add the definitions for them to be used by named
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CPU models.
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Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Message-Id: <20191225063018.20038-2-xiaoyao.li@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
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---
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target/i386/cpu.h | 13 ++++++++-----
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1 file changed, 8 insertions(+), 5 deletions(-)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 58d8c48964..7ff8ddd464 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -743,12 +743,15 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
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/* MSR Feature Bits */
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-#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
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-#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
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-#define MSR_ARCH_CAP_RSBA (1U << 2)
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+#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
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+#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
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+#define MSR_ARCH_CAP_RSBA (1U << 2)
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#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
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-#define MSR_ARCH_CAP_SSB_NO (1U << 4)
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-#define MSR_ARCH_CAP_MDS_NO (1U << 5)
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+#define MSR_ARCH_CAP_SSB_NO (1U << 4)
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+#define MSR_ARCH_CAP_MDS_NO (1U << 5)
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+#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
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+#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
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+#define MSR_ARCH_CAP_TAA_NO (1U << 8)
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#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
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--
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2.27.0
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