qemu/target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch
Jiabo Feng 0121fec7e1 QEMU update to version 8.2.0-14;
- target/riscv/cpu.c: fix Zvkb extension config
- target/i386: Add new Hygon 'Dharma' CPU model
- target/i386: Add Hygon Dhyana-v3 CPU model
- ui/gtk: Fix mouse/motion event scaling issue with GTK display backend
- hw/ufs: Fix buffer overflow bug
- arm/virt: Set vcpus_count of CPU as 1 to compatible with libvirt
- ppc/pnv: I2C controller is not user creatablei

Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
2024-06-15 08:54:46 +08:00

44 lines
1.3 KiB
Diff

From 7d4bc795419a69457ee5f2e32674183dc009d48f Mon Sep 17 00:00:00 2001
From: Yanjing Zhou <zhouyanjing@hygon.cn>
Date: Wed, 15 May 2024 13:49:19 +0800
Subject: [PATCH] target/i386: Add Hygon Dhyana-v3 CPU model
Add the following feature bits for Dhyana CPU model:
perfctr-core, clzero, xsaveerptr, aes, pclmulqdq, sha-ni
Disable xsaves feature bit for Erratum 1386
Signed-off-by: Yanjing Zhou <zhouyanjing@hygon.cn>
---
target/i386/cpu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fd32c64f99..f4c22f32c6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4793,6 +4793,20 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
},
},
+ { .version = 3,
+ .props = (PropValue[]) {
+ { "xsaves", "off" },
+ { "perfctr-core", "on" },
+ { "clzero", "on" },
+ { "xsaveerptr", "on" },
+ { "aes", "on" },
+ { "pclmulqdq", "on" },
+ { "sha-ni", "on" },
+ { "model-id",
+ "Hygon Dhyana-v3 processor" },
+ { /* end of list */ }
+ },
+ },
{ /* end of list */ }
}
},
--
2.41.0.windows.1