80a22cff37
- hw/virtio/virtio-pmem: Replace impossible check by assertion - tests: Fix printf format string in acpi-utils.c - softmmu/dirtylimit: Add parameter check for hmp "set_vcpu_dirty_limit" - disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14 - qga: Fix memory leak when output stream is unused - ui/vnc-clipboard: fix infinite loop in inflate_buffer (CVE-2023-3255) - target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model - target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES - target/i386: Allow MCDT_NO if host supports - target/i386: Add support for MCDT_NO in CPUID enumeration - target/i386: Export MSR_ARCH_CAPABILITIES bits to guests - target/i386: add support for FB_CLEAR feature - target/i386: add support for FLUSH_L1D feature - crypto: remove shadowed 'ret' variable - hw/i2c/pmbus_device: Fix modifying QOM class internals from instance - hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
113 lines
4.3 KiB
Diff
113 lines
4.3 KiB
Diff
From a7329b80a2c8a50e53da17aa4eff0ef50aa21413 Mon Sep 17 00:00:00 2001
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From: Tao Su <tao1.su@linux.intel.com>
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Date: Thu, 6 Jul 2023 13:49:45 +0800
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Subject: [PATCH] target/i386: Add support for MCDT_NO in CPUID enumeration
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commit 9dd8b71091f47bac395f543779269c14d8d93c60 upstream.
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CPUID.(EAX=7,ECX=2):EDX[bit 5] enumerates MCDT_NO. Processors enumerate
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this bit as 1 do not exhibit MXCSR Configuration Dependent Timing (MCDT)
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behavior and do not need to be mitigated to avoid data-dependent behavior
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for certain instructions.
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Since MCDT_NO is in a new sub-leaf, add a new CPUID feature word
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FEAT_7_2_EDX. Also update cpuid_level_func7 by FEAT_7_2_EDX.
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Intel-SIG: commit 9dd8b71091f4 ("target/i386: Add support for MCDT_NO in CPUID enumeration")
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Backport support for MCDT_NO in CPUID enumeration
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Message-ID: <20230706054949.66556-3-tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ jason: resolve conflict with FEAT_7_1_EDX which not backported yet ]
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Signed-off-by: Jason Zeng <jason.zeng@intel.com>
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---
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target/i386/cpu.c | 26 ++++++++++++++++++++++++++
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target/i386/cpu.h | 4 ++++
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2 files changed, 30 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index b878a1bf20..685bfca37e 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -663,6 +663,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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#define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM
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#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
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CPUID_7_1_EAX_FSRC)
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+#define TCG_7_2_EDX_FEATURES 0
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#define TCG_APM_FEATURES 0
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#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
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#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
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@@ -886,6 +887,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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},
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.tcg_features = TCG_7_1_EAX_FEATURES,
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},
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+ [FEAT_7_2_EDX] = {
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+ .type = CPUID_FEATURE_WORD,
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+ .feat_names = {
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+ NULL, NULL, NULL, NULL,
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+ NULL, "mcdt-no", NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ },
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+ .cpuid = {
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+ .eax = 7,
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+ .needs_ecx = true, .ecx = 2,
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+ .reg = R_EDX,
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+ },
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+ .tcg_features = TCG_7_2_EDX_FEATURES,
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+ },
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[FEAT_8000_0007_EDX] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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@@ -5531,6 +5551,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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*ebx = 0;
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*ecx = 0;
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*edx = 0;
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+ } else if (count == 2) {
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+ *edx = env->features[FEAT_7_2_EDX];
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+ *eax = 0;
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+ *ebx = 0;
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+ *ecx = 0;
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} else {
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*eax = 0;
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*ebx = 0;
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@@ -6361,6 +6386,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
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x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
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x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
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x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
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+ x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX);
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x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
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x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
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x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index d9aac5acd2..edbaba0d62 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -601,6 +601,7 @@ typedef enum FeatureWord {
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FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
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FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
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FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
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+ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */
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FEATURE_WORDS,
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} FeatureWord;
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@@ -889,6 +890,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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/* Fast Short REP CMPS/SCAS */
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#define CPUID_7_1_EAX_FSRC (1U << 12)
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+/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
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+#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
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+
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/* XFD Extend Feature Disabled */
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#define CPUID_D_1_EAX_XFD (1U << 4)
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--
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2.41.0.windows.1
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