0b0e518312
- thread-pool: optimize scheduling of completion bottom half - migration/rdma: zore out head.repeat to make the error more clear - vhost-user-fs: Back up vqs before cleaning up vhost_dev - hw/vfio/pci-quirks: Sanitize capability pointer - hw/vfio/pci-quirks: Support alternate offset for GPUDirect Cliques - replay: fix event queue flush for qemu shutdown - hw/net: Fix read of uninitialized memory in ftgmac100 - target/ppc: Fix tlbie - target/i386: fix INVD vmexit - qtest/npcm7xx_pwm-test: Fix memory leak in mft_qom_set - aio-posix: zero out io_uring sqe user_data Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
96 lines
3.6 KiB
Diff
96 lines
3.6 KiB
Diff
From d672e2f137933b26bd9b3488a873830435eadba5 Mon Sep 17 00:00:00 2001
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From: tangzhongrui <tangzhongrui@cmss.chinamobile.com>
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Date: Thu, 3 Aug 2023 15:10:16 +0800
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Subject: [PATCH] hw/vfio/pci-quirks: Support alternate offset for GPUDirect
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Cliques
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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NVIDIA Turing and newer GPUs implement the MSI-X capability at the offset
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previously reserved for use by hypervisors to implement the GPUDirect
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Cliques capability. A revised specification provides an alternate
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location. Add a config space walk to the quirk to check for conflicts,
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allowing us to fall back to the new location or generate an error at the
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quirk setup rather than when the real conflicting capability is added
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should there be no available location.
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Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
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Reviewed-by: Cédric Le Goater <clg@redhat.com>
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Signed-off-by: Cédric Le Goater <clg@redhat.com>
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Signed-off-by: Zhongrui Tang <tangzhongrui_yewu@cmss.chinamobile.com>
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---
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hw/vfio/pci-quirks.c | 41 ++++++++++++++++++++++++++++++++++++++++-
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1 file changed, 40 insertions(+), 1 deletion(-)
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diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
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index 1222ccff0b..7a8e6efcdc 100644
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--- a/hw/vfio/pci-quirks.c
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+++ b/hw/vfio/pci-quirks.c
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@@ -1677,6 +1677,9 @@ void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev)
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* +---------------------------------+---------------------------------+
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*
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* https://lists.gnu.org/archive/html/qemu-devel/2017-08/pdfUda5iEpgOS.pdf
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+ *
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+ * Specification for Turning and later GPU architectures:
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+ * https://lists.gnu.org/archive/html/qemu-devel/2023-06/pdf142OR4O4c2.pdf
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*/
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static void get_nv_gpudirect_clique_id(Object *obj, Visitor *v,
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const char *name, void *opaque,
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@@ -1717,7 +1720,9 @@ const PropertyInfo qdev_prop_nv_gpudirect_clique = {
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static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp)
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{
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PCIDevice *pdev = &vdev->pdev;
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- int ret, pos = 0xC8;
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+ int ret, pos;
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+ bool c8_conflict = false, d4_conflict = false;
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+ uint8_t tmp;
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if (vdev->nv_gpudirect_clique == 0xFF) {
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return 0;
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@@ -1734,6 +1739,40 @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp)
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return -EINVAL;
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}
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+ /*
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+ * Per the updated specification above, it's recommended to use offset
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+ * D4h for Turing and later GPU architectures due to a conflict of the
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+ * MSI-X capability at C8h. We don't know how to determine the GPU
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+ * architecture, instead we walk the capability chain to mark conflicts
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+ * and choose one or error based on the result.
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+ *
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+ * NB. Cap list head in pdev->config is already cleared, read from device.
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+ */
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+ ret = pread(vdev->vbasedev.fd, &tmp, 1,
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+ vdev->config_offset + PCI_CAPABILITY_LIST);
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+ if (ret != 1 || !tmp) {
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+ error_setg(errp, "NVIDIA GPUDirect Clique ID: error getting cap list");
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+ return -EINVAL;
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+ }
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+
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+ do {
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+ if (tmp == 0xC8) {
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+ c8_conflict = true;
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+ } else if (tmp == 0xD4) {
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+ d4_conflict = true;
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+ }
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+ tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT];
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+ } while (tmp);
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+
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+ if (!c8_conflict) {
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+ pos = 0xC8;
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+ } else if (!d4_conflict) {
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+ pos = 0xD4;
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+ } else {
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+ error_setg(errp, "NVIDIA GPUDirect Clique ID: invalid config space");
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+ return -EINVAL;
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+ }
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+
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ret = pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8, errp);
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if (ret < 0) {
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error_prepend(errp, "Failed to add NVIDIA GPUDirect cap: ");
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--
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2.41.0.windows.1
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