0b329b7ce3
The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform and could be passed to the guest. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
45 lines
1.8 KiB
Diff
45 lines
1.8 KiB
Diff
From a6206163d42156cb9de290f914c6883c77b012b9 Mon Sep 17 00:00:00 2001
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From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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Date: Wed, 25 Sep 2019 23:49:48 +0200
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Subject: [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR
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The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform
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and could be passed to the guest.
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Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 2 +-
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target/i386/cpu.h | 2 ++
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index f09612f9da..e65f372f25 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1134,7 +1134,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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[FEAT_8000_0008_EBX] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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- NULL, NULL, NULL, NULL,
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+ "clzero", NULL, "xsaveerptr", NULL,
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NULL, NULL, NULL, NULL,
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NULL, "wbnoinvd", NULL, NULL,
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"ibpb", NULL, NULL, NULL,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 7ff8ddd464..24d489db0f 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -696,6 +696,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction */
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+#define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* CLZERO instruction */
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+#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */
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#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
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do not invalidate cache */
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#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
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--
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2.27.0
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