b36d41c519
- cvm : bug fix for undefined reference to 'virtcca_cvm_allowed' while compiling - cvm : bug-fix for incorrect device name check for vhost-user-fs - target/i386: add control bits support for LAM - target/i386: add support for LAM in CPUID enumeration - Add support for the virtcca cvm feature. - target/sparc: use signed denominator in sdiv helper - crypto: Introduce SM4 symmetric cipher algorithm - ppc/vof: Fix unaligned FDT property access - vl: fix "type is NULL" in -vga help - hw/display/bcm2835_fb: fix fb_use_offsets condition - aspeed/smc: Fix possible integer overflow - hw/nvme: fix number of PIDs for FDP RUH update - hw/nvme: fix memory leak in nvme_dsm - hvf: arm: Do not advance PC when raising an exception - physmem: Bail out qemu_ram_block_from_host() for invalid ram addrs Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
70 lines
2.4 KiB
Diff
70 lines
2.4 KiB
Diff
From 8bc3dd094a9daa348d49436dc4d0867b7b514ba7 Mon Sep 17 00:00:00 2001
|
|
From: Robert Hoo <robert.hu@linux.intel.com>
|
|
Date: Fri, 12 Jan 2024 14:00:41 +0800
|
|
Subject: [PATCH] target/i386: add support for LAM in CPUID enumeration
|
|
|
|
commit ba6780905943696d790cc880c8e5684b51f027fe upstream.
|
|
|
|
Linear Address Masking (LAM) is a new Intel CPU feature, which allows
|
|
software to use of the untranslated address bits for metadata.
|
|
|
|
The bit definition:
|
|
CPUID.(EAX=7,ECX=1):EAX[26]
|
|
|
|
Add CPUID definition for LAM.
|
|
|
|
Note LAM feature is not supported for TCG of target-i386, LAM CPIUD bit
|
|
will not be added to TCG_7_1_EAX_FEATURES.
|
|
|
|
More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING(LAM)"
|
|
https://cdrdv2.intel.com/v1/dl/getContent/671368
|
|
|
|
Intel-SIG: commit ba6780905943 target/i386: add support for LAM in CPUID
|
|
enumeration
|
|
Backport Qemu Linear Address Masking (LAM) support.
|
|
|
|
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
|
|
Co-developed-by: Binbin Wu <binbin.wu@linux.intel.com>
|
|
Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com>
|
|
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
|
|
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
|
|
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
|
|
Message-ID: <20240112060042.19925-2-binbin.wu@linux.intel.com>
|
|
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
[ Zhiquan Li: amend commit log ]
|
|
Signed-off-by: Zhiquan Li <zhiquan1.li@intel.com>
|
|
---
|
|
target/i386/cpu.c | 2 +-
|
|
target/i386/cpu.h | 2 ++
|
|
2 files changed, 3 insertions(+), 1 deletion(-)
|
|
|
|
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
|
index 711370d9b8..19ebd49e8c 100644
|
|
--- a/target/i386/cpu.c
|
|
+++ b/target/i386/cpu.c
|
|
@@ -967,7 +967,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
|
"fsrc", NULL, NULL, NULL,
|
|
NULL, NULL, NULL, NULL,
|
|
NULL, "amx-fp16", NULL, "avx-ifma",
|
|
- NULL, NULL, NULL, NULL,
|
|
+ NULL, NULL, "lam", NULL,
|
|
NULL, NULL, NULL, NULL,
|
|
},
|
|
.cpuid = {
|
|
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
|
index 6993552cd9..8dbcb4a35f 100644
|
|
--- a/target/i386/cpu.h
|
|
+++ b/target/i386/cpu.h
|
|
@@ -926,6 +926,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
|
|
#define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
|
|
/* Support for VPMADD52[H,L]UQ */
|
|
#define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
|
|
+/* Linear Address Masking */
|
|
+#define CPUID_7_1_EAX_LAM (1U << 26)
|
|
|
|
/* Support for VPDPB[SU,UU,SS]D[,S] */
|
|
#define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)
|
|
--
|
|
2.41.0.windows.1
|
|
|