dddaf7aa9e
- vdpa-dev: Fix initialisation order to restore VDUSE compatibility - tcg: Allow top bit of SIMD_DATA_BITS to be set in simd_desc() - migration: fix-possible-int-overflow - target/m68k: Map FPU exceptions to FPSR register - qemu-options: Fix CXL Fixed Memory Window interleave-granularity typo - hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registers - hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n> - qio: Inherit follow_coroutine_ctx across TLS - target/riscv: Fix the element agnostic function problem - accel/tcg: Fix typo causing tb->page_addr[1] to not be recorded - tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers - migration: Fix file migration with fdset - ui/vnc: don't return an empty SASL mechlist to the client - target/arm: Fix FJCVTZS vs flush-to-zero - hw/ppc/e500: Prefer QOM cast - sphinx/qapidoc: Fix to generate doc for explicit, unboxed arguments - hw/ppc/e500: Remove unused "irqs" parameter - hw/ppc/e500: Add missing device tree properties to i2c controller node - hw/i386/amd_iommu: Don't leak memory in amdvi_update_iotlb() - hw/arm/mps2-tz.c: fix RX/TX interrupts order - target/i386: csv: Add support to migrate the incoming context for CSV3 guest - target/i386: csv: Add support to migrate the outgoing context for CSV3 guest - target/i386: csv: Add support to migrate the incoming page for CSV3 guest - target/i386: csv: Add support to migrate the outgoing page for CSV3 guest - linux-headers: update kernel headers to include CSV3 migration cmds - vfio: Only map shared region for CSV3 virtual machine - vga: Force full update for CSV3 guest - target/i386: csv: Load initial image to private memory for CSV3 guest - target/i386: csv: Do not register/unregister guest secure memory for CSV3 guest - target/i386: cpu: Populate CPUID 0x8000_001F when CSV3 is active - target/i386: csv: Add command to load vmcb to CSV3 guest memory - target/i386: csv: Add command to load data to CSV3 guest memory - target/i386: csv: Add command to initialize CSV3 context - target/i386: csv: Add CSV3 context - next-kbd: convert to use qemu_input_handler_register() - qemu/bswap: Undefine CPU_CONVERT() once done - exec/memop: Remove unused memop_big_endian() helper - hw/nvme: fix handling of over-committed queues - 9pfs: fix crash on 'Treaddir' request - hw/misc/psp: Pin the hugepage memory specified by mem2 during use for psp - hw/misc: support tkm use mem2 memory - hw/i386: add mem2 option for qemu - kvm: add support for guest physical bits - target/i386: add guest-phys-bits cpu property Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com> (cherry picked from commit f45f35e88509a4ffa9f62332ee9601e9fe1f8d09)
51 lines
2.3 KiB
Diff
51 lines
2.3 KiB
Diff
From 322f39889ff60a6fda87d7d95a6f233efb558e8a Mon Sep 17 00:00:00 2001
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From: Marco Palumbi <Marco.Palumbi@tii.ae>
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Date: Thu, 1 Aug 2024 10:15:02 +0100
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Subject: [PATCH] hw/arm/mps2-tz.c: fix RX/TX interrupts order
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The order of the RX and TX interrupts are swapped.
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This commit fixes the order as per the following documents:
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* https://developer.arm.com/documentation/dai0505/latest/
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* https://developer.arm.com/documentation/dai0521/latest/
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* https://developer.arm.com/documentation/dai0524/latest/
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* https://developer.arm.com/documentation/dai0547/latest/
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Marco Palumbi <Marco.Palumbi@tii.ae>
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Message-id: 20240730073123.72992-1-marco@palumbi.it
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit 5a558be93ad628e5bed6e0ee062870f49251725c)
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Signed-off-by: zhujun2 <zhujun2_yewu@cmss.chinamobile.com>
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---
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hw/arm/mps2-tz.c | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
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index 668db5ed61..9d9c263ef8 100644
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--- a/hw/arm/mps2-tz.c
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+++ b/hw/arm/mps2-tz.c
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@@ -435,7 +435,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
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const char *name, hwaddr size,
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const int *irqs, const PPCExtraData *extradata)
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{
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- /* The irq[] array is tx, rx, combined, in that order */
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+ /* The irq[] array is rx, tx, combined, in that order */
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MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
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CMSDKAPBUART *uart = opaque;
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int i = uart - &mms->uart[0];
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@@ -447,8 +447,8 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
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qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq);
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sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
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s = SYS_BUS_DEVICE(uart);
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- sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
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- sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1]));
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+ sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[1]));
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+ sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[0]));
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sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
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sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
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sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2]));
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--
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2.41.0.windows.1
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