39a0a891d8
- vdpa: move memory listener to the realize stage - vdpa: implement vdpa device migration - vhost: implement post resume bh - vhost: implement migration state notifier for vdpa device - vhost: implement savevm_hanlder for vdpa device - vhost: implement vhost_vdpa_device_suspend/resume - vhost: implement vhost-vdpa suspend/resume - vhost: add vhost_dev_suspend/resume_op - vhost: introduce bytemap for vhost backend logging - vhost-vdpa: add migration log ops for VhostOps - vhost-vdpa: add VHOST_BACKEND_F_BYTEMAPLOG - vhost: fix null pointer access - ui/gtk: prevent ui lock up when dpy_gl_update called again before current draw event occurs - hw/usb: dev-mtp: Use g_mkdir() - target/ppc/cpu-models: Remove the "default" CPU alias - hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ - Fixed a QEMU hang when guest poweroff in COLO mode - migration/colo: More accurate update checkpoint time - scripts/entitlement.sh: Use backward-compatible cp flags - block/nvme: fix infinite loop in nvme_free_req_queue_cb() - hw/net: npcm7xx_emc fix missing queue_flush - Add dummy Aspeed AST2600 Display Port MCU (DPMCU) - hw/arm: ast2600: Fix address mapping of second SPI controller - vhost-user-blk: reconnect on any error during realize - vhost-user-blk: propagate error return from generic vhost - hw/riscv: boot: Reduce FDT address alignment constraints - Revert "hw/virtio/virtio-iommu-pci: Enforce the device is plugged on the root bus" - Fix STM32F2XX USART data register readout - block: use 'unsigned' for in_flight field on driver state - sphinx: change default language to 'en' - tests/qtest: Fix two format strings - trivial typos: namesapce - hw/ide/atapi.c: Correct typos (CD-CDROM -> CD-ROM) - hw/virtio/virtio-iommu-pci: Enforce the device is plugged on the root bus - hw/display/next-fb: Fix comment typo - xen/pass-through: merge emulated bits correctly mainline inclusion commit be9c61da9fc57eb7d293f380d0805ca6f46c2657 category: bugfix - tests/qtest/migration-test.c: spelling fix: bandwith - target/i386/cpu: Improve error message for property "vendor" - balloon: Fix a misleading error message - target/arm: Don't set syndrome ISS for loads and stores with writeback mainline inclusion commit 53ae2fdef1f5661cbaa2ea571c517f98e6041cb8 category: bugfix - disas/hppa: Show hexcode of instruction along with disassembly - tcg/loongarch64: Fix tcg_out_mov() Aborted - ui/qmp-cmds: Improve two error messages - qga: Improve guest-exec-status error message - hmp: Improve sync-profile error message - spapr/pci: Correct "does not support hotplugging error messages - xen/pass-through: don't create needless register group mainline inclusion commit c0e86b7624cb9d6db03e0d48cf82659e5b89a6a6 category: bugfix Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
52 lines
1.8 KiB
Diff
52 lines
1.8 KiB
Diff
From dd5bf5817259ea414f40b25f4aef3864eddb9706 Mon Sep 17 00:00:00 2001
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From: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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Date: Mon, 27 Nov 2023 03:24:57 +0000
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Subject: [PATCH] target/arm: Don't set syndrome ISS for loads and stores with
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writeback mainline inclusion commit 53ae2fdef1f5661cbaa2ea571c517f98e6041cb8
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category: bugfix
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---------------------------------------------------------------
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The architecture requires that for faults on loads and stores which
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do writeback, the syndrome information does not have the ISS
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instruction syndrome information (i.e. ISV is 0). We got this wrong
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for the load and store instructions covered by disas_ldst_reg_imm9().
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Calculate iss_valid correctly so that if the insn is a writeback one
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it is false.
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1057
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220715123323.1550983-1-peter.maydell@linaro.org
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Signed-off-by: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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---
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target/arm/translate-a64.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
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index cec672f229..549a671bea 100644
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--- a/target/arm/translate-a64.c
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+++ b/target/arm/translate-a64.c
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@@ -3039,7 +3039,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
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bool is_store = false;
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bool is_extended = false;
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bool is_unpriv = (idx == 2);
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- bool iss_valid = !is_vector;
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+ bool iss_valid;
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bool post_index;
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bool writeback;
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int memidx;
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@@ -3092,6 +3092,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
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g_assert_not_reached();
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}
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+ iss_valid = !is_vector && !writeback;
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+
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if (rn == 31) {
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gen_check_sp_alignment(s);
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}
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--
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2.27.0
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