dddaf7aa9e
- vdpa-dev: Fix initialisation order to restore VDUSE compatibility - tcg: Allow top bit of SIMD_DATA_BITS to be set in simd_desc() - migration: fix-possible-int-overflow - target/m68k: Map FPU exceptions to FPSR register - qemu-options: Fix CXL Fixed Memory Window interleave-granularity typo - hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registers - hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n> - qio: Inherit follow_coroutine_ctx across TLS - target/riscv: Fix the element agnostic function problem - accel/tcg: Fix typo causing tb->page_addr[1] to not be recorded - tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers - migration: Fix file migration with fdset - ui/vnc: don't return an empty SASL mechlist to the client - target/arm: Fix FJCVTZS vs flush-to-zero - hw/ppc/e500: Prefer QOM cast - sphinx/qapidoc: Fix to generate doc for explicit, unboxed arguments - hw/ppc/e500: Remove unused "irqs" parameter - hw/ppc/e500: Add missing device tree properties to i2c controller node - hw/i386/amd_iommu: Don't leak memory in amdvi_update_iotlb() - hw/arm/mps2-tz.c: fix RX/TX interrupts order - target/i386: csv: Add support to migrate the incoming context for CSV3 guest - target/i386: csv: Add support to migrate the outgoing context for CSV3 guest - target/i386: csv: Add support to migrate the incoming page for CSV3 guest - target/i386: csv: Add support to migrate the outgoing page for CSV3 guest - linux-headers: update kernel headers to include CSV3 migration cmds - vfio: Only map shared region for CSV3 virtual machine - vga: Force full update for CSV3 guest - target/i386: csv: Load initial image to private memory for CSV3 guest - target/i386: csv: Do not register/unregister guest secure memory for CSV3 guest - target/i386: cpu: Populate CPUID 0x8000_001F when CSV3 is active - target/i386: csv: Add command to load vmcb to CSV3 guest memory - target/i386: csv: Add command to load data to CSV3 guest memory - target/i386: csv: Add command to initialize CSV3 context - target/i386: csv: Add CSV3 context - next-kbd: convert to use qemu_input_handler_register() - qemu/bswap: Undefine CPU_CONVERT() once done - exec/memop: Remove unused memop_big_endian() helper - hw/nvme: fix handling of over-committed queues - 9pfs: fix crash on 'Treaddir' request - hw/misc/psp: Pin the hugepage memory specified by mem2 during use for psp - hw/misc: support tkm use mem2 memory - hw/i386: add mem2 option for qemu - kvm: add support for guest physical bits - target/i386: add guest-phys-bits cpu property Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com> (cherry picked from commit f45f35e88509a4ffa9f62332ee9601e9fe1f8d09)
61 lines
2.1 KiB
Diff
61 lines
2.1 KiB
Diff
From 194c3cadc1879ff4c3d2fc6c5f962ad751c83d9c Mon Sep 17 00:00:00 2001
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From: Huang Tao <eric.huang@linux.alibaba.com>
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Date: Mon, 25 Mar 2024 10:16:54 +0800
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Subject: [PATCH] target/riscv: Fix the element agnostic function problem
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In RVV and vcrypto instructions, the masked and tail elements are set to 1s
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using vext_set_elems_1s function if the vma/vta bit is set. It is the element
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agnostic policy.
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However, this function can't deal the big endian situation. This patch fixes
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the problem by adding handling of such case.
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Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
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Suggested-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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Cc: qemu-stable <qemu-stable@nongnu.org>
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Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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(cherry picked from commit 75115d880c6d396f8a2d56aab8c12236d85a90e0)
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Signed-off-by: zhujun2 <zhujun2_yewu@cmss.chinamobile.com>
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---
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target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
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1 file changed, 22 insertions(+)
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diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
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index 9cf5c17cde..be6eb040d2 100644
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--- a/target/riscv/vector_internals.c
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+++ b/target/riscv/vector_internals.c
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@@ -29,6 +29,28 @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
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if (tot - cnt == 0) {
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return ;
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}
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+
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+ if (HOST_BIG_ENDIAN) {
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+ /*
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+ * Deal the situation when the elements are insdie
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+ * only one uint64 block including setting the
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+ * masked-off element.
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+ */
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+ if (((tot - 1) ^ cnt) < 8) {
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+ memset(base + H1(tot - 1), -1, tot - cnt);
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+ return;
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+ }
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+ /*
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+ * Otherwise, at least cross two uint64_t blocks.
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+ * Set first unaligned block.
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+ */
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+ if (cnt % 8 != 0) {
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+ uint32_t j = ROUND_UP(cnt, 8);
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+ memset(base + H1(j - 1), -1, j - cnt);
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+ cnt = j;
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+ }
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+ /* Set other 64bit aligend blocks */
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+ }
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memset(base + cnt, -1, tot - cnt);
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}
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--
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2.41.0.windows.1
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