45af991ec3
- disable keyring option - loongarch: Change the UEFI loading mode to loongarch - target/loongarch: Fix qtest test-hmp error when KVM-only build - target/loongarch/kvm: Enable LSX/LASX extension - target/loongarch: Set cpuid CSR register only once with kvm mode - configure: Add linux header compile support for LoongArch - hw/intc/loongarch_extioi: Add vmstate post_load support - hw/intc/loongarch_extioi: Add dynamic cpu number support - hw/loongarch/virt: Set iocsr address space per-board rather than percpu - hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi ops - target/loongarch: Add loongarch kvm into meson build - target/loongarch: Implement set vcpu intr for kvm - target/loongarch: Restrict TCG-specific code - target/loongarch: Implement kvm_arch_handle_exit - target/loongarch: Implement kvm_arch_init_vcpu - target/loongarch: Implement kvm_arch_init function - target/loongarch: Implement kvm get/set registers - target/loongarch: Supplement vcpu env initial when vcpu reset - target/loongarch: Define some kvm_arch interfaces - linux-headers: Synchronize linux headers from linux v6.7.0-rc8 - linux-headers: Update to Linux v6.7-rc5 - target/loongarch: move translate modules to tcg/ - target/loongarch/meson: move gdbstub.c to loongarch.ss - target/loongarch: Add timer information dump support - hw/loongarch/virt: Align high memory base address with super page size Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com> (cherry picked from commit b2263e41ffa3428f1d9f9ff6e214c8e3a19e06e8)
60 lines
2.2 KiB
Diff
60 lines
2.2 KiB
Diff
From 48dae5f461bf2cde206e879d52df6cf1bad3ac6e Mon Sep 17 00:00:00 2001
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From: Tianrui Zhao <zhaotianrui@loongson.cn>
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Date: Fri, 5 Jan 2024 15:57:58 +0800
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Subject: [PATCH] target/loongarch: Supplement vcpu env initial when vcpu reset
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Supplement vcpu env initial when vcpu reset, including
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init vcpu CSR_CPUID,CSR_TID to cpu->cpu_index. The two
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regs will be used in kvm_get/set_csr_ioctl.
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Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
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Signed-off-by: xianglai li <lixianglai@loongson.cn>
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Reviewed-by: Song Gao <gaosong@loongson.cn>
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Message-Id: <20240105075804.1228596-4-zhaotianrui@loongson.cn>
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Signed-off-by: Song Gao <gaosong@loongson.cn>
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---
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target/loongarch/cpu.c | 2 ++
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target/loongarch/cpu.h | 2 +-
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
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index db9a421cc4..021592798a 100644
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--- a/target/loongarch/cpu.c
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+++ b/target/loongarch/cpu.c
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@@ -531,10 +531,12 @@ static void loongarch_cpu_reset_hold(Object *obj)
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env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
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env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
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+ env->CSR_CPUID = cs->cpu_index;
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env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
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env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
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env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
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env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
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+ env->CSR_TID = cs->cpu_index;
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env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
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env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
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diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
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index 00d1fba597..f6d5ef0852 100644
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--- a/target/loongarch/cpu.h
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+++ b/target/loongarch/cpu.h
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@@ -319,6 +319,7 @@ typedef struct CPUArchState {
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uint64_t CSR_PWCH;
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uint64_t CSR_STLBPS;
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uint64_t CSR_RVACFG;
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+ uint64_t CSR_CPUID;
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uint64_t CSR_PRCFG1;
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uint64_t CSR_PRCFG2;
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uint64_t CSR_PRCFG3;
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@@ -350,7 +351,6 @@ typedef struct CPUArchState {
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uint64_t CSR_DBG;
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uint64_t CSR_DERA;
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uint64_t CSR_DSAVE;
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- uint64_t CSR_CPUID;
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#ifndef CONFIG_USER_ONLY
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LoongArchTLB tlb[LOONGARCH_TLB_MAX];
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--
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2.27.0
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