5636aff5b1
- target/i386: csv: Support inject secret for CSV3 guest only if the extension is enabled
- target/i386: csv: Support load kernel hashes for CSV3 guest only if the extension is enabled
- target/i386: csv: Request to set private memory of CSV3 guest if the extension is enabled
- target/i386: kvm: Support to get and enable extensions for Hygon CoCo guest
- qapi/qom,target/i386: csv-guest: Introduce secret-header-file=str and secret-file=str options
- bakcend: VirtCCA:resolve hugepage memory waste issue in vhost-user scenario
- parallels: fix ext_off assertion failure due to overflow
- backends/cryptodev-vhost-user: Fix local_error leaks
- hw/usb/hcd-ehci: Fix debug printf format string
- target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
- target/riscv/vector_helper.c: optimize loops in ldst helpers
- target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
- target/hexagon: don't look for static glib
- virtio-net: Fix network stall at the host side waiting for kick
- Add if condition to avoid assertion failed error in blockdev_init
- target/arm: Use float_status copy in sme_fmopa_s
- target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
- target/arm: Reinstate "vfp" property on AArch32 CPUs
- target/i386/cpu: Fix notes for CPU models
- target/arm: LDAPR should honour SCTLR_ELx.nAA
- target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()
- hvf: remove unused but set variable
- hw/misc/nrf51_rng: Don't use BIT_MASK() when we mean BIT()
- Avoid taking address of out-of-bounds array index
- target/arm: Fix VCMLA Dd, Dn, Dm[idx]
- target/arm: Fix UMOPA/UMOPS of 16-bit values
- target/arm: Fix SVE/SME gross MTE suppression checks
- target/arm: Fix nregs computation in do_{ld,st}_zpa
- crypto: fix error check on gcry_md_open
- Change vmstate_cpuhp_sts vmstateDescription version_id
- hw/pci: Remove unused pci_irq_pulse() method
- hw/intc: Don't clear pending bits on IRQ lowering
- target/arm: Drop user-only special case in sve_stN_r
- migration: Ensure vmstate_save() sets errp
- target/i386: fix hang when using slow path for ptw_setl
- contrib/plugins: add compat for g_memdup2
- hw/audio/hda: fix memory leak on audio setup
- crypto: perform runtime check for hash/hmac support in gcrypt
- target/arm: Fix incorrect aa64_tidcp1 feature check
- target/arm: fix exception syndrome for AArch32 bkpt insn
- target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
- linux-user: Print tid not pid with strace
- target/arm: Fix A64 scalar SQSHRN and SQRSHRN
- target/arm: Don't assert for 128-bit tile accesses when SVL is 128
- hw/timer/exynos4210_mct: fix possible int overflow
- target/arm: Avoid shifts by -1 in tszimm_shr() and tszimm_shl()
- hw/audio/virtio-snd: Always use little endian audio format
- target/riscv: Fix vcompress with rvv_ta_all_1s
- usb-hub: Fix handling port power control messages
Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
(cherry picked from commit d4a20b24ff377fd07fcbf2b72eecaf07a3ac4cc0)
67 lines
2.3 KiB
Diff
67 lines
2.3 KiB
Diff
From 7810c5462cc56c92f50ecf3878525c15000212f6 Mon Sep 17 00:00:00 2001
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From: gubin <gubin_yewu@cmss.chinamobile.com>
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Date: Fri, 22 Nov 2024 18:02:26 +0800
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Subject: [PATCH] target/arm: Avoid shifts by -1 in tszimm_shr() and
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tszimm_shl()
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cherry-pick from 76916dfa89e8900639c1055c07a295c06628a0bc
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The function tszimm_esz() returns a shift amount, or possibly -1 in
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certain cases that correspond to unallocated encodings in the
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instruction set. We catch these later in the trans_ functions
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(generally with an "a-esz < 0" check), but before we do the
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decodetree-generated code will also call tszimm_shr() or tszimm_sl(),
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which will use the tszimm_esz() return value as a shift count without
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checking that it is not negative, which is undefined behaviour.
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Avoid the UB by checking the return value in tszimm_shr() and
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tszimm_shl().
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Cc: qemu-stable@nongnu.org
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Resolves: Coverity CID 1547617, 1547694
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20240722172957.1041231-4-peter.maydell@linaro.org
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Signed-off-by: gubin <gubin_yewu@cmss.chinamobile.com>
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---
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target/arm/tcg/translate-sve.c | 18 ++++++++++++++++--
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1 file changed, 16 insertions(+), 2 deletions(-)
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diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
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index 296e7d1ce2..dd0c633897 100644
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--- a/target/arm/tcg/translate-sve.c
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+++ b/target/arm/tcg/translate-sve.c
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@@ -50,13 +50,27 @@ static int tszimm_esz(DisasContext *s, int x)
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static int tszimm_shr(DisasContext *s, int x)
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{
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- return (16 << tszimm_esz(s, x)) - x;
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+ /*
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+ * We won't use the tszimm_shr() value if tszimm_esz() returns -1 (the
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+ * trans function will check for esz < 0), so we can return any
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+ * value we like from here in that case as long as we avoid UB.
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+ */
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+ int esz = tszimm_esz(s, x);
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+ if (esz < 0) {
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+ return esz;
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+ }
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+ return (16 << esz) - x;
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}
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/* See e.g. LSL (immediate, predicated). */
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static int tszimm_shl(DisasContext *s, int x)
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{
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- return x - (8 << tszimm_esz(s, x));
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+ /* As with tszimm_shr(), value will be unused if esz < 0 */
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+ int esz = tszimm_esz(s, x);
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+ if (esz < 0) {
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+ return esz;
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+ }
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+ return x - (8 << esz);
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}
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/* The SH bit is in bit 8. Extract the low 8 and shift. */
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--
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2.41.0.windows.1
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