qemu/target-riscv-cpu.c-fix-Zvkb-extension-config.patch
Jiabo Feng 0121fec7e1 QEMU update to version 8.2.0-14;
- target/riscv/cpu.c: fix Zvkb extension config
- target/i386: Add new Hygon 'Dharma' CPU model
- target/i386: Add Hygon Dhyana-v3 CPU model
- ui/gtk: Fix mouse/motion event scaling issue with GTK display backend
- hw/ufs: Fix buffer overflow bug
- arm/virt: Set vcpus_count of CPU as 1 to compatible with libvirt
- ppc/pnv: I2C controller is not user creatablei

Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
2024-06-15 08:54:46 +08:00

44 lines
1.7 KiB
Diff
Raw Blame History

This file contains invisible Unicode characters

This file contains invisible Unicode characters that are indistinguishable to humans but may be processed differently by a computer. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

From c7c526af0bb4de631e2e5f1d38518beb8fa5a8a4 Mon Sep 17 00:00:00 2001
From: qihao <qihao_yewu@cmss.chinamobile.com>
Date: Wed, 5 Jun 2024 15:21:06 +0800
Subject: [PATCH] target/riscv/cpu.c: fix Zvkb extension config
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
cheery-pick from ff33b7a9699e977a050a1014c617a89da1bf8295
This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: qihao_yewu <qihao_yewu@cmss.chinamobile.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 83c7c0cf07..77cb59b8a1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1359,7 +1359,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
/* Vector cryptography extensions */
MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
- MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+ MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
--
2.41.0.windows.1