12ece8009b
- target/loongarch: Fix qemu-system-loongarch64 assert - target/loongarch: Fix qemu-loongarch64 hang when executing 'll.d , , 0' - target/loongarch: Fix tlb huge page loading issue - target/loongarch/kvm: Add software breakpoint support - target/loongarch/kvm: sync kernel header files - hw/intc/loongarch_extioi: Add virt extension support - target/loongarch/kvm: Add pmu support - target/loongarch/kvm: Fix vm restore failed - target/loongarch/kvm: Add pv steal time support - target/loongarch/kvm: fpu save the vreg registers high Signed-off-by: Song Gao <gaosong@loongson.cn>
137 lines
5.1 KiB
Diff
137 lines
5.1 KiB
Diff
From 3db0118d3663c5d56841dac30e4bf95ccfff21bd Mon Sep 17 00:00:00 2001
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From: Song Gao <gaosong@loongson.cn>
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Date: Tue, 2 Apr 2024 09:39:36 +0800
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Subject: [PATCH] target/loongarch: Fix qemu-system-loongarch64 assert
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failed with the option '-d int'
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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qemu-system-loongarch64 assert failed with the option '-d int',
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the helper_idle() raise an exception EXCP_HLT, but the exception name is undefined.
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-----
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merge patch:
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0cbb322f70e8a87e4acbffecef5ea8f9448f3513（target/loongarch/cpu.c: typo fix: expection）
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Signed-off-by: Song Gao <gaosong@loongson.cn>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Message-Id: <20240321123606.1704900-1-gaosong@loongson.cn>
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---
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target/loongarch/cpu.c | 74 +++++++++++++++++++++++-------------------
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1 file changed, 40 insertions(+), 34 deletions(-)
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diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
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index b098b1c6f3..0b3f954b64 100644
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--- a/target/loongarch/cpu.c
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+++ b/target/loongarch/cpu.c
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@@ -43,33 +43,45 @@ const char * const fregnames[32] = {
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
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};
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-static const char * const excp_names[] = {
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- [EXCCODE_INT] = "Interrupt",
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- [EXCCODE_PIL] = "Page invalid exception for load",
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- [EXCCODE_PIS] = "Page invalid exception for store",
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- [EXCCODE_PIF] = "Page invalid exception for fetch",
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- [EXCCODE_PME] = "Page modified exception",
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- [EXCCODE_PNR] = "Page Not Readable exception",
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- [EXCCODE_PNX] = "Page Not Executable exception",
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- [EXCCODE_PPI] = "Page Privilege error",
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- [EXCCODE_ADEF] = "Address error for instruction fetch",
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- [EXCCODE_ADEM] = "Address error for Memory access",
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- [EXCCODE_SYS] = "Syscall",
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- [EXCCODE_BRK] = "Break",
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- [EXCCODE_INE] = "Instruction Non-Existent",
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- [EXCCODE_IPE] = "Instruction privilege error",
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- [EXCCODE_FPD] = "Floating Point Disabled",
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- [EXCCODE_FPE] = "Floating Point Exception",
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- [EXCCODE_DBP] = "Debug breakpoint",
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- [EXCCODE_BCE] = "Bound Check Exception",
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- [EXCCODE_SXD] = "128 bit vector instructions Disable exception",
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- [EXCCODE_ASXD] = "256 bit vector instructions Disable exception",
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+struct TypeExcp {
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+ int32_t exccode;
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+ const char * const name;
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+};
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+
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+static const struct TypeExcp excp_names[] = {
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+ {EXCCODE_INT, "Interrupt"},
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+ {EXCCODE_PIL, "Page invalid exception for load"},
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+ {EXCCODE_PIS, "Page invalid exception for store"},
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+ {EXCCODE_PIF, "Page invalid exception for fetch"},
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+ {EXCCODE_PME, "Page modified exception"},
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+ {EXCCODE_PNR, "Page Not Readable exception"},
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+ {EXCCODE_PNX, "Page Not Executable exception"},
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+ {EXCCODE_PPI, "Page Privilege error"},
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+ {EXCCODE_ADEF, "Address error for instruction fetch"},
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+ {EXCCODE_ADEM, "Address error for Memory access"},
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+ {EXCCODE_SYS, "Syscall"},
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+ {EXCCODE_BRK, "Break"},
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+ {EXCCODE_INE, "Instruction Non-Existent"},
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+ {EXCCODE_IPE, "Instruction privilege error"},
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+ {EXCCODE_FPD, "Floating Point Disabled"},
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+ {EXCCODE_FPE, "Floating Point Exception"},
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+ {EXCCODE_DBP, "Debug breakpoint"},
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+ {EXCCODE_BCE, "Bound Check Exception"},
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+ {EXCCODE_SXD, "128 bit vector instructions Disable exception"},
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+ {EXCCODE_ASXD, "256 bit vector instructions Disable exception"},
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+ {EXCP_HLT, "EXCP_HLT"},
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};
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const char *loongarch_exception_name(int32_t exception)
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{
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- assert(excp_names[exception]);
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- return excp_names[exception];
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(excp_names); i++) {
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+ if (excp_names[i].exccode == exception) {
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+ return excp_names[i].name;
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+ }
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+ }
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+ return "Unknown";
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}
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void G_NORETURN do_raise_exception(CPULoongArchState *env,
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@@ -78,7 +90,7 @@ void G_NORETURN do_raise_exception(CPULoongArchState *env,
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{
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CPUState *cs = env_cpu(env);
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- qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n",
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+ qemu_log_mask(CPU_LOG_INT, "%s: exception: %d (%s)\n",
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__func__,
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exception,
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loongarch_exception_name(exception));
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@@ -159,22 +171,16 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
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CPULoongArchState *env = &cpu->env;
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bool update_badinstr = 1;
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int cause = -1;
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- const char *name;
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bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
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uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
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if (cs->exception_index != EXCCODE_INT) {
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- if (cs->exception_index < 0 ||
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- cs->exception_index >= ARRAY_SIZE(excp_names)) {
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- name = "unknown";
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- } else {
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- name = excp_names[cs->exception_index];
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- }
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-
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qemu_log_mask(CPU_LOG_INT,
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"%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
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- " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
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- env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
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+ " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n",
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+ __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA,
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+ cs->exception_index,
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+ loongarch_exception_name(cs->exception_index));
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}
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switch (cs->exception_index) {
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--
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2.33.0
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