0c39e725b0
To support CPU feature in AArch64, we need to move some field from ARMCPU to ARMISARegisters, add more definitions of ID fields, and add suport query-cpu-model-expansion qmp command. Let's backport upstream patches to do these. Signed-off-by: Peng Liang <liangpeng10@huawei.com>
78 lines
2.4 KiB
Diff
78 lines
2.4 KiB
Diff
From 6f18e959eabf9c752659eb3851f193bf343346c5 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Sat, 8 Feb 2020 12:57:59 +0000
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Subject: [PATCH 01/13] target/arm: Add isar_feature tests for PAN + ATS1E1
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Include definitions for all of the bits in ID_MMFR3.
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We already have a definition for ID_AA64MMFR1.PAN.
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20200208125816.14954-4-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/cpu.h | 29 +++++++++++++++++++++++++++++
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1 file changed, 29 insertions(+)
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index 86eb79cd..fe310828 100644
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--- a/target/arm/cpu.h
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+++ b/target/arm/cpu.h
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@@ -1680,6 +1680,15 @@ FIELD(ID_ISAR6, FHM, 8, 4)
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FIELD(ID_ISAR6, SB, 12, 4)
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FIELD(ID_ISAR6, SPECRES, 16, 4)
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+FIELD(ID_MMFR3, CMAINTVA, 0, 4)
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+FIELD(ID_MMFR3, CMAINTSW, 4, 4)
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+FIELD(ID_MMFR3, BPMAINT, 8, 4)
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+FIELD(ID_MMFR3, MAINTBCST, 12, 4)
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+FIELD(ID_MMFR3, PAN, 16, 4)
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+FIELD(ID_MMFR3, COHWALK, 20, 4)
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+FIELD(ID_MMFR3, CMEMSZ, 24, 4)
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+FIELD(ID_MMFR3, SUPERSEC, 28, 4)
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+
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FIELD(ID_MMFR4, SPECSEI, 0, 4)
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FIELD(ID_MMFR4, AC2, 4, 4)
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FIELD(ID_MMFR4, XNX, 8, 4)
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@@ -3445,6 +3454,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
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return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
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}
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+static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0;
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+}
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+
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+static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
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+}
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+
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/*
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* 64-bit feature tests via id registers.
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*/
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@@ -3589,6 +3608,16 @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
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}
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+static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
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+}
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+
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+static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
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+}
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+
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static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
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--
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2.25.1
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