c4dab45526
- qga/win32: Use rundll for VSS installation - qga/win32: Remove change action from MSI installer - ide: Increment BB in-flight counter for TRIM BH - hw/pci-bridge/pxb: Fix missing swizzle - host-vdpa: make notifiers _init()/_uninit() symmetric - hw/virtio: vdpa: Fix leak of host-notifier memory-region - accel/tcg/cpu-exec: Fix precise single-stepping after interrupt - Allow setting up to 8 bytes with the generic loader - hw/net/virtio-net: make some VirtIONet const - accel/tcg: Optimize jump cache flush during tlb range flush - 9pfs: prevent opening special files (CVE-2023-2861) - tcg: Reduce tcg_assert_listed_vecop() scope - gitlab: Disable plugins for cross-i386-tci - vfio/pci: Fix a segfault in vfio_realize - block/iscsi: fix double-free on BUSY or similar statuses - tests/tcg: fix unused variable in linux-test - hw/net/vmxnet3: allow VMXNET3_MAX_MTU itself as a value - qga/vss-win32: fix warning for clang++-15 - vnc: avoid underflow when accessing user-provided address - block/monitor: Fix crash when executing HMP commit - virtio-gpu: add a FIXME for virtio_gpu_load() - hw/ppc/Kconfig: MAC_NEWWORLD should always select USB_OHCI_PCI - migration: report compress thread pid to libvirt Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
53 lines
2.0 KiB
Diff
53 lines
2.0 KiB
Diff
From bf6161d03c1d6a8cb378a2f84743aa45b0ddf84b Mon Sep 17 00:00:00 2001
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From: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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Date: Wed, 26 Jul 2023 02:34:48 +0000
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Subject: [PATCH] hw/pci-bridge/pxb: Fix missing swizzle mainline inclusion
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commit e609301b458bf6daba478299dc5aea5d1fbaea39 category: bugfix
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---------------------------------------------------------------
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pxb_map_irq_fn() handled the necessary removal of the swizzle
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applied to the PXB interrupts by the bus to which it was attached
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but neglected to apply the normal swizzle for PCI root ports
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on the expander bridge.
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Result of this was on ARM virt, the PME interrupts for a second
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RP on a PXB instance were miss-routed to #45 rather than #46.
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Tested with a selection of different configurations with 1 to 5
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RP per PXB instance. Note on my x86 test setup the PME interrupts
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are not triggered so I haven't been able to test this.
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Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Cc: Michael S. Tsirkin <mst@redhat.com>
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Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
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Message-Id: <20220118174855.19325-1-Jonathan.Cameron@huawei.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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---
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hw/pci-bridge/pci_expander_bridge.c | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c
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index 10e6e7c2ab..de932286b5 100644
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--- a/hw/pci-bridge/pci_expander_bridge.c
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+++ b/hw/pci-bridge/pci_expander_bridge.c
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@@ -192,6 +192,12 @@ static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin)
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{
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PCIDevice *pxb = pci_get_bus(pci_dev)->parent_dev;
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+ /*
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+ * First carry out normal swizzle to handle
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+ * multple root ports on a pxb instance.
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+ */
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+ pin = pci_swizzle_map_irq_fn(pci_dev, pin);
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+
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/*
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* The bios does not index the pxb slot number when
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* it computes the IRQ because it resides on bus 0
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--
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2.41.0.windows.1
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