5636aff5b1
- target/i386: csv: Support inject secret for CSV3 guest only if the extension is enabled
- target/i386: csv: Support load kernel hashes for CSV3 guest only if the extension is enabled
- target/i386: csv: Request to set private memory of CSV3 guest if the extension is enabled
- target/i386: kvm: Support to get and enable extensions for Hygon CoCo guest
- qapi/qom,target/i386: csv-guest: Introduce secret-header-file=str and secret-file=str options
- bakcend: VirtCCA:resolve hugepage memory waste issue in vhost-user scenario
- parallels: fix ext_off assertion failure due to overflow
- backends/cryptodev-vhost-user: Fix local_error leaks
- hw/usb/hcd-ehci: Fix debug printf format string
- target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
- target/riscv/vector_helper.c: optimize loops in ldst helpers
- target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
- target/hexagon: don't look for static glib
- virtio-net: Fix network stall at the host side waiting for kick
- Add if condition to avoid assertion failed error in blockdev_init
- target/arm: Use float_status copy in sme_fmopa_s
- target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
- target/arm: Reinstate "vfp" property on AArch32 CPUs
- target/i386/cpu: Fix notes for CPU models
- target/arm: LDAPR should honour SCTLR_ELx.nAA
- target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()
- hvf: remove unused but set variable
- hw/misc/nrf51_rng: Don't use BIT_MASK() when we mean BIT()
- Avoid taking address of out-of-bounds array index
- target/arm: Fix VCMLA Dd, Dn, Dm[idx]
- target/arm: Fix UMOPA/UMOPS of 16-bit values
- target/arm: Fix SVE/SME gross MTE suppression checks
- target/arm: Fix nregs computation in do_{ld,st}_zpa
- crypto: fix error check on gcry_md_open
- Change vmstate_cpuhp_sts vmstateDescription version_id
- hw/pci: Remove unused pci_irq_pulse() method
- hw/intc: Don't clear pending bits on IRQ lowering
- target/arm: Drop user-only special case in sve_stN_r
- migration: Ensure vmstate_save() sets errp
- target/i386: fix hang when using slow path for ptw_setl
- contrib/plugins: add compat for g_memdup2
- hw/audio/hda: fix memory leak on audio setup
- crypto: perform runtime check for hash/hmac support in gcrypt
- target/arm: Fix incorrect aa64_tidcp1 feature check
- target/arm: fix exception syndrome for AArch32 bkpt insn
- target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
- linux-user: Print tid not pid with strace
- target/arm: Fix A64 scalar SQSHRN and SQRSHRN
- target/arm: Don't assert for 128-bit tile accesses when SVL is 128
- hw/timer/exynos4210_mct: fix possible int overflow
- target/arm: Avoid shifts by -1 in tszimm_shr() and tszimm_shl()
- hw/audio/virtio-snd: Always use little endian audio format
- target/riscv: Fix vcompress with rvv_ta_all_1s
- usb-hub: Fix handling port power control messages
Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
(cherry picked from commit d4a20b24ff377fd07fcbf2b72eecaf07a3ac4cc0)
57 lines
2.2 KiB
Diff
57 lines
2.2 KiB
Diff
From a820983749a2d3eebcc36b5a3ae34436fd52db45 Mon Sep 17 00:00:00 2001
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From: gubin <gubin_yewu@cmss.chinamobile.com>
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Date: Sat, 11 Jan 2025 10:54:33 +0800
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Subject: [PATCH] target/riscv/vector_helper.c: optimize loops in ldst helpers
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cherry-pick from 0a11629c915f61df798919db51a18ffe4649cb65
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Change the for loops in ldst helpers to do a single increment in the
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counter, and assign it env->vstart, to avoid re-reading from vstart
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every time.
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Suggested-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-ID: <20240314175704.478276-11-dbarboza@ventanamicro.com>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Signed-off-by: gubin <gubin_yewu@cmss.chinamobile.com>
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---
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target/riscv/vector_helper.c | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
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index 42ffd3a68a..b5acf81cc0 100644
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--- a/target/riscv/vector_helper.c
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+++ b/target/riscv/vector_helper.c
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@@ -196,7 +196,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
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uint32_t esz = 1 << log2_esz;
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uint32_t vma = vext_vma(desc);
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- for (i = env->vstart; i < env->vl; i++, env->vstart++) {
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+ for (i = env->vstart; i < env->vl; env->vstart = ++i) {
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k = 0;
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while (k < nf) {
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if (!vm && !vext_elem_mask(v0, i)) {
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@@ -262,7 +262,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
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uint32_t esz = 1 << log2_esz;
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/* load bytes from guest memory */
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- for (i = env->vstart; i < evl; i++, env->vstart++) {
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+ for (i = env->vstart; i < evl; env->vstart = ++i) {
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k = 0;
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while (k < nf) {
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target_ulong addr = base + ((i * nf + k) << log2_esz);
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@@ -376,7 +376,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
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uint32_t vma = vext_vma(desc);
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/* load bytes from guest memory */
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- for (i = env->vstart; i < env->vl; i++, env->vstart++) {
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+ for (i = env->vstart; i < env->vl; env->vstart = ++i) {
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k = 0;
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while (k < nf) {
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if (!vm && !vext_elem_mask(v0, i)) {
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--
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2.41.0.windows.1
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