5636aff5b1
- target/i386: csv: Support inject secret for CSV3 guest only if the extension is enabled
- target/i386: csv: Support load kernel hashes for CSV3 guest only if the extension is enabled
- target/i386: csv: Request to set private memory of CSV3 guest if the extension is enabled
- target/i386: kvm: Support to get and enable extensions for Hygon CoCo guest
- qapi/qom,target/i386: csv-guest: Introduce secret-header-file=str and secret-file=str options
- bakcend: VirtCCA:resolve hugepage memory waste issue in vhost-user scenario
- parallels: fix ext_off assertion failure due to overflow
- backends/cryptodev-vhost-user: Fix local_error leaks
- hw/usb/hcd-ehci: Fix debug printf format string
- target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
- target/riscv/vector_helper.c: optimize loops in ldst helpers
- target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
- target/hexagon: don't look for static glib
- virtio-net: Fix network stall at the host side waiting for kick
- Add if condition to avoid assertion failed error in blockdev_init
- target/arm: Use float_status copy in sme_fmopa_s
- target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
- target/arm: Reinstate "vfp" property on AArch32 CPUs
- target/i386/cpu: Fix notes for CPU models
- target/arm: LDAPR should honour SCTLR_ELx.nAA
- target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()
- hvf: remove unused but set variable
- hw/misc/nrf51_rng: Don't use BIT_MASK() when we mean BIT()
- Avoid taking address of out-of-bounds array index
- target/arm: Fix VCMLA Dd, Dn, Dm[idx]
- target/arm: Fix UMOPA/UMOPS of 16-bit values
- target/arm: Fix SVE/SME gross MTE suppression checks
- target/arm: Fix nregs computation in do_{ld,st}_zpa
- crypto: fix error check on gcry_md_open
- Change vmstate_cpuhp_sts vmstateDescription version_id
- hw/pci: Remove unused pci_irq_pulse() method
- hw/intc: Don't clear pending bits on IRQ lowering
- target/arm: Drop user-only special case in sve_stN_r
- migration: Ensure vmstate_save() sets errp
- target/i386: fix hang when using slow path for ptw_setl
- contrib/plugins: add compat for g_memdup2
- hw/audio/hda: fix memory leak on audio setup
- crypto: perform runtime check for hash/hmac support in gcrypt
- target/arm: Fix incorrect aa64_tidcp1 feature check
- target/arm: fix exception syndrome for AArch32 bkpt insn
- target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
- linux-user: Print tid not pid with strace
- target/arm: Fix A64 scalar SQSHRN and SQRSHRN
- target/arm: Don't assert for 128-bit tile accesses when SVL is 128
- hw/timer/exynos4210_mct: fix possible int overflow
- target/arm: Avoid shifts by -1 in tszimm_shr() and tszimm_shl()
- hw/audio/virtio-snd: Always use little endian audio format
- target/riscv: Fix vcompress with rvv_ta_all_1s
- usb-hub: Fix handling port power control messages
Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
(cherry picked from commit d4a20b24ff377fd07fcbf2b72eecaf07a3ac4cc0)
64 lines
3.0 KiB
Diff
64 lines
3.0 KiB
Diff
From 07dfcad1b3d9ecbf1afe65d3457a6dbcb31f1b94 Mon Sep 17 00:00:00 2001
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From: gubin <gubin_yewu@cmss.chinamobile.com>
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Date: Tue, 17 Dec 2024 14:47:59 +0800
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Subject: [PATCH] target/arm: Fix UMOPA/UMOPS of 16-bit values
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cherry-pick from ea3f5a90f036734522e9af3bffd77e69e9f47355
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The UMOPA/UMOPS instructions are supposed to multiply unsigned 8 or
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16 bit elements and accumulate the products into a 64-bit element.
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In the Arm ARM pseudocode, this is done with the usual
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infinite-precision signed arithmetic. However our implementation
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doesn't quite get it right, because in the DEF_IMOP_64() macro we do:
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sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0);
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where NTYPE and MTYPE are uint16_t or int16_t. In the uint16_t case,
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the C usual arithmetic conversions mean the values are converted to
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"int" type and the multiply is done as a 32-bit multiply. This means
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that if the inputs are, for example, 0xffff and 0xffff then the
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result is 0xFFFE0001 as an int, which is then promoted to uint64_t
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for the accumulation into sum; this promotion incorrectly sign
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extends the multiply.
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Avoid the incorrect sign extension by casting to int64_t before
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the multiply, so we do the multiply as 64-bit signed arithmetic,
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which is a type large enough that the multiply can never
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overflow into the sign bit.
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(The equivalent 8-bit operations in DEF_IMOP_32() are fine, because
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the 8-bit multiplies can never overflow into the sign bit of a
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32-bit integer.)
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Cc: qemu-stable@nongnu.org
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2372
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20240722172957.1041231-3-peter.maydell@linaro.org
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Signed-off-by: gubin <gubin_yewu@cmss.chinamobile.com>
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---
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target/arm/tcg/sme_helper.c | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
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index 1ee2690ceb..e94b5335e1 100644
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--- a/target/arm/tcg/sme_helper.c
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+++ b/target/arm/tcg/sme_helper.c
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@@ -1134,10 +1134,10 @@ static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
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uint64_t sum = 0; \
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/* Apply P to N as a mask, making the inactive elements 0. */ \
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n &= expand_pred_h(p); \
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- sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
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- sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
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- sum += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \
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- sum += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \
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+ sum += (int64_t)(NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
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+ sum += (int64_t)(NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
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+ sum += (int64_t)(NTYPE)(n >> 32) * (MTYPE)(m >> 32); \
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+ sum += (int64_t)(NTYPE)(n >> 48) * (MTYPE)(m >> 48); \
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return neg ? a - sum : a + sum; \
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}
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--
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2.41.0.windows.1
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