0c39e725b0
To support CPU feature in AArch64, we need to move some field from ARMCPU to ARMISARegisters, add more definitions of ID fields, and add suport query-cpu-model-expansion qmp command. Let's backport upstream patches to do these. Signed-off-by: Peng Liang <liangpeng10@huawei.com>
77 lines
2.7 KiB
Diff
77 lines
2.7 KiB
Diff
From 4001f3040937094660eab44dbb49b86817317ea9 Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Fri, 14 Feb 2020 17:51:01 +0000
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Subject: [PATCH 03/13] target/arm: Add and use FIELD definitions for
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ID_AA64DFR0_EL1
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them
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where we currently have hard-coded bit values.
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20200214175116.9164-7-peter.maydell@linaro.org
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---
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target/arm/cpu.c | 2 +-
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target/arm/cpu.h | 10 ++++++++++
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target/arm/helper.c | 6 +++---
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3 files changed, 14 insertions(+), 4 deletions(-)
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diff --git a/target/arm/cpu.c b/target/arm/cpu.c
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index 811e5c63..dbd05e01 100644
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--- a/target/arm/cpu.c
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+++ b/target/arm/cpu.c
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@@ -1522,7 +1522,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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cpu);
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#endif
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} else {
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- cpu->id_aa64dfr0 &= ~0xf00;
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+ cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
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cpu->id_dfr0 &= ~(0xf << 24);
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cpu->pmceid0 = 0;
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cpu->pmceid1 = 0;
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index 3e65bc50..91cc02b4 100644
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--- a/target/arm/cpu.h
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+++ b/target/arm/cpu.h
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@@ -1779,6 +1779,16 @@ FIELD(ID_AA64MMFR2, BBM, 52, 4)
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FIELD(ID_AA64MMFR2, EVT, 56, 4)
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FIELD(ID_AA64MMFR2, E0PD, 60, 4)
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+FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
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+FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
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+FIELD(ID_AA64DFR0, PMUVER, 8, 4)
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+FIELD(ID_AA64DFR0, BRPS, 12, 4)
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+FIELD(ID_AA64DFR0, WRPS, 20, 4)
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+FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
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+FIELD(ID_AA64DFR0, PMSVER, 32, 4)
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+FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
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+FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
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+
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FIELD(ID_DFR0, COPDBG, 0, 4)
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FIELD(ID_DFR0, COPSDBG, 4, 4)
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FIELD(ID_DFR0, MMAPDBG, 8, 4)
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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index c50b1ba1..419be640 100644
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--- a/target/arm/helper.c
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+++ b/target/arm/helper.c
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@@ -5611,9 +5611,9 @@ static void define_debug_regs(ARMCPU *cpu)
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* check that if they both exist then they agree.
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*/
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if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
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- assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
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- assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
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- assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
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+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) == brps);
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+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps);
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+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) == ctx_cmps);
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}
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define_one_arm_cp_reg(cpu, &dbgdidr);
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--
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2.25.1
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