7428290d4a
- fix compile error on loongarch
- hw/loongarch: fix cpu hotplug reset
- hw/loongarch/boot: Use warn_report when no kernel filename
- hw/loongarch: clean code
- hw/loongarch: Add KVM pch msi device support
- hw/loongarch: Add KVM pch pic device support
- hw/loongarch: Add KVM extioi device support
- hw/loongarch: Add KVM IPI device support
- hw/loongarch/virt: Update the ACPI table for hotplug cpu
- hw/loongarch/virt: Add basic CPU plug support
- hw/loongarch/virt: Add CPU topology support
- accel/kvm/kvm-all: Fixes the missing break in vCPU unpark logic
- gdbstub: Add helper function to unregister GDB register space
- physmem: Add helper function to destroy CPU AddressSpace
- hw/acpi: Update CPUs AML with cpu-(ctrl)dev change
- hw/acpi: Update ACPI GED framework to support vCPU Hotplug
- hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file
- accel/kvm: Extract common KVM vCPU {creation,parking} code
- target/loongarch: Add steal time support on migration
- linux-headers: loongarch: Add kvm_para.h and unistd_64.h
- target/loongarch/kvm: Implement LoongArch PMU extension
- target/loongarch: Implement lbt registers save/restore function
- target/loongarch: Add loongson binary translation feature
- sync loongarch linux-headers
- target/loongarch: Avoid bits shift exceeding width of bool type
- target/loongarch: Use explicit little-endian LD/ST API
- target/loongarch: fix -Werror=maybe-uninitialized false-positive
- target/loongarch: Support QMP dump-guest-memory
- target/loongarch/kvm: Add vCPU reset function
- target/loongarch: Add compatible support about VM reboot
- target/loongarch: Fix cpu_reset set wrong CSR_CRMD
- target/loongarch: Set CSR_PRCFG1 and CSR_PRCFG2 values
- target/loongarch: Remove avail_64 in trans_srai_w() and simplify it
- target/loongarch/kvm: Add software breakpoint support
- target/loongarch: Add loongarch vector property unconditionally
- target/loongarch/kvm: Fix VM recovery from disk failures
- target/loongarch: Put cpucfg operation before CSR register
- target/loongarch: Add TCG macro in structure CPUArchState
- hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
- hw/loongarch/virt: Add FDT table support with acpi ged pm register
- hw/loongarch/virt: Add description for virt machine type
- hw/loongarch: Add acpi SPCR table support
- hw/loongarch: virt: pass random seed to fdt
- hw/loongarch: virt: support up to 4 serial ports
- hw/loongarch: Remove default enable with VIRTIO_VGA device
- hw/loongarch: Fix length for lowram in ACPI SRAT
- hw/loongarch/virt: Remove unused assignment
- hw/loongarch: Change the tpm support by default
- hw/loongarch/boot.c: fix out-of-bound reading
- hw/loongarch/virt: Use MemTxAttrs interface for misc ops
- tests/libqos: Add loongarch virt machine node
- hw/loongarch: Remove minimum and default memory size
- hw/loongarch: Refine system dram memory region
- hw/loongarch: Refine fwcfg memory map
- hw/loongarch: Refine fadt memory table for numa memory
- hw/loongarch: Refine acpi srat table for numa memory
- hw/loongarch: Add VM mode in IOCSR feature register in kvm mode
- hw/loongarch: Refine default numa id calculation
- hw/loongarch: Rename LoongArchMachineState with LoongArchVirtMachineState
- hw/loongarch: Rename LOONGARCH_MACHINE with LOONGARCH_VIRT_MACHINE
- hw/loongarch: move memory map to boot.c
- loongarch: switch boards to "default y"
- hw/loongarch: Add cells missing from rtc node
- hw/loongarch: Add cells missing from uart node
- hw/loongarch: fdt remove unused irqchip node
- hw/loongarch: fdt adds pcie irq_map node
- hw/loongarch: fdt adds pch_msi Controller
- hw/loongarch: fdt adds pch_pic Controller
- hw/loongarch: fdt adds Extend I/O Interrupt Controller
- hw/loongarch: fdt adds cpu interrupt controller node
- hw/loongarch: Init efi_fdt table
- hw/loongarch: Init efi_initrd table
- hw/loongarch: Init efi_boot_memmap table
- hw/loongarch: Init efi_system_table
- hw/loongarch: Add init_cmdline
- hw/loongarch: Add slave cpu boot_code
- hw/loongarch: Add load initrd
- hw/loongarch: Move boot functions to boot.c
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
(cherry picked from commit 04ca9e6c8ff19630116722240ae0136cea831c5c)
70 lines
2.5 KiB
Diff
70 lines
2.5 KiB
Diff
From cd506fbf0d9a00aa0f25de1e7bd26ad4335c8257 Mon Sep 17 00:00:00 2001
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From: Song Gao <gaosong@loongson.cn>
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Date: Fri, 26 Apr 2024 17:15:44 +0800
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Subject: [PATCH 09/78] hw/loongarch: fdt adds cpu interrupt controller node
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fdt adds cpu interrupt controller node,
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we use 'loongson,cpu-interrupt-controller'.
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See:
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https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongarch-cpu.c
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https://lore.kernel.org/r/20221114113824.1880-2-liupeibao@loongson.cn
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Signed-off-by: Song Gao <gaosong@loongson.cn>
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Reviewed-by: Bibo Mao <maobibo@loongson.cn>
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Message-Id: <20240426091551.2397867-11-gaosong@loongson.cn>
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Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
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---
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hw/loongarch/virt.c | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
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index 99a3dc8696..fdc4a5d708 100644
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--- a/hw/loongarch/virt.c
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+++ b/hw/loongarch/virt.c
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@@ -133,6 +133,23 @@ static void virt_flash_map(LoongArchMachineState *lams,
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virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem);
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}
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+static void fdt_add_cpuic_node(LoongArchMachineState *lams,
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+ uint32_t *cpuintc_phandle)
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+{
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+ MachineState *ms = MACHINE(lams);
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+ char *nodename;
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+
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+ *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt);
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+ nodename = g_strdup_printf("/cpuic");
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+ qemu_fdt_add_subnode(ms->fdt, nodename);
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+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle);
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+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
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+ "loongson,cpu-interrupt-controller");
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+ qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
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+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
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+ g_free(nodename);
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+}
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+
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static void fdt_add_flash_node(LoongArchMachineState *lams)
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{
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MachineState *ms = MACHINE(lams);
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@@ -557,6 +574,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
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CPULoongArchState *env;
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CPUState *cpu_state;
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int cpu, pin, i, start, num;
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+ uint32_t cpuintc_phandle;
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/*
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* The connection of interrupts:
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@@ -591,6 +609,9 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
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memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
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+ /* Add cpu interrupt-controller */
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+ fdt_add_cpuic_node(lams, &cpuintc_phandle);
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+
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for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
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cpu_state = qemu_get_cpu(cpu);
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cpudev = DEVICE(cpu_state);
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--
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2.39.1
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