dddaf7aa9e
- vdpa-dev: Fix initialisation order to restore VDUSE compatibility - tcg: Allow top bit of SIMD_DATA_BITS to be set in simd_desc() - migration: fix-possible-int-overflow - target/m68k: Map FPU exceptions to FPSR register - qemu-options: Fix CXL Fixed Memory Window interleave-granularity typo - hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registers - hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n> - qio: Inherit follow_coroutine_ctx across TLS - target/riscv: Fix the element agnostic function problem - accel/tcg: Fix typo causing tb->page_addr[1] to not be recorded - tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers - migration: Fix file migration with fdset - ui/vnc: don't return an empty SASL mechlist to the client - target/arm: Fix FJCVTZS vs flush-to-zero - hw/ppc/e500: Prefer QOM cast - sphinx/qapidoc: Fix to generate doc for explicit, unboxed arguments - hw/ppc/e500: Remove unused "irqs" parameter - hw/ppc/e500: Add missing device tree properties to i2c controller node - hw/i386/amd_iommu: Don't leak memory in amdvi_update_iotlb() - hw/arm/mps2-tz.c: fix RX/TX interrupts order - target/i386: csv: Add support to migrate the incoming context for CSV3 guest - target/i386: csv: Add support to migrate the outgoing context for CSV3 guest - target/i386: csv: Add support to migrate the incoming page for CSV3 guest - target/i386: csv: Add support to migrate the outgoing page for CSV3 guest - linux-headers: update kernel headers to include CSV3 migration cmds - vfio: Only map shared region for CSV3 virtual machine - vga: Force full update for CSV3 guest - target/i386: csv: Load initial image to private memory for CSV3 guest - target/i386: csv: Do not register/unregister guest secure memory for CSV3 guest - target/i386: cpu: Populate CPUID 0x8000_001F when CSV3 is active - target/i386: csv: Add command to load vmcb to CSV3 guest memory - target/i386: csv: Add command to load data to CSV3 guest memory - target/i386: csv: Add command to initialize CSV3 context - target/i386: csv: Add CSV3 context - next-kbd: convert to use qemu_input_handler_register() - qemu/bswap: Undefine CPU_CONVERT() once done - exec/memop: Remove unused memop_big_endian() helper - hw/nvme: fix handling of over-committed queues - 9pfs: fix crash on 'Treaddir' request - hw/misc/psp: Pin the hugepage memory specified by mem2 during use for psp - hw/misc: support tkm use mem2 memory - hw/i386: add mem2 option for qemu - kvm: add support for guest physical bits - target/i386: add guest-phys-bits cpu property Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com> (cherry picked from commit f45f35e88509a4ffa9f62332ee9601e9fe1f8d09)
78 lines
2.9 KiB
Diff
78 lines
2.9 KiB
Diff
From 6477ff9d89317a6124f3a46215b1567306b6ebe4 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Wed, 19 Jun 2024 05:41:13 +0000
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Subject: [PATCH] tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers
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Simplify the logic for two-part, 32-bit pc-relative addresses.
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Rather than assume all such fit in int32_t, do some arithmetic
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and assert a result, do some arithmetic first and then check
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to see if the pieces are in range.
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Cc: qemu-stable@nongnu.org
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Fixes: dacc51720db ("tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi")
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Reviewed-by: Song Gao <gaosong@loongson.cn>
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Reported-by: Song Gao <gaosong@loongson.cn>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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(cherry picked from commit 521d7fb3ebdf88112ed13556a93e3037742b9eb8)
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Signed-off-by: zhujun2 <zhujun2_yewu@cmss.chinamobile.com>
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---
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tcg/loongarch64/tcg-target.c.inc | 32 +++++++++++++++-----------------
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1 file changed, 15 insertions(+), 17 deletions(-)
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diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
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index bab0a173a3..ad2690b90d 100644
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--- a/tcg/loongarch64/tcg-target.c.inc
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+++ b/tcg/loongarch64/tcg-target.c.inc
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@@ -365,8 +365,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
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* back to the slow path.
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*/
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- intptr_t pc_offset;
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- tcg_target_long val_lo, val_hi, pc_hi, offset_hi;
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+ intptr_t src_rx, pc_offset;
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tcg_target_long hi12, hi32, hi52;
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/* Value fits in signed i32. */
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@@ -376,24 +375,23 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
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}
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/* PC-relative cases. */
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- pc_offset = tcg_pcrel_diff(s, (void *)val);
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- if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) {
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- /* Single pcaddu2i. */
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- tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2);
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- return;
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+ src_rx = (intptr_t)tcg_splitwx_to_rx(s->code_ptr);
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+ if ((val & 3) == 0) {
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+ pc_offset = val - src_rx;
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+ if (pc_offset == sextreg(pc_offset, 0, 22)) {
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+ /* Single pcaddu2i. */
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+ tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2);
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+ return;
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+ }
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}
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- if (pc_offset == (int32_t)pc_offset) {
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- /* Offset within 32 bits; load with pcalau12i + ori. */
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- val_lo = sextreg(val, 0, 12);
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- val_hi = val >> 12;
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- pc_hi = (val - pc_offset) >> 12;
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- offset_hi = val_hi - pc_hi;
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-
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- tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20));
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- tcg_out_opc_pcalau12i(s, rd, offset_hi);
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+ pc_offset = (val >> 12) - (src_rx >> 12);
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+ if (pc_offset == sextreg(pc_offset, 0, 20)) {
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+ /* Load with pcalau12i + ori. */
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+ tcg_target_long val_lo = val & 0xfff;
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+ tcg_out_opc_pcalau12i(s, rd, pc_offset);
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if (val_lo != 0) {
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- tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff);
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+ tcg_out_opc_ori(s, rd, rd, val_lo);
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}
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return;
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}
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--
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2.41.0.windows.1
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