7428290d4a
- fix compile error on loongarch
- hw/loongarch: fix cpu hotplug reset
- hw/loongarch/boot: Use warn_report when no kernel filename
- hw/loongarch: clean code
- hw/loongarch: Add KVM pch msi device support
- hw/loongarch: Add KVM pch pic device support
- hw/loongarch: Add KVM extioi device support
- hw/loongarch: Add KVM IPI device support
- hw/loongarch/virt: Update the ACPI table for hotplug cpu
- hw/loongarch/virt: Add basic CPU plug support
- hw/loongarch/virt: Add CPU topology support
- accel/kvm/kvm-all: Fixes the missing break in vCPU unpark logic
- gdbstub: Add helper function to unregister GDB register space
- physmem: Add helper function to destroy CPU AddressSpace
- hw/acpi: Update CPUs AML with cpu-(ctrl)dev change
- hw/acpi: Update ACPI GED framework to support vCPU Hotplug
- hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file
- accel/kvm: Extract common KVM vCPU {creation,parking} code
- target/loongarch: Add steal time support on migration
- linux-headers: loongarch: Add kvm_para.h and unistd_64.h
- target/loongarch/kvm: Implement LoongArch PMU extension
- target/loongarch: Implement lbt registers save/restore function
- target/loongarch: Add loongson binary translation feature
- sync loongarch linux-headers
- target/loongarch: Avoid bits shift exceeding width of bool type
- target/loongarch: Use explicit little-endian LD/ST API
- target/loongarch: fix -Werror=maybe-uninitialized false-positive
- target/loongarch: Support QMP dump-guest-memory
- target/loongarch/kvm: Add vCPU reset function
- target/loongarch: Add compatible support about VM reboot
- target/loongarch: Fix cpu_reset set wrong CSR_CRMD
- target/loongarch: Set CSR_PRCFG1 and CSR_PRCFG2 values
- target/loongarch: Remove avail_64 in trans_srai_w() and simplify it
- target/loongarch/kvm: Add software breakpoint support
- target/loongarch: Add loongarch vector property unconditionally
- target/loongarch/kvm: Fix VM recovery from disk failures
- target/loongarch: Put cpucfg operation before CSR register
- target/loongarch: Add TCG macro in structure CPUArchState
- hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
- hw/loongarch/virt: Add FDT table support with acpi ged pm register
- hw/loongarch/virt: Add description for virt machine type
- hw/loongarch: Add acpi SPCR table support
- hw/loongarch: virt: pass random seed to fdt
- hw/loongarch: virt: support up to 4 serial ports
- hw/loongarch: Remove default enable with VIRTIO_VGA device
- hw/loongarch: Fix length for lowram in ACPI SRAT
- hw/loongarch/virt: Remove unused assignment
- hw/loongarch: Change the tpm support by default
- hw/loongarch/boot.c: fix out-of-bound reading
- hw/loongarch/virt: Use MemTxAttrs interface for misc ops
- tests/libqos: Add loongarch virt machine node
- hw/loongarch: Remove minimum and default memory size
- hw/loongarch: Refine system dram memory region
- hw/loongarch: Refine fwcfg memory map
- hw/loongarch: Refine fadt memory table for numa memory
- hw/loongarch: Refine acpi srat table for numa memory
- hw/loongarch: Add VM mode in IOCSR feature register in kvm mode
- hw/loongarch: Refine default numa id calculation
- hw/loongarch: Rename LoongArchMachineState with LoongArchVirtMachineState
- hw/loongarch: Rename LOONGARCH_MACHINE with LOONGARCH_VIRT_MACHINE
- hw/loongarch: move memory map to boot.c
- loongarch: switch boards to "default y"
- hw/loongarch: Add cells missing from rtc node
- hw/loongarch: Add cells missing from uart node
- hw/loongarch: fdt remove unused irqchip node
- hw/loongarch: fdt adds pcie irq_map node
- hw/loongarch: fdt adds pch_msi Controller
- hw/loongarch: fdt adds pch_pic Controller
- hw/loongarch: fdt adds Extend I/O Interrupt Controller
- hw/loongarch: fdt adds cpu interrupt controller node
- hw/loongarch: Init efi_fdt table
- hw/loongarch: Init efi_initrd table
- hw/loongarch: Init efi_boot_memmap table
- hw/loongarch: Init efi_system_table
- hw/loongarch: Add init_cmdline
- hw/loongarch: Add slave cpu boot_code
- hw/loongarch: Add load initrd
- hw/loongarch: Move boot functions to boot.c
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
(cherry picked from commit 04ca9e6c8ff19630116722240ae0136cea831c5c)
55 lines
2.4 KiB
Diff
55 lines
2.4 KiB
Diff
From 16d44ddb63becd559cc2185549c4b18d26feab60 Mon Sep 17 00:00:00 2001
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From: Salil Mehta <salil.mehta@huawei.com>
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Date: Tue, 16 Jul 2024 12:15:00 +0100
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Subject: [PATCH 65/78] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change
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CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO port
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based and existing CPUs AML code assumes _CRS objects would evaluate to a system
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resource which describes IO Port address. But on ARM arch CPUs control
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device(\\_SB.PRES) register interface is memory-mapped hence _CRS object should
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evaluate to system resource which describes memory-mapped base address. Update
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build CPUs AML function to accept both IO/MEMORY region spaces and accordingly
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update the _CRS object.
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Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com>
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Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
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Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
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Reviewed-by: Gavin Shan <gshan@redhat.com>
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Tested-by: Vishnu Pajjuri <vishnu@os.amperecomputing.com>
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Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Tested-by: Xianglai Li <lixianglai@loongson.cn>
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Tested-by: Miguel Luis <miguel.luis@oracle.com>
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Reviewed-by: Shaoqin Huang <shahuang@redhat.com>
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Tested-by: Zhao Liu <zhao1.liu@intel.com>
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Reviewed-by: Igor Mammedov <imammedo@redhat.com>
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Message-Id: <20240716111502.202344-6-salil.mehta@huawei.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
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---
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hw/acpi/cpu.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
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index 292e1daca2..5e9093991e 100644
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--- a/hw/acpi/cpu.c
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+++ b/hw/acpi/cpu.c
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@@ -392,11 +392,13 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
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aml_name_decl("_UID", aml_string("CPU Hotplug resources")));
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aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
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+ assert((rs == AML_SYSTEM_IO) || (rs == AML_SYSTEM_MEMORY));
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+
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crs = aml_resource_template();
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if (rs == AML_SYSTEM_IO) {
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aml_append(crs, aml_io(AML_DECODE16, base_addr, base_addr, 1,
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ACPI_CPU_HOTPLUG_REG_LEN));
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- } else {
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+ } else if (rs == AML_SYSTEM_MEMORY) {
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aml_append(crs, aml_memory32_fixed(base_addr,
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ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE));
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}
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--
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2.39.1
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