From 52eed626a2200da02e67aa93c2a8d59cb529737b Mon Sep 17 00:00:00 2001 From: Jing Liu Date: Wed, 16 Feb 2022 22:04:30 -0800 Subject: [PATCH 05/10] x86: Add XFD faulting bit for state components from mainline-v7.0.0-rc0 commit 0f17f6b30f3b051f0f96ccc98c9f7f395713699f category: feature feature: SPR AMX support for Qemu bugzilla: https://gitee.com/openeuler/intel-qemu/issues/I5VHOB Intel-SIG: commit 0f17f6b30f3b ("x86: Add XFD faulting bit for state components") ------------------------------------------------- x86: Add XFD faulting bit for state components Intel introduces XFD faulting mechanism for extended XSAVE features to dynamically enable the features in runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set as 1, it indicates support for XFD faulting of this state component. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong Message-Id: <20220217060434.52460-5-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini Signed-off-by: Jason Zeng --- target/i386/cpu.c | 3 ++- target/i386/cpu.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fb6b4c86de..da81e47dc3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5515,7 +5515,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, const ExtSaveArea *esa = &x86_ext_save_areas[count]; *eax = esa->size; *ebx = esa->offset; - *ecx = esa->ecx & ESA_FEATURE_ALIGN64_MASK; + *ecx = esa->ecx & + (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); } } break; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 93d1c60ac1..09c725ee13 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -556,8 +556,10 @@ typedef enum X86Seg { #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK) #define ESA_FEATURE_ALIGN64_BIT 1 +#define ESA_FEATURE_XFD_BIT 2 #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT) +#define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT) /* CPUID feature words */ -- 2.27.0