From c9b226f4a56bb13d4f0924ea3ce4b334e65e6db2 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 1 Aug 2022 16:21:18 +0100 Subject: [PATCH 2/5] target/arm: Set KVM_ARM_VCPU_SVE while probing the host Because we weren't setting this flag, our probe of ID_AA64ZFR0 was always returning zero. This also obviates the adjustment of ID_AA64PFR0, which had sanitized the SVE field. The effects of the bug are not visible, because the only thing that ID_AA64ZFR0 is used for within qemu at present is tcg translation. The other tests for SVE within KVM are via ID_AA64PFR0.SVE. Reported-by: Zenghui Yu Signed-off-by: Richard Henderson Message-id: 20220726045828.53697-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell Signed-off-by: Kunkun Jiang --- target/arm/kvm64.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index b7e34a4580..5b15d0582d 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -501,7 +501,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) int fdarray[3]; bool sve_supported; uint64_t features = 0; - uint64_t t; int err; /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -521,6 +520,15 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) */ struct kvm_vcpu_init init = { .target = -1, }; + /* + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, + * which is otherwise RAZ. + */ + sve_supported = kvm_arm_sve_supported(); + if (sve_supported) { + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; + } + if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { return false; } @@ -648,19 +656,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } } - sve_supported = kvm_arm_sve_supported(); - - /* Add feature bits that can't appear until after VCPU init. */ if (sve_supported) { - t = ahcf->isar.regs[ID_AA64PFR0]; - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - ahcf->isar.regs[ID_AA64PFR0] = t; - /* - * Before v5.1, KVM did not support SVE and did not expose - * ID_AA64ZFR0_EL1 even as RAZ. After v5.1, KVM still does - * not expose the register to "user" requests like this - * unless the host supports SVE. + * There is a range of kernels between kernel commit 73433762fcae + * and f81cb2c3ad41 which have a bug where the kernel doesn't expose + * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled + * SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. */ err |= read_sys_reg64(fdarray[2], &ahcf->isar.regs[ID_AA64ZFR0], ARM64_SYS_REG(3, 0, 0, 4, 4)); -- 2.27.0