From 98ca0862f34c891a0e381bd382306398b88ac5bc Mon Sep 17 00:00:00 2001 From: Kunkun Jiang Date: Fri, 18 Nov 2022 15:22:56 +0800 Subject: [PATCH 33/36] Revert "hw/arm/smmuv3: Improve stage1 ASID invalidation" This reverts commit de53feaa37a267a21ed30a642e1e64c5fcfbc4a4. Signed-off-by: Kunkun Jiang --- hw/arm/smmuv3.c | 44 ++------------------------------------------ hw/arm/trace-events | 1 - 2 files changed, 2 insertions(+), 43 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index f4de66827d..0e8fe646aa 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -840,31 +840,6 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, memory_region_notify_iommu_one(n, &event); } -/** - * smmuv3_notify_asid - call the notifier @n for a given asid - * - * @mr: IOMMU mr region handle - * @n: notifier to be called - * @asid: address space ID or negative value if we don't care - */ -static void smmuv3_notify_asid(IOMMUMemoryRegion *mr, - IOMMUNotifier *n, int asid) -{ - IOMMUTLBEvent event = {}; - - event.type = IOMMU_NOTIFIER_UNMAP; - event.entry.target_as = &address_space_memory; - event.entry.perm = IOMMU_NONE; - event.entry.granularity = IOMMU_INV_GRAN_PASID; - event.entry.flags = IOMMU_INV_FLAGS_ARCHID; - event.entry.arch_id = asid; - event.entry.iova = n->start; - event.entry.addr_mask = n->end - n->start; - - memory_region_notify_iommu_one(n, &event); -} - - /* invalidate an asid/iova range tuple in all mr's */ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova, uint8_t tg, uint64_t num_pages) @@ -942,22 +917,6 @@ smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data) return true; } -static void smmuv3_s1_asid_inval(SMMUState *s, uint16_t asid) -{ - SMMUDevice *sdev; - - trace_smmuv3_s1_asid_inval(asid); - QLIST_FOREACH(sdev, &s->devices_with_notifiers, next) { - IOMMUMemoryRegion *mr = &sdev->iommu; - IOMMUNotifier *n; - - IOMMU_NOTIFIER_FOREACH(n, mr) { - smmuv3_notify_asid(mr, n, asid); - } - } - smmu_iotlb_inv_asid(s, asid); -} - static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs = ARM_SMMU(s); @@ -1072,7 +1031,8 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) uint16_t asid = CMD_ASID(&cmd); trace_smmuv3_cmdq_tlbi_nh_asid(asid); - smmuv3_s1_asid_inval(bs, asid); + smmu_inv_notifiers_all(&s->smmu_state); + smmu_iotlb_inv_asid(bs, asid); break; } case SMMU_CMD_TLBI_NH_ALL: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 1447ad5a90..2dee296c8f 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -46,7 +46,6 @@ smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)" smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d" -smmuv3_s1_asid_inval(int asid) "asid=%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x" -- 2.27.0