From fac9784bbedb50dc964feb9cf70b6f37472fcf60 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Fri, 21 Apr 2023 22:10:44 -0700 Subject: [PATCH] hw/arm/smmuv3: Check idr registers for STE_S1CDMAX and STE_S1STALLD With nested translation, the underlying HW could support those two fields. Allow them according to the updated idr registers after the hw_info ioctl. Signed-off-by: Nicolin Chen --- hw/arm/smmuv3.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 4208325ab3..253d297eec 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -622,13 +622,14 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, } } - if (STE_S1CDMAX(ste) != 0) { + if (!FIELD_EX32(s->idr[1], IDR1, SSIDSIZE) && STE_S1CDMAX(ste) != 0) { qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support multiple context descriptors yet\n"); goto bad_ste; } - if (STE_S1STALLD(ste)) { + /* STALL_MODEL being 0b01 means "stall is not supported" */ + if ((FIELD_EX32(s->idr[0], IDR0, STALL_MODEL) & 0x1) && STE_S1STALLD(ste)) { qemu_log_mask(LOG_UNIMP, "SMMUv3 S1 stalling fault model not allowed yet\n"); goto bad_ste; -- 2.41.0.windows.1