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3 Commits

Author SHA1 Message Date
Chen Qun
efdfacd31d target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest 
Some AArch64 CPU doesn't support AArch32 mode, and the values of AArch32
registers are all 0.  Hence, We'd better not to modify AArch32 registers
in AArch64 mode.

Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
Signed-off-by: Dongxu Sun <sundongxu3@huawei.com>
 2022-03-19 14:42:31 +08:00
liuxiangdong
787ea25064 Package init 
Signed-off-by: yezengruan <yezengruan@huawei.com>
 2022-03-19 14:31:23 +08:00
imxcc
d609107256 some bugfix sync from 20.09 
Signed-off-by: imxcc <xingchaochao@huawei.com>
 2021-07-28 15:19:15 +08:00